1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_IcelakeServer: 142 setFeatureEnabledImpl(Features, "pconfig", true); 143 setFeatureEnabledImpl(Features, "wbnoinvd", true); 144 LLVM_FALLTHROUGH; 145 case CK_IcelakeClient: 146 setFeatureEnabledImpl(Features, "vaes", true); 147 setFeatureEnabledImpl(Features, "gfni", true); 148 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 149 setFeatureEnabledImpl(Features, "avx512bitalg", true); 150 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 151 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 152 setFeatureEnabledImpl(Features, "rdpid", true); 153 LLVM_FALLTHROUGH; 154 case CK_Cannonlake: 155 setFeatureEnabledImpl(Features, "avx512ifma", true); 156 setFeatureEnabledImpl(Features, "avx512vbmi", true); 157 setFeatureEnabledImpl(Features, "sha", true); 158 LLVM_FALLTHROUGH; 159 case CK_Cascadelake: 160 //Cannonlake has no VNNI feature inside while Icelake has 161 if (Kind != CK_Cannonlake) 162 // CLK inherits all SKX features plus AVX512_VNNI 163 setFeatureEnabledImpl(Features, "avx512vnni", true); 164 LLVM_FALLTHROUGH; 165 case CK_SkylakeServer: 166 setFeatureEnabledImpl(Features, "avx512f", true); 167 setFeatureEnabledImpl(Features, "avx512cd", true); 168 setFeatureEnabledImpl(Features, "avx512dq", true); 169 setFeatureEnabledImpl(Features, "avx512bw", true); 170 setFeatureEnabledImpl(Features, "avx512vl", true); 171 setFeatureEnabledImpl(Features, "pku", true); 172 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 173 setFeatureEnabledImpl(Features, "clwb", true); 174 LLVM_FALLTHROUGH; 175 case CK_SkylakeClient: 176 setFeatureEnabledImpl(Features, "xsavec", true); 177 setFeatureEnabledImpl(Features, "xsaves", true); 178 setFeatureEnabledImpl(Features, "mpx", true); 179 if (Kind != CK_SkylakeServer 180 && Kind != CK_Cascadelake) 181 // SKX/CLX inherits all SKL features, except SGX 182 setFeatureEnabledImpl(Features, "sgx", true); 183 setFeatureEnabledImpl(Features, "clflushopt", true); 184 setFeatureEnabledImpl(Features, "aes", true); 185 LLVM_FALLTHROUGH; 186 case CK_Broadwell: 187 setFeatureEnabledImpl(Features, "rdseed", true); 188 setFeatureEnabledImpl(Features, "adx", true); 189 setFeatureEnabledImpl(Features, "prfchw", true); 190 LLVM_FALLTHROUGH; 191 case CK_Haswell: 192 setFeatureEnabledImpl(Features, "avx2", true); 193 setFeatureEnabledImpl(Features, "lzcnt", true); 194 setFeatureEnabledImpl(Features, "bmi", true); 195 setFeatureEnabledImpl(Features, "bmi2", true); 196 setFeatureEnabledImpl(Features, "fma", true); 197 setFeatureEnabledImpl(Features, "invpcid", true); 198 setFeatureEnabledImpl(Features, "movbe", true); 199 LLVM_FALLTHROUGH; 200 case CK_IvyBridge: 201 setFeatureEnabledImpl(Features, "rdrnd", true); 202 setFeatureEnabledImpl(Features, "f16c", true); 203 setFeatureEnabledImpl(Features, "fsgsbase", true); 204 LLVM_FALLTHROUGH; 205 case CK_SandyBridge: 206 setFeatureEnabledImpl(Features, "avx", true); 207 setFeatureEnabledImpl(Features, "xsave", true); 208 setFeatureEnabledImpl(Features, "xsaveopt", true); 209 LLVM_FALLTHROUGH; 210 case CK_Westmere: 211 setFeatureEnabledImpl(Features, "pclmul", true); 212 LLVM_FALLTHROUGH; 213 case CK_Nehalem: 214 setFeatureEnabledImpl(Features, "sse4.2", true); 215 LLVM_FALLTHROUGH; 216 case CK_Penryn: 217 setFeatureEnabledImpl(Features, "sse4.1", true); 218 LLVM_FALLTHROUGH; 219 case CK_Core2: 220 setFeatureEnabledImpl(Features, "ssse3", true); 221 setFeatureEnabledImpl(Features, "sahf", true); 222 LLVM_FALLTHROUGH; 223 case CK_Nocona: 224 setFeatureEnabledImpl(Features, "cx16", true); 225 LLVM_FALLTHROUGH; 226 case CK_Yonah: 227 case CK_Prescott: 228 setFeatureEnabledImpl(Features, "sse3", true); 229 LLVM_FALLTHROUGH; 230 case CK_PentiumM: 231 case CK_Pentium4: 232 case CK_x86_64: 233 setFeatureEnabledImpl(Features, "sse2", true); 234 LLVM_FALLTHROUGH; 235 case CK_Pentium3: 236 case CK_C3_2: 237 setFeatureEnabledImpl(Features, "sse", true); 238 setFeatureEnabledImpl(Features, "fxsr", true); 239 break; 240 241 case CK_Tremont: 242 setFeatureEnabledImpl(Features, "cldemote", true); 243 setFeatureEnabledImpl(Features, "movdiri", true); 244 setFeatureEnabledImpl(Features, "movdir64b", true); 245 setFeatureEnabledImpl(Features, "gfni", true); 246 setFeatureEnabledImpl(Features, "waitpkg", true); 247 LLVM_FALLTHROUGH; 248 case CK_GoldmontPlus: 249 setFeatureEnabledImpl(Features, "ptwrite", true); 250 setFeatureEnabledImpl(Features, "rdpid", true); 251 setFeatureEnabledImpl(Features, "sgx", true); 252 LLVM_FALLTHROUGH; 253 case CK_Goldmont: 254 setFeatureEnabledImpl(Features, "sha", true); 255 setFeatureEnabledImpl(Features, "rdseed", true); 256 setFeatureEnabledImpl(Features, "xsave", true); 257 setFeatureEnabledImpl(Features, "xsaveopt", true); 258 setFeatureEnabledImpl(Features, "xsavec", true); 259 setFeatureEnabledImpl(Features, "xsaves", true); 260 setFeatureEnabledImpl(Features, "clflushopt", true); 261 setFeatureEnabledImpl(Features, "mpx", true); 262 setFeatureEnabledImpl(Features, "fsgsbase", true); 263 setFeatureEnabledImpl(Features, "aes", true); 264 LLVM_FALLTHROUGH; 265 case CK_Silvermont: 266 setFeatureEnabledImpl(Features, "rdrnd", true); 267 setFeatureEnabledImpl(Features, "pclmul", true); 268 setFeatureEnabledImpl(Features, "sse4.2", true); 269 setFeatureEnabledImpl(Features, "prfchw", true); 270 LLVM_FALLTHROUGH; 271 case CK_Bonnell: 272 setFeatureEnabledImpl(Features, "movbe", true); 273 setFeatureEnabledImpl(Features, "ssse3", true); 274 setFeatureEnabledImpl(Features, "fxsr", true); 275 setFeatureEnabledImpl(Features, "cx16", true); 276 setFeatureEnabledImpl(Features, "sahf", true); 277 break; 278 279 case CK_KNM: 280 // TODO: Add avx5124fmaps/avx5124vnniw. 281 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 282 LLVM_FALLTHROUGH; 283 case CK_KNL: 284 setFeatureEnabledImpl(Features, "avx512f", true); 285 setFeatureEnabledImpl(Features, "avx512cd", true); 286 setFeatureEnabledImpl(Features, "avx512er", true); 287 setFeatureEnabledImpl(Features, "avx512pf", true); 288 setFeatureEnabledImpl(Features, "prfchw", true); 289 setFeatureEnabledImpl(Features, "prefetchwt1", true); 290 setFeatureEnabledImpl(Features, "fxsr", true); 291 setFeatureEnabledImpl(Features, "rdseed", true); 292 setFeatureEnabledImpl(Features, "adx", true); 293 setFeatureEnabledImpl(Features, "lzcnt", true); 294 setFeatureEnabledImpl(Features, "bmi", true); 295 setFeatureEnabledImpl(Features, "bmi2", true); 296 setFeatureEnabledImpl(Features, "fma", true); 297 setFeatureEnabledImpl(Features, "rdrnd", true); 298 setFeatureEnabledImpl(Features, "f16c", true); 299 setFeatureEnabledImpl(Features, "fsgsbase", true); 300 setFeatureEnabledImpl(Features, "aes", true); 301 setFeatureEnabledImpl(Features, "pclmul", true); 302 setFeatureEnabledImpl(Features, "cx16", true); 303 setFeatureEnabledImpl(Features, "xsaveopt", true); 304 setFeatureEnabledImpl(Features, "xsave", true); 305 setFeatureEnabledImpl(Features, "movbe", true); 306 setFeatureEnabledImpl(Features, "sahf", true); 307 break; 308 309 case CK_K6_2: 310 case CK_K6_3: 311 case CK_WinChip2: 312 case CK_C3: 313 setFeatureEnabledImpl(Features, "3dnow", true); 314 break; 315 316 case CK_AMDFAM10: 317 setFeatureEnabledImpl(Features, "sse4a", true); 318 setFeatureEnabledImpl(Features, "lzcnt", true); 319 setFeatureEnabledImpl(Features, "popcnt", true); 320 setFeatureEnabledImpl(Features, "sahf", true); 321 LLVM_FALLTHROUGH; 322 case CK_K8SSE3: 323 setFeatureEnabledImpl(Features, "sse3", true); 324 LLVM_FALLTHROUGH; 325 case CK_K8: 326 setFeatureEnabledImpl(Features, "sse2", true); 327 LLVM_FALLTHROUGH; 328 case CK_AthlonXP: 329 setFeatureEnabledImpl(Features, "sse", true); 330 setFeatureEnabledImpl(Features, "fxsr", true); 331 LLVM_FALLTHROUGH; 332 case CK_Athlon: 333 case CK_Geode: 334 setFeatureEnabledImpl(Features, "3dnowa", true); 335 break; 336 337 case CK_BTVER2: 338 setFeatureEnabledImpl(Features, "avx", true); 339 setFeatureEnabledImpl(Features, "aes", true); 340 setFeatureEnabledImpl(Features, "pclmul", true); 341 setFeatureEnabledImpl(Features, "bmi", true); 342 setFeatureEnabledImpl(Features, "f16c", true); 343 setFeatureEnabledImpl(Features, "xsaveopt", true); 344 setFeatureEnabledImpl(Features, "movbe", true); 345 LLVM_FALLTHROUGH; 346 case CK_BTVER1: 347 setFeatureEnabledImpl(Features, "ssse3", true); 348 setFeatureEnabledImpl(Features, "sse4a", true); 349 setFeatureEnabledImpl(Features, "lzcnt", true); 350 setFeatureEnabledImpl(Features, "popcnt", true); 351 setFeatureEnabledImpl(Features, "prfchw", true); 352 setFeatureEnabledImpl(Features, "cx16", true); 353 setFeatureEnabledImpl(Features, "fxsr", true); 354 setFeatureEnabledImpl(Features, "sahf", true); 355 break; 356 357 case CK_ZNVER2: 358 setFeatureEnabledImpl(Features, "clwb", true); 359 setFeatureEnabledImpl(Features, "rdpid", true); 360 setFeatureEnabledImpl(Features, "wbnoinvd", true); 361 LLVM_FALLTHROUGH; 362 case CK_ZNVER1: 363 setFeatureEnabledImpl(Features, "adx", true); 364 setFeatureEnabledImpl(Features, "aes", true); 365 setFeatureEnabledImpl(Features, "avx2", true); 366 setFeatureEnabledImpl(Features, "bmi", true); 367 setFeatureEnabledImpl(Features, "bmi2", true); 368 setFeatureEnabledImpl(Features, "clflushopt", true); 369 setFeatureEnabledImpl(Features, "clzero", true); 370 setFeatureEnabledImpl(Features, "cx16", true); 371 setFeatureEnabledImpl(Features, "f16c", true); 372 setFeatureEnabledImpl(Features, "fma", true); 373 setFeatureEnabledImpl(Features, "fsgsbase", true); 374 setFeatureEnabledImpl(Features, "fxsr", true); 375 setFeatureEnabledImpl(Features, "lzcnt", true); 376 setFeatureEnabledImpl(Features, "mwaitx", true); 377 setFeatureEnabledImpl(Features, "movbe", true); 378 setFeatureEnabledImpl(Features, "pclmul", true); 379 setFeatureEnabledImpl(Features, "popcnt", true); 380 setFeatureEnabledImpl(Features, "prfchw", true); 381 setFeatureEnabledImpl(Features, "rdrnd", true); 382 setFeatureEnabledImpl(Features, "rdseed", true); 383 setFeatureEnabledImpl(Features, "sahf", true); 384 setFeatureEnabledImpl(Features, "sha", true); 385 setFeatureEnabledImpl(Features, "sse4a", true); 386 setFeatureEnabledImpl(Features, "xsave", true); 387 setFeatureEnabledImpl(Features, "xsavec", true); 388 setFeatureEnabledImpl(Features, "xsaveopt", true); 389 setFeatureEnabledImpl(Features, "xsaves", true); 390 break; 391 392 case CK_BDVER4: 393 setFeatureEnabledImpl(Features, "avx2", true); 394 setFeatureEnabledImpl(Features, "bmi2", true); 395 setFeatureEnabledImpl(Features, "mwaitx", true); 396 LLVM_FALLTHROUGH; 397 case CK_BDVER3: 398 setFeatureEnabledImpl(Features, "fsgsbase", true); 399 setFeatureEnabledImpl(Features, "xsaveopt", true); 400 LLVM_FALLTHROUGH; 401 case CK_BDVER2: 402 setFeatureEnabledImpl(Features, "bmi", true); 403 setFeatureEnabledImpl(Features, "fma", true); 404 setFeatureEnabledImpl(Features, "f16c", true); 405 setFeatureEnabledImpl(Features, "tbm", true); 406 LLVM_FALLTHROUGH; 407 case CK_BDVER1: 408 // xop implies avx, sse4a and fma4. 409 setFeatureEnabledImpl(Features, "xop", true); 410 setFeatureEnabledImpl(Features, "lwp", true); 411 setFeatureEnabledImpl(Features, "lzcnt", true); 412 setFeatureEnabledImpl(Features, "aes", true); 413 setFeatureEnabledImpl(Features, "pclmul", true); 414 setFeatureEnabledImpl(Features, "prfchw", true); 415 setFeatureEnabledImpl(Features, "cx16", true); 416 setFeatureEnabledImpl(Features, "fxsr", true); 417 setFeatureEnabledImpl(Features, "xsave", true); 418 setFeatureEnabledImpl(Features, "sahf", true); 419 break; 420 } 421 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 422 return false; 423 424 // Can't do this earlier because we need to be able to explicitly enable 425 // or disable these features and the things that they depend upon. 426 427 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 428 auto I = Features.find("sse4.2"); 429 if (I != Features.end() && I->getValue() && 430 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 431 Features["popcnt"] = true; 432 433 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 434 I = Features.find("3dnow"); 435 if (I != Features.end() && I->getValue() && 436 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 437 Features["prfchw"] = true; 438 439 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 440 // then enable MMX. 441 I = Features.find("sse"); 442 if (I != Features.end() && I->getValue() && 443 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 444 Features["mmx"] = true; 445 446 return true; 447 } 448 449 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 450 X86SSEEnum Level, bool Enabled) { 451 if (Enabled) { 452 switch (Level) { 453 case AVX512F: 454 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 455 LLVM_FALLTHROUGH; 456 case AVX2: 457 Features["avx2"] = true; 458 LLVM_FALLTHROUGH; 459 case AVX: 460 Features["avx"] = true; 461 Features["xsave"] = true; 462 LLVM_FALLTHROUGH; 463 case SSE42: 464 Features["sse4.2"] = true; 465 LLVM_FALLTHROUGH; 466 case SSE41: 467 Features["sse4.1"] = true; 468 LLVM_FALLTHROUGH; 469 case SSSE3: 470 Features["ssse3"] = true; 471 LLVM_FALLTHROUGH; 472 case SSE3: 473 Features["sse3"] = true; 474 LLVM_FALLTHROUGH; 475 case SSE2: 476 Features["sse2"] = true; 477 LLVM_FALLTHROUGH; 478 case SSE1: 479 Features["sse"] = true; 480 LLVM_FALLTHROUGH; 481 case NoSSE: 482 break; 483 } 484 return; 485 } 486 487 switch (Level) { 488 case NoSSE: 489 case SSE1: 490 Features["sse"] = false; 491 LLVM_FALLTHROUGH; 492 case SSE2: 493 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 494 Features["gfni"] = false; 495 LLVM_FALLTHROUGH; 496 case SSE3: 497 Features["sse3"] = false; 498 setXOPLevel(Features, NoXOP, false); 499 LLVM_FALLTHROUGH; 500 case SSSE3: 501 Features["ssse3"] = false; 502 LLVM_FALLTHROUGH; 503 case SSE41: 504 Features["sse4.1"] = false; 505 LLVM_FALLTHROUGH; 506 case SSE42: 507 Features["sse4.2"] = false; 508 LLVM_FALLTHROUGH; 509 case AVX: 510 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 511 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 512 setXOPLevel(Features, FMA4, false); 513 LLVM_FALLTHROUGH; 514 case AVX2: 515 Features["avx2"] = false; 516 LLVM_FALLTHROUGH; 517 case AVX512F: 518 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 519 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 520 Features["avx512vl"] = Features["avx512vbmi"] = 521 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 522 Features["avx512bitalg"] = Features["avx512vnni"] = 523 Features["avx512vbmi2"] = false; 524 break; 525 } 526 } 527 528 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 529 MMX3DNowEnum Level, bool Enabled) { 530 if (Enabled) { 531 switch (Level) { 532 case AMD3DNowAthlon: 533 Features["3dnowa"] = true; 534 LLVM_FALLTHROUGH; 535 case AMD3DNow: 536 Features["3dnow"] = true; 537 LLVM_FALLTHROUGH; 538 case MMX: 539 Features["mmx"] = true; 540 LLVM_FALLTHROUGH; 541 case NoMMX3DNow: 542 break; 543 } 544 return; 545 } 546 547 switch (Level) { 548 case NoMMX3DNow: 549 case MMX: 550 Features["mmx"] = false; 551 LLVM_FALLTHROUGH; 552 case AMD3DNow: 553 Features["3dnow"] = false; 554 LLVM_FALLTHROUGH; 555 case AMD3DNowAthlon: 556 Features["3dnowa"] = false; 557 break; 558 } 559 } 560 561 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 562 bool Enabled) { 563 if (Enabled) { 564 switch (Level) { 565 case XOP: 566 Features["xop"] = true; 567 LLVM_FALLTHROUGH; 568 case FMA4: 569 Features["fma4"] = true; 570 setSSELevel(Features, AVX, true); 571 LLVM_FALLTHROUGH; 572 case SSE4A: 573 Features["sse4a"] = true; 574 setSSELevel(Features, SSE3, true); 575 LLVM_FALLTHROUGH; 576 case NoXOP: 577 break; 578 } 579 return; 580 } 581 582 switch (Level) { 583 case NoXOP: 584 case SSE4A: 585 Features["sse4a"] = false; 586 LLVM_FALLTHROUGH; 587 case FMA4: 588 Features["fma4"] = false; 589 LLVM_FALLTHROUGH; 590 case XOP: 591 Features["xop"] = false; 592 break; 593 } 594 } 595 596 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 597 StringRef Name, bool Enabled) { 598 // This is a bit of a hack to deal with the sse4 target feature when used 599 // as part of the target attribute. We handle sse4 correctly everywhere 600 // else. See below for more information on how we handle the sse4 options. 601 if (Name != "sse4") 602 Features[Name] = Enabled; 603 604 if (Name == "mmx") { 605 setMMXLevel(Features, MMX, Enabled); 606 } else if (Name == "sse") { 607 setSSELevel(Features, SSE1, Enabled); 608 } else if (Name == "sse2") { 609 setSSELevel(Features, SSE2, Enabled); 610 } else if (Name == "sse3") { 611 setSSELevel(Features, SSE3, Enabled); 612 } else if (Name == "ssse3") { 613 setSSELevel(Features, SSSE3, Enabled); 614 } else if (Name == "sse4.2") { 615 setSSELevel(Features, SSE42, Enabled); 616 } else if (Name == "sse4.1") { 617 setSSELevel(Features, SSE41, Enabled); 618 } else if (Name == "3dnow") { 619 setMMXLevel(Features, AMD3DNow, Enabled); 620 } else if (Name == "3dnowa") { 621 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 622 } else if (Name == "aes") { 623 if (Enabled) 624 setSSELevel(Features, SSE2, Enabled); 625 else 626 Features["vaes"] = false; 627 } else if (Name == "vaes") { 628 if (Enabled) { 629 setSSELevel(Features, AVX, Enabled); 630 Features["aes"] = true; 631 } 632 } else if (Name == "pclmul") { 633 if (Enabled) 634 setSSELevel(Features, SSE2, Enabled); 635 else 636 Features["vpclmulqdq"] = false; 637 } else if (Name == "vpclmulqdq") { 638 if (Enabled) { 639 setSSELevel(Features, AVX, Enabled); 640 Features["pclmul"] = true; 641 } 642 } else if (Name == "gfni") { 643 if (Enabled) 644 setSSELevel(Features, SSE2, Enabled); 645 } else if (Name == "avx") { 646 setSSELevel(Features, AVX, Enabled); 647 } else if (Name == "avx2") { 648 setSSELevel(Features, AVX2, Enabled); 649 } else if (Name == "avx512f") { 650 setSSELevel(Features, AVX512F, Enabled); 651 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 652 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 653 Name == "avx512vbmi" || Name == "avx512ifma" || 654 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 655 Name == "avx512vnni" || Name == "avx512vbmi2") { 656 if (Enabled) 657 setSSELevel(Features, AVX512F, Enabled); 658 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 659 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 660 Features["avx512bw"] = true; 661 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 662 if (Name == "avx512bw" && !Enabled) 663 Features["avx512vbmi"] = Features["avx512vbmi2"] = 664 Features["avx512bitalg"] = false; 665 } else if (Name == "fma") { 666 if (Enabled) 667 setSSELevel(Features, AVX, Enabled); 668 else 669 setSSELevel(Features, AVX512F, Enabled); 670 } else if (Name == "fma4") { 671 setXOPLevel(Features, FMA4, Enabled); 672 } else if (Name == "xop") { 673 setXOPLevel(Features, XOP, Enabled); 674 } else if (Name == "sse4a") { 675 setXOPLevel(Features, SSE4A, Enabled); 676 } else if (Name == "f16c") { 677 if (Enabled) 678 setSSELevel(Features, AVX, Enabled); 679 else 680 setSSELevel(Features, AVX512F, Enabled); 681 } else if (Name == "sha") { 682 if (Enabled) 683 setSSELevel(Features, SSE2, Enabled); 684 } else if (Name == "sse4") { 685 // We can get here via the __target__ attribute since that's not controlled 686 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 687 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 688 // disabled. 689 if (Enabled) 690 setSSELevel(Features, SSE42, Enabled); 691 else 692 setSSELevel(Features, SSE41, Enabled); 693 } else if (Name == "xsave") { 694 if (!Enabled) 695 Features["xsaveopt"] = false; 696 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 697 if (Enabled) 698 Features["xsave"] = true; 699 } 700 } 701 702 /// handleTargetFeatures - Perform initialization based on the user 703 /// configured set of features. 704 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 705 DiagnosticsEngine &Diags) { 706 for (const auto &Feature : Features) { 707 if (Feature[0] != '+') 708 continue; 709 710 if (Feature == "+aes") { 711 HasAES = true; 712 } else if (Feature == "+vaes") { 713 HasVAES = true; 714 } else if (Feature == "+pclmul") { 715 HasPCLMUL = true; 716 } else if (Feature == "+vpclmulqdq") { 717 HasVPCLMULQDQ = true; 718 } else if (Feature == "+lzcnt") { 719 HasLZCNT = true; 720 } else if (Feature == "+rdrnd") { 721 HasRDRND = true; 722 } else if (Feature == "+fsgsbase") { 723 HasFSGSBASE = true; 724 } else if (Feature == "+bmi") { 725 HasBMI = true; 726 } else if (Feature == "+bmi2") { 727 HasBMI2 = true; 728 } else if (Feature == "+popcnt") { 729 HasPOPCNT = true; 730 } else if (Feature == "+rtm") { 731 HasRTM = true; 732 } else if (Feature == "+prfchw") { 733 HasPRFCHW = true; 734 } else if (Feature == "+rdseed") { 735 HasRDSEED = true; 736 } else if (Feature == "+adx") { 737 HasADX = true; 738 } else if (Feature == "+tbm") { 739 HasTBM = true; 740 } else if (Feature == "+lwp") { 741 HasLWP = true; 742 } else if (Feature == "+fma") { 743 HasFMA = true; 744 } else if (Feature == "+f16c") { 745 HasF16C = true; 746 } else if (Feature == "+gfni") { 747 HasGFNI = true; 748 } else if (Feature == "+avx512cd") { 749 HasAVX512CD = true; 750 } else if (Feature == "+avx512vpopcntdq") { 751 HasAVX512VPOPCNTDQ = true; 752 } else if (Feature == "+avx512vnni") { 753 HasAVX512VNNI = true; 754 } else if (Feature == "+avx512er") { 755 HasAVX512ER = true; 756 } else if (Feature == "+avx512pf") { 757 HasAVX512PF = true; 758 } else if (Feature == "+avx512dq") { 759 HasAVX512DQ = true; 760 } else if (Feature == "+avx512bitalg") { 761 HasAVX512BITALG = true; 762 } else if (Feature == "+avx512bw") { 763 HasAVX512BW = true; 764 } else if (Feature == "+avx512vl") { 765 HasAVX512VL = true; 766 } else if (Feature == "+avx512vbmi") { 767 HasAVX512VBMI = true; 768 } else if (Feature == "+avx512vbmi2") { 769 HasAVX512VBMI2 = true; 770 } else if (Feature == "+avx512ifma") { 771 HasAVX512IFMA = true; 772 } else if (Feature == "+sha") { 773 HasSHA = true; 774 } else if (Feature == "+mpx") { 775 HasMPX = true; 776 } else if (Feature == "+shstk") { 777 HasSHSTK = true; 778 } else if (Feature == "+movbe") { 779 HasMOVBE = true; 780 } else if (Feature == "+sgx") { 781 HasSGX = true; 782 } else if (Feature == "+cx8") { 783 HasCX8 = true; 784 } else if (Feature == "+cx16") { 785 HasCX16 = true; 786 } else if (Feature == "+fxsr") { 787 HasFXSR = true; 788 } else if (Feature == "+xsave") { 789 HasXSAVE = true; 790 } else if (Feature == "+xsaveopt") { 791 HasXSAVEOPT = true; 792 } else if (Feature == "+xsavec") { 793 HasXSAVEC = true; 794 } else if (Feature == "+xsaves") { 795 HasXSAVES = true; 796 } else if (Feature == "+mwaitx") { 797 HasMWAITX = true; 798 } else if (Feature == "+pku") { 799 HasPKU = true; 800 } else if (Feature == "+clflushopt") { 801 HasCLFLUSHOPT = true; 802 } else if (Feature == "+clwb") { 803 HasCLWB = true; 804 } else if (Feature == "+wbnoinvd") { 805 HasWBNOINVD = true; 806 } else if (Feature == "+prefetchwt1") { 807 HasPREFETCHWT1 = true; 808 } else if (Feature == "+clzero") { 809 HasCLZERO = true; 810 } else if (Feature == "+cldemote") { 811 HasCLDEMOTE = true; 812 } else if (Feature == "+rdpid") { 813 HasRDPID = true; 814 } else if (Feature == "+retpoline-external-thunk") { 815 HasRetpolineExternalThunk = true; 816 } else if (Feature == "+sahf") { 817 HasLAHFSAHF = true; 818 } else if (Feature == "+waitpkg") { 819 HasWAITPKG = true; 820 } else if (Feature == "+movdiri") { 821 HasMOVDIRI = true; 822 } else if (Feature == "+movdir64b") { 823 HasMOVDIR64B = true; 824 } else if (Feature == "+pconfig") { 825 HasPCONFIG = true; 826 } else if (Feature == "+ptwrite") { 827 HasPTWRITE = true; 828 } else if (Feature == "+invpcid") { 829 HasINVPCID = true; 830 } 831 832 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 833 .Case("+avx512f", AVX512F) 834 .Case("+avx2", AVX2) 835 .Case("+avx", AVX) 836 .Case("+sse4.2", SSE42) 837 .Case("+sse4.1", SSE41) 838 .Case("+ssse3", SSSE3) 839 .Case("+sse3", SSE3) 840 .Case("+sse2", SSE2) 841 .Case("+sse", SSE1) 842 .Default(NoSSE); 843 SSELevel = std::max(SSELevel, Level); 844 845 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 846 .Case("+3dnowa", AMD3DNowAthlon) 847 .Case("+3dnow", AMD3DNow) 848 .Case("+mmx", MMX) 849 .Default(NoMMX3DNow); 850 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 851 852 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 853 .Case("+xop", XOP) 854 .Case("+fma4", FMA4) 855 .Case("+sse4a", SSE4A) 856 .Default(NoXOP); 857 XOPLevel = std::max(XOPLevel, XLevel); 858 } 859 860 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 861 // matches the selected sse level. 862 if ((FPMath == FP_SSE && SSELevel < SSE1) || 863 (FPMath == FP_387 && SSELevel >= SSE1)) { 864 Diags.Report(diag::err_target_unsupported_fpmath) 865 << (FPMath == FP_SSE ? "sse" : "387"); 866 return false; 867 } 868 869 SimdDefaultAlign = 870 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 871 return true; 872 } 873 874 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 875 /// definitions for this particular subtarget. 876 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 877 MacroBuilder &Builder) const { 878 // Inline assembly supports X86 flag outputs. 879 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 880 881 std::string CodeModel = getTargetOpts().CodeModel; 882 if (CodeModel == "default") 883 CodeModel = "small"; 884 Builder.defineMacro("__code_model_" + CodeModel + "_"); 885 886 // Target identification. 887 if (getTriple().getArch() == llvm::Triple::x86_64) { 888 Builder.defineMacro("__amd64__"); 889 Builder.defineMacro("__amd64"); 890 Builder.defineMacro("__x86_64"); 891 Builder.defineMacro("__x86_64__"); 892 if (getTriple().getArchName() == "x86_64h") { 893 Builder.defineMacro("__x86_64h"); 894 Builder.defineMacro("__x86_64h__"); 895 } 896 } else { 897 DefineStd(Builder, "i386", Opts); 898 } 899 900 // Subtarget options. 901 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 902 // truly should be based on -mtune options. 903 switch (CPU) { 904 case CK_Generic: 905 break; 906 case CK_i386: 907 // The rest are coming from the i386 define above. 908 Builder.defineMacro("__tune_i386__"); 909 break; 910 case CK_i486: 911 case CK_WinChipC6: 912 case CK_WinChip2: 913 case CK_C3: 914 defineCPUMacros(Builder, "i486"); 915 break; 916 case CK_PentiumMMX: 917 Builder.defineMacro("__pentium_mmx__"); 918 Builder.defineMacro("__tune_pentium_mmx__"); 919 LLVM_FALLTHROUGH; 920 case CK_i586: 921 case CK_Pentium: 922 defineCPUMacros(Builder, "i586"); 923 defineCPUMacros(Builder, "pentium"); 924 break; 925 case CK_Pentium3: 926 case CK_PentiumM: 927 Builder.defineMacro("__tune_pentium3__"); 928 LLVM_FALLTHROUGH; 929 case CK_Pentium2: 930 case CK_C3_2: 931 Builder.defineMacro("__tune_pentium2__"); 932 LLVM_FALLTHROUGH; 933 case CK_PentiumPro: 934 case CK_i686: 935 defineCPUMacros(Builder, "i686"); 936 defineCPUMacros(Builder, "pentiumpro"); 937 break; 938 case CK_Pentium4: 939 defineCPUMacros(Builder, "pentium4"); 940 break; 941 case CK_Yonah: 942 case CK_Prescott: 943 case CK_Nocona: 944 defineCPUMacros(Builder, "nocona"); 945 break; 946 case CK_Core2: 947 case CK_Penryn: 948 defineCPUMacros(Builder, "core2"); 949 break; 950 case CK_Bonnell: 951 defineCPUMacros(Builder, "atom"); 952 break; 953 case CK_Silvermont: 954 defineCPUMacros(Builder, "slm"); 955 break; 956 case CK_Goldmont: 957 defineCPUMacros(Builder, "goldmont"); 958 break; 959 case CK_GoldmontPlus: 960 defineCPUMacros(Builder, "goldmont_plus"); 961 break; 962 case CK_Tremont: 963 defineCPUMacros(Builder, "tremont"); 964 break; 965 case CK_Nehalem: 966 case CK_Westmere: 967 case CK_SandyBridge: 968 case CK_IvyBridge: 969 case CK_Haswell: 970 case CK_Broadwell: 971 case CK_SkylakeClient: 972 case CK_SkylakeServer: 973 case CK_Cascadelake: 974 case CK_Cannonlake: 975 case CK_IcelakeClient: 976 case CK_IcelakeServer: 977 // FIXME: Historically, we defined this legacy name, it would be nice to 978 // remove it at some point. We've never exposed fine-grained names for 979 // recent primary x86 CPUs, and we should keep it that way. 980 defineCPUMacros(Builder, "corei7"); 981 break; 982 case CK_KNL: 983 defineCPUMacros(Builder, "knl"); 984 break; 985 case CK_KNM: 986 break; 987 case CK_Lakemont: 988 defineCPUMacros(Builder, "i586", /*Tuning*/false); 989 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 990 Builder.defineMacro("__tune_lakemont__"); 991 break; 992 case CK_K6_2: 993 Builder.defineMacro("__k6_2__"); 994 Builder.defineMacro("__tune_k6_2__"); 995 LLVM_FALLTHROUGH; 996 case CK_K6_3: 997 if (CPU != CK_K6_2) { // In case of fallthrough 998 // FIXME: GCC may be enabling these in cases where some other k6 999 // architecture is specified but -m3dnow is explicitly provided. The 1000 // exact semantics need to be determined and emulated here. 1001 Builder.defineMacro("__k6_3__"); 1002 Builder.defineMacro("__tune_k6_3__"); 1003 } 1004 LLVM_FALLTHROUGH; 1005 case CK_K6: 1006 defineCPUMacros(Builder, "k6"); 1007 break; 1008 case CK_Athlon: 1009 case CK_AthlonXP: 1010 defineCPUMacros(Builder, "athlon"); 1011 if (SSELevel != NoSSE) { 1012 Builder.defineMacro("__athlon_sse__"); 1013 Builder.defineMacro("__tune_athlon_sse__"); 1014 } 1015 break; 1016 case CK_K8: 1017 case CK_K8SSE3: 1018 case CK_x86_64: 1019 defineCPUMacros(Builder, "k8"); 1020 break; 1021 case CK_AMDFAM10: 1022 defineCPUMacros(Builder, "amdfam10"); 1023 break; 1024 case CK_BTVER1: 1025 defineCPUMacros(Builder, "btver1"); 1026 break; 1027 case CK_BTVER2: 1028 defineCPUMacros(Builder, "btver2"); 1029 break; 1030 case CK_BDVER1: 1031 defineCPUMacros(Builder, "bdver1"); 1032 break; 1033 case CK_BDVER2: 1034 defineCPUMacros(Builder, "bdver2"); 1035 break; 1036 case CK_BDVER3: 1037 defineCPUMacros(Builder, "bdver3"); 1038 break; 1039 case CK_BDVER4: 1040 defineCPUMacros(Builder, "bdver4"); 1041 break; 1042 case CK_ZNVER1: 1043 defineCPUMacros(Builder, "znver1"); 1044 break; 1045 case CK_ZNVER2: 1046 defineCPUMacros(Builder, "znver2"); 1047 break; 1048 case CK_Geode: 1049 defineCPUMacros(Builder, "geode"); 1050 break; 1051 } 1052 1053 // Target properties. 1054 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1055 1056 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1057 // functions in glibc header files that use FP Stack inline asm which the 1058 // backend can't deal with (PR879). 1059 Builder.defineMacro("__NO_MATH_INLINES"); 1060 1061 if (HasAES) 1062 Builder.defineMacro("__AES__"); 1063 1064 if (HasVAES) 1065 Builder.defineMacro("__VAES__"); 1066 1067 if (HasPCLMUL) 1068 Builder.defineMacro("__PCLMUL__"); 1069 1070 if (HasVPCLMULQDQ) 1071 Builder.defineMacro("__VPCLMULQDQ__"); 1072 1073 if (HasLZCNT) 1074 Builder.defineMacro("__LZCNT__"); 1075 1076 if (HasRDRND) 1077 Builder.defineMacro("__RDRND__"); 1078 1079 if (HasFSGSBASE) 1080 Builder.defineMacro("__FSGSBASE__"); 1081 1082 if (HasBMI) 1083 Builder.defineMacro("__BMI__"); 1084 1085 if (HasBMI2) 1086 Builder.defineMacro("__BMI2__"); 1087 1088 if (HasPOPCNT) 1089 Builder.defineMacro("__POPCNT__"); 1090 1091 if (HasRTM) 1092 Builder.defineMacro("__RTM__"); 1093 1094 if (HasPRFCHW) 1095 Builder.defineMacro("__PRFCHW__"); 1096 1097 if (HasRDSEED) 1098 Builder.defineMacro("__RDSEED__"); 1099 1100 if (HasADX) 1101 Builder.defineMacro("__ADX__"); 1102 1103 if (HasTBM) 1104 Builder.defineMacro("__TBM__"); 1105 1106 if (HasLWP) 1107 Builder.defineMacro("__LWP__"); 1108 1109 if (HasMWAITX) 1110 Builder.defineMacro("__MWAITX__"); 1111 1112 if (HasMOVBE) 1113 Builder.defineMacro("__MOVBE__"); 1114 1115 switch (XOPLevel) { 1116 case XOP: 1117 Builder.defineMacro("__XOP__"); 1118 LLVM_FALLTHROUGH; 1119 case FMA4: 1120 Builder.defineMacro("__FMA4__"); 1121 LLVM_FALLTHROUGH; 1122 case SSE4A: 1123 Builder.defineMacro("__SSE4A__"); 1124 LLVM_FALLTHROUGH; 1125 case NoXOP: 1126 break; 1127 } 1128 1129 if (HasFMA) 1130 Builder.defineMacro("__FMA__"); 1131 1132 if (HasF16C) 1133 Builder.defineMacro("__F16C__"); 1134 1135 if (HasGFNI) 1136 Builder.defineMacro("__GFNI__"); 1137 1138 if (HasAVX512CD) 1139 Builder.defineMacro("__AVX512CD__"); 1140 if (HasAVX512VPOPCNTDQ) 1141 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1142 if (HasAVX512VNNI) 1143 Builder.defineMacro("__AVX512VNNI__"); 1144 if (HasAVX512ER) 1145 Builder.defineMacro("__AVX512ER__"); 1146 if (HasAVX512PF) 1147 Builder.defineMacro("__AVX512PF__"); 1148 if (HasAVX512DQ) 1149 Builder.defineMacro("__AVX512DQ__"); 1150 if (HasAVX512BITALG) 1151 Builder.defineMacro("__AVX512BITALG__"); 1152 if (HasAVX512BW) 1153 Builder.defineMacro("__AVX512BW__"); 1154 if (HasAVX512VL) 1155 Builder.defineMacro("__AVX512VL__"); 1156 if (HasAVX512VBMI) 1157 Builder.defineMacro("__AVX512VBMI__"); 1158 if (HasAVX512VBMI2) 1159 Builder.defineMacro("__AVX512VBMI2__"); 1160 if (HasAVX512IFMA) 1161 Builder.defineMacro("__AVX512IFMA__"); 1162 1163 if (HasSHA) 1164 Builder.defineMacro("__SHA__"); 1165 1166 if (HasFXSR) 1167 Builder.defineMacro("__FXSR__"); 1168 if (HasXSAVE) 1169 Builder.defineMacro("__XSAVE__"); 1170 if (HasXSAVEOPT) 1171 Builder.defineMacro("__XSAVEOPT__"); 1172 if (HasXSAVEC) 1173 Builder.defineMacro("__XSAVEC__"); 1174 if (HasXSAVES) 1175 Builder.defineMacro("__XSAVES__"); 1176 if (HasPKU) 1177 Builder.defineMacro("__PKU__"); 1178 if (HasCLFLUSHOPT) 1179 Builder.defineMacro("__CLFLUSHOPT__"); 1180 if (HasCLWB) 1181 Builder.defineMacro("__CLWB__"); 1182 if (HasWBNOINVD) 1183 Builder.defineMacro("__WBNOINVD__"); 1184 if (HasMPX) 1185 Builder.defineMacro("__MPX__"); 1186 if (HasSHSTK) 1187 Builder.defineMacro("__SHSTK__"); 1188 if (HasSGX) 1189 Builder.defineMacro("__SGX__"); 1190 if (HasPREFETCHWT1) 1191 Builder.defineMacro("__PREFETCHWT1__"); 1192 if (HasCLZERO) 1193 Builder.defineMacro("__CLZERO__"); 1194 if (HasRDPID) 1195 Builder.defineMacro("__RDPID__"); 1196 if (HasCLDEMOTE) 1197 Builder.defineMacro("__CLDEMOTE__"); 1198 if (HasWAITPKG) 1199 Builder.defineMacro("__WAITPKG__"); 1200 if (HasMOVDIRI) 1201 Builder.defineMacro("__MOVDIRI__"); 1202 if (HasMOVDIR64B) 1203 Builder.defineMacro("__MOVDIR64B__"); 1204 if (HasPCONFIG) 1205 Builder.defineMacro("__PCONFIG__"); 1206 if (HasPTWRITE) 1207 Builder.defineMacro("__PTWRITE__"); 1208 if (HasINVPCID) 1209 Builder.defineMacro("__INVPCID__"); 1210 1211 // Each case falls through to the previous one here. 1212 switch (SSELevel) { 1213 case AVX512F: 1214 Builder.defineMacro("__AVX512F__"); 1215 LLVM_FALLTHROUGH; 1216 case AVX2: 1217 Builder.defineMacro("__AVX2__"); 1218 LLVM_FALLTHROUGH; 1219 case AVX: 1220 Builder.defineMacro("__AVX__"); 1221 LLVM_FALLTHROUGH; 1222 case SSE42: 1223 Builder.defineMacro("__SSE4_2__"); 1224 LLVM_FALLTHROUGH; 1225 case SSE41: 1226 Builder.defineMacro("__SSE4_1__"); 1227 LLVM_FALLTHROUGH; 1228 case SSSE3: 1229 Builder.defineMacro("__SSSE3__"); 1230 LLVM_FALLTHROUGH; 1231 case SSE3: 1232 Builder.defineMacro("__SSE3__"); 1233 LLVM_FALLTHROUGH; 1234 case SSE2: 1235 Builder.defineMacro("__SSE2__"); 1236 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1237 LLVM_FALLTHROUGH; 1238 case SSE1: 1239 Builder.defineMacro("__SSE__"); 1240 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1241 LLVM_FALLTHROUGH; 1242 case NoSSE: 1243 break; 1244 } 1245 1246 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1247 switch (SSELevel) { 1248 case AVX512F: 1249 case AVX2: 1250 case AVX: 1251 case SSE42: 1252 case SSE41: 1253 case SSSE3: 1254 case SSE3: 1255 case SSE2: 1256 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1257 break; 1258 case SSE1: 1259 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1260 break; 1261 default: 1262 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1263 break; 1264 } 1265 } 1266 1267 // Each case falls through to the previous one here. 1268 switch (MMX3DNowLevel) { 1269 case AMD3DNowAthlon: 1270 Builder.defineMacro("__3dNOW_A__"); 1271 LLVM_FALLTHROUGH; 1272 case AMD3DNow: 1273 Builder.defineMacro("__3dNOW__"); 1274 LLVM_FALLTHROUGH; 1275 case MMX: 1276 Builder.defineMacro("__MMX__"); 1277 LLVM_FALLTHROUGH; 1278 case NoMMX3DNow: 1279 break; 1280 } 1281 1282 if (CPU >= CK_i486 || CPU == CK_Generic) { 1283 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1284 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1285 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1286 } 1287 if (HasCX8) 1288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1289 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1291 1292 if (HasFloat128) 1293 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1294 } 1295 1296 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1297 return llvm::StringSwitch<bool>(Name) 1298 .Case("3dnow", true) 1299 .Case("3dnowa", true) 1300 .Case("adx", true) 1301 .Case("aes", true) 1302 .Case("avx", true) 1303 .Case("avx2", true) 1304 .Case("avx512f", true) 1305 .Case("avx512cd", true) 1306 .Case("avx512vpopcntdq", true) 1307 .Case("avx512vnni", true) 1308 .Case("avx512er", true) 1309 .Case("avx512pf", true) 1310 .Case("avx512dq", true) 1311 .Case("avx512bitalg", true) 1312 .Case("avx512bw", true) 1313 .Case("avx512vl", true) 1314 .Case("avx512vbmi", true) 1315 .Case("avx512vbmi2", true) 1316 .Case("avx512ifma", true) 1317 .Case("bmi", true) 1318 .Case("bmi2", true) 1319 .Case("cldemote", true) 1320 .Case("clflushopt", true) 1321 .Case("clwb", true) 1322 .Case("clzero", true) 1323 .Case("cx16", true) 1324 .Case("f16c", true) 1325 .Case("fma", true) 1326 .Case("fma4", true) 1327 .Case("fsgsbase", true) 1328 .Case("fxsr", true) 1329 .Case("gfni", true) 1330 .Case("invpcid", true) 1331 .Case("lwp", true) 1332 .Case("lzcnt", true) 1333 .Case("mmx", true) 1334 .Case("movbe", true) 1335 .Case("movdiri", true) 1336 .Case("movdir64b", true) 1337 .Case("mpx", true) 1338 .Case("mwaitx", true) 1339 .Case("pclmul", true) 1340 .Case("pconfig", true) 1341 .Case("pku", true) 1342 .Case("popcnt", true) 1343 .Case("prefetchwt1", true) 1344 .Case("prfchw", true) 1345 .Case("ptwrite", true) 1346 .Case("rdpid", true) 1347 .Case("rdrnd", true) 1348 .Case("rdseed", true) 1349 .Case("rtm", true) 1350 .Case("sahf", true) 1351 .Case("sgx", true) 1352 .Case("sha", true) 1353 .Case("shstk", true) 1354 .Case("sse", true) 1355 .Case("sse2", true) 1356 .Case("sse3", true) 1357 .Case("ssse3", true) 1358 .Case("sse4", true) 1359 .Case("sse4.1", true) 1360 .Case("sse4.2", true) 1361 .Case("sse4a", true) 1362 .Case("tbm", true) 1363 .Case("vaes", true) 1364 .Case("vpclmulqdq", true) 1365 .Case("wbnoinvd", true) 1366 .Case("waitpkg", true) 1367 .Case("x87", true) 1368 .Case("xop", true) 1369 .Case("xsave", true) 1370 .Case("xsavec", true) 1371 .Case("xsaves", true) 1372 .Case("xsaveopt", true) 1373 .Default(false); 1374 } 1375 1376 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1377 return llvm::StringSwitch<bool>(Feature) 1378 .Case("adx", HasADX) 1379 .Case("aes", HasAES) 1380 .Case("avx", SSELevel >= AVX) 1381 .Case("avx2", SSELevel >= AVX2) 1382 .Case("avx512f", SSELevel >= AVX512F) 1383 .Case("avx512cd", HasAVX512CD) 1384 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1385 .Case("avx512vnni", HasAVX512VNNI) 1386 .Case("avx512er", HasAVX512ER) 1387 .Case("avx512pf", HasAVX512PF) 1388 .Case("avx512dq", HasAVX512DQ) 1389 .Case("avx512bitalg", HasAVX512BITALG) 1390 .Case("avx512bw", HasAVX512BW) 1391 .Case("avx512vl", HasAVX512VL) 1392 .Case("avx512vbmi", HasAVX512VBMI) 1393 .Case("avx512vbmi2", HasAVX512VBMI2) 1394 .Case("avx512ifma", HasAVX512IFMA) 1395 .Case("bmi", HasBMI) 1396 .Case("bmi2", HasBMI2) 1397 .Case("cldemote", HasCLDEMOTE) 1398 .Case("clflushopt", HasCLFLUSHOPT) 1399 .Case("clwb", HasCLWB) 1400 .Case("clzero", HasCLZERO) 1401 .Case("cx8", HasCX8) 1402 .Case("cx16", HasCX16) 1403 .Case("f16c", HasF16C) 1404 .Case("fma", HasFMA) 1405 .Case("fma4", XOPLevel >= FMA4) 1406 .Case("fsgsbase", HasFSGSBASE) 1407 .Case("fxsr", HasFXSR) 1408 .Case("gfni", HasGFNI) 1409 .Case("invpcid", HasINVPCID) 1410 .Case("lwp", HasLWP) 1411 .Case("lzcnt", HasLZCNT) 1412 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1413 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1414 .Case("mmx", MMX3DNowLevel >= MMX) 1415 .Case("movbe", HasMOVBE) 1416 .Case("movdiri", HasMOVDIRI) 1417 .Case("movdir64b", HasMOVDIR64B) 1418 .Case("mpx", HasMPX) 1419 .Case("mwaitx", HasMWAITX) 1420 .Case("pclmul", HasPCLMUL) 1421 .Case("pconfig", HasPCONFIG) 1422 .Case("pku", HasPKU) 1423 .Case("popcnt", HasPOPCNT) 1424 .Case("prefetchwt1", HasPREFETCHWT1) 1425 .Case("prfchw", HasPRFCHW) 1426 .Case("ptwrite", HasPTWRITE) 1427 .Case("rdpid", HasRDPID) 1428 .Case("rdrnd", HasRDRND) 1429 .Case("rdseed", HasRDSEED) 1430 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1431 .Case("rtm", HasRTM) 1432 .Case("sahf", HasLAHFSAHF) 1433 .Case("sgx", HasSGX) 1434 .Case("sha", HasSHA) 1435 .Case("shstk", HasSHSTK) 1436 .Case("sse", SSELevel >= SSE1) 1437 .Case("sse2", SSELevel >= SSE2) 1438 .Case("sse3", SSELevel >= SSE3) 1439 .Case("ssse3", SSELevel >= SSSE3) 1440 .Case("sse4.1", SSELevel >= SSE41) 1441 .Case("sse4.2", SSELevel >= SSE42) 1442 .Case("sse4a", XOPLevel >= SSE4A) 1443 .Case("tbm", HasTBM) 1444 .Case("vaes", HasVAES) 1445 .Case("vpclmulqdq", HasVPCLMULQDQ) 1446 .Case("wbnoinvd", HasWBNOINVD) 1447 .Case("waitpkg", HasWAITPKG) 1448 .Case("x86", true) 1449 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1450 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1451 .Case("xop", XOPLevel >= XOP) 1452 .Case("xsave", HasXSAVE) 1453 .Case("xsavec", HasXSAVEC) 1454 .Case("xsaves", HasXSAVES) 1455 .Case("xsaveopt", HasXSAVEOPT) 1456 .Default(false); 1457 } 1458 1459 // We can't use a generic validation scheme for the features accepted here 1460 // versus subtarget features accepted in the target attribute because the 1461 // bitfield structure that's initialized in the runtime only supports the 1462 // below currently rather than the full range of subtarget features. (See 1463 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1464 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1465 return llvm::StringSwitch<bool>(FeatureStr) 1466 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1467 #include "llvm/Support/X86TargetParser.def" 1468 .Default(false); 1469 } 1470 1471 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1472 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1473 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1474 #include "llvm/Support/X86TargetParser.def" 1475 ; 1476 // Note, this function should only be used after ensuring the value is 1477 // correct, so it asserts if the value is out of range. 1478 } 1479 1480 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1481 enum class FeatPriority { 1482 #define FEATURE(FEAT) FEAT, 1483 #include "clang/Basic/X86Target.def" 1484 }; 1485 switch (Feat) { 1486 #define FEATURE(FEAT) \ 1487 case llvm::X86::FEAT: \ 1488 return static_cast<unsigned>(FeatPriority::FEAT); 1489 #include "clang/Basic/X86Target.def" 1490 default: 1491 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1492 } 1493 } 1494 1495 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1496 // Valid CPUs have a 'key feature' that compares just better than its key 1497 // feature. 1498 CPUKind Kind = getCPUKind(Name); 1499 if (Kind != CK_Generic) { 1500 switch (Kind) { 1501 default: 1502 llvm_unreachable( 1503 "CPU Type without a key feature used in 'target' attribute"); 1504 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1505 case CK_##ENUM: \ 1506 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1507 #include "clang/Basic/X86Target.def" 1508 } 1509 } 1510 1511 // Now we know we have a feature, so get its priority and shift it a few so 1512 // that we have sufficient room for the CPUs (above). 1513 return getFeaturePriority(getFeature(Name)) << 1; 1514 } 1515 1516 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1517 return llvm::StringSwitch<bool>(Name) 1518 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1519 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1520 #include "clang/Basic/X86Target.def" 1521 .Default(false); 1522 } 1523 1524 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1525 return llvm::StringSwitch<StringRef>(Name) 1526 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1527 #include "clang/Basic/X86Target.def" 1528 .Default(Name); 1529 } 1530 1531 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1532 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1533 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1534 #include "clang/Basic/X86Target.def" 1535 .Default(0); 1536 } 1537 1538 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1539 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1540 StringRef WholeList = 1541 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1542 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1543 #include "clang/Basic/X86Target.def" 1544 .Default(""); 1545 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1546 } 1547 1548 // We can't use a generic validation scheme for the cpus accepted here 1549 // versus subtarget cpus accepted in the target attribute because the 1550 // variables intitialized by the runtime only support the below currently 1551 // rather than the full range of cpus. 1552 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1553 return llvm::StringSwitch<bool>(FeatureStr) 1554 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1555 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1556 .Cases(STR, ALIAS, true) 1557 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1558 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1559 #include "llvm/Support/X86TargetParser.def" 1560 .Default(false); 1561 } 1562 1563 static unsigned matchAsmCCConstraint(const char *&Name) { 1564 auto RV = llvm::StringSwitch<unsigned>(Name) 1565 .Case("@cca", 4) 1566 .Case("@ccae", 5) 1567 .Case("@ccb", 4) 1568 .Case("@ccbe", 5) 1569 .Case("@ccc", 4) 1570 .Case("@cce", 4) 1571 .Case("@ccz", 4) 1572 .Case("@ccg", 4) 1573 .Case("@ccge", 5) 1574 .Case("@ccl", 4) 1575 .Case("@ccle", 5) 1576 .Case("@ccna", 5) 1577 .Case("@ccnae", 6) 1578 .Case("@ccnb", 5) 1579 .Case("@ccnbe", 6) 1580 .Case("@ccnc", 5) 1581 .Case("@ccne", 5) 1582 .Case("@ccnz", 5) 1583 .Case("@ccng", 5) 1584 .Case("@ccnge", 6) 1585 .Case("@ccnl", 5) 1586 .Case("@ccnle", 6) 1587 .Case("@ccno", 5) 1588 .Case("@ccnp", 5) 1589 .Case("@ccns", 5) 1590 .Case("@cco", 4) 1591 .Case("@ccp", 4) 1592 .Case("@ccs", 4) 1593 .Default(0); 1594 return RV; 1595 } 1596 1597 bool X86TargetInfo::validateAsmConstraint( 1598 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1599 switch (*Name) { 1600 default: 1601 return false; 1602 // Constant constraints. 1603 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1604 // instructions. 1605 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1606 // x86_64 instructions. 1607 case 's': 1608 Info.setRequiresImmediate(); 1609 return true; 1610 case 'I': 1611 Info.setRequiresImmediate(0, 31); 1612 return true; 1613 case 'J': 1614 Info.setRequiresImmediate(0, 63); 1615 return true; 1616 case 'K': 1617 Info.setRequiresImmediate(-128, 127); 1618 return true; 1619 case 'L': 1620 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1621 return true; 1622 case 'M': 1623 Info.setRequiresImmediate(0, 3); 1624 return true; 1625 case 'N': 1626 Info.setRequiresImmediate(0, 255); 1627 return true; 1628 case 'O': 1629 Info.setRequiresImmediate(0, 127); 1630 return true; 1631 // Register constraints. 1632 case 'Y': // 'Y' is the first character for several 2-character constraints. 1633 // Shift the pointer to the second character of the constraint. 1634 Name++; 1635 switch (*Name) { 1636 default: 1637 return false; 1638 case 'z': 1639 case '0': // First SSE register. 1640 case '2': 1641 case 't': // Any SSE register, when SSE2 is enabled. 1642 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1643 case 'm': // Any MMX register, when inter-unit moves enabled. 1644 case 'k': // AVX512 arch mask registers: k1-k7. 1645 Info.setAllowsRegister(); 1646 return true; 1647 } 1648 case 'f': // Any x87 floating point stack register. 1649 // Constraint 'f' cannot be used for output operands. 1650 if (Info.ConstraintStr[0] == '=') 1651 return false; 1652 Info.setAllowsRegister(); 1653 return true; 1654 case 'a': // eax. 1655 case 'b': // ebx. 1656 case 'c': // ecx. 1657 case 'd': // edx. 1658 case 'S': // esi. 1659 case 'D': // edi. 1660 case 'A': // edx:eax. 1661 case 't': // Top of floating point stack. 1662 case 'u': // Second from top of floating point stack. 1663 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1664 case 'y': // Any MMX register. 1665 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1666 case 'x': // Any SSE register. 1667 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1668 // for intermideate k reg operations). 1669 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1670 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1671 case 'l': // "Index" registers: any general register that can be used as an 1672 // index in a base+index memory access. 1673 Info.setAllowsRegister(); 1674 return true; 1675 // Floating point constant constraints. 1676 case 'C': // SSE floating point constant. 1677 case 'G': // x87 floating point constant. 1678 return true; 1679 case '@': 1680 // CC condition changes. 1681 if (auto Len = matchAsmCCConstraint(Name)) { 1682 Name += Len - 1; 1683 Info.setAllowsRegister(); 1684 return true; 1685 } 1686 return false; 1687 } 1688 } 1689 1690 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1691 unsigned Size) const { 1692 // Strip off constraint modifiers. 1693 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1694 Constraint = Constraint.substr(1); 1695 1696 return validateOperandSize(Constraint, Size); 1697 } 1698 1699 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1700 unsigned Size) const { 1701 return validateOperandSize(Constraint, Size); 1702 } 1703 1704 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1705 unsigned Size) const { 1706 switch (Constraint[0]) { 1707 default: 1708 break; 1709 case 'k': 1710 // Registers k0-k7 (AVX512) size limit is 64 bit. 1711 case 'y': 1712 return Size <= 64; 1713 case 'f': 1714 case 't': 1715 case 'u': 1716 return Size <= 128; 1717 case 'Y': 1718 // 'Y' is the first character for several 2-character constraints. 1719 switch (Constraint[1]) { 1720 default: 1721 return false; 1722 case 'm': 1723 // 'Ym' is synonymous with 'y'. 1724 case 'k': 1725 return Size <= 64; 1726 case 'z': 1727 case '0': 1728 // XMM0 1729 if (SSELevel >= SSE1) 1730 return Size <= 128U; 1731 return false; 1732 case 'i': 1733 case 't': 1734 case '2': 1735 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1736 if (SSELevel < SSE2) 1737 return false; 1738 break; 1739 } 1740 LLVM_FALLTHROUGH; 1741 case 'v': 1742 case 'x': 1743 if (SSELevel >= AVX512F) 1744 // 512-bit zmm registers can be used if target supports AVX512F. 1745 return Size <= 512U; 1746 else if (SSELevel >= AVX) 1747 // 256-bit ymm registers can be used if target supports AVX. 1748 return Size <= 256U; 1749 return Size <= 128U; 1750 1751 } 1752 1753 return true; 1754 } 1755 1756 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1757 switch (*Constraint) { 1758 case '@': 1759 if (auto Len = matchAsmCCConstraint(Constraint)) { 1760 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1761 Constraint += Len - 1; 1762 return Converted; 1763 } 1764 return std::string(1, *Constraint); 1765 case 'a': 1766 return std::string("{ax}"); 1767 case 'b': 1768 return std::string("{bx}"); 1769 case 'c': 1770 return std::string("{cx}"); 1771 case 'd': 1772 return std::string("{dx}"); 1773 case 'S': 1774 return std::string("{si}"); 1775 case 'D': 1776 return std::string("{di}"); 1777 case 'p': // address 1778 return std::string("im"); 1779 case 't': // top of floating point stack. 1780 return std::string("{st}"); 1781 case 'u': // second from top of floating point stack. 1782 return std::string("{st(1)}"); // second from top of floating point stack. 1783 case 'Y': 1784 switch (Constraint[1]) { 1785 default: 1786 // Break from inner switch and fall through (copy single char), 1787 // continue parsing after copying the current constraint into 1788 // the return string. 1789 break; 1790 case 'k': 1791 case 'm': 1792 case 'i': 1793 case 't': 1794 case 'z': 1795 case '0': 1796 case '2': 1797 // "^" hints llvm that this is a 2 letter constraint. 1798 // "Constraint++" is used to promote the string iterator 1799 // to the next constraint. 1800 return std::string("^") + std::string(Constraint++, 2); 1801 } 1802 LLVM_FALLTHROUGH; 1803 default: 1804 return std::string(1, *Constraint); 1805 } 1806 } 1807 1808 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1809 // Perform any per-CPU checks necessary to determine if this CPU is 1810 // acceptable. 1811 switch (Kind) { 1812 case CK_Generic: 1813 // No processor selected! 1814 return false; 1815 #define PROC(ENUM, STRING, IS64BIT) \ 1816 case CK_##ENUM: \ 1817 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1818 #include "clang/Basic/X86Target.def" 1819 } 1820 llvm_unreachable("Unhandled CPU kind"); 1821 } 1822 1823 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1824 #define PROC(ENUM, STRING, IS64BIT) \ 1825 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1826 Values.emplace_back(STRING); 1827 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1828 #define PROC_ALIAS(ENUM, ALIAS) \ 1829 if (checkCPUKind(CK_##ENUM)) \ 1830 Values.emplace_back(ALIAS); 1831 #include "clang/Basic/X86Target.def" 1832 } 1833 1834 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1835 return llvm::StringSwitch<CPUKind>(CPU) 1836 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1837 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1838 #include "clang/Basic/X86Target.def" 1839 .Default(CK_Generic); 1840 } 1841 1842 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1843 return llvm::makeArrayRef(GCCRegNames); 1844 } 1845 1846 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1847 return llvm::makeArrayRef(AddlRegNames); 1848 } 1849 1850 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1851 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1852 Builtin::FirstTSBuiltin + 1); 1853 } 1854 1855 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1856 return llvm::makeArrayRef(BuiltinInfoX86, 1857 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1858 } 1859