1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::checkCFProtectionReturnSupported( 105 DiagnosticsEngine &Diags) const { 106 if (HasSHSTK) 107 return true; 108 109 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 110 << "-mshstk"; 111 return false; 112 } 113 114 bool X86TargetInfo::checkCFProtectionBranchSupported( 115 DiagnosticsEngine &Diags) const { 116 if (HasIBT) 117 return true; 118 119 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 120 << "-mibt"; 121 return false; 122 } 123 124 bool X86TargetInfo::initFeatureMap( 125 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 126 const std::vector<std::string> &FeaturesVec) const { 127 // FIXME: This *really* should not be here. 128 // X86_64 always has SSE2. 129 if (getTriple().getArch() == llvm::Triple::x86_64) 130 setFeatureEnabledImpl(Features, "sse2", true); 131 132 const CPUKind Kind = getCPUKind(CPU); 133 134 // Enable X87 for all X86 processors but Lakemont. 135 if (Kind != CK_Lakemont) 136 setFeatureEnabledImpl(Features, "x87", true); 137 138 switch (Kind) { 139 case CK_Generic: 140 case CK_i386: 141 case CK_i486: 142 case CK_i586: 143 case CK_Pentium: 144 case CK_PentiumPro: 145 case CK_Lakemont: 146 break; 147 148 case CK_PentiumMMX: 149 case CK_Pentium2: 150 case CK_K6: 151 case CK_WinChipC6: 152 setFeatureEnabledImpl(Features, "mmx", true); 153 break; 154 155 case CK_Icelake: 156 setFeatureEnabledImpl(Features, "vaes", true); 157 setFeatureEnabledImpl(Features, "gfni", true); 158 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 159 setFeatureEnabledImpl(Features, "avx512bitalg", true); 160 setFeatureEnabledImpl(Features, "avx512vnni", true); 161 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 162 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 163 LLVM_FALLTHROUGH; 164 case CK_Cannonlake: 165 setFeatureEnabledImpl(Features, "avx512ifma", true); 166 setFeatureEnabledImpl(Features, "avx512vbmi", true); 167 setFeatureEnabledImpl(Features, "sha", true); 168 LLVM_FALLTHROUGH; 169 case CK_SkylakeServer: 170 setFeatureEnabledImpl(Features, "avx512f", true); 171 setFeatureEnabledImpl(Features, "avx512cd", true); 172 setFeatureEnabledImpl(Features, "avx512dq", true); 173 setFeatureEnabledImpl(Features, "avx512bw", true); 174 setFeatureEnabledImpl(Features, "avx512vl", true); 175 setFeatureEnabledImpl(Features, "pku", true); 176 setFeatureEnabledImpl(Features, "clwb", true); 177 LLVM_FALLTHROUGH; 178 case CK_SkylakeClient: 179 setFeatureEnabledImpl(Features, "xsavec", true); 180 setFeatureEnabledImpl(Features, "xsaves", true); 181 setFeatureEnabledImpl(Features, "mpx", true); 182 setFeatureEnabledImpl(Features, "sgx", true); 183 setFeatureEnabledImpl(Features, "clflushopt", true); 184 setFeatureEnabledImpl(Features, "rtm", true); 185 LLVM_FALLTHROUGH; 186 case CK_Broadwell: 187 setFeatureEnabledImpl(Features, "rdseed", true); 188 setFeatureEnabledImpl(Features, "adx", true); 189 setFeatureEnabledImpl(Features, "prfchw", true); 190 LLVM_FALLTHROUGH; 191 case CK_Haswell: 192 setFeatureEnabledImpl(Features, "avx2", true); 193 setFeatureEnabledImpl(Features, "lzcnt", true); 194 setFeatureEnabledImpl(Features, "bmi", true); 195 setFeatureEnabledImpl(Features, "bmi2", true); 196 setFeatureEnabledImpl(Features, "fma", true); 197 setFeatureEnabledImpl(Features, "movbe", true); 198 LLVM_FALLTHROUGH; 199 case CK_IvyBridge: 200 setFeatureEnabledImpl(Features, "rdrnd", true); 201 setFeatureEnabledImpl(Features, "f16c", true); 202 setFeatureEnabledImpl(Features, "fsgsbase", true); 203 LLVM_FALLTHROUGH; 204 case CK_SandyBridge: 205 setFeatureEnabledImpl(Features, "avx", true); 206 setFeatureEnabledImpl(Features, "xsave", true); 207 setFeatureEnabledImpl(Features, "xsaveopt", true); 208 LLVM_FALLTHROUGH; 209 case CK_Westmere: 210 setFeatureEnabledImpl(Features, "aes", true); 211 setFeatureEnabledImpl(Features, "pclmul", true); 212 LLVM_FALLTHROUGH; 213 case CK_Nehalem: 214 setFeatureEnabledImpl(Features, "sse4.2", true); 215 LLVM_FALLTHROUGH; 216 case CK_Penryn: 217 setFeatureEnabledImpl(Features, "sse4.1", true); 218 LLVM_FALLTHROUGH; 219 case CK_Core2: 220 setFeatureEnabledImpl(Features, "ssse3", true); 221 LLVM_FALLTHROUGH; 222 case CK_Yonah: 223 case CK_Prescott: 224 case CK_Nocona: 225 setFeatureEnabledImpl(Features, "sse3", true); 226 setFeatureEnabledImpl(Features, "cx16", true); 227 LLVM_FALLTHROUGH; 228 case CK_PentiumM: 229 case CK_Pentium4: 230 case CK_x86_64: 231 setFeatureEnabledImpl(Features, "sse2", true); 232 LLVM_FALLTHROUGH; 233 case CK_Pentium3: 234 case CK_C3_2: 235 setFeatureEnabledImpl(Features, "sse", true); 236 setFeatureEnabledImpl(Features, "fxsr", true); 237 break; 238 239 case CK_Goldmont: 240 setFeatureEnabledImpl(Features, "sha", true); 241 setFeatureEnabledImpl(Features, "rdrnd", true); 242 setFeatureEnabledImpl(Features, "rdseed", true); 243 setFeatureEnabledImpl(Features, "xsave", true); 244 setFeatureEnabledImpl(Features, "xsaveopt", true); 245 setFeatureEnabledImpl(Features, "xsavec", true); 246 setFeatureEnabledImpl(Features, "xsaves", true); 247 setFeatureEnabledImpl(Features, "clflushopt", true); 248 setFeatureEnabledImpl(Features, "mpx", true); 249 setFeatureEnabledImpl(Features, "fsgsbase", true); 250 LLVM_FALLTHROUGH; 251 case CK_Silvermont: 252 setFeatureEnabledImpl(Features, "aes", true); 253 setFeatureEnabledImpl(Features, "pclmul", true); 254 setFeatureEnabledImpl(Features, "sse4.2", true); 255 setFeatureEnabledImpl(Features, "prfchw", true); 256 LLVM_FALLTHROUGH; 257 case CK_Bonnell: 258 setFeatureEnabledImpl(Features, "movbe", true); 259 setFeatureEnabledImpl(Features, "ssse3", true); 260 setFeatureEnabledImpl(Features, "fxsr", true); 261 setFeatureEnabledImpl(Features, "cx16", true); 262 break; 263 264 case CK_KNM: 265 // TODO: Add avx5124fmaps/avx5124vnniw. 266 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 267 LLVM_FALLTHROUGH; 268 case CK_KNL: 269 setFeatureEnabledImpl(Features, "avx512f", true); 270 setFeatureEnabledImpl(Features, "avx512cd", true); 271 setFeatureEnabledImpl(Features, "avx512er", true); 272 setFeatureEnabledImpl(Features, "avx512pf", true); 273 setFeatureEnabledImpl(Features, "prfchw", true); 274 setFeatureEnabledImpl(Features, "prefetchwt1", true); 275 setFeatureEnabledImpl(Features, "fxsr", true); 276 setFeatureEnabledImpl(Features, "rdseed", true); 277 setFeatureEnabledImpl(Features, "adx", true); 278 setFeatureEnabledImpl(Features, "lzcnt", true); 279 setFeatureEnabledImpl(Features, "bmi", true); 280 setFeatureEnabledImpl(Features, "bmi2", true); 281 setFeatureEnabledImpl(Features, "rtm", true); 282 setFeatureEnabledImpl(Features, "fma", true); 283 setFeatureEnabledImpl(Features, "rdrnd", true); 284 setFeatureEnabledImpl(Features, "f16c", true); 285 setFeatureEnabledImpl(Features, "fsgsbase", true); 286 setFeatureEnabledImpl(Features, "aes", true); 287 setFeatureEnabledImpl(Features, "pclmul", true); 288 setFeatureEnabledImpl(Features, "cx16", true); 289 setFeatureEnabledImpl(Features, "xsaveopt", true); 290 setFeatureEnabledImpl(Features, "xsave", true); 291 setFeatureEnabledImpl(Features, "movbe", true); 292 break; 293 294 case CK_K6_2: 295 case CK_K6_3: 296 case CK_WinChip2: 297 case CK_C3: 298 setFeatureEnabledImpl(Features, "3dnow", true); 299 break; 300 301 case CK_AMDFAM10: 302 setFeatureEnabledImpl(Features, "sse4a", true); 303 setFeatureEnabledImpl(Features, "lzcnt", true); 304 setFeatureEnabledImpl(Features, "popcnt", true); 305 LLVM_FALLTHROUGH; 306 case CK_K8SSE3: 307 setFeatureEnabledImpl(Features, "sse3", true); 308 LLVM_FALLTHROUGH; 309 case CK_K8: 310 setFeatureEnabledImpl(Features, "sse2", true); 311 LLVM_FALLTHROUGH; 312 case CK_AthlonXP: 313 setFeatureEnabledImpl(Features, "sse", true); 314 setFeatureEnabledImpl(Features, "fxsr", true); 315 LLVM_FALLTHROUGH; 316 case CK_Athlon: 317 case CK_Geode: 318 setFeatureEnabledImpl(Features, "3dnowa", true); 319 break; 320 321 case CK_BTVER2: 322 setFeatureEnabledImpl(Features, "avx", true); 323 setFeatureEnabledImpl(Features, "aes", true); 324 setFeatureEnabledImpl(Features, "pclmul", true); 325 setFeatureEnabledImpl(Features, "bmi", true); 326 setFeatureEnabledImpl(Features, "f16c", true); 327 setFeatureEnabledImpl(Features, "xsaveopt", true); 328 setFeatureEnabledImpl(Features, "movbe", true); 329 LLVM_FALLTHROUGH; 330 case CK_BTVER1: 331 setFeatureEnabledImpl(Features, "ssse3", true); 332 setFeatureEnabledImpl(Features, "sse4a", true); 333 setFeatureEnabledImpl(Features, "lzcnt", true); 334 setFeatureEnabledImpl(Features, "popcnt", true); 335 setFeatureEnabledImpl(Features, "prfchw", true); 336 setFeatureEnabledImpl(Features, "cx16", true); 337 setFeatureEnabledImpl(Features, "fxsr", true); 338 break; 339 340 case CK_ZNVER1: 341 setFeatureEnabledImpl(Features, "adx", true); 342 setFeatureEnabledImpl(Features, "aes", true); 343 setFeatureEnabledImpl(Features, "avx2", true); 344 setFeatureEnabledImpl(Features, "bmi", true); 345 setFeatureEnabledImpl(Features, "bmi2", true); 346 setFeatureEnabledImpl(Features, "clflushopt", true); 347 setFeatureEnabledImpl(Features, "clzero", true); 348 setFeatureEnabledImpl(Features, "cx16", true); 349 setFeatureEnabledImpl(Features, "f16c", true); 350 setFeatureEnabledImpl(Features, "fma", true); 351 setFeatureEnabledImpl(Features, "fsgsbase", true); 352 setFeatureEnabledImpl(Features, "fxsr", true); 353 setFeatureEnabledImpl(Features, "lzcnt", true); 354 setFeatureEnabledImpl(Features, "mwaitx", true); 355 setFeatureEnabledImpl(Features, "movbe", true); 356 setFeatureEnabledImpl(Features, "pclmul", true); 357 setFeatureEnabledImpl(Features, "popcnt", true); 358 setFeatureEnabledImpl(Features, "prfchw", true); 359 setFeatureEnabledImpl(Features, "rdrnd", true); 360 setFeatureEnabledImpl(Features, "rdseed", true); 361 setFeatureEnabledImpl(Features, "sha", true); 362 setFeatureEnabledImpl(Features, "sse4a", true); 363 setFeatureEnabledImpl(Features, "xsave", true); 364 setFeatureEnabledImpl(Features, "xsavec", true); 365 setFeatureEnabledImpl(Features, "xsaveopt", true); 366 setFeatureEnabledImpl(Features, "xsaves", true); 367 break; 368 369 case CK_BDVER4: 370 setFeatureEnabledImpl(Features, "avx2", true); 371 setFeatureEnabledImpl(Features, "bmi2", true); 372 setFeatureEnabledImpl(Features, "mwaitx", true); 373 LLVM_FALLTHROUGH; 374 case CK_BDVER3: 375 setFeatureEnabledImpl(Features, "fsgsbase", true); 376 setFeatureEnabledImpl(Features, "xsaveopt", true); 377 LLVM_FALLTHROUGH; 378 case CK_BDVER2: 379 setFeatureEnabledImpl(Features, "bmi", true); 380 setFeatureEnabledImpl(Features, "fma", true); 381 setFeatureEnabledImpl(Features, "f16c", true); 382 setFeatureEnabledImpl(Features, "tbm", true); 383 LLVM_FALLTHROUGH; 384 case CK_BDVER1: 385 // xop implies avx, sse4a and fma4. 386 setFeatureEnabledImpl(Features, "xop", true); 387 setFeatureEnabledImpl(Features, "lwp", true); 388 setFeatureEnabledImpl(Features, "lzcnt", true); 389 setFeatureEnabledImpl(Features, "aes", true); 390 setFeatureEnabledImpl(Features, "pclmul", true); 391 setFeatureEnabledImpl(Features, "prfchw", true); 392 setFeatureEnabledImpl(Features, "cx16", true); 393 setFeatureEnabledImpl(Features, "fxsr", true); 394 setFeatureEnabledImpl(Features, "xsave", true); 395 break; 396 } 397 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 398 return false; 399 400 // Can't do this earlier because we need to be able to explicitly enable 401 // or disable these features and the things that they depend upon. 402 403 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 404 auto I = Features.find("sse4.2"); 405 if (I != Features.end() && I->getValue() && 406 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 407 FeaturesVec.end()) 408 Features["popcnt"] = true; 409 410 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 411 I = Features.find("3dnow"); 412 if (I != Features.end() && I->getValue() && 413 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 414 FeaturesVec.end()) 415 Features["prfchw"] = true; 416 417 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 418 // then enable MMX. 419 I = Features.find("sse"); 420 if (I != Features.end() && I->getValue() && 421 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 422 FeaturesVec.end()) 423 Features["mmx"] = true; 424 425 return true; 426 } 427 428 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 429 X86SSEEnum Level, bool Enabled) { 430 if (Enabled) { 431 switch (Level) { 432 case AVX512F: 433 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 434 LLVM_FALLTHROUGH; 435 case AVX2: 436 Features["avx2"] = true; 437 LLVM_FALLTHROUGH; 438 case AVX: 439 Features["avx"] = true; 440 Features["xsave"] = true; 441 LLVM_FALLTHROUGH; 442 case SSE42: 443 Features["sse4.2"] = true; 444 LLVM_FALLTHROUGH; 445 case SSE41: 446 Features["sse4.1"] = true; 447 LLVM_FALLTHROUGH; 448 case SSSE3: 449 Features["ssse3"] = true; 450 LLVM_FALLTHROUGH; 451 case SSE3: 452 Features["sse3"] = true; 453 LLVM_FALLTHROUGH; 454 case SSE2: 455 Features["sse2"] = true; 456 LLVM_FALLTHROUGH; 457 case SSE1: 458 Features["sse"] = true; 459 LLVM_FALLTHROUGH; 460 case NoSSE: 461 break; 462 } 463 return; 464 } 465 466 switch (Level) { 467 case NoSSE: 468 case SSE1: 469 Features["sse"] = false; 470 LLVM_FALLTHROUGH; 471 case SSE2: 472 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 473 Features["gfni"] = false; 474 LLVM_FALLTHROUGH; 475 case SSE3: 476 Features["sse3"] = false; 477 setXOPLevel(Features, NoXOP, false); 478 LLVM_FALLTHROUGH; 479 case SSSE3: 480 Features["ssse3"] = false; 481 LLVM_FALLTHROUGH; 482 case SSE41: 483 Features["sse4.1"] = false; 484 LLVM_FALLTHROUGH; 485 case SSE42: 486 Features["sse4.2"] = false; 487 LLVM_FALLTHROUGH; 488 case AVX: 489 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 490 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 491 setXOPLevel(Features, FMA4, false); 492 LLVM_FALLTHROUGH; 493 case AVX2: 494 Features["avx2"] = false; 495 LLVM_FALLTHROUGH; 496 case AVX512F: 497 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 498 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 499 Features["avx512vl"] = Features["avx512vbmi"] = 500 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 501 Features["avx512bitalg"] = Features["avx512vnni"] = 502 Features["avx512vbmi2"] = false; 503 break; 504 } 505 } 506 507 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 508 MMX3DNowEnum Level, bool Enabled) { 509 if (Enabled) { 510 switch (Level) { 511 case AMD3DNowAthlon: 512 Features["3dnowa"] = true; 513 LLVM_FALLTHROUGH; 514 case AMD3DNow: 515 Features["3dnow"] = true; 516 LLVM_FALLTHROUGH; 517 case MMX: 518 Features["mmx"] = true; 519 LLVM_FALLTHROUGH; 520 case NoMMX3DNow: 521 break; 522 } 523 return; 524 } 525 526 switch (Level) { 527 case NoMMX3DNow: 528 case MMX: 529 Features["mmx"] = false; 530 LLVM_FALLTHROUGH; 531 case AMD3DNow: 532 Features["3dnow"] = false; 533 LLVM_FALLTHROUGH; 534 case AMD3DNowAthlon: 535 Features["3dnowa"] = false; 536 break; 537 } 538 } 539 540 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 541 bool Enabled) { 542 if (Enabled) { 543 switch (Level) { 544 case XOP: 545 Features["xop"] = true; 546 LLVM_FALLTHROUGH; 547 case FMA4: 548 Features["fma4"] = true; 549 setSSELevel(Features, AVX, true); 550 LLVM_FALLTHROUGH; 551 case SSE4A: 552 Features["sse4a"] = true; 553 setSSELevel(Features, SSE3, true); 554 LLVM_FALLTHROUGH; 555 case NoXOP: 556 break; 557 } 558 return; 559 } 560 561 switch (Level) { 562 case NoXOP: 563 case SSE4A: 564 Features["sse4a"] = false; 565 LLVM_FALLTHROUGH; 566 case FMA4: 567 Features["fma4"] = false; 568 LLVM_FALLTHROUGH; 569 case XOP: 570 Features["xop"] = false; 571 break; 572 } 573 } 574 575 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 576 StringRef Name, bool Enabled) { 577 // This is a bit of a hack to deal with the sse4 target feature when used 578 // as part of the target attribute. We handle sse4 correctly everywhere 579 // else. See below for more information on how we handle the sse4 options. 580 if (Name != "sse4") 581 Features[Name] = Enabled; 582 583 if (Name == "mmx") { 584 setMMXLevel(Features, MMX, Enabled); 585 } else if (Name == "sse") { 586 setSSELevel(Features, SSE1, Enabled); 587 } else if (Name == "sse2") { 588 setSSELevel(Features, SSE2, Enabled); 589 } else if (Name == "sse3") { 590 setSSELevel(Features, SSE3, Enabled); 591 } else if (Name == "ssse3") { 592 setSSELevel(Features, SSSE3, Enabled); 593 } else if (Name == "sse4.2") { 594 setSSELevel(Features, SSE42, Enabled); 595 } else if (Name == "sse4.1") { 596 setSSELevel(Features, SSE41, Enabled); 597 } else if (Name == "3dnow") { 598 setMMXLevel(Features, AMD3DNow, Enabled); 599 } else if (Name == "3dnowa") { 600 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 601 } else if (Name == "aes") { 602 if (Enabled) 603 setSSELevel(Features, SSE2, Enabled); 604 else 605 Features["vaes"] = false; 606 } else if (Name == "vaes") { 607 if (Enabled) { 608 setSSELevel(Features, AVX, Enabled); 609 Features["aes"] = true; 610 } 611 } else if (Name == "pclmul") { 612 if (Enabled) 613 setSSELevel(Features, SSE2, Enabled); 614 else 615 Features["vpclmulqdq"] = false; 616 } else if (Name == "vpclmulqdq") { 617 if (Enabled) { 618 setSSELevel(Features, AVX, Enabled); 619 Features["pclmul"] = true; 620 } 621 } else if (Name == "gfni") { 622 if (Enabled) 623 setSSELevel(Features, SSE2, Enabled); 624 } else if (Name == "avx") { 625 setSSELevel(Features, AVX, Enabled); 626 } else if (Name == "avx2") { 627 setSSELevel(Features, AVX2, Enabled); 628 } else if (Name == "avx512f") { 629 setSSELevel(Features, AVX512F, Enabled); 630 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 631 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 632 Name == "avx512vbmi" || Name == "avx512ifma" || 633 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 634 Name == "avx512vnni" || Name == "avx512vbmi2") { 635 if (Enabled) 636 setSSELevel(Features, AVX512F, Enabled); 637 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 638 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 639 Features["avx512bw"] = true; 640 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 641 if (Name == "avx512bw" && !Enabled) 642 Features["avx512vbmi"] = Features["avx512vbmi2"] = 643 Features["avx512bitalg"] = false; 644 } else if (Name == "fma") { 645 if (Enabled) 646 setSSELevel(Features, AVX, Enabled); 647 else 648 setSSELevel(Features, AVX512F, Enabled); 649 } else if (Name == "fma4") { 650 setXOPLevel(Features, FMA4, Enabled); 651 } else if (Name == "xop") { 652 setXOPLevel(Features, XOP, Enabled); 653 } else if (Name == "sse4a") { 654 setXOPLevel(Features, SSE4A, Enabled); 655 } else if (Name == "f16c") { 656 if (Enabled) 657 setSSELevel(Features, AVX, Enabled); 658 else 659 setSSELevel(Features, AVX512F, Enabled); 660 } else if (Name == "sha") { 661 if (Enabled) 662 setSSELevel(Features, SSE2, Enabled); 663 } else if (Name == "sse4") { 664 // We can get here via the __target__ attribute since that's not controlled 665 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 666 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 667 // disabled. 668 if (Enabled) 669 setSSELevel(Features, SSE42, Enabled); 670 else 671 setSSELevel(Features, SSE41, Enabled); 672 } else if (Name == "xsave") { 673 if (!Enabled) 674 Features["xsaveopt"] = false; 675 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 676 if (Enabled) 677 Features["xsave"] = true; 678 } 679 } 680 681 /// handleTargetFeatures - Perform initialization based on the user 682 /// configured set of features. 683 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 684 DiagnosticsEngine &Diags) { 685 for (const auto &Feature : Features) { 686 if (Feature[0] != '+') 687 continue; 688 689 if (Feature == "+aes") { 690 HasAES = true; 691 } else if (Feature == "+vaes") { 692 HasVAES = true; 693 } else if (Feature == "+pclmul") { 694 HasPCLMUL = true; 695 } else if (Feature == "+vpclmulqdq") { 696 HasVPCLMULQDQ = true; 697 } else if (Feature == "+lzcnt") { 698 HasLZCNT = true; 699 } else if (Feature == "+rdrnd") { 700 HasRDRND = true; 701 } else if (Feature == "+fsgsbase") { 702 HasFSGSBASE = true; 703 } else if (Feature == "+bmi") { 704 HasBMI = true; 705 } else if (Feature == "+bmi2") { 706 HasBMI2 = true; 707 } else if (Feature == "+popcnt") { 708 HasPOPCNT = true; 709 } else if (Feature == "+rtm") { 710 HasRTM = true; 711 } else if (Feature == "+prfchw") { 712 HasPRFCHW = true; 713 } else if (Feature == "+rdseed") { 714 HasRDSEED = true; 715 } else if (Feature == "+adx") { 716 HasADX = true; 717 } else if (Feature == "+tbm") { 718 HasTBM = true; 719 } else if (Feature == "+lwp") { 720 HasLWP = true; 721 } else if (Feature == "+fma") { 722 HasFMA = true; 723 } else if (Feature == "+f16c") { 724 HasF16C = true; 725 } else if (Feature == "+gfni") { 726 HasGFNI = true; 727 } else if (Feature == "+avx512cd") { 728 HasAVX512CD = true; 729 } else if (Feature == "+avx512vpopcntdq") { 730 HasAVX512VPOPCNTDQ = true; 731 } else if (Feature == "+avx512vnni") { 732 HasAVX512VNNI = true; 733 } else if (Feature == "+avx512er") { 734 HasAVX512ER = true; 735 } else if (Feature == "+avx512pf") { 736 HasAVX512PF = true; 737 } else if (Feature == "+avx512dq") { 738 HasAVX512DQ = true; 739 } else if (Feature == "+avx512bitalg") { 740 HasAVX512BITALG = true; 741 } else if (Feature == "+avx512bw") { 742 HasAVX512BW = true; 743 } else if (Feature == "+avx512vl") { 744 HasAVX512VL = true; 745 } else if (Feature == "+avx512vbmi") { 746 HasAVX512VBMI = true; 747 } else if (Feature == "+avx512vbmi2") { 748 HasAVX512VBMI2 = true; 749 } else if (Feature == "+avx512ifma") { 750 HasAVX512IFMA = true; 751 } else if (Feature == "+sha") { 752 HasSHA = true; 753 } else if (Feature == "+mpx") { 754 HasMPX = true; 755 } else if (Feature == "+shstk") { 756 HasSHSTK = true; 757 } else if (Feature == "+ibt") { 758 HasIBT = true; 759 } else if (Feature == "+movbe") { 760 HasMOVBE = true; 761 } else if (Feature == "+sgx") { 762 HasSGX = true; 763 } else if (Feature == "+cx16") { 764 HasCX16 = true; 765 } else if (Feature == "+fxsr") { 766 HasFXSR = true; 767 } else if (Feature == "+xsave") { 768 HasXSAVE = true; 769 } else if (Feature == "+xsaveopt") { 770 HasXSAVEOPT = true; 771 } else if (Feature == "+xsavec") { 772 HasXSAVEC = true; 773 } else if (Feature == "+xsaves") { 774 HasXSAVES = true; 775 } else if (Feature == "+mwaitx") { 776 HasMWAITX = true; 777 } else if (Feature == "+pku") { 778 HasPKU = true; 779 } else if (Feature == "+clflushopt") { 780 HasCLFLUSHOPT = true; 781 } else if (Feature == "+clwb") { 782 HasCLWB = true; 783 } else if (Feature == "+prefetchwt1") { 784 HasPREFETCHWT1 = true; 785 } else if (Feature == "+clzero") { 786 HasCLZERO = true; 787 } 788 789 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 790 .Case("+avx512f", AVX512F) 791 .Case("+avx2", AVX2) 792 .Case("+avx", AVX) 793 .Case("+sse4.2", SSE42) 794 .Case("+sse4.1", SSE41) 795 .Case("+ssse3", SSSE3) 796 .Case("+sse3", SSE3) 797 .Case("+sse2", SSE2) 798 .Case("+sse", SSE1) 799 .Default(NoSSE); 800 SSELevel = std::max(SSELevel, Level); 801 802 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 803 .Case("+3dnowa", AMD3DNowAthlon) 804 .Case("+3dnow", AMD3DNow) 805 .Case("+mmx", MMX) 806 .Default(NoMMX3DNow); 807 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 808 809 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 810 .Case("+xop", XOP) 811 .Case("+fma4", FMA4) 812 .Case("+sse4a", SSE4A) 813 .Default(NoXOP); 814 XOPLevel = std::max(XOPLevel, XLevel); 815 } 816 817 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 818 // matches the selected sse level. 819 if ((FPMath == FP_SSE && SSELevel < SSE1) || 820 (FPMath == FP_387 && SSELevel >= SSE1)) { 821 Diags.Report(diag::err_target_unsupported_fpmath) 822 << (FPMath == FP_SSE ? "sse" : "387"); 823 return false; 824 } 825 826 SimdDefaultAlign = 827 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 828 return true; 829 } 830 831 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 832 /// definitions for this particular subtarget. 833 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 834 MacroBuilder &Builder) const { 835 // Target identification. 836 if (getTriple().getArch() == llvm::Triple::x86_64) { 837 Builder.defineMacro("__amd64__"); 838 Builder.defineMacro("__amd64"); 839 Builder.defineMacro("__x86_64"); 840 Builder.defineMacro("__x86_64__"); 841 if (getTriple().getArchName() == "x86_64h") { 842 Builder.defineMacro("__x86_64h"); 843 Builder.defineMacro("__x86_64h__"); 844 } 845 } else { 846 DefineStd(Builder, "i386", Opts); 847 } 848 849 // Subtarget options. 850 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 851 // truly should be based on -mtune options. 852 switch (CPU) { 853 case CK_Generic: 854 break; 855 case CK_i386: 856 // The rest are coming from the i386 define above. 857 Builder.defineMacro("__tune_i386__"); 858 break; 859 case CK_i486: 860 case CK_WinChipC6: 861 case CK_WinChip2: 862 case CK_C3: 863 defineCPUMacros(Builder, "i486"); 864 break; 865 case CK_PentiumMMX: 866 Builder.defineMacro("__pentium_mmx__"); 867 Builder.defineMacro("__tune_pentium_mmx__"); 868 LLVM_FALLTHROUGH; 869 case CK_i586: 870 case CK_Pentium: 871 defineCPUMacros(Builder, "i586"); 872 defineCPUMacros(Builder, "pentium"); 873 break; 874 case CK_Pentium3: 875 case CK_PentiumM: 876 Builder.defineMacro("__tune_pentium3__"); 877 LLVM_FALLTHROUGH; 878 case CK_Pentium2: 879 case CK_C3_2: 880 Builder.defineMacro("__tune_pentium2__"); 881 LLVM_FALLTHROUGH; 882 case CK_PentiumPro: 883 defineCPUMacros(Builder, "i686"); 884 defineCPUMacros(Builder, "pentiumpro"); 885 break; 886 case CK_Pentium4: 887 defineCPUMacros(Builder, "pentium4"); 888 break; 889 case CK_Yonah: 890 case CK_Prescott: 891 case CK_Nocona: 892 defineCPUMacros(Builder, "nocona"); 893 break; 894 case CK_Core2: 895 case CK_Penryn: 896 defineCPUMacros(Builder, "core2"); 897 break; 898 case CK_Bonnell: 899 defineCPUMacros(Builder, "atom"); 900 break; 901 case CK_Silvermont: 902 defineCPUMacros(Builder, "slm"); 903 break; 904 case CK_Goldmont: 905 defineCPUMacros(Builder, "goldmont"); 906 break; 907 case CK_Nehalem: 908 case CK_Westmere: 909 case CK_SandyBridge: 910 case CK_IvyBridge: 911 case CK_Haswell: 912 case CK_Broadwell: 913 case CK_SkylakeClient: 914 case CK_SkylakeServer: 915 case CK_Cannonlake: 916 case CK_Icelake: 917 // FIXME: Historically, we defined this legacy name, it would be nice to 918 // remove it at some point. We've never exposed fine-grained names for 919 // recent primary x86 CPUs, and we should keep it that way. 920 defineCPUMacros(Builder, "corei7"); 921 break; 922 case CK_KNL: 923 defineCPUMacros(Builder, "knl"); 924 break; 925 case CK_KNM: 926 break; 927 case CK_Lakemont: 928 defineCPUMacros(Builder, "i586", /*Tuning*/false); 929 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 930 Builder.defineMacro("__tune_lakemont__"); 931 break; 932 case CK_K6_2: 933 Builder.defineMacro("__k6_2__"); 934 Builder.defineMacro("__tune_k6_2__"); 935 LLVM_FALLTHROUGH; 936 case CK_K6_3: 937 if (CPU != CK_K6_2) { // In case of fallthrough 938 // FIXME: GCC may be enabling these in cases where some other k6 939 // architecture is specified but -m3dnow is explicitly provided. The 940 // exact semantics need to be determined and emulated here. 941 Builder.defineMacro("__k6_3__"); 942 Builder.defineMacro("__tune_k6_3__"); 943 } 944 LLVM_FALLTHROUGH; 945 case CK_K6: 946 defineCPUMacros(Builder, "k6"); 947 break; 948 case CK_Athlon: 949 case CK_AthlonXP: 950 defineCPUMacros(Builder, "athlon"); 951 if (SSELevel != NoSSE) { 952 Builder.defineMacro("__athlon_sse__"); 953 Builder.defineMacro("__tune_athlon_sse__"); 954 } 955 break; 956 case CK_K8: 957 case CK_K8SSE3: 958 case CK_x86_64: 959 defineCPUMacros(Builder, "k8"); 960 break; 961 case CK_AMDFAM10: 962 defineCPUMacros(Builder, "amdfam10"); 963 break; 964 case CK_BTVER1: 965 defineCPUMacros(Builder, "btver1"); 966 break; 967 case CK_BTVER2: 968 defineCPUMacros(Builder, "btver2"); 969 break; 970 case CK_BDVER1: 971 defineCPUMacros(Builder, "bdver1"); 972 break; 973 case CK_BDVER2: 974 defineCPUMacros(Builder, "bdver2"); 975 break; 976 case CK_BDVER3: 977 defineCPUMacros(Builder, "bdver3"); 978 break; 979 case CK_BDVER4: 980 defineCPUMacros(Builder, "bdver4"); 981 break; 982 case CK_ZNVER1: 983 defineCPUMacros(Builder, "znver1"); 984 break; 985 case CK_Geode: 986 defineCPUMacros(Builder, "geode"); 987 break; 988 } 989 990 // Target properties. 991 Builder.defineMacro("__REGISTER_PREFIX__", ""); 992 993 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 994 // functions in glibc header files that use FP Stack inline asm which the 995 // backend can't deal with (PR879). 996 Builder.defineMacro("__NO_MATH_INLINES"); 997 998 if (HasAES) 999 Builder.defineMacro("__AES__"); 1000 1001 if (HasVAES) 1002 Builder.defineMacro("__VAES__"); 1003 1004 if (HasPCLMUL) 1005 Builder.defineMacro("__PCLMUL__"); 1006 1007 if (HasVPCLMULQDQ) 1008 Builder.defineMacro("__VPCLMULQDQ__"); 1009 1010 if (HasLZCNT) 1011 Builder.defineMacro("__LZCNT__"); 1012 1013 if (HasRDRND) 1014 Builder.defineMacro("__RDRND__"); 1015 1016 if (HasFSGSBASE) 1017 Builder.defineMacro("__FSGSBASE__"); 1018 1019 if (HasBMI) 1020 Builder.defineMacro("__BMI__"); 1021 1022 if (HasBMI2) 1023 Builder.defineMacro("__BMI2__"); 1024 1025 if (HasPOPCNT) 1026 Builder.defineMacro("__POPCNT__"); 1027 1028 if (HasRTM) 1029 Builder.defineMacro("__RTM__"); 1030 1031 if (HasPRFCHW) 1032 Builder.defineMacro("__PRFCHW__"); 1033 1034 if (HasRDSEED) 1035 Builder.defineMacro("__RDSEED__"); 1036 1037 if (HasADX) 1038 Builder.defineMacro("__ADX__"); 1039 1040 if (HasTBM) 1041 Builder.defineMacro("__TBM__"); 1042 1043 if (HasLWP) 1044 Builder.defineMacro("__LWP__"); 1045 1046 if (HasMWAITX) 1047 Builder.defineMacro("__MWAITX__"); 1048 1049 switch (XOPLevel) { 1050 case XOP: 1051 Builder.defineMacro("__XOP__"); 1052 LLVM_FALLTHROUGH; 1053 case FMA4: 1054 Builder.defineMacro("__FMA4__"); 1055 LLVM_FALLTHROUGH; 1056 case SSE4A: 1057 Builder.defineMacro("__SSE4A__"); 1058 LLVM_FALLTHROUGH; 1059 case NoXOP: 1060 break; 1061 } 1062 1063 if (HasFMA) 1064 Builder.defineMacro("__FMA__"); 1065 1066 if (HasF16C) 1067 Builder.defineMacro("__F16C__"); 1068 1069 if (HasGFNI) 1070 Builder.defineMacro("__GFNI__"); 1071 1072 if (HasAVX512CD) 1073 Builder.defineMacro("__AVX512CD__"); 1074 if (HasAVX512VPOPCNTDQ) 1075 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1076 if (HasAVX512VNNI) 1077 Builder.defineMacro("__AVX512VNNI__"); 1078 if (HasAVX512ER) 1079 Builder.defineMacro("__AVX512ER__"); 1080 if (HasAVX512PF) 1081 Builder.defineMacro("__AVX512PF__"); 1082 if (HasAVX512DQ) 1083 Builder.defineMacro("__AVX512DQ__"); 1084 if (HasAVX512BITALG) 1085 Builder.defineMacro("__AVX512BITALG__"); 1086 if (HasAVX512BW) 1087 Builder.defineMacro("__AVX512BW__"); 1088 if (HasAVX512VL) 1089 Builder.defineMacro("__AVX512VL__"); 1090 if (HasAVX512VBMI) 1091 Builder.defineMacro("__AVX512VBMI__"); 1092 if (HasAVX512VBMI2) 1093 Builder.defineMacro("__AVX512VBMI2__"); 1094 if (HasAVX512IFMA) 1095 Builder.defineMacro("__AVX512IFMA__"); 1096 1097 if (HasSHA) 1098 Builder.defineMacro("__SHA__"); 1099 1100 if (HasFXSR) 1101 Builder.defineMacro("__FXSR__"); 1102 if (HasXSAVE) 1103 Builder.defineMacro("__XSAVE__"); 1104 if (HasXSAVEOPT) 1105 Builder.defineMacro("__XSAVEOPT__"); 1106 if (HasXSAVEC) 1107 Builder.defineMacro("__XSAVEC__"); 1108 if (HasXSAVES) 1109 Builder.defineMacro("__XSAVES__"); 1110 if (HasPKU) 1111 Builder.defineMacro("__PKU__"); 1112 if (HasCX16) 1113 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1114 if (HasCLFLUSHOPT) 1115 Builder.defineMacro("__CLFLUSHOPT__"); 1116 if (HasCLWB) 1117 Builder.defineMacro("__CLWB__"); 1118 if (HasMPX) 1119 Builder.defineMacro("__MPX__"); 1120 if (HasSHSTK) 1121 Builder.defineMacro("__SHSTK__"); 1122 if (HasSGX) 1123 Builder.defineMacro("__SGX__"); 1124 if (HasPREFETCHWT1) 1125 Builder.defineMacro("__PREFETCHWT1__"); 1126 if (HasCLZERO) 1127 Builder.defineMacro("__CLZERO__"); 1128 1129 // Each case falls through to the previous one here. 1130 switch (SSELevel) { 1131 case AVX512F: 1132 Builder.defineMacro("__AVX512F__"); 1133 LLVM_FALLTHROUGH; 1134 case AVX2: 1135 Builder.defineMacro("__AVX2__"); 1136 LLVM_FALLTHROUGH; 1137 case AVX: 1138 Builder.defineMacro("__AVX__"); 1139 LLVM_FALLTHROUGH; 1140 case SSE42: 1141 Builder.defineMacro("__SSE4_2__"); 1142 LLVM_FALLTHROUGH; 1143 case SSE41: 1144 Builder.defineMacro("__SSE4_1__"); 1145 LLVM_FALLTHROUGH; 1146 case SSSE3: 1147 Builder.defineMacro("__SSSE3__"); 1148 LLVM_FALLTHROUGH; 1149 case SSE3: 1150 Builder.defineMacro("__SSE3__"); 1151 LLVM_FALLTHROUGH; 1152 case SSE2: 1153 Builder.defineMacro("__SSE2__"); 1154 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1155 LLVM_FALLTHROUGH; 1156 case SSE1: 1157 Builder.defineMacro("__SSE__"); 1158 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1159 LLVM_FALLTHROUGH; 1160 case NoSSE: 1161 break; 1162 } 1163 1164 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1165 switch (SSELevel) { 1166 case AVX512F: 1167 case AVX2: 1168 case AVX: 1169 case SSE42: 1170 case SSE41: 1171 case SSSE3: 1172 case SSE3: 1173 case SSE2: 1174 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1175 break; 1176 case SSE1: 1177 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1178 break; 1179 default: 1180 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1181 break; 1182 } 1183 } 1184 1185 // Each case falls through to the previous one here. 1186 switch (MMX3DNowLevel) { 1187 case AMD3DNowAthlon: 1188 Builder.defineMacro("__3dNOW_A__"); 1189 LLVM_FALLTHROUGH; 1190 case AMD3DNow: 1191 Builder.defineMacro("__3dNOW__"); 1192 LLVM_FALLTHROUGH; 1193 case MMX: 1194 Builder.defineMacro("__MMX__"); 1195 LLVM_FALLTHROUGH; 1196 case NoMMX3DNow: 1197 break; 1198 } 1199 1200 if (CPU >= CK_i486) { 1201 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1202 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1203 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1204 } 1205 if (CPU >= CK_i586) 1206 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1207 1208 if (HasFloat128) 1209 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1210 } 1211 1212 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1213 return llvm::StringSwitch<bool>(Name) 1214 .Case("3dnow", true) 1215 .Case("3dnowa", true) 1216 .Case("adx", true) 1217 .Case("aes", true) 1218 .Case("avx", true) 1219 .Case("avx2", true) 1220 .Case("avx512f", true) 1221 .Case("avx512cd", true) 1222 .Case("avx512vpopcntdq", true) 1223 .Case("avx512vnni", true) 1224 .Case("avx512er", true) 1225 .Case("avx512pf", true) 1226 .Case("avx512dq", true) 1227 .Case("avx512bitalg", true) 1228 .Case("avx512bw", true) 1229 .Case("avx512vl", true) 1230 .Case("avx512vbmi", true) 1231 .Case("avx512vbmi2", true) 1232 .Case("avx512ifma", true) 1233 .Case("bmi", true) 1234 .Case("bmi2", true) 1235 .Case("clflushopt", true) 1236 .Case("clwb", true) 1237 .Case("clzero", true) 1238 .Case("cx16", true) 1239 .Case("f16c", true) 1240 .Case("fma", true) 1241 .Case("fma4", true) 1242 .Case("fsgsbase", true) 1243 .Case("fxsr", true) 1244 .Case("gfni", true) 1245 .Case("lwp", true) 1246 .Case("lzcnt", true) 1247 .Case("mmx", true) 1248 .Case("movbe", true) 1249 .Case("mpx", true) 1250 .Case("mwaitx", true) 1251 .Case("pclmul", true) 1252 .Case("pku", true) 1253 .Case("popcnt", true) 1254 .Case("prefetchwt1", true) 1255 .Case("prfchw", true) 1256 .Case("rdrnd", true) 1257 .Case("rdseed", true) 1258 .Case("rtm", true) 1259 .Case("sgx", true) 1260 .Case("sha", true) 1261 .Case("shstk", true) 1262 .Case("sse", true) 1263 .Case("sse2", true) 1264 .Case("sse3", true) 1265 .Case("ssse3", true) 1266 .Case("sse4", true) 1267 .Case("sse4.1", true) 1268 .Case("sse4.2", true) 1269 .Case("sse4a", true) 1270 .Case("tbm", true) 1271 .Case("vaes", true) 1272 .Case("vpclmulqdq", true) 1273 .Case("x87", true) 1274 .Case("xop", true) 1275 .Case("xsave", true) 1276 .Case("xsavec", true) 1277 .Case("xsaves", true) 1278 .Case("xsaveopt", true) 1279 .Default(false); 1280 } 1281 1282 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1283 return llvm::StringSwitch<bool>(Feature) 1284 .Case("adx", HasADX) 1285 .Case("aes", HasAES) 1286 .Case("avx", SSELevel >= AVX) 1287 .Case("avx2", SSELevel >= AVX2) 1288 .Case("avx512f", SSELevel >= AVX512F) 1289 .Case("avx512cd", HasAVX512CD) 1290 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1291 .Case("avx512vnni", HasAVX512VNNI) 1292 .Case("avx512er", HasAVX512ER) 1293 .Case("avx512pf", HasAVX512PF) 1294 .Case("avx512dq", HasAVX512DQ) 1295 .Case("avx512bitalg", HasAVX512BITALG) 1296 .Case("avx512bw", HasAVX512BW) 1297 .Case("avx512vl", HasAVX512VL) 1298 .Case("avx512vbmi", HasAVX512VBMI) 1299 .Case("avx512vbmi2", HasAVX512VBMI2) 1300 .Case("avx512ifma", HasAVX512IFMA) 1301 .Case("bmi", HasBMI) 1302 .Case("bmi2", HasBMI2) 1303 .Case("clflushopt", HasCLFLUSHOPT) 1304 .Case("clwb", HasCLWB) 1305 .Case("clzero", HasCLZERO) 1306 .Case("cx16", HasCX16) 1307 .Case("f16c", HasF16C) 1308 .Case("fma", HasFMA) 1309 .Case("fma4", XOPLevel >= FMA4) 1310 .Case("fsgsbase", HasFSGSBASE) 1311 .Case("fxsr", HasFXSR) 1312 .Case("gfni", HasGFNI) 1313 .Case("ibt", HasIBT) 1314 .Case("lwp", HasLWP) 1315 .Case("lzcnt", HasLZCNT) 1316 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1317 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1318 .Case("mmx", MMX3DNowLevel >= MMX) 1319 .Case("movbe", HasMOVBE) 1320 .Case("mpx", HasMPX) 1321 .Case("mwaitx", HasMWAITX) 1322 .Case("pclmul", HasPCLMUL) 1323 .Case("pku", HasPKU) 1324 .Case("popcnt", HasPOPCNT) 1325 .Case("prefetchwt1", HasPREFETCHWT1) 1326 .Case("prfchw", HasPRFCHW) 1327 .Case("rdrnd", HasRDRND) 1328 .Case("rdseed", HasRDSEED) 1329 .Case("rtm", HasRTM) 1330 .Case("sgx", HasSGX) 1331 .Case("sha", HasSHA) 1332 .Case("shstk", HasSHSTK) 1333 .Case("sse", SSELevel >= SSE1) 1334 .Case("sse2", SSELevel >= SSE2) 1335 .Case("sse3", SSELevel >= SSE3) 1336 .Case("ssse3", SSELevel >= SSSE3) 1337 .Case("sse4.1", SSELevel >= SSE41) 1338 .Case("sse4.2", SSELevel >= SSE42) 1339 .Case("sse4a", XOPLevel >= SSE4A) 1340 .Case("tbm", HasTBM) 1341 .Case("vaes", HasVAES) 1342 .Case("vpclmulqdq", HasVPCLMULQDQ) 1343 .Case("x86", true) 1344 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1345 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1346 .Case("xop", XOPLevel >= XOP) 1347 .Case("xsave", HasXSAVE) 1348 .Case("xsavec", HasXSAVEC) 1349 .Case("xsaves", HasXSAVES) 1350 .Case("xsaveopt", HasXSAVEOPT) 1351 .Default(false); 1352 } 1353 1354 // We can't use a generic validation scheme for the features accepted here 1355 // versus subtarget features accepted in the target attribute because the 1356 // bitfield structure that's initialized in the runtime only supports the 1357 // below currently rather than the full range of subtarget features. (See 1358 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1359 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1360 return llvm::StringSwitch<bool>(FeatureStr) 1361 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1362 #include "llvm/Support/X86TargetParser.def" 1363 .Default(false); 1364 } 1365 1366 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1367 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1368 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1369 #include "llvm/Support/X86TargetParser.def" 1370 ; 1371 // Note, this function should only be used after ensuring the value is 1372 // correct, so it asserts if the value is out of range. 1373 } 1374 1375 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1376 enum class FeatPriority { 1377 #define FEATURE(FEAT) FEAT, 1378 #include "clang/Basic/X86Target.def" 1379 }; 1380 switch (Feat) { 1381 #define FEATURE(FEAT) \ 1382 case llvm::X86::FEAT: \ 1383 return static_cast<unsigned>(FeatPriority::FEAT); 1384 #include "clang/Basic/X86Target.def" 1385 default: 1386 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1387 } 1388 } 1389 1390 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1391 // Valid CPUs have a 'key feature' that compares just better than its key 1392 // feature. 1393 CPUKind Kind = getCPUKind(Name); 1394 if (Kind != CK_Generic) { 1395 switch (Kind) { 1396 default: 1397 llvm_unreachable( 1398 "CPU Type without a key feature used in 'target' attribute"); 1399 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1400 case CK_##ENUM: \ 1401 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1402 #include "clang/Basic/X86Target.def" 1403 } 1404 } 1405 1406 // Now we know we have a feature, so get its priority and shift it a few so 1407 // that we have sufficient room for the CPUs (above). 1408 return getFeaturePriority(getFeature(Name)) << 1; 1409 } 1410 1411 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1412 switch (Kind) { 1413 case CK_Generic: 1414 return ""; 1415 #define PROC(ENUM, STRING, IS64BIT) \ 1416 case CK_##ENUM: \ 1417 return STRING; 1418 #include "clang/Basic/X86Target.def" 1419 } 1420 llvm_unreachable("Invalid CPUKind"); 1421 } 1422 1423 // We can't use a generic validation scheme for the cpus accepted here 1424 // versus subtarget cpus accepted in the target attribute because the 1425 // variables intitialized by the runtime only support the below currently 1426 // rather than the full range of cpus. 1427 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1428 return llvm::StringSwitch<bool>(FeatureStr) 1429 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1430 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1431 .Cases(STR, ALIAS, true) 1432 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1433 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1434 #include "llvm/Support/X86TargetParser.def" 1435 .Default(false); 1436 } 1437 1438 bool X86TargetInfo::validateAsmConstraint( 1439 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1440 switch (*Name) { 1441 default: 1442 return false; 1443 // Constant constraints. 1444 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1445 // instructions. 1446 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1447 // x86_64 instructions. 1448 case 's': 1449 Info.setRequiresImmediate(); 1450 return true; 1451 case 'I': 1452 Info.setRequiresImmediate(0, 31); 1453 return true; 1454 case 'J': 1455 Info.setRequiresImmediate(0, 63); 1456 return true; 1457 case 'K': 1458 Info.setRequiresImmediate(-128, 127); 1459 return true; 1460 case 'L': 1461 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1462 return true; 1463 case 'M': 1464 Info.setRequiresImmediate(0, 3); 1465 return true; 1466 case 'N': 1467 Info.setRequiresImmediate(0, 255); 1468 return true; 1469 case 'O': 1470 Info.setRequiresImmediate(0, 127); 1471 return true; 1472 // Register constraints. 1473 case 'Y': // 'Y' is the first character for several 2-character constraints. 1474 // Shift the pointer to the second character of the constraint. 1475 Name++; 1476 switch (*Name) { 1477 default: 1478 return false; 1479 case 'z': 1480 case '0': // First SSE register. 1481 case '2': 1482 case 't': // Any SSE register, when SSE2 is enabled. 1483 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1484 case 'm': // Any MMX register, when inter-unit moves enabled. 1485 case 'k': // AVX512 arch mask registers: k1-k7. 1486 Info.setAllowsRegister(); 1487 return true; 1488 } 1489 case 'f': // Any x87 floating point stack register. 1490 // Constraint 'f' cannot be used for output operands. 1491 if (Info.ConstraintStr[0] == '=') 1492 return false; 1493 Info.setAllowsRegister(); 1494 return true; 1495 case 'a': // eax. 1496 case 'b': // ebx. 1497 case 'c': // ecx. 1498 case 'd': // edx. 1499 case 'S': // esi. 1500 case 'D': // edi. 1501 case 'A': // edx:eax. 1502 case 't': // Top of floating point stack. 1503 case 'u': // Second from top of floating point stack. 1504 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1505 case 'y': // Any MMX register. 1506 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1507 case 'x': // Any SSE register. 1508 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1509 // for intermideate k reg operations). 1510 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1511 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1512 case 'l': // "Index" registers: any general register that can be used as an 1513 // index in a base+index memory access. 1514 Info.setAllowsRegister(); 1515 return true; 1516 // Floating point constant constraints. 1517 case 'C': // SSE floating point constant. 1518 case 'G': // x87 floating point constant. 1519 return true; 1520 } 1521 } 1522 1523 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1524 unsigned Size) const { 1525 // Strip off constraint modifiers. 1526 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1527 Constraint = Constraint.substr(1); 1528 1529 return validateOperandSize(Constraint, Size); 1530 } 1531 1532 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1533 unsigned Size) const { 1534 return validateOperandSize(Constraint, Size); 1535 } 1536 1537 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1538 unsigned Size) const { 1539 switch (Constraint[0]) { 1540 default: 1541 break; 1542 case 'k': 1543 // Registers k0-k7 (AVX512) size limit is 64 bit. 1544 case 'y': 1545 return Size <= 64; 1546 case 'f': 1547 case 't': 1548 case 'u': 1549 return Size <= 128; 1550 case 'Y': 1551 // 'Y' is the first character for several 2-character constraints. 1552 switch (Constraint[1]) { 1553 default: 1554 return false; 1555 case 'm': 1556 // 'Ym' is synonymous with 'y'. 1557 case 'k': 1558 return Size <= 64; 1559 case 'z': 1560 case '0': 1561 // XMM0 1562 if (SSELevel >= SSE1) 1563 return Size <= 128U; 1564 return false; 1565 case 'i': 1566 case 't': 1567 case '2': 1568 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1569 if (SSELevel < SSE2) 1570 return false; 1571 break; 1572 } 1573 case 'v': 1574 case 'x': 1575 if (SSELevel >= AVX512F) 1576 // 512-bit zmm registers can be used if target supports AVX512F. 1577 return Size <= 512U; 1578 else if (SSELevel >= AVX) 1579 // 256-bit ymm registers can be used if target supports AVX. 1580 return Size <= 256U; 1581 return Size <= 128U; 1582 1583 } 1584 1585 return true; 1586 } 1587 1588 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1589 switch (*Constraint) { 1590 case 'a': 1591 return std::string("{ax}"); 1592 case 'b': 1593 return std::string("{bx}"); 1594 case 'c': 1595 return std::string("{cx}"); 1596 case 'd': 1597 return std::string("{dx}"); 1598 case 'S': 1599 return std::string("{si}"); 1600 case 'D': 1601 return std::string("{di}"); 1602 case 'p': // address 1603 return std::string("im"); 1604 case 't': // top of floating point stack. 1605 return std::string("{st}"); 1606 case 'u': // second from top of floating point stack. 1607 return std::string("{st(1)}"); // second from top of floating point stack. 1608 case 'Y': 1609 switch (Constraint[1]) { 1610 default: 1611 // Break from inner switch and fall through (copy single char), 1612 // continue parsing after copying the current constraint into 1613 // the return string. 1614 break; 1615 case 'k': 1616 case 'm': 1617 case 'i': 1618 case 't': 1619 case 'z': 1620 case '0': 1621 case '2': 1622 // "^" hints llvm that this is a 2 letter constraint. 1623 // "Constraint++" is used to promote the string iterator 1624 // to the next constraint. 1625 return std::string("^") + std::string(Constraint++, 2); 1626 } 1627 LLVM_FALLTHROUGH; 1628 default: 1629 return std::string(1, *Constraint); 1630 } 1631 } 1632 1633 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1634 // Perform any per-CPU checks necessary to determine if this CPU is 1635 // acceptable. 1636 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1637 // invalid without explaining *why*. 1638 switch (Kind) { 1639 case CK_Generic: 1640 // No processor selected! 1641 return false; 1642 #define PROC(ENUM, STRING, IS64BIT) \ 1643 case CK_##ENUM: \ 1644 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1645 #include "clang/Basic/X86Target.def" 1646 } 1647 llvm_unreachable("Unhandled CPU kind"); 1648 } 1649 1650 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1651 return llvm::StringSwitch<CPUKind>(CPU) 1652 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1653 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1654 #include "clang/Basic/X86Target.def" 1655 .Default(CK_Generic); 1656 } 1657 1658 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1659 return llvm::makeArrayRef(GCCRegNames); 1660 } 1661 1662 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1663 return llvm::makeArrayRef(AddlRegNames); 1664 } 1665 1666 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1667 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1668 Builtin::FirstTSBuiltin + 1); 1669 } 1670 1671 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1672 return llvm::makeArrayRef(BuiltinInfoX86, 1673 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1674 } 1675