1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 } else if (Feature == "+avx512pf") { 243 HasAVX512PF = true; 244 } else if (Feature == "+avx512dq") { 245 HasAVX512DQ = true; 246 } else if (Feature == "+avx512bitalg") { 247 HasAVX512BITALG = true; 248 } else if (Feature == "+avx512bw") { 249 HasAVX512BW = true; 250 } else if (Feature == "+avx512vl") { 251 HasAVX512VL = true; 252 } else if (Feature == "+avx512vbmi") { 253 HasAVX512VBMI = true; 254 } else if (Feature == "+avx512vbmi2") { 255 HasAVX512VBMI2 = true; 256 } else if (Feature == "+avx512ifma") { 257 HasAVX512IFMA = true; 258 } else if (Feature == "+avx512vp2intersect") { 259 HasAVX512VP2INTERSECT = true; 260 } else if (Feature == "+sha") { 261 HasSHA = true; 262 } else if (Feature == "+shstk") { 263 HasSHSTK = true; 264 } else if (Feature == "+movbe") { 265 HasMOVBE = true; 266 } else if (Feature == "+sgx") { 267 HasSGX = true; 268 } else if (Feature == "+cx8") { 269 HasCX8 = true; 270 } else if (Feature == "+cx16") { 271 HasCX16 = true; 272 } else if (Feature == "+fxsr") { 273 HasFXSR = true; 274 } else if (Feature == "+xsave") { 275 HasXSAVE = true; 276 } else if (Feature == "+xsaveopt") { 277 HasXSAVEOPT = true; 278 } else if (Feature == "+xsavec") { 279 HasXSAVEC = true; 280 } else if (Feature == "+xsaves") { 281 HasXSAVES = true; 282 } else if (Feature == "+mwaitx") { 283 HasMWAITX = true; 284 } else if (Feature == "+pku") { 285 HasPKU = true; 286 } else if (Feature == "+clflushopt") { 287 HasCLFLUSHOPT = true; 288 } else if (Feature == "+clwb") { 289 HasCLWB = true; 290 } else if (Feature == "+wbnoinvd") { 291 HasWBNOINVD = true; 292 } else if (Feature == "+prefetchwt1") { 293 HasPREFETCHWT1 = true; 294 } else if (Feature == "+clzero") { 295 HasCLZERO = true; 296 } else if (Feature == "+cldemote") { 297 HasCLDEMOTE = true; 298 } else if (Feature == "+rdpid") { 299 HasRDPID = true; 300 } else if (Feature == "+kl") { 301 HasKL = true; 302 } else if (Feature == "+widekl") { 303 HasWIDEKL = true; 304 } else if (Feature == "+retpoline-external-thunk") { 305 HasRetpolineExternalThunk = true; 306 } else if (Feature == "+sahf") { 307 HasLAHFSAHF = true; 308 } else if (Feature == "+waitpkg") { 309 HasWAITPKG = true; 310 } else if (Feature == "+movdiri") { 311 HasMOVDIRI = true; 312 } else if (Feature == "+movdir64b") { 313 HasMOVDIR64B = true; 314 } else if (Feature == "+pconfig") { 315 HasPCONFIG = true; 316 } else if (Feature == "+ptwrite") { 317 HasPTWRITE = true; 318 } else if (Feature == "+invpcid") { 319 HasINVPCID = true; 320 } else if (Feature == "+enqcmd") { 321 HasENQCMD = true; 322 } else if (Feature == "+hreset") { 323 HasHRESET = true; 324 } else if (Feature == "+amx-bf16") { 325 HasAMXBF16 = true; 326 } else if (Feature == "+amx-int8") { 327 HasAMXINT8 = true; 328 } else if (Feature == "+amx-tile") { 329 HasAMXTILE = true; 330 } else if (Feature == "+avxvnni") { 331 HasAVXVNNI = true; 332 } else if (Feature == "+serialize") { 333 HasSERIALIZE = true; 334 } else if (Feature == "+tsxldtrk") { 335 HasTSXLDTRK = true; 336 } else if (Feature == "+uintr") { 337 HasUINTR = true; 338 } else if (Feature == "+crc32") { 339 HasCRC32 = true; 340 } else if (Feature == "+x87") { 341 HasX87 = true; 342 } 343 344 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 345 .Case("+avx512f", AVX512F) 346 .Case("+avx2", AVX2) 347 .Case("+avx", AVX) 348 .Case("+sse4.2", SSE42) 349 .Case("+sse4.1", SSE41) 350 .Case("+ssse3", SSSE3) 351 .Case("+sse3", SSE3) 352 .Case("+sse2", SSE2) 353 .Case("+sse", SSE1) 354 .Default(NoSSE); 355 SSELevel = std::max(SSELevel, Level); 356 357 HasFloat16 = SSELevel >= SSE2; 358 359 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 360 .Case("+3dnowa", AMD3DNowAthlon) 361 .Case("+3dnow", AMD3DNow) 362 .Case("+mmx", MMX) 363 .Default(NoMMX3DNow); 364 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 365 366 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 367 .Case("+xop", XOP) 368 .Case("+fma4", FMA4) 369 .Case("+sse4a", SSE4A) 370 .Default(NoXOP); 371 XOPLevel = std::max(XOPLevel, XLevel); 372 } 373 374 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 375 // matches the selected sse level. 376 if ((FPMath == FP_SSE && SSELevel < SSE1) || 377 (FPMath == FP_387 && SSELevel >= SSE1)) { 378 Diags.Report(diag::err_target_unsupported_fpmath) 379 << (FPMath == FP_SSE ? "sse" : "387"); 380 return false; 381 } 382 383 SimdDefaultAlign = 384 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 385 386 // FIXME: We should allow long double type on 32-bits to match with GCC. 387 // This requires backend to be able to lower f80 without x87 first. 388 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 389 HasLongDouble = false; 390 391 return true; 392 } 393 394 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 395 /// definitions for this particular subtarget. 396 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 397 MacroBuilder &Builder) const { 398 // Inline assembly supports X86 flag outputs. 399 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 400 401 std::string CodeModel = getTargetOpts().CodeModel; 402 if (CodeModel == "default") 403 CodeModel = "small"; 404 Builder.defineMacro("__code_model_" + CodeModel + "__"); 405 406 // Target identification. 407 if (getTriple().getArch() == llvm::Triple::x86_64) { 408 Builder.defineMacro("__amd64__"); 409 Builder.defineMacro("__amd64"); 410 Builder.defineMacro("__x86_64"); 411 Builder.defineMacro("__x86_64__"); 412 if (getTriple().getArchName() == "x86_64h") { 413 Builder.defineMacro("__x86_64h"); 414 Builder.defineMacro("__x86_64h__"); 415 } 416 } else { 417 DefineStd(Builder, "i386", Opts); 418 } 419 420 Builder.defineMacro("__SEG_GS"); 421 Builder.defineMacro("__SEG_FS"); 422 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 423 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 424 425 // Subtarget options. 426 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 427 // truly should be based on -mtune options. 428 using namespace llvm::X86; 429 switch (CPU) { 430 case CK_None: 431 break; 432 case CK_i386: 433 // The rest are coming from the i386 define above. 434 Builder.defineMacro("__tune_i386__"); 435 break; 436 case CK_i486: 437 case CK_WinChipC6: 438 case CK_WinChip2: 439 case CK_C3: 440 defineCPUMacros(Builder, "i486"); 441 break; 442 case CK_PentiumMMX: 443 Builder.defineMacro("__pentium_mmx__"); 444 Builder.defineMacro("__tune_pentium_mmx__"); 445 LLVM_FALLTHROUGH; 446 case CK_i586: 447 case CK_Pentium: 448 defineCPUMacros(Builder, "i586"); 449 defineCPUMacros(Builder, "pentium"); 450 break; 451 case CK_Pentium3: 452 case CK_PentiumM: 453 Builder.defineMacro("__tune_pentium3__"); 454 LLVM_FALLTHROUGH; 455 case CK_Pentium2: 456 case CK_C3_2: 457 Builder.defineMacro("__tune_pentium2__"); 458 LLVM_FALLTHROUGH; 459 case CK_PentiumPro: 460 case CK_i686: 461 defineCPUMacros(Builder, "i686"); 462 defineCPUMacros(Builder, "pentiumpro"); 463 break; 464 case CK_Pentium4: 465 defineCPUMacros(Builder, "pentium4"); 466 break; 467 case CK_Yonah: 468 case CK_Prescott: 469 case CK_Nocona: 470 defineCPUMacros(Builder, "nocona"); 471 break; 472 case CK_Core2: 473 case CK_Penryn: 474 defineCPUMacros(Builder, "core2"); 475 break; 476 case CK_Bonnell: 477 defineCPUMacros(Builder, "atom"); 478 break; 479 case CK_Silvermont: 480 defineCPUMacros(Builder, "slm"); 481 break; 482 case CK_Goldmont: 483 defineCPUMacros(Builder, "goldmont"); 484 break; 485 case CK_GoldmontPlus: 486 defineCPUMacros(Builder, "goldmont_plus"); 487 break; 488 case CK_Tremont: 489 defineCPUMacros(Builder, "tremont"); 490 break; 491 case CK_Nehalem: 492 case CK_Westmere: 493 case CK_SandyBridge: 494 case CK_IvyBridge: 495 case CK_Haswell: 496 case CK_Broadwell: 497 case CK_SkylakeClient: 498 case CK_SkylakeServer: 499 case CK_Cascadelake: 500 case CK_Cooperlake: 501 case CK_Cannonlake: 502 case CK_IcelakeClient: 503 case CK_Rocketlake: 504 case CK_IcelakeServer: 505 case CK_Tigerlake: 506 case CK_SapphireRapids: 507 case CK_Alderlake: 508 // FIXME: Historically, we defined this legacy name, it would be nice to 509 // remove it at some point. We've never exposed fine-grained names for 510 // recent primary x86 CPUs, and we should keep it that way. 511 defineCPUMacros(Builder, "corei7"); 512 break; 513 case CK_KNL: 514 defineCPUMacros(Builder, "knl"); 515 break; 516 case CK_KNM: 517 break; 518 case CK_Lakemont: 519 defineCPUMacros(Builder, "i586", /*Tuning*/false); 520 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 521 Builder.defineMacro("__tune_lakemont__"); 522 break; 523 case CK_K6_2: 524 Builder.defineMacro("__k6_2__"); 525 Builder.defineMacro("__tune_k6_2__"); 526 LLVM_FALLTHROUGH; 527 case CK_K6_3: 528 if (CPU != CK_K6_2) { // In case of fallthrough 529 // FIXME: GCC may be enabling these in cases where some other k6 530 // architecture is specified but -m3dnow is explicitly provided. The 531 // exact semantics need to be determined and emulated here. 532 Builder.defineMacro("__k6_3__"); 533 Builder.defineMacro("__tune_k6_3__"); 534 } 535 LLVM_FALLTHROUGH; 536 case CK_K6: 537 defineCPUMacros(Builder, "k6"); 538 break; 539 case CK_Athlon: 540 case CK_AthlonXP: 541 defineCPUMacros(Builder, "athlon"); 542 if (SSELevel != NoSSE) { 543 Builder.defineMacro("__athlon_sse__"); 544 Builder.defineMacro("__tune_athlon_sse__"); 545 } 546 break; 547 case CK_K8: 548 case CK_K8SSE3: 549 case CK_x86_64: 550 defineCPUMacros(Builder, "k8"); 551 break; 552 case CK_x86_64_v2: 553 case CK_x86_64_v3: 554 case CK_x86_64_v4: 555 break; 556 case CK_AMDFAM10: 557 defineCPUMacros(Builder, "amdfam10"); 558 break; 559 case CK_BTVER1: 560 defineCPUMacros(Builder, "btver1"); 561 break; 562 case CK_BTVER2: 563 defineCPUMacros(Builder, "btver2"); 564 break; 565 case CK_BDVER1: 566 defineCPUMacros(Builder, "bdver1"); 567 break; 568 case CK_BDVER2: 569 defineCPUMacros(Builder, "bdver2"); 570 break; 571 case CK_BDVER3: 572 defineCPUMacros(Builder, "bdver3"); 573 break; 574 case CK_BDVER4: 575 defineCPUMacros(Builder, "bdver4"); 576 break; 577 case CK_ZNVER1: 578 defineCPUMacros(Builder, "znver1"); 579 break; 580 case CK_ZNVER2: 581 defineCPUMacros(Builder, "znver2"); 582 break; 583 case CK_ZNVER3: 584 defineCPUMacros(Builder, "znver3"); 585 break; 586 case CK_Geode: 587 defineCPUMacros(Builder, "geode"); 588 break; 589 } 590 591 // Target properties. 592 Builder.defineMacro("__REGISTER_PREFIX__", ""); 593 594 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 595 // functions in glibc header files that use FP Stack inline asm which the 596 // backend can't deal with (PR879). 597 Builder.defineMacro("__NO_MATH_INLINES"); 598 599 if (HasAES) 600 Builder.defineMacro("__AES__"); 601 602 if (HasVAES) 603 Builder.defineMacro("__VAES__"); 604 605 if (HasPCLMUL) 606 Builder.defineMacro("__PCLMUL__"); 607 608 if (HasVPCLMULQDQ) 609 Builder.defineMacro("__VPCLMULQDQ__"); 610 611 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 612 // the feature flag only applies to 64-bit mode. 613 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 614 Builder.defineMacro("__LAHF_SAHF__"); 615 616 if (HasLZCNT) 617 Builder.defineMacro("__LZCNT__"); 618 619 if (HasRDRND) 620 Builder.defineMacro("__RDRND__"); 621 622 if (HasFSGSBASE) 623 Builder.defineMacro("__FSGSBASE__"); 624 625 if (HasBMI) 626 Builder.defineMacro("__BMI__"); 627 628 if (HasBMI2) 629 Builder.defineMacro("__BMI2__"); 630 631 if (HasPOPCNT) 632 Builder.defineMacro("__POPCNT__"); 633 634 if (HasRTM) 635 Builder.defineMacro("__RTM__"); 636 637 if (HasPRFCHW) 638 Builder.defineMacro("__PRFCHW__"); 639 640 if (HasRDSEED) 641 Builder.defineMacro("__RDSEED__"); 642 643 if (HasADX) 644 Builder.defineMacro("__ADX__"); 645 646 if (HasTBM) 647 Builder.defineMacro("__TBM__"); 648 649 if (HasLWP) 650 Builder.defineMacro("__LWP__"); 651 652 if (HasMWAITX) 653 Builder.defineMacro("__MWAITX__"); 654 655 if (HasMOVBE) 656 Builder.defineMacro("__MOVBE__"); 657 658 switch (XOPLevel) { 659 case XOP: 660 Builder.defineMacro("__XOP__"); 661 LLVM_FALLTHROUGH; 662 case FMA4: 663 Builder.defineMacro("__FMA4__"); 664 LLVM_FALLTHROUGH; 665 case SSE4A: 666 Builder.defineMacro("__SSE4A__"); 667 LLVM_FALLTHROUGH; 668 case NoXOP: 669 break; 670 } 671 672 if (HasFMA) 673 Builder.defineMacro("__FMA__"); 674 675 if (HasF16C) 676 Builder.defineMacro("__F16C__"); 677 678 if (HasGFNI) 679 Builder.defineMacro("__GFNI__"); 680 681 if (HasAVX512CD) 682 Builder.defineMacro("__AVX512CD__"); 683 if (HasAVX512VPOPCNTDQ) 684 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 685 if (HasAVX512VNNI) 686 Builder.defineMacro("__AVX512VNNI__"); 687 if (HasAVX512BF16) 688 Builder.defineMacro("__AVX512BF16__"); 689 if (HasAVX512ER) 690 Builder.defineMacro("__AVX512ER__"); 691 if (HasAVX512FP16) 692 Builder.defineMacro("__AVX512FP16__"); 693 if (HasAVX512PF) 694 Builder.defineMacro("__AVX512PF__"); 695 if (HasAVX512DQ) 696 Builder.defineMacro("__AVX512DQ__"); 697 if (HasAVX512BITALG) 698 Builder.defineMacro("__AVX512BITALG__"); 699 if (HasAVX512BW) 700 Builder.defineMacro("__AVX512BW__"); 701 if (HasAVX512VL) 702 Builder.defineMacro("__AVX512VL__"); 703 if (HasAVX512VBMI) 704 Builder.defineMacro("__AVX512VBMI__"); 705 if (HasAVX512VBMI2) 706 Builder.defineMacro("__AVX512VBMI2__"); 707 if (HasAVX512IFMA) 708 Builder.defineMacro("__AVX512IFMA__"); 709 if (HasAVX512VP2INTERSECT) 710 Builder.defineMacro("__AVX512VP2INTERSECT__"); 711 if (HasSHA) 712 Builder.defineMacro("__SHA__"); 713 714 if (HasFXSR) 715 Builder.defineMacro("__FXSR__"); 716 if (HasXSAVE) 717 Builder.defineMacro("__XSAVE__"); 718 if (HasXSAVEOPT) 719 Builder.defineMacro("__XSAVEOPT__"); 720 if (HasXSAVEC) 721 Builder.defineMacro("__XSAVEC__"); 722 if (HasXSAVES) 723 Builder.defineMacro("__XSAVES__"); 724 if (HasPKU) 725 Builder.defineMacro("__PKU__"); 726 if (HasCLFLUSHOPT) 727 Builder.defineMacro("__CLFLUSHOPT__"); 728 if (HasCLWB) 729 Builder.defineMacro("__CLWB__"); 730 if (HasWBNOINVD) 731 Builder.defineMacro("__WBNOINVD__"); 732 if (HasSHSTK) 733 Builder.defineMacro("__SHSTK__"); 734 if (HasSGX) 735 Builder.defineMacro("__SGX__"); 736 if (HasPREFETCHWT1) 737 Builder.defineMacro("__PREFETCHWT1__"); 738 if (HasCLZERO) 739 Builder.defineMacro("__CLZERO__"); 740 if (HasKL) 741 Builder.defineMacro("__KL__"); 742 if (HasWIDEKL) 743 Builder.defineMacro("__WIDEKL__"); 744 if (HasRDPID) 745 Builder.defineMacro("__RDPID__"); 746 if (HasCLDEMOTE) 747 Builder.defineMacro("__CLDEMOTE__"); 748 if (HasWAITPKG) 749 Builder.defineMacro("__WAITPKG__"); 750 if (HasMOVDIRI) 751 Builder.defineMacro("__MOVDIRI__"); 752 if (HasMOVDIR64B) 753 Builder.defineMacro("__MOVDIR64B__"); 754 if (HasPCONFIG) 755 Builder.defineMacro("__PCONFIG__"); 756 if (HasPTWRITE) 757 Builder.defineMacro("__PTWRITE__"); 758 if (HasINVPCID) 759 Builder.defineMacro("__INVPCID__"); 760 if (HasENQCMD) 761 Builder.defineMacro("__ENQCMD__"); 762 if (HasHRESET) 763 Builder.defineMacro("__HRESET__"); 764 if (HasAMXTILE) 765 Builder.defineMacro("__AMXTILE__"); 766 if (HasAMXINT8) 767 Builder.defineMacro("__AMXINT8__"); 768 if (HasAMXBF16) 769 Builder.defineMacro("__AMXBF16__"); 770 if (HasAVXVNNI) 771 Builder.defineMacro("__AVXVNNI__"); 772 if (HasSERIALIZE) 773 Builder.defineMacro("__SERIALIZE__"); 774 if (HasTSXLDTRK) 775 Builder.defineMacro("__TSXLDTRK__"); 776 if (HasUINTR) 777 Builder.defineMacro("__UINTR__"); 778 if (HasCRC32) 779 Builder.defineMacro("__CRC32__"); 780 781 // Each case falls through to the previous one here. 782 switch (SSELevel) { 783 case AVX512F: 784 Builder.defineMacro("__AVX512F__"); 785 LLVM_FALLTHROUGH; 786 case AVX2: 787 Builder.defineMacro("__AVX2__"); 788 LLVM_FALLTHROUGH; 789 case AVX: 790 Builder.defineMacro("__AVX__"); 791 LLVM_FALLTHROUGH; 792 case SSE42: 793 Builder.defineMacro("__SSE4_2__"); 794 LLVM_FALLTHROUGH; 795 case SSE41: 796 Builder.defineMacro("__SSE4_1__"); 797 LLVM_FALLTHROUGH; 798 case SSSE3: 799 Builder.defineMacro("__SSSE3__"); 800 LLVM_FALLTHROUGH; 801 case SSE3: 802 Builder.defineMacro("__SSE3__"); 803 LLVM_FALLTHROUGH; 804 case SSE2: 805 Builder.defineMacro("__SSE2__"); 806 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 807 LLVM_FALLTHROUGH; 808 case SSE1: 809 Builder.defineMacro("__SSE__"); 810 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 811 LLVM_FALLTHROUGH; 812 case NoSSE: 813 break; 814 } 815 816 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 817 switch (SSELevel) { 818 case AVX512F: 819 case AVX2: 820 case AVX: 821 case SSE42: 822 case SSE41: 823 case SSSE3: 824 case SSE3: 825 case SSE2: 826 Builder.defineMacro("_M_IX86_FP", Twine(2)); 827 break; 828 case SSE1: 829 Builder.defineMacro("_M_IX86_FP", Twine(1)); 830 break; 831 default: 832 Builder.defineMacro("_M_IX86_FP", Twine(0)); 833 break; 834 } 835 } 836 837 // Each case falls through to the previous one here. 838 switch (MMX3DNowLevel) { 839 case AMD3DNowAthlon: 840 Builder.defineMacro("__3dNOW_A__"); 841 LLVM_FALLTHROUGH; 842 case AMD3DNow: 843 Builder.defineMacro("__3dNOW__"); 844 LLVM_FALLTHROUGH; 845 case MMX: 846 Builder.defineMacro("__MMX__"); 847 LLVM_FALLTHROUGH; 848 case NoMMX3DNow: 849 break; 850 } 851 852 if (CPU >= CK_i486 || CPU == CK_None) { 853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 854 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 855 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 856 } 857 if (HasCX8) 858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 859 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 860 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 861 862 if (HasFloat128) 863 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 864 } 865 866 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 867 return llvm::StringSwitch<bool>(Name) 868 .Case("3dnow", true) 869 .Case("3dnowa", true) 870 .Case("adx", true) 871 .Case("aes", true) 872 .Case("amx-bf16", true) 873 .Case("amx-int8", true) 874 .Case("amx-tile", true) 875 .Case("avx", true) 876 .Case("avx2", true) 877 .Case("avx512f", true) 878 .Case("avx512cd", true) 879 .Case("avx512vpopcntdq", true) 880 .Case("avx512vnni", true) 881 .Case("avx512bf16", true) 882 .Case("avx512er", true) 883 .Case("avx512fp16", true) 884 .Case("avx512pf", true) 885 .Case("avx512dq", true) 886 .Case("avx512bitalg", true) 887 .Case("avx512bw", true) 888 .Case("avx512vl", true) 889 .Case("avx512vbmi", true) 890 .Case("avx512vbmi2", true) 891 .Case("avx512ifma", true) 892 .Case("avx512vp2intersect", true) 893 .Case("avxvnni", true) 894 .Case("bmi", true) 895 .Case("bmi2", true) 896 .Case("cldemote", true) 897 .Case("clflushopt", true) 898 .Case("clwb", true) 899 .Case("clzero", true) 900 .Case("crc32", true) 901 .Case("cx16", true) 902 .Case("enqcmd", true) 903 .Case("f16c", true) 904 .Case("fma", true) 905 .Case("fma4", true) 906 .Case("fsgsbase", true) 907 .Case("fxsr", true) 908 .Case("general-regs-only", true) 909 .Case("gfni", true) 910 .Case("hreset", true) 911 .Case("invpcid", true) 912 .Case("kl", true) 913 .Case("widekl", true) 914 .Case("lwp", true) 915 .Case("lzcnt", true) 916 .Case("mmx", true) 917 .Case("movbe", true) 918 .Case("movdiri", true) 919 .Case("movdir64b", true) 920 .Case("mwaitx", true) 921 .Case("pclmul", true) 922 .Case("pconfig", true) 923 .Case("pku", true) 924 .Case("popcnt", true) 925 .Case("prefetchwt1", true) 926 .Case("prfchw", true) 927 .Case("ptwrite", true) 928 .Case("rdpid", true) 929 .Case("rdrnd", true) 930 .Case("rdseed", true) 931 .Case("rtm", true) 932 .Case("sahf", true) 933 .Case("serialize", true) 934 .Case("sgx", true) 935 .Case("sha", true) 936 .Case("shstk", true) 937 .Case("sse", true) 938 .Case("sse2", true) 939 .Case("sse3", true) 940 .Case("ssse3", true) 941 .Case("sse4", true) 942 .Case("sse4.1", true) 943 .Case("sse4.2", true) 944 .Case("sse4a", true) 945 .Case("tbm", true) 946 .Case("tsxldtrk", true) 947 .Case("uintr", true) 948 .Case("vaes", true) 949 .Case("vpclmulqdq", true) 950 .Case("wbnoinvd", true) 951 .Case("waitpkg", true) 952 .Case("x87", true) 953 .Case("xop", true) 954 .Case("xsave", true) 955 .Case("xsavec", true) 956 .Case("xsaves", true) 957 .Case("xsaveopt", true) 958 .Default(false); 959 } 960 961 bool X86TargetInfo::hasFeature(StringRef Feature) const { 962 return llvm::StringSwitch<bool>(Feature) 963 .Case("adx", HasADX) 964 .Case("aes", HasAES) 965 .Case("amx-bf16", HasAMXBF16) 966 .Case("amx-int8", HasAMXINT8) 967 .Case("amx-tile", HasAMXTILE) 968 .Case("avxvnni", HasAVXVNNI) 969 .Case("avx", SSELevel >= AVX) 970 .Case("avx2", SSELevel >= AVX2) 971 .Case("avx512f", SSELevel >= AVX512F) 972 .Case("avx512cd", HasAVX512CD) 973 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 974 .Case("avx512vnni", HasAVX512VNNI) 975 .Case("avx512bf16", HasAVX512BF16) 976 .Case("avx512er", HasAVX512ER) 977 .Case("avx512fp16", HasAVX512FP16) 978 .Case("avx512pf", HasAVX512PF) 979 .Case("avx512dq", HasAVX512DQ) 980 .Case("avx512bitalg", HasAVX512BITALG) 981 .Case("avx512bw", HasAVX512BW) 982 .Case("avx512vl", HasAVX512VL) 983 .Case("avx512vbmi", HasAVX512VBMI) 984 .Case("avx512vbmi2", HasAVX512VBMI2) 985 .Case("avx512ifma", HasAVX512IFMA) 986 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 987 .Case("bmi", HasBMI) 988 .Case("bmi2", HasBMI2) 989 .Case("cldemote", HasCLDEMOTE) 990 .Case("clflushopt", HasCLFLUSHOPT) 991 .Case("clwb", HasCLWB) 992 .Case("clzero", HasCLZERO) 993 .Case("crc32", HasCRC32) 994 .Case("cx8", HasCX8) 995 .Case("cx16", HasCX16) 996 .Case("enqcmd", HasENQCMD) 997 .Case("f16c", HasF16C) 998 .Case("fma", HasFMA) 999 .Case("fma4", XOPLevel >= FMA4) 1000 .Case("fsgsbase", HasFSGSBASE) 1001 .Case("fxsr", HasFXSR) 1002 .Case("gfni", HasGFNI) 1003 .Case("hreset", HasHRESET) 1004 .Case("invpcid", HasINVPCID) 1005 .Case("kl", HasKL) 1006 .Case("widekl", HasWIDEKL) 1007 .Case("lwp", HasLWP) 1008 .Case("lzcnt", HasLZCNT) 1009 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1010 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1011 .Case("mmx", MMX3DNowLevel >= MMX) 1012 .Case("movbe", HasMOVBE) 1013 .Case("movdiri", HasMOVDIRI) 1014 .Case("movdir64b", HasMOVDIR64B) 1015 .Case("mwaitx", HasMWAITX) 1016 .Case("pclmul", HasPCLMUL) 1017 .Case("pconfig", HasPCONFIG) 1018 .Case("pku", HasPKU) 1019 .Case("popcnt", HasPOPCNT) 1020 .Case("prefetchwt1", HasPREFETCHWT1) 1021 .Case("prfchw", HasPRFCHW) 1022 .Case("ptwrite", HasPTWRITE) 1023 .Case("rdpid", HasRDPID) 1024 .Case("rdrnd", HasRDRND) 1025 .Case("rdseed", HasRDSEED) 1026 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1027 .Case("rtm", HasRTM) 1028 .Case("sahf", HasLAHFSAHF) 1029 .Case("serialize", HasSERIALIZE) 1030 .Case("sgx", HasSGX) 1031 .Case("sha", HasSHA) 1032 .Case("shstk", HasSHSTK) 1033 .Case("sse", SSELevel >= SSE1) 1034 .Case("sse2", SSELevel >= SSE2) 1035 .Case("sse3", SSELevel >= SSE3) 1036 .Case("ssse3", SSELevel >= SSSE3) 1037 .Case("sse4.1", SSELevel >= SSE41) 1038 .Case("sse4.2", SSELevel >= SSE42) 1039 .Case("sse4a", XOPLevel >= SSE4A) 1040 .Case("tbm", HasTBM) 1041 .Case("tsxldtrk", HasTSXLDTRK) 1042 .Case("uintr", HasUINTR) 1043 .Case("vaes", HasVAES) 1044 .Case("vpclmulqdq", HasVPCLMULQDQ) 1045 .Case("wbnoinvd", HasWBNOINVD) 1046 .Case("waitpkg", HasWAITPKG) 1047 .Case("x86", true) 1048 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1049 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1050 .Case("x87", HasX87) 1051 .Case("xop", XOPLevel >= XOP) 1052 .Case("xsave", HasXSAVE) 1053 .Case("xsavec", HasXSAVEC) 1054 .Case("xsaves", HasXSAVES) 1055 .Case("xsaveopt", HasXSAVEOPT) 1056 .Default(false); 1057 } 1058 1059 // We can't use a generic validation scheme for the features accepted here 1060 // versus subtarget features accepted in the target attribute because the 1061 // bitfield structure that's initialized in the runtime only supports the 1062 // below currently rather than the full range of subtarget features. (See 1063 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1064 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1065 return llvm::StringSwitch<bool>(FeatureStr) 1066 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1067 #include "llvm/Support/X86TargetParser.def" 1068 .Default(false); 1069 } 1070 1071 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1072 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1073 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1074 .Case(STR, llvm::X86::FEATURE_##ENUM) 1075 1076 #include "llvm/Support/X86TargetParser.def" 1077 ; 1078 // Note, this function should only be used after ensuring the value is 1079 // correct, so it asserts if the value is out of range. 1080 } 1081 1082 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1083 // Valid CPUs have a 'key feature' that compares just better than its key 1084 // feature. 1085 using namespace llvm::X86; 1086 CPUKind Kind = parseArchX86(Name); 1087 if (Kind != CK_None) { 1088 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1089 return (getFeaturePriority(KeyFeature) << 1) + 1; 1090 } 1091 1092 // Now we know we have a feature, so get its priority and shift it a few so 1093 // that we have sufficient room for the CPUs (above). 1094 return getFeaturePriority(getFeature(Name)) << 1; 1095 } 1096 1097 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1098 return llvm::StringSwitch<bool>(Name) 1099 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true) 1100 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true) 1101 #include "llvm/Support/X86TargetParser.def" 1102 .Default(false); 1103 } 1104 1105 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1106 return llvm::StringSwitch<StringRef>(Name) 1107 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME) 1108 #include "llvm/Support/X86TargetParser.def" 1109 .Default(Name); 1110 } 1111 1112 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1113 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1114 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1115 #include "llvm/Support/X86TargetParser.def" 1116 .Default(0); 1117 } 1118 1119 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1120 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1121 StringRef WholeList = 1122 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1123 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1124 #include "llvm/Support/X86TargetParser.def" 1125 .Default(""); 1126 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1127 } 1128 1129 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const { 1130 return llvm::StringSwitch<StringRef>(Name) 1131 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME) 1132 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME) 1133 #include "llvm/Support/X86TargetParser.def" 1134 .Default(""); 1135 } 1136 1137 // We can't use a generic validation scheme for the cpus accepted here 1138 // versus subtarget cpus accepted in the target attribute because the 1139 // variables intitialized by the runtime only support the below currently 1140 // rather than the full range of cpus. 1141 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1142 return llvm::StringSwitch<bool>(FeatureStr) 1143 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1144 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1145 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1146 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1147 #include "llvm/Support/X86TargetParser.def" 1148 .Default(false); 1149 } 1150 1151 static unsigned matchAsmCCConstraint(const char *&Name) { 1152 auto RV = llvm::StringSwitch<unsigned>(Name) 1153 .Case("@cca", 4) 1154 .Case("@ccae", 5) 1155 .Case("@ccb", 4) 1156 .Case("@ccbe", 5) 1157 .Case("@ccc", 4) 1158 .Case("@cce", 4) 1159 .Case("@ccz", 4) 1160 .Case("@ccg", 4) 1161 .Case("@ccge", 5) 1162 .Case("@ccl", 4) 1163 .Case("@ccle", 5) 1164 .Case("@ccna", 5) 1165 .Case("@ccnae", 6) 1166 .Case("@ccnb", 5) 1167 .Case("@ccnbe", 6) 1168 .Case("@ccnc", 5) 1169 .Case("@ccne", 5) 1170 .Case("@ccnz", 5) 1171 .Case("@ccng", 5) 1172 .Case("@ccnge", 6) 1173 .Case("@ccnl", 5) 1174 .Case("@ccnle", 6) 1175 .Case("@ccno", 5) 1176 .Case("@ccnp", 5) 1177 .Case("@ccns", 5) 1178 .Case("@cco", 4) 1179 .Case("@ccp", 4) 1180 .Case("@ccs", 4) 1181 .Default(0); 1182 return RV; 1183 } 1184 1185 bool X86TargetInfo::validateAsmConstraint( 1186 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1187 switch (*Name) { 1188 default: 1189 return false; 1190 // Constant constraints. 1191 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1192 // instructions. 1193 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1194 // x86_64 instructions. 1195 case 's': 1196 Info.setRequiresImmediate(); 1197 return true; 1198 case 'I': 1199 Info.setRequiresImmediate(0, 31); 1200 return true; 1201 case 'J': 1202 Info.setRequiresImmediate(0, 63); 1203 return true; 1204 case 'K': 1205 Info.setRequiresImmediate(-128, 127); 1206 return true; 1207 case 'L': 1208 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1209 return true; 1210 case 'M': 1211 Info.setRequiresImmediate(0, 3); 1212 return true; 1213 case 'N': 1214 Info.setRequiresImmediate(0, 255); 1215 return true; 1216 case 'O': 1217 Info.setRequiresImmediate(0, 127); 1218 return true; 1219 // Register constraints. 1220 case 'Y': // 'Y' is the first character for several 2-character constraints. 1221 // Shift the pointer to the second character of the constraint. 1222 Name++; 1223 switch (*Name) { 1224 default: 1225 return false; 1226 case 'z': // First SSE register. 1227 case '2': 1228 case 't': // Any SSE register, when SSE2 is enabled. 1229 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1230 case 'm': // Any MMX register, when inter-unit moves enabled. 1231 case 'k': // AVX512 arch mask registers: k1-k7. 1232 Info.setAllowsRegister(); 1233 return true; 1234 } 1235 case 'f': // Any x87 floating point stack register. 1236 // Constraint 'f' cannot be used for output operands. 1237 if (Info.ConstraintStr[0] == '=') 1238 return false; 1239 Info.setAllowsRegister(); 1240 return true; 1241 case 'a': // eax. 1242 case 'b': // ebx. 1243 case 'c': // ecx. 1244 case 'd': // edx. 1245 case 'S': // esi. 1246 case 'D': // edi. 1247 case 'A': // edx:eax. 1248 case 't': // Top of floating point stack. 1249 case 'u': // Second from top of floating point stack. 1250 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1251 case 'y': // Any MMX register. 1252 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1253 case 'x': // Any SSE register. 1254 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1255 // for intermideate k reg operations). 1256 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1257 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1258 case 'l': // "Index" registers: any general register that can be used as an 1259 // index in a base+index memory access. 1260 Info.setAllowsRegister(); 1261 return true; 1262 // Floating point constant constraints. 1263 case 'C': // SSE floating point constant. 1264 case 'G': // x87 floating point constant. 1265 return true; 1266 case '@': 1267 // CC condition changes. 1268 if (auto Len = matchAsmCCConstraint(Name)) { 1269 Name += Len - 1; 1270 Info.setAllowsRegister(); 1271 return true; 1272 } 1273 return false; 1274 } 1275 } 1276 1277 // Below is based on the following information: 1278 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1279 // | Processor Name | Cache Line Size (Bytes) | Source | 1280 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1281 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1282 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1283 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1284 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1285 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1286 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1287 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1288 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1289 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1290 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1291 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1292 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1293 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1294 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1295 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1296 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1297 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1298 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1299 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1300 using namespace llvm::X86; 1301 switch (CPU) { 1302 // i386 1303 case CK_i386: 1304 // i486 1305 case CK_i486: 1306 case CK_WinChipC6: 1307 case CK_WinChip2: 1308 case CK_C3: 1309 // Lakemont 1310 case CK_Lakemont: 1311 return 16; 1312 1313 // i586 1314 case CK_i586: 1315 case CK_Pentium: 1316 case CK_PentiumMMX: 1317 // i686 1318 case CK_PentiumPro: 1319 case CK_i686: 1320 case CK_Pentium2: 1321 case CK_Pentium3: 1322 case CK_PentiumM: 1323 case CK_C3_2: 1324 // K6 1325 case CK_K6: 1326 case CK_K6_2: 1327 case CK_K6_3: 1328 // Geode 1329 case CK_Geode: 1330 return 32; 1331 1332 // Netburst 1333 case CK_Pentium4: 1334 case CK_Prescott: 1335 case CK_Nocona: 1336 // Atom 1337 case CK_Bonnell: 1338 case CK_Silvermont: 1339 case CK_Goldmont: 1340 case CK_GoldmontPlus: 1341 case CK_Tremont: 1342 1343 case CK_Westmere: 1344 case CK_SandyBridge: 1345 case CK_IvyBridge: 1346 case CK_Haswell: 1347 case CK_Broadwell: 1348 case CK_SkylakeClient: 1349 case CK_SkylakeServer: 1350 case CK_Cascadelake: 1351 case CK_Nehalem: 1352 case CK_Cooperlake: 1353 case CK_Cannonlake: 1354 case CK_Tigerlake: 1355 case CK_SapphireRapids: 1356 case CK_IcelakeClient: 1357 case CK_Rocketlake: 1358 case CK_IcelakeServer: 1359 case CK_Alderlake: 1360 case CK_KNL: 1361 case CK_KNM: 1362 // K7 1363 case CK_Athlon: 1364 case CK_AthlonXP: 1365 // K8 1366 case CK_K8: 1367 case CK_K8SSE3: 1368 case CK_AMDFAM10: 1369 // Bobcat 1370 case CK_BTVER1: 1371 case CK_BTVER2: 1372 // Bulldozer 1373 case CK_BDVER1: 1374 case CK_BDVER2: 1375 case CK_BDVER3: 1376 case CK_BDVER4: 1377 // Zen 1378 case CK_ZNVER1: 1379 case CK_ZNVER2: 1380 case CK_ZNVER3: 1381 // Deprecated 1382 case CK_x86_64: 1383 case CK_x86_64_v2: 1384 case CK_x86_64_v3: 1385 case CK_x86_64_v4: 1386 case CK_Yonah: 1387 case CK_Penryn: 1388 case CK_Core2: 1389 return 64; 1390 1391 // The following currently have unknown cache line sizes (but they are probably all 64): 1392 // Core 1393 case CK_None: 1394 return None; 1395 } 1396 llvm_unreachable("Unknown CPU kind"); 1397 } 1398 1399 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1400 StringRef Constraint, 1401 unsigned Size) const { 1402 // Strip off constraint modifiers. 1403 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1404 Constraint = Constraint.substr(1); 1405 1406 return validateOperandSize(FeatureMap, Constraint, Size); 1407 } 1408 1409 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1410 StringRef Constraint, 1411 unsigned Size) const { 1412 return validateOperandSize(FeatureMap, Constraint, Size); 1413 } 1414 1415 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1416 StringRef Constraint, 1417 unsigned Size) const { 1418 switch (Constraint[0]) { 1419 default: 1420 break; 1421 case 'k': 1422 // Registers k0-k7 (AVX512) size limit is 64 bit. 1423 case 'y': 1424 return Size <= 64; 1425 case 'f': 1426 case 't': 1427 case 'u': 1428 return Size <= 128; 1429 case 'Y': 1430 // 'Y' is the first character for several 2-character constraints. 1431 switch (Constraint[1]) { 1432 default: 1433 return false; 1434 case 'm': 1435 // 'Ym' is synonymous with 'y'. 1436 case 'k': 1437 return Size <= 64; 1438 case 'z': 1439 // XMM0/YMM/ZMM0 1440 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1441 // ZMM0 can be used if target supports AVX512F. 1442 return Size <= 512U; 1443 else if (hasFeatureEnabled(FeatureMap, "avx")) 1444 // YMM0 can be used if target supports AVX. 1445 return Size <= 256U; 1446 else if (hasFeatureEnabled(FeatureMap, "sse")) 1447 return Size <= 128U; 1448 return false; 1449 case 'i': 1450 case 't': 1451 case '2': 1452 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1453 if (SSELevel < SSE2) 1454 return false; 1455 break; 1456 } 1457 break; 1458 case 'v': 1459 case 'x': 1460 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1461 // 512-bit zmm registers can be used if target supports AVX512F. 1462 return Size <= 512U; 1463 else if (hasFeatureEnabled(FeatureMap, "avx")) 1464 // 256-bit ymm registers can be used if target supports AVX. 1465 return Size <= 256U; 1466 return Size <= 128U; 1467 1468 } 1469 1470 return true; 1471 } 1472 1473 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1474 switch (*Constraint) { 1475 case '@': 1476 if (auto Len = matchAsmCCConstraint(Constraint)) { 1477 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1478 Constraint += Len - 1; 1479 return Converted; 1480 } 1481 return std::string(1, *Constraint); 1482 case 'a': 1483 return std::string("{ax}"); 1484 case 'b': 1485 return std::string("{bx}"); 1486 case 'c': 1487 return std::string("{cx}"); 1488 case 'd': 1489 return std::string("{dx}"); 1490 case 'S': 1491 return std::string("{si}"); 1492 case 'D': 1493 return std::string("{di}"); 1494 case 'p': // Keep 'p' constraint (address). 1495 return std::string("p"); 1496 case 't': // top of floating point stack. 1497 return std::string("{st}"); 1498 case 'u': // second from top of floating point stack. 1499 return std::string("{st(1)}"); // second from top of floating point stack. 1500 case 'Y': 1501 switch (Constraint[1]) { 1502 default: 1503 // Break from inner switch and fall through (copy single char), 1504 // continue parsing after copying the current constraint into 1505 // the return string. 1506 break; 1507 case 'k': 1508 case 'm': 1509 case 'i': 1510 case 't': 1511 case 'z': 1512 case '2': 1513 // "^" hints llvm that this is a 2 letter constraint. 1514 // "Constraint++" is used to promote the string iterator 1515 // to the next constraint. 1516 return std::string("^") + std::string(Constraint++, 2); 1517 } 1518 LLVM_FALLTHROUGH; 1519 default: 1520 return std::string(1, *Constraint); 1521 } 1522 } 1523 1524 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1525 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1526 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1527 } 1528 1529 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1530 llvm::X86::fillValidTuneCPUList(Values); 1531 } 1532 1533 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1534 return llvm::makeArrayRef(GCCRegNames); 1535 } 1536 1537 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1538 return llvm::makeArrayRef(AddlRegNames); 1539 } 1540 1541 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1542 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1543 Builtin::FirstTSBuiltin + 1); 1544 } 1545 1546 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1547 return llvm::makeArrayRef(BuiltinInfoX86, 1548 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1549 } 1550