1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 HasFloat16 = true; 243 } else if (Feature == "+avx512pf") { 244 HasAVX512PF = true; 245 } else if (Feature == "+avx512dq") { 246 HasAVX512DQ = true; 247 } else if (Feature == "+avx512bitalg") { 248 HasAVX512BITALG = true; 249 } else if (Feature == "+avx512bw") { 250 HasAVX512BW = true; 251 } else if (Feature == "+avx512vl") { 252 HasAVX512VL = true; 253 } else if (Feature == "+avx512vbmi") { 254 HasAVX512VBMI = true; 255 } else if (Feature == "+avx512vbmi2") { 256 HasAVX512VBMI2 = true; 257 } else if (Feature == "+avx512ifma") { 258 HasAVX512IFMA = true; 259 } else if (Feature == "+avx512vp2intersect") { 260 HasAVX512VP2INTERSECT = true; 261 } else if (Feature == "+sha") { 262 HasSHA = true; 263 } else if (Feature == "+shstk") { 264 HasSHSTK = true; 265 } else if (Feature == "+movbe") { 266 HasMOVBE = true; 267 } else if (Feature == "+sgx") { 268 HasSGX = true; 269 } else if (Feature == "+cx8") { 270 HasCX8 = true; 271 } else if (Feature == "+cx16") { 272 HasCX16 = true; 273 } else if (Feature == "+fxsr") { 274 HasFXSR = true; 275 } else if (Feature == "+xsave") { 276 HasXSAVE = true; 277 } else if (Feature == "+xsaveopt") { 278 HasXSAVEOPT = true; 279 } else if (Feature == "+xsavec") { 280 HasXSAVEC = true; 281 } else if (Feature == "+xsaves") { 282 HasXSAVES = true; 283 } else if (Feature == "+mwaitx") { 284 HasMWAITX = true; 285 } else if (Feature == "+pku") { 286 HasPKU = true; 287 } else if (Feature == "+clflushopt") { 288 HasCLFLUSHOPT = true; 289 } else if (Feature == "+clwb") { 290 HasCLWB = true; 291 } else if (Feature == "+wbnoinvd") { 292 HasWBNOINVD = true; 293 } else if (Feature == "+prefetchwt1") { 294 HasPREFETCHWT1 = true; 295 } else if (Feature == "+clzero") { 296 HasCLZERO = true; 297 } else if (Feature == "+cldemote") { 298 HasCLDEMOTE = true; 299 } else if (Feature == "+rdpid") { 300 HasRDPID = true; 301 } else if (Feature == "+kl") { 302 HasKL = true; 303 } else if (Feature == "+widekl") { 304 HasWIDEKL = true; 305 } else if (Feature == "+retpoline-external-thunk") { 306 HasRetpolineExternalThunk = true; 307 } else if (Feature == "+sahf") { 308 HasLAHFSAHF = true; 309 } else if (Feature == "+waitpkg") { 310 HasWAITPKG = true; 311 } else if (Feature == "+movdiri") { 312 HasMOVDIRI = true; 313 } else if (Feature == "+movdir64b") { 314 HasMOVDIR64B = true; 315 } else if (Feature == "+pconfig") { 316 HasPCONFIG = true; 317 } else if (Feature == "+ptwrite") { 318 HasPTWRITE = true; 319 } else if (Feature == "+invpcid") { 320 HasINVPCID = true; 321 } else if (Feature == "+enqcmd") { 322 HasENQCMD = true; 323 } else if (Feature == "+hreset") { 324 HasHRESET = true; 325 } else if (Feature == "+amx-bf16") { 326 HasAMXBF16 = true; 327 } else if (Feature == "+amx-int8") { 328 HasAMXINT8 = true; 329 } else if (Feature == "+amx-tile") { 330 HasAMXTILE = true; 331 } else if (Feature == "+avxvnni") { 332 HasAVXVNNI = true; 333 } else if (Feature == "+serialize") { 334 HasSERIALIZE = true; 335 } else if (Feature == "+tsxldtrk") { 336 HasTSXLDTRK = true; 337 } else if (Feature == "+uintr") { 338 HasUINTR = true; 339 } else if (Feature == "+crc32") { 340 HasCRC32 = true; 341 } 342 343 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 344 .Case("+avx512f", AVX512F) 345 .Case("+avx2", AVX2) 346 .Case("+avx", AVX) 347 .Case("+sse4.2", SSE42) 348 .Case("+sse4.1", SSE41) 349 .Case("+ssse3", SSSE3) 350 .Case("+sse3", SSE3) 351 .Case("+sse2", SSE2) 352 .Case("+sse", SSE1) 353 .Default(NoSSE); 354 SSELevel = std::max(SSELevel, Level); 355 356 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 357 .Case("+3dnowa", AMD3DNowAthlon) 358 .Case("+3dnow", AMD3DNow) 359 .Case("+mmx", MMX) 360 .Default(NoMMX3DNow); 361 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 362 363 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 364 .Case("+xop", XOP) 365 .Case("+fma4", FMA4) 366 .Case("+sse4a", SSE4A) 367 .Default(NoXOP); 368 XOPLevel = std::max(XOPLevel, XLevel); 369 } 370 371 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 372 // matches the selected sse level. 373 if ((FPMath == FP_SSE && SSELevel < SSE1) || 374 (FPMath == FP_387 && SSELevel >= SSE1)) { 375 Diags.Report(diag::err_target_unsupported_fpmath) 376 << (FPMath == FP_SSE ? "sse" : "387"); 377 return false; 378 } 379 380 SimdDefaultAlign = 381 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 382 return true; 383 } 384 385 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 386 /// definitions for this particular subtarget. 387 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 388 MacroBuilder &Builder) const { 389 // Inline assembly supports X86 flag outputs. 390 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 391 392 std::string CodeModel = getTargetOpts().CodeModel; 393 if (CodeModel == "default") 394 CodeModel = "small"; 395 Builder.defineMacro("__code_model_" + CodeModel + "__"); 396 397 // Target identification. 398 if (getTriple().getArch() == llvm::Triple::x86_64) { 399 Builder.defineMacro("__amd64__"); 400 Builder.defineMacro("__amd64"); 401 Builder.defineMacro("__x86_64"); 402 Builder.defineMacro("__x86_64__"); 403 if (getTriple().getArchName() == "x86_64h") { 404 Builder.defineMacro("__x86_64h"); 405 Builder.defineMacro("__x86_64h__"); 406 } 407 } else { 408 DefineStd(Builder, "i386", Opts); 409 } 410 411 Builder.defineMacro("__SEG_GS"); 412 Builder.defineMacro("__SEG_FS"); 413 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 414 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 415 416 // Subtarget options. 417 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 418 // truly should be based on -mtune options. 419 using namespace llvm::X86; 420 switch (CPU) { 421 case CK_None: 422 break; 423 case CK_i386: 424 // The rest are coming from the i386 define above. 425 Builder.defineMacro("__tune_i386__"); 426 break; 427 case CK_i486: 428 case CK_WinChipC6: 429 case CK_WinChip2: 430 case CK_C3: 431 defineCPUMacros(Builder, "i486"); 432 break; 433 case CK_PentiumMMX: 434 Builder.defineMacro("__pentium_mmx__"); 435 Builder.defineMacro("__tune_pentium_mmx__"); 436 LLVM_FALLTHROUGH; 437 case CK_i586: 438 case CK_Pentium: 439 defineCPUMacros(Builder, "i586"); 440 defineCPUMacros(Builder, "pentium"); 441 break; 442 case CK_Pentium3: 443 case CK_PentiumM: 444 Builder.defineMacro("__tune_pentium3__"); 445 LLVM_FALLTHROUGH; 446 case CK_Pentium2: 447 case CK_C3_2: 448 Builder.defineMacro("__tune_pentium2__"); 449 LLVM_FALLTHROUGH; 450 case CK_PentiumPro: 451 case CK_i686: 452 defineCPUMacros(Builder, "i686"); 453 defineCPUMacros(Builder, "pentiumpro"); 454 break; 455 case CK_Pentium4: 456 defineCPUMacros(Builder, "pentium4"); 457 break; 458 case CK_Yonah: 459 case CK_Prescott: 460 case CK_Nocona: 461 defineCPUMacros(Builder, "nocona"); 462 break; 463 case CK_Core2: 464 case CK_Penryn: 465 defineCPUMacros(Builder, "core2"); 466 break; 467 case CK_Bonnell: 468 defineCPUMacros(Builder, "atom"); 469 break; 470 case CK_Silvermont: 471 defineCPUMacros(Builder, "slm"); 472 break; 473 case CK_Goldmont: 474 defineCPUMacros(Builder, "goldmont"); 475 break; 476 case CK_GoldmontPlus: 477 defineCPUMacros(Builder, "goldmont_plus"); 478 break; 479 case CK_Tremont: 480 defineCPUMacros(Builder, "tremont"); 481 break; 482 case CK_Nehalem: 483 case CK_Westmere: 484 case CK_SandyBridge: 485 case CK_IvyBridge: 486 case CK_Haswell: 487 case CK_Broadwell: 488 case CK_SkylakeClient: 489 case CK_SkylakeServer: 490 case CK_Cascadelake: 491 case CK_Cooperlake: 492 case CK_Cannonlake: 493 case CK_IcelakeClient: 494 case CK_Rocketlake: 495 case CK_IcelakeServer: 496 case CK_Tigerlake: 497 case CK_SapphireRapids: 498 case CK_Alderlake: 499 // FIXME: Historically, we defined this legacy name, it would be nice to 500 // remove it at some point. We've never exposed fine-grained names for 501 // recent primary x86 CPUs, and we should keep it that way. 502 defineCPUMacros(Builder, "corei7"); 503 break; 504 case CK_KNL: 505 defineCPUMacros(Builder, "knl"); 506 break; 507 case CK_KNM: 508 break; 509 case CK_Lakemont: 510 defineCPUMacros(Builder, "i586", /*Tuning*/false); 511 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 512 Builder.defineMacro("__tune_lakemont__"); 513 break; 514 case CK_K6_2: 515 Builder.defineMacro("__k6_2__"); 516 Builder.defineMacro("__tune_k6_2__"); 517 LLVM_FALLTHROUGH; 518 case CK_K6_3: 519 if (CPU != CK_K6_2) { // In case of fallthrough 520 // FIXME: GCC may be enabling these in cases where some other k6 521 // architecture is specified but -m3dnow is explicitly provided. The 522 // exact semantics need to be determined and emulated here. 523 Builder.defineMacro("__k6_3__"); 524 Builder.defineMacro("__tune_k6_3__"); 525 } 526 LLVM_FALLTHROUGH; 527 case CK_K6: 528 defineCPUMacros(Builder, "k6"); 529 break; 530 case CK_Athlon: 531 case CK_AthlonXP: 532 defineCPUMacros(Builder, "athlon"); 533 if (SSELevel != NoSSE) { 534 Builder.defineMacro("__athlon_sse__"); 535 Builder.defineMacro("__tune_athlon_sse__"); 536 } 537 break; 538 case CK_K8: 539 case CK_K8SSE3: 540 case CK_x86_64: 541 defineCPUMacros(Builder, "k8"); 542 break; 543 case CK_x86_64_v2: 544 case CK_x86_64_v3: 545 case CK_x86_64_v4: 546 break; 547 case CK_AMDFAM10: 548 defineCPUMacros(Builder, "amdfam10"); 549 break; 550 case CK_BTVER1: 551 defineCPUMacros(Builder, "btver1"); 552 break; 553 case CK_BTVER2: 554 defineCPUMacros(Builder, "btver2"); 555 break; 556 case CK_BDVER1: 557 defineCPUMacros(Builder, "bdver1"); 558 break; 559 case CK_BDVER2: 560 defineCPUMacros(Builder, "bdver2"); 561 break; 562 case CK_BDVER3: 563 defineCPUMacros(Builder, "bdver3"); 564 break; 565 case CK_BDVER4: 566 defineCPUMacros(Builder, "bdver4"); 567 break; 568 case CK_ZNVER1: 569 defineCPUMacros(Builder, "znver1"); 570 break; 571 case CK_ZNVER2: 572 defineCPUMacros(Builder, "znver2"); 573 break; 574 case CK_ZNVER3: 575 defineCPUMacros(Builder, "znver3"); 576 break; 577 case CK_Geode: 578 defineCPUMacros(Builder, "geode"); 579 break; 580 } 581 582 // Target properties. 583 Builder.defineMacro("__REGISTER_PREFIX__", ""); 584 585 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 586 // functions in glibc header files that use FP Stack inline asm which the 587 // backend can't deal with (PR879). 588 Builder.defineMacro("__NO_MATH_INLINES"); 589 590 if (HasAES) 591 Builder.defineMacro("__AES__"); 592 593 if (HasVAES) 594 Builder.defineMacro("__VAES__"); 595 596 if (HasPCLMUL) 597 Builder.defineMacro("__PCLMUL__"); 598 599 if (HasVPCLMULQDQ) 600 Builder.defineMacro("__VPCLMULQDQ__"); 601 602 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 603 // the feature flag only applies to 64-bit mode. 604 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 605 Builder.defineMacro("__LAHF_SAHF__"); 606 607 if (HasLZCNT) 608 Builder.defineMacro("__LZCNT__"); 609 610 if (HasRDRND) 611 Builder.defineMacro("__RDRND__"); 612 613 if (HasFSGSBASE) 614 Builder.defineMacro("__FSGSBASE__"); 615 616 if (HasBMI) 617 Builder.defineMacro("__BMI__"); 618 619 if (HasBMI2) 620 Builder.defineMacro("__BMI2__"); 621 622 if (HasPOPCNT) 623 Builder.defineMacro("__POPCNT__"); 624 625 if (HasRTM) 626 Builder.defineMacro("__RTM__"); 627 628 if (HasPRFCHW) 629 Builder.defineMacro("__PRFCHW__"); 630 631 if (HasRDSEED) 632 Builder.defineMacro("__RDSEED__"); 633 634 if (HasADX) 635 Builder.defineMacro("__ADX__"); 636 637 if (HasTBM) 638 Builder.defineMacro("__TBM__"); 639 640 if (HasLWP) 641 Builder.defineMacro("__LWP__"); 642 643 if (HasMWAITX) 644 Builder.defineMacro("__MWAITX__"); 645 646 if (HasMOVBE) 647 Builder.defineMacro("__MOVBE__"); 648 649 switch (XOPLevel) { 650 case XOP: 651 Builder.defineMacro("__XOP__"); 652 LLVM_FALLTHROUGH; 653 case FMA4: 654 Builder.defineMacro("__FMA4__"); 655 LLVM_FALLTHROUGH; 656 case SSE4A: 657 Builder.defineMacro("__SSE4A__"); 658 LLVM_FALLTHROUGH; 659 case NoXOP: 660 break; 661 } 662 663 if (HasFMA) 664 Builder.defineMacro("__FMA__"); 665 666 if (HasF16C) 667 Builder.defineMacro("__F16C__"); 668 669 if (HasGFNI) 670 Builder.defineMacro("__GFNI__"); 671 672 if (HasAVX512CD) 673 Builder.defineMacro("__AVX512CD__"); 674 if (HasAVX512VPOPCNTDQ) 675 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 676 if (HasAVX512VNNI) 677 Builder.defineMacro("__AVX512VNNI__"); 678 if (HasAVX512BF16) 679 Builder.defineMacro("__AVX512BF16__"); 680 if (HasAVX512ER) 681 Builder.defineMacro("__AVX512ER__"); 682 if (HasAVX512FP16) 683 Builder.defineMacro("__AVX512FP16__"); 684 if (HasAVX512PF) 685 Builder.defineMacro("__AVX512PF__"); 686 if (HasAVX512DQ) 687 Builder.defineMacro("__AVX512DQ__"); 688 if (HasAVX512BITALG) 689 Builder.defineMacro("__AVX512BITALG__"); 690 if (HasAVX512BW) 691 Builder.defineMacro("__AVX512BW__"); 692 if (HasAVX512VL) 693 Builder.defineMacro("__AVX512VL__"); 694 if (HasAVX512VBMI) 695 Builder.defineMacro("__AVX512VBMI__"); 696 if (HasAVX512VBMI2) 697 Builder.defineMacro("__AVX512VBMI2__"); 698 if (HasAVX512IFMA) 699 Builder.defineMacro("__AVX512IFMA__"); 700 if (HasAVX512VP2INTERSECT) 701 Builder.defineMacro("__AVX512VP2INTERSECT__"); 702 if (HasSHA) 703 Builder.defineMacro("__SHA__"); 704 705 if (HasFXSR) 706 Builder.defineMacro("__FXSR__"); 707 if (HasXSAVE) 708 Builder.defineMacro("__XSAVE__"); 709 if (HasXSAVEOPT) 710 Builder.defineMacro("__XSAVEOPT__"); 711 if (HasXSAVEC) 712 Builder.defineMacro("__XSAVEC__"); 713 if (HasXSAVES) 714 Builder.defineMacro("__XSAVES__"); 715 if (HasPKU) 716 Builder.defineMacro("__PKU__"); 717 if (HasCLFLUSHOPT) 718 Builder.defineMacro("__CLFLUSHOPT__"); 719 if (HasCLWB) 720 Builder.defineMacro("__CLWB__"); 721 if (HasWBNOINVD) 722 Builder.defineMacro("__WBNOINVD__"); 723 if (HasSHSTK) 724 Builder.defineMacro("__SHSTK__"); 725 if (HasSGX) 726 Builder.defineMacro("__SGX__"); 727 if (HasPREFETCHWT1) 728 Builder.defineMacro("__PREFETCHWT1__"); 729 if (HasCLZERO) 730 Builder.defineMacro("__CLZERO__"); 731 if (HasKL) 732 Builder.defineMacro("__KL__"); 733 if (HasWIDEKL) 734 Builder.defineMacro("__WIDEKL__"); 735 if (HasRDPID) 736 Builder.defineMacro("__RDPID__"); 737 if (HasCLDEMOTE) 738 Builder.defineMacro("__CLDEMOTE__"); 739 if (HasWAITPKG) 740 Builder.defineMacro("__WAITPKG__"); 741 if (HasMOVDIRI) 742 Builder.defineMacro("__MOVDIRI__"); 743 if (HasMOVDIR64B) 744 Builder.defineMacro("__MOVDIR64B__"); 745 if (HasPCONFIG) 746 Builder.defineMacro("__PCONFIG__"); 747 if (HasPTWRITE) 748 Builder.defineMacro("__PTWRITE__"); 749 if (HasINVPCID) 750 Builder.defineMacro("__INVPCID__"); 751 if (HasENQCMD) 752 Builder.defineMacro("__ENQCMD__"); 753 if (HasHRESET) 754 Builder.defineMacro("__HRESET__"); 755 if (HasAMXTILE) 756 Builder.defineMacro("__AMXTILE__"); 757 if (HasAMXINT8) 758 Builder.defineMacro("__AMXINT8__"); 759 if (HasAMXBF16) 760 Builder.defineMacro("__AMXBF16__"); 761 if (HasAVXVNNI) 762 Builder.defineMacro("__AVXVNNI__"); 763 if (HasSERIALIZE) 764 Builder.defineMacro("__SERIALIZE__"); 765 if (HasTSXLDTRK) 766 Builder.defineMacro("__TSXLDTRK__"); 767 if (HasUINTR) 768 Builder.defineMacro("__UINTR__"); 769 if (HasCRC32) 770 Builder.defineMacro("__CRC32__"); 771 772 // Each case falls through to the previous one here. 773 switch (SSELevel) { 774 case AVX512F: 775 Builder.defineMacro("__AVX512F__"); 776 LLVM_FALLTHROUGH; 777 case AVX2: 778 Builder.defineMacro("__AVX2__"); 779 LLVM_FALLTHROUGH; 780 case AVX: 781 Builder.defineMacro("__AVX__"); 782 LLVM_FALLTHROUGH; 783 case SSE42: 784 Builder.defineMacro("__SSE4_2__"); 785 LLVM_FALLTHROUGH; 786 case SSE41: 787 Builder.defineMacro("__SSE4_1__"); 788 LLVM_FALLTHROUGH; 789 case SSSE3: 790 Builder.defineMacro("__SSSE3__"); 791 LLVM_FALLTHROUGH; 792 case SSE3: 793 Builder.defineMacro("__SSE3__"); 794 LLVM_FALLTHROUGH; 795 case SSE2: 796 Builder.defineMacro("__SSE2__"); 797 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 798 LLVM_FALLTHROUGH; 799 case SSE1: 800 Builder.defineMacro("__SSE__"); 801 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 802 LLVM_FALLTHROUGH; 803 case NoSSE: 804 break; 805 } 806 807 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 808 switch (SSELevel) { 809 case AVX512F: 810 case AVX2: 811 case AVX: 812 case SSE42: 813 case SSE41: 814 case SSSE3: 815 case SSE3: 816 case SSE2: 817 Builder.defineMacro("_M_IX86_FP", Twine(2)); 818 break; 819 case SSE1: 820 Builder.defineMacro("_M_IX86_FP", Twine(1)); 821 break; 822 default: 823 Builder.defineMacro("_M_IX86_FP", Twine(0)); 824 break; 825 } 826 } 827 828 // Each case falls through to the previous one here. 829 switch (MMX3DNowLevel) { 830 case AMD3DNowAthlon: 831 Builder.defineMacro("__3dNOW_A__"); 832 LLVM_FALLTHROUGH; 833 case AMD3DNow: 834 Builder.defineMacro("__3dNOW__"); 835 LLVM_FALLTHROUGH; 836 case MMX: 837 Builder.defineMacro("__MMX__"); 838 LLVM_FALLTHROUGH; 839 case NoMMX3DNow: 840 break; 841 } 842 843 if (CPU >= CK_i486 || CPU == CK_None) { 844 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 845 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 846 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 847 } 848 if (HasCX8) 849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 850 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 851 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 852 853 if (HasFloat128) 854 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 855 } 856 857 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 858 return llvm::StringSwitch<bool>(Name) 859 .Case("3dnow", true) 860 .Case("3dnowa", true) 861 .Case("adx", true) 862 .Case("aes", true) 863 .Case("amx-bf16", true) 864 .Case("amx-int8", true) 865 .Case("amx-tile", true) 866 .Case("avx", true) 867 .Case("avx2", true) 868 .Case("avx512f", true) 869 .Case("avx512cd", true) 870 .Case("avx512vpopcntdq", true) 871 .Case("avx512vnni", true) 872 .Case("avx512bf16", true) 873 .Case("avx512er", true) 874 .Case("avx512fp16", true) 875 .Case("avx512pf", true) 876 .Case("avx512dq", true) 877 .Case("avx512bitalg", true) 878 .Case("avx512bw", true) 879 .Case("avx512vl", true) 880 .Case("avx512vbmi", true) 881 .Case("avx512vbmi2", true) 882 .Case("avx512ifma", true) 883 .Case("avx512vp2intersect", true) 884 .Case("avxvnni", true) 885 .Case("bmi", true) 886 .Case("bmi2", true) 887 .Case("cldemote", true) 888 .Case("clflushopt", true) 889 .Case("clwb", true) 890 .Case("clzero", true) 891 .Case("crc32", true) 892 .Case("cx16", true) 893 .Case("enqcmd", true) 894 .Case("f16c", true) 895 .Case("fma", true) 896 .Case("fma4", true) 897 .Case("fsgsbase", true) 898 .Case("fxsr", true) 899 .Case("general-regs-only", true) 900 .Case("gfni", true) 901 .Case("hreset", true) 902 .Case("invpcid", true) 903 .Case("kl", true) 904 .Case("widekl", true) 905 .Case("lwp", true) 906 .Case("lzcnt", true) 907 .Case("mmx", true) 908 .Case("movbe", true) 909 .Case("movdiri", true) 910 .Case("movdir64b", true) 911 .Case("mwaitx", true) 912 .Case("pclmul", true) 913 .Case("pconfig", true) 914 .Case("pku", true) 915 .Case("popcnt", true) 916 .Case("prefetchwt1", true) 917 .Case("prfchw", true) 918 .Case("ptwrite", true) 919 .Case("rdpid", true) 920 .Case("rdrnd", true) 921 .Case("rdseed", true) 922 .Case("rtm", true) 923 .Case("sahf", true) 924 .Case("serialize", true) 925 .Case("sgx", true) 926 .Case("sha", true) 927 .Case("shstk", true) 928 .Case("sse", true) 929 .Case("sse2", true) 930 .Case("sse3", true) 931 .Case("ssse3", true) 932 .Case("sse4", true) 933 .Case("sse4.1", true) 934 .Case("sse4.2", true) 935 .Case("sse4a", true) 936 .Case("tbm", true) 937 .Case("tsxldtrk", true) 938 .Case("uintr", true) 939 .Case("vaes", true) 940 .Case("vpclmulqdq", true) 941 .Case("wbnoinvd", true) 942 .Case("waitpkg", true) 943 .Case("x87", true) 944 .Case("xop", true) 945 .Case("xsave", true) 946 .Case("xsavec", true) 947 .Case("xsaves", true) 948 .Case("xsaveopt", true) 949 .Default(false); 950 } 951 952 bool X86TargetInfo::hasFeature(StringRef Feature) const { 953 return llvm::StringSwitch<bool>(Feature) 954 .Case("adx", HasADX) 955 .Case("aes", HasAES) 956 .Case("amx-bf16", HasAMXBF16) 957 .Case("amx-int8", HasAMXINT8) 958 .Case("amx-tile", HasAMXTILE) 959 .Case("avxvnni", HasAVXVNNI) 960 .Case("avx", SSELevel >= AVX) 961 .Case("avx2", SSELevel >= AVX2) 962 .Case("avx512f", SSELevel >= AVX512F) 963 .Case("avx512cd", HasAVX512CD) 964 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 965 .Case("avx512vnni", HasAVX512VNNI) 966 .Case("avx512bf16", HasAVX512BF16) 967 .Case("avx512er", HasAVX512ER) 968 .Case("avx512fp16", HasAVX512FP16) 969 .Case("avx512pf", HasAVX512PF) 970 .Case("avx512dq", HasAVX512DQ) 971 .Case("avx512bitalg", HasAVX512BITALG) 972 .Case("avx512bw", HasAVX512BW) 973 .Case("avx512vl", HasAVX512VL) 974 .Case("avx512vbmi", HasAVX512VBMI) 975 .Case("avx512vbmi2", HasAVX512VBMI2) 976 .Case("avx512ifma", HasAVX512IFMA) 977 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 978 .Case("bmi", HasBMI) 979 .Case("bmi2", HasBMI2) 980 .Case("cldemote", HasCLDEMOTE) 981 .Case("clflushopt", HasCLFLUSHOPT) 982 .Case("clwb", HasCLWB) 983 .Case("clzero", HasCLZERO) 984 .Case("crc32", HasCRC32) 985 .Case("cx8", HasCX8) 986 .Case("cx16", HasCX16) 987 .Case("enqcmd", HasENQCMD) 988 .Case("f16c", HasF16C) 989 .Case("fma", HasFMA) 990 .Case("fma4", XOPLevel >= FMA4) 991 .Case("fsgsbase", HasFSGSBASE) 992 .Case("fxsr", HasFXSR) 993 .Case("gfni", HasGFNI) 994 .Case("hreset", HasHRESET) 995 .Case("invpcid", HasINVPCID) 996 .Case("kl", HasKL) 997 .Case("widekl", HasWIDEKL) 998 .Case("lwp", HasLWP) 999 .Case("lzcnt", HasLZCNT) 1000 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1001 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1002 .Case("mmx", MMX3DNowLevel >= MMX) 1003 .Case("movbe", HasMOVBE) 1004 .Case("movdiri", HasMOVDIRI) 1005 .Case("movdir64b", HasMOVDIR64B) 1006 .Case("mwaitx", HasMWAITX) 1007 .Case("pclmul", HasPCLMUL) 1008 .Case("pconfig", HasPCONFIG) 1009 .Case("pku", HasPKU) 1010 .Case("popcnt", HasPOPCNT) 1011 .Case("prefetchwt1", HasPREFETCHWT1) 1012 .Case("prfchw", HasPRFCHW) 1013 .Case("ptwrite", HasPTWRITE) 1014 .Case("rdpid", HasRDPID) 1015 .Case("rdrnd", HasRDRND) 1016 .Case("rdseed", HasRDSEED) 1017 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1018 .Case("rtm", HasRTM) 1019 .Case("sahf", HasLAHFSAHF) 1020 .Case("serialize", HasSERIALIZE) 1021 .Case("sgx", HasSGX) 1022 .Case("sha", HasSHA) 1023 .Case("shstk", HasSHSTK) 1024 .Case("sse", SSELevel >= SSE1) 1025 .Case("sse2", SSELevel >= SSE2) 1026 .Case("sse3", SSELevel >= SSE3) 1027 .Case("ssse3", SSELevel >= SSSE3) 1028 .Case("sse4.1", SSELevel >= SSE41) 1029 .Case("sse4.2", SSELevel >= SSE42) 1030 .Case("sse4a", XOPLevel >= SSE4A) 1031 .Case("tbm", HasTBM) 1032 .Case("tsxldtrk", HasTSXLDTRK) 1033 .Case("uintr", HasUINTR) 1034 .Case("vaes", HasVAES) 1035 .Case("vpclmulqdq", HasVPCLMULQDQ) 1036 .Case("wbnoinvd", HasWBNOINVD) 1037 .Case("waitpkg", HasWAITPKG) 1038 .Case("x86", true) 1039 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1040 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1041 .Case("xop", XOPLevel >= XOP) 1042 .Case("xsave", HasXSAVE) 1043 .Case("xsavec", HasXSAVEC) 1044 .Case("xsaves", HasXSAVES) 1045 .Case("xsaveopt", HasXSAVEOPT) 1046 .Default(false); 1047 } 1048 1049 // We can't use a generic validation scheme for the features accepted here 1050 // versus subtarget features accepted in the target attribute because the 1051 // bitfield structure that's initialized in the runtime only supports the 1052 // below currently rather than the full range of subtarget features. (See 1053 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1054 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1055 return llvm::StringSwitch<bool>(FeatureStr) 1056 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1057 #include "llvm/Support/X86TargetParser.def" 1058 .Default(false); 1059 } 1060 1061 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1062 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1063 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1064 .Case(STR, llvm::X86::FEATURE_##ENUM) 1065 1066 #include "llvm/Support/X86TargetParser.def" 1067 ; 1068 // Note, this function should only be used after ensuring the value is 1069 // correct, so it asserts if the value is out of range. 1070 } 1071 1072 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1073 // Valid CPUs have a 'key feature' that compares just better than its key 1074 // feature. 1075 using namespace llvm::X86; 1076 CPUKind Kind = parseArchX86(Name); 1077 if (Kind != CK_None) { 1078 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1079 return (getFeaturePriority(KeyFeature) << 1) + 1; 1080 } 1081 1082 // Now we know we have a feature, so get its priority and shift it a few so 1083 // that we have sufficient room for the CPUs (above). 1084 return getFeaturePriority(getFeature(Name)) << 1; 1085 } 1086 1087 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1088 return llvm::StringSwitch<bool>(Name) 1089 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1090 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1091 #include "llvm/Support/X86TargetParser.def" 1092 .Default(false); 1093 } 1094 1095 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1096 return llvm::StringSwitch<StringRef>(Name) 1097 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1098 #include "llvm/Support/X86TargetParser.def" 1099 .Default(Name); 1100 } 1101 1102 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1103 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1104 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1105 #include "llvm/Support/X86TargetParser.def" 1106 .Default(0); 1107 } 1108 1109 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1110 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1111 StringRef WholeList = 1112 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1113 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1114 #include "llvm/Support/X86TargetParser.def" 1115 .Default(""); 1116 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1117 } 1118 1119 // We can't use a generic validation scheme for the cpus accepted here 1120 // versus subtarget cpus accepted in the target attribute because the 1121 // variables intitialized by the runtime only support the below currently 1122 // rather than the full range of cpus. 1123 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1124 return llvm::StringSwitch<bool>(FeatureStr) 1125 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1126 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1127 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1128 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1129 #include "llvm/Support/X86TargetParser.def" 1130 .Default(false); 1131 } 1132 1133 static unsigned matchAsmCCConstraint(const char *&Name) { 1134 auto RV = llvm::StringSwitch<unsigned>(Name) 1135 .Case("@cca", 4) 1136 .Case("@ccae", 5) 1137 .Case("@ccb", 4) 1138 .Case("@ccbe", 5) 1139 .Case("@ccc", 4) 1140 .Case("@cce", 4) 1141 .Case("@ccz", 4) 1142 .Case("@ccg", 4) 1143 .Case("@ccge", 5) 1144 .Case("@ccl", 4) 1145 .Case("@ccle", 5) 1146 .Case("@ccna", 5) 1147 .Case("@ccnae", 6) 1148 .Case("@ccnb", 5) 1149 .Case("@ccnbe", 6) 1150 .Case("@ccnc", 5) 1151 .Case("@ccne", 5) 1152 .Case("@ccnz", 5) 1153 .Case("@ccng", 5) 1154 .Case("@ccnge", 6) 1155 .Case("@ccnl", 5) 1156 .Case("@ccnle", 6) 1157 .Case("@ccno", 5) 1158 .Case("@ccnp", 5) 1159 .Case("@ccns", 5) 1160 .Case("@cco", 4) 1161 .Case("@ccp", 4) 1162 .Case("@ccs", 4) 1163 .Default(0); 1164 return RV; 1165 } 1166 1167 bool X86TargetInfo::validateAsmConstraint( 1168 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1169 switch (*Name) { 1170 default: 1171 return false; 1172 // Constant constraints. 1173 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1174 // instructions. 1175 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1176 // x86_64 instructions. 1177 case 's': 1178 Info.setRequiresImmediate(); 1179 return true; 1180 case 'I': 1181 Info.setRequiresImmediate(0, 31); 1182 return true; 1183 case 'J': 1184 Info.setRequiresImmediate(0, 63); 1185 return true; 1186 case 'K': 1187 Info.setRequiresImmediate(-128, 127); 1188 return true; 1189 case 'L': 1190 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1191 return true; 1192 case 'M': 1193 Info.setRequiresImmediate(0, 3); 1194 return true; 1195 case 'N': 1196 Info.setRequiresImmediate(0, 255); 1197 return true; 1198 case 'O': 1199 Info.setRequiresImmediate(0, 127); 1200 return true; 1201 // Register constraints. 1202 case 'Y': // 'Y' is the first character for several 2-character constraints. 1203 // Shift the pointer to the second character of the constraint. 1204 Name++; 1205 switch (*Name) { 1206 default: 1207 return false; 1208 case 'z': // First SSE register. 1209 case '2': 1210 case 't': // Any SSE register, when SSE2 is enabled. 1211 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1212 case 'm': // Any MMX register, when inter-unit moves enabled. 1213 case 'k': // AVX512 arch mask registers: k1-k7. 1214 Info.setAllowsRegister(); 1215 return true; 1216 } 1217 case 'f': // Any x87 floating point stack register. 1218 // Constraint 'f' cannot be used for output operands. 1219 if (Info.ConstraintStr[0] == '=') 1220 return false; 1221 Info.setAllowsRegister(); 1222 return true; 1223 case 'a': // eax. 1224 case 'b': // ebx. 1225 case 'c': // ecx. 1226 case 'd': // edx. 1227 case 'S': // esi. 1228 case 'D': // edi. 1229 case 'A': // edx:eax. 1230 case 't': // Top of floating point stack. 1231 case 'u': // Second from top of floating point stack. 1232 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1233 case 'y': // Any MMX register. 1234 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1235 case 'x': // Any SSE register. 1236 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1237 // for intermideate k reg operations). 1238 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1239 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1240 case 'l': // "Index" registers: any general register that can be used as an 1241 // index in a base+index memory access. 1242 Info.setAllowsRegister(); 1243 return true; 1244 // Floating point constant constraints. 1245 case 'C': // SSE floating point constant. 1246 case 'G': // x87 floating point constant. 1247 return true; 1248 case '@': 1249 // CC condition changes. 1250 if (auto Len = matchAsmCCConstraint(Name)) { 1251 Name += Len - 1; 1252 Info.setAllowsRegister(); 1253 return true; 1254 } 1255 return false; 1256 } 1257 } 1258 1259 // Below is based on the following information: 1260 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1261 // | Processor Name | Cache Line Size (Bytes) | Source | 1262 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1263 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1264 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1265 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1266 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1267 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1268 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1269 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1270 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1271 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1272 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1273 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1274 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1275 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1276 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1277 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1278 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1279 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1280 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1281 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1282 using namespace llvm::X86; 1283 switch (CPU) { 1284 // i386 1285 case CK_i386: 1286 // i486 1287 case CK_i486: 1288 case CK_WinChipC6: 1289 case CK_WinChip2: 1290 case CK_C3: 1291 // Lakemont 1292 case CK_Lakemont: 1293 return 16; 1294 1295 // i586 1296 case CK_i586: 1297 case CK_Pentium: 1298 case CK_PentiumMMX: 1299 // i686 1300 case CK_PentiumPro: 1301 case CK_i686: 1302 case CK_Pentium2: 1303 case CK_Pentium3: 1304 case CK_PentiumM: 1305 case CK_C3_2: 1306 // K6 1307 case CK_K6: 1308 case CK_K6_2: 1309 case CK_K6_3: 1310 // Geode 1311 case CK_Geode: 1312 return 32; 1313 1314 // Netburst 1315 case CK_Pentium4: 1316 case CK_Prescott: 1317 case CK_Nocona: 1318 // Atom 1319 case CK_Bonnell: 1320 case CK_Silvermont: 1321 case CK_Goldmont: 1322 case CK_GoldmontPlus: 1323 case CK_Tremont: 1324 1325 case CK_Westmere: 1326 case CK_SandyBridge: 1327 case CK_IvyBridge: 1328 case CK_Haswell: 1329 case CK_Broadwell: 1330 case CK_SkylakeClient: 1331 case CK_SkylakeServer: 1332 case CK_Cascadelake: 1333 case CK_Nehalem: 1334 case CK_Cooperlake: 1335 case CK_Cannonlake: 1336 case CK_Tigerlake: 1337 case CK_SapphireRapids: 1338 case CK_IcelakeClient: 1339 case CK_Rocketlake: 1340 case CK_IcelakeServer: 1341 case CK_Alderlake: 1342 case CK_KNL: 1343 case CK_KNM: 1344 // K7 1345 case CK_Athlon: 1346 case CK_AthlonXP: 1347 // K8 1348 case CK_K8: 1349 case CK_K8SSE3: 1350 case CK_AMDFAM10: 1351 // Bobcat 1352 case CK_BTVER1: 1353 case CK_BTVER2: 1354 // Bulldozer 1355 case CK_BDVER1: 1356 case CK_BDVER2: 1357 case CK_BDVER3: 1358 case CK_BDVER4: 1359 // Zen 1360 case CK_ZNVER1: 1361 case CK_ZNVER2: 1362 case CK_ZNVER3: 1363 // Deprecated 1364 case CK_x86_64: 1365 case CK_x86_64_v2: 1366 case CK_x86_64_v3: 1367 case CK_x86_64_v4: 1368 case CK_Yonah: 1369 case CK_Penryn: 1370 case CK_Core2: 1371 return 64; 1372 1373 // The following currently have unknown cache line sizes (but they are probably all 64): 1374 // Core 1375 case CK_None: 1376 return None; 1377 } 1378 llvm_unreachable("Unknown CPU kind"); 1379 } 1380 1381 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1382 StringRef Constraint, 1383 unsigned Size) const { 1384 // Strip off constraint modifiers. 1385 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1386 Constraint = Constraint.substr(1); 1387 1388 return validateOperandSize(FeatureMap, Constraint, Size); 1389 } 1390 1391 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1392 StringRef Constraint, 1393 unsigned Size) const { 1394 return validateOperandSize(FeatureMap, Constraint, Size); 1395 } 1396 1397 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1398 StringRef Constraint, 1399 unsigned Size) const { 1400 switch (Constraint[0]) { 1401 default: 1402 break; 1403 case 'k': 1404 // Registers k0-k7 (AVX512) size limit is 64 bit. 1405 case 'y': 1406 return Size <= 64; 1407 case 'f': 1408 case 't': 1409 case 'u': 1410 return Size <= 128; 1411 case 'Y': 1412 // 'Y' is the first character for several 2-character constraints. 1413 switch (Constraint[1]) { 1414 default: 1415 return false; 1416 case 'm': 1417 // 'Ym' is synonymous with 'y'. 1418 case 'k': 1419 return Size <= 64; 1420 case 'z': 1421 // XMM0/YMM/ZMM0 1422 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1423 // ZMM0 can be used if target supports AVX512F. 1424 return Size <= 512U; 1425 else if (hasFeatureEnabled(FeatureMap, "avx")) 1426 // YMM0 can be used if target supports AVX. 1427 return Size <= 256U; 1428 else if (hasFeatureEnabled(FeatureMap, "sse")) 1429 return Size <= 128U; 1430 return false; 1431 case 'i': 1432 case 't': 1433 case '2': 1434 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1435 if (SSELevel < SSE2) 1436 return false; 1437 break; 1438 } 1439 break; 1440 case 'v': 1441 case 'x': 1442 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1443 // 512-bit zmm registers can be used if target supports AVX512F. 1444 return Size <= 512U; 1445 else if (hasFeatureEnabled(FeatureMap, "avx")) 1446 // 256-bit ymm registers can be used if target supports AVX. 1447 return Size <= 256U; 1448 return Size <= 128U; 1449 1450 } 1451 1452 return true; 1453 } 1454 1455 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1456 switch (*Constraint) { 1457 case '@': 1458 if (auto Len = matchAsmCCConstraint(Constraint)) { 1459 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1460 Constraint += Len - 1; 1461 return Converted; 1462 } 1463 return std::string(1, *Constraint); 1464 case 'a': 1465 return std::string("{ax}"); 1466 case 'b': 1467 return std::string("{bx}"); 1468 case 'c': 1469 return std::string("{cx}"); 1470 case 'd': 1471 return std::string("{dx}"); 1472 case 'S': 1473 return std::string("{si}"); 1474 case 'D': 1475 return std::string("{di}"); 1476 case 'p': // address 1477 return std::string("im"); 1478 case 't': // top of floating point stack. 1479 return std::string("{st}"); 1480 case 'u': // second from top of floating point stack. 1481 return std::string("{st(1)}"); // second from top of floating point stack. 1482 case 'Y': 1483 switch (Constraint[1]) { 1484 default: 1485 // Break from inner switch and fall through (copy single char), 1486 // continue parsing after copying the current constraint into 1487 // the return string. 1488 break; 1489 case 'k': 1490 case 'm': 1491 case 'i': 1492 case 't': 1493 case 'z': 1494 case '2': 1495 // "^" hints llvm that this is a 2 letter constraint. 1496 // "Constraint++" is used to promote the string iterator 1497 // to the next constraint. 1498 return std::string("^") + std::string(Constraint++, 2); 1499 } 1500 LLVM_FALLTHROUGH; 1501 default: 1502 return std::string(1, *Constraint); 1503 } 1504 } 1505 1506 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1507 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1508 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1509 } 1510 1511 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1512 llvm::X86::fillValidTuneCPUList(Values); 1513 } 1514 1515 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1516 return llvm::makeArrayRef(GCCRegNames); 1517 } 1518 1519 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1520 return llvm::makeArrayRef(AddlRegNames); 1521 } 1522 1523 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1524 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1525 Builtin::FirstTSBuiltin + 1); 1526 } 1527 1528 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1529 return llvm::makeArrayRef(BuiltinInfoX86, 1530 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1531 } 1532