1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+amx-bf16") { 302 HasAMXBF16 = true; 303 } else if (Feature == "+amx-int8") { 304 HasAMXINT8 = true; 305 } else if (Feature == "+amx-tile") { 306 HasAMXTILE = true; 307 } else if (Feature == "+serialize") { 308 HasSERIALIZE = true; 309 } else if (Feature == "+tsxldtrk") { 310 HasTSXLDTRK = true; 311 } 312 313 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 314 .Case("+avx512f", AVX512F) 315 .Case("+avx2", AVX2) 316 .Case("+avx", AVX) 317 .Case("+sse4.2", SSE42) 318 .Case("+sse4.1", SSE41) 319 .Case("+ssse3", SSSE3) 320 .Case("+sse3", SSE3) 321 .Case("+sse2", SSE2) 322 .Case("+sse", SSE1) 323 .Default(NoSSE); 324 SSELevel = std::max(SSELevel, Level); 325 326 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 327 .Case("+3dnowa", AMD3DNowAthlon) 328 .Case("+3dnow", AMD3DNow) 329 .Case("+mmx", MMX) 330 .Default(NoMMX3DNow); 331 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 332 333 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 334 .Case("+xop", XOP) 335 .Case("+fma4", FMA4) 336 .Case("+sse4a", SSE4A) 337 .Default(NoXOP); 338 XOPLevel = std::max(XOPLevel, XLevel); 339 } 340 341 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 342 // matches the selected sse level. 343 if ((FPMath == FP_SSE && SSELevel < SSE1) || 344 (FPMath == FP_387 && SSELevel >= SSE1)) { 345 Diags.Report(diag::err_target_unsupported_fpmath) 346 << (FPMath == FP_SSE ? "sse" : "387"); 347 return false; 348 } 349 350 SimdDefaultAlign = 351 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 352 return true; 353 } 354 355 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 356 /// definitions for this particular subtarget. 357 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 358 MacroBuilder &Builder) const { 359 // Inline assembly supports X86 flag outputs. 360 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 361 362 std::string CodeModel = getTargetOpts().CodeModel; 363 if (CodeModel == "default") 364 CodeModel = "small"; 365 Builder.defineMacro("__code_model_" + CodeModel + "__"); 366 367 // Target identification. 368 if (getTriple().getArch() == llvm::Triple::x86_64) { 369 Builder.defineMacro("__amd64__"); 370 Builder.defineMacro("__amd64"); 371 Builder.defineMacro("__x86_64"); 372 Builder.defineMacro("__x86_64__"); 373 if (getTriple().getArchName() == "x86_64h") { 374 Builder.defineMacro("__x86_64h"); 375 Builder.defineMacro("__x86_64h__"); 376 } 377 } else { 378 DefineStd(Builder, "i386", Opts); 379 } 380 381 Builder.defineMacro("__SEG_GS"); 382 Builder.defineMacro("__SEG_FS"); 383 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 384 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 385 386 // Subtarget options. 387 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 388 // truly should be based on -mtune options. 389 using namespace llvm::X86; 390 switch (CPU) { 391 case CK_None: 392 break; 393 case CK_i386: 394 // The rest are coming from the i386 define above. 395 Builder.defineMacro("__tune_i386__"); 396 break; 397 case CK_i486: 398 case CK_WinChipC6: 399 case CK_WinChip2: 400 case CK_C3: 401 defineCPUMacros(Builder, "i486"); 402 break; 403 case CK_PentiumMMX: 404 Builder.defineMacro("__pentium_mmx__"); 405 Builder.defineMacro("__tune_pentium_mmx__"); 406 LLVM_FALLTHROUGH; 407 case CK_i586: 408 case CK_Pentium: 409 defineCPUMacros(Builder, "i586"); 410 defineCPUMacros(Builder, "pentium"); 411 break; 412 case CK_Pentium3: 413 case CK_PentiumM: 414 Builder.defineMacro("__tune_pentium3__"); 415 LLVM_FALLTHROUGH; 416 case CK_Pentium2: 417 case CK_C3_2: 418 Builder.defineMacro("__tune_pentium2__"); 419 LLVM_FALLTHROUGH; 420 case CK_PentiumPro: 421 case CK_i686: 422 defineCPUMacros(Builder, "i686"); 423 defineCPUMacros(Builder, "pentiumpro"); 424 break; 425 case CK_Pentium4: 426 defineCPUMacros(Builder, "pentium4"); 427 break; 428 case CK_Yonah: 429 case CK_Prescott: 430 case CK_Nocona: 431 defineCPUMacros(Builder, "nocona"); 432 break; 433 case CK_Core2: 434 case CK_Penryn: 435 defineCPUMacros(Builder, "core2"); 436 break; 437 case CK_Bonnell: 438 defineCPUMacros(Builder, "atom"); 439 break; 440 case CK_Silvermont: 441 defineCPUMacros(Builder, "slm"); 442 break; 443 case CK_Goldmont: 444 defineCPUMacros(Builder, "goldmont"); 445 break; 446 case CK_GoldmontPlus: 447 defineCPUMacros(Builder, "goldmont_plus"); 448 break; 449 case CK_Tremont: 450 defineCPUMacros(Builder, "tremont"); 451 break; 452 case CK_Nehalem: 453 case CK_Westmere: 454 case CK_SandyBridge: 455 case CK_IvyBridge: 456 case CK_Haswell: 457 case CK_Broadwell: 458 case CK_SkylakeClient: 459 case CK_SkylakeServer: 460 case CK_Cascadelake: 461 case CK_Cooperlake: 462 case CK_Cannonlake: 463 case CK_IcelakeClient: 464 case CK_IcelakeServer: 465 case CK_Tigerlake: 466 case CK_SapphireRapids: 467 // FIXME: Historically, we defined this legacy name, it would be nice to 468 // remove it at some point. We've never exposed fine-grained names for 469 // recent primary x86 CPUs, and we should keep it that way. 470 defineCPUMacros(Builder, "corei7"); 471 break; 472 case CK_KNL: 473 defineCPUMacros(Builder, "knl"); 474 break; 475 case CK_KNM: 476 break; 477 case CK_Lakemont: 478 defineCPUMacros(Builder, "i586", /*Tuning*/false); 479 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 480 Builder.defineMacro("__tune_lakemont__"); 481 break; 482 case CK_K6_2: 483 Builder.defineMacro("__k6_2__"); 484 Builder.defineMacro("__tune_k6_2__"); 485 LLVM_FALLTHROUGH; 486 case CK_K6_3: 487 if (CPU != CK_K6_2) { // In case of fallthrough 488 // FIXME: GCC may be enabling these in cases where some other k6 489 // architecture is specified but -m3dnow is explicitly provided. The 490 // exact semantics need to be determined and emulated here. 491 Builder.defineMacro("__k6_3__"); 492 Builder.defineMacro("__tune_k6_3__"); 493 } 494 LLVM_FALLTHROUGH; 495 case CK_K6: 496 defineCPUMacros(Builder, "k6"); 497 break; 498 case CK_Athlon: 499 case CK_AthlonXP: 500 defineCPUMacros(Builder, "athlon"); 501 if (SSELevel != NoSSE) { 502 Builder.defineMacro("__athlon_sse__"); 503 Builder.defineMacro("__tune_athlon_sse__"); 504 } 505 break; 506 case CK_K8: 507 case CK_K8SSE3: 508 case CK_x86_64: 509 defineCPUMacros(Builder, "k8"); 510 break; 511 case CK_AMDFAM10: 512 defineCPUMacros(Builder, "amdfam10"); 513 break; 514 case CK_BTVER1: 515 defineCPUMacros(Builder, "btver1"); 516 break; 517 case CK_BTVER2: 518 defineCPUMacros(Builder, "btver2"); 519 break; 520 case CK_BDVER1: 521 defineCPUMacros(Builder, "bdver1"); 522 break; 523 case CK_BDVER2: 524 defineCPUMacros(Builder, "bdver2"); 525 break; 526 case CK_BDVER3: 527 defineCPUMacros(Builder, "bdver3"); 528 break; 529 case CK_BDVER4: 530 defineCPUMacros(Builder, "bdver4"); 531 break; 532 case CK_ZNVER1: 533 defineCPUMacros(Builder, "znver1"); 534 break; 535 case CK_ZNVER2: 536 defineCPUMacros(Builder, "znver2"); 537 break; 538 case CK_Geode: 539 defineCPUMacros(Builder, "geode"); 540 break; 541 } 542 543 // Target properties. 544 Builder.defineMacro("__REGISTER_PREFIX__", ""); 545 546 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 547 // functions in glibc header files that use FP Stack inline asm which the 548 // backend can't deal with (PR879). 549 Builder.defineMacro("__NO_MATH_INLINES"); 550 551 if (HasAES) 552 Builder.defineMacro("__AES__"); 553 554 if (HasVAES) 555 Builder.defineMacro("__VAES__"); 556 557 if (HasPCLMUL) 558 Builder.defineMacro("__PCLMUL__"); 559 560 if (HasVPCLMULQDQ) 561 Builder.defineMacro("__VPCLMULQDQ__"); 562 563 if (HasLZCNT) 564 Builder.defineMacro("__LZCNT__"); 565 566 if (HasRDRND) 567 Builder.defineMacro("__RDRND__"); 568 569 if (HasFSGSBASE) 570 Builder.defineMacro("__FSGSBASE__"); 571 572 if (HasBMI) 573 Builder.defineMacro("__BMI__"); 574 575 if (HasBMI2) 576 Builder.defineMacro("__BMI2__"); 577 578 if (HasPOPCNT) 579 Builder.defineMacro("__POPCNT__"); 580 581 if (HasRTM) 582 Builder.defineMacro("__RTM__"); 583 584 if (HasPRFCHW) 585 Builder.defineMacro("__PRFCHW__"); 586 587 if (HasRDSEED) 588 Builder.defineMacro("__RDSEED__"); 589 590 if (HasADX) 591 Builder.defineMacro("__ADX__"); 592 593 if (HasTBM) 594 Builder.defineMacro("__TBM__"); 595 596 if (HasLWP) 597 Builder.defineMacro("__LWP__"); 598 599 if (HasMWAITX) 600 Builder.defineMacro("__MWAITX__"); 601 602 if (HasMOVBE) 603 Builder.defineMacro("__MOVBE__"); 604 605 switch (XOPLevel) { 606 case XOP: 607 Builder.defineMacro("__XOP__"); 608 LLVM_FALLTHROUGH; 609 case FMA4: 610 Builder.defineMacro("__FMA4__"); 611 LLVM_FALLTHROUGH; 612 case SSE4A: 613 Builder.defineMacro("__SSE4A__"); 614 LLVM_FALLTHROUGH; 615 case NoXOP: 616 break; 617 } 618 619 if (HasFMA) 620 Builder.defineMacro("__FMA__"); 621 622 if (HasF16C) 623 Builder.defineMacro("__F16C__"); 624 625 if (HasGFNI) 626 Builder.defineMacro("__GFNI__"); 627 628 if (HasAVX512CD) 629 Builder.defineMacro("__AVX512CD__"); 630 if (HasAVX512VPOPCNTDQ) 631 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 632 if (HasAVX512VNNI) 633 Builder.defineMacro("__AVX512VNNI__"); 634 if (HasAVX512BF16) 635 Builder.defineMacro("__AVX512BF16__"); 636 if (HasAVX512ER) 637 Builder.defineMacro("__AVX512ER__"); 638 if (HasAVX512PF) 639 Builder.defineMacro("__AVX512PF__"); 640 if (HasAVX512DQ) 641 Builder.defineMacro("__AVX512DQ__"); 642 if (HasAVX512BITALG) 643 Builder.defineMacro("__AVX512BITALG__"); 644 if (HasAVX512BW) 645 Builder.defineMacro("__AVX512BW__"); 646 if (HasAVX512VL) 647 Builder.defineMacro("__AVX512VL__"); 648 if (HasAVX512VBMI) 649 Builder.defineMacro("__AVX512VBMI__"); 650 if (HasAVX512VBMI2) 651 Builder.defineMacro("__AVX512VBMI2__"); 652 if (HasAVX512IFMA) 653 Builder.defineMacro("__AVX512IFMA__"); 654 if (HasAVX512VP2INTERSECT) 655 Builder.defineMacro("__AVX512VP2INTERSECT__"); 656 if (HasSHA) 657 Builder.defineMacro("__SHA__"); 658 659 if (HasFXSR) 660 Builder.defineMacro("__FXSR__"); 661 if (HasXSAVE) 662 Builder.defineMacro("__XSAVE__"); 663 if (HasXSAVEOPT) 664 Builder.defineMacro("__XSAVEOPT__"); 665 if (HasXSAVEC) 666 Builder.defineMacro("__XSAVEC__"); 667 if (HasXSAVES) 668 Builder.defineMacro("__XSAVES__"); 669 if (HasPKU) 670 Builder.defineMacro("__PKU__"); 671 if (HasCLFLUSHOPT) 672 Builder.defineMacro("__CLFLUSHOPT__"); 673 if (HasCLWB) 674 Builder.defineMacro("__CLWB__"); 675 if (HasWBNOINVD) 676 Builder.defineMacro("__WBNOINVD__"); 677 if (HasSHSTK) 678 Builder.defineMacro("__SHSTK__"); 679 if (HasSGX) 680 Builder.defineMacro("__SGX__"); 681 if (HasPREFETCHWT1) 682 Builder.defineMacro("__PREFETCHWT1__"); 683 if (HasCLZERO) 684 Builder.defineMacro("__CLZERO__"); 685 if (HasKL) 686 Builder.defineMacro("__KL__"); 687 if (HasWIDEKL) 688 Builder.defineMacro("__WIDEKL__"); 689 if (HasRDPID) 690 Builder.defineMacro("__RDPID__"); 691 if (HasCLDEMOTE) 692 Builder.defineMacro("__CLDEMOTE__"); 693 if (HasWAITPKG) 694 Builder.defineMacro("__WAITPKG__"); 695 if (HasMOVDIRI) 696 Builder.defineMacro("__MOVDIRI__"); 697 if (HasMOVDIR64B) 698 Builder.defineMacro("__MOVDIR64B__"); 699 if (HasPCONFIG) 700 Builder.defineMacro("__PCONFIG__"); 701 if (HasPTWRITE) 702 Builder.defineMacro("__PTWRITE__"); 703 if (HasINVPCID) 704 Builder.defineMacro("__INVPCID__"); 705 if (HasENQCMD) 706 Builder.defineMacro("__ENQCMD__"); 707 if (HasAMXTILE) 708 Builder.defineMacro("__AMXTILE__"); 709 if (HasAMXINT8) 710 Builder.defineMacro("__AMXINT8__"); 711 if (HasAMXBF16) 712 Builder.defineMacro("__AMXBF16__"); 713 if (HasSERIALIZE) 714 Builder.defineMacro("__SERIALIZE__"); 715 if (HasTSXLDTRK) 716 Builder.defineMacro("__TSXLDTRK__"); 717 718 // Each case falls through to the previous one here. 719 switch (SSELevel) { 720 case AVX512F: 721 Builder.defineMacro("__AVX512F__"); 722 LLVM_FALLTHROUGH; 723 case AVX2: 724 Builder.defineMacro("__AVX2__"); 725 LLVM_FALLTHROUGH; 726 case AVX: 727 Builder.defineMacro("__AVX__"); 728 LLVM_FALLTHROUGH; 729 case SSE42: 730 Builder.defineMacro("__SSE4_2__"); 731 LLVM_FALLTHROUGH; 732 case SSE41: 733 Builder.defineMacro("__SSE4_1__"); 734 LLVM_FALLTHROUGH; 735 case SSSE3: 736 Builder.defineMacro("__SSSE3__"); 737 LLVM_FALLTHROUGH; 738 case SSE3: 739 Builder.defineMacro("__SSE3__"); 740 LLVM_FALLTHROUGH; 741 case SSE2: 742 Builder.defineMacro("__SSE2__"); 743 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 744 LLVM_FALLTHROUGH; 745 case SSE1: 746 Builder.defineMacro("__SSE__"); 747 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 748 LLVM_FALLTHROUGH; 749 case NoSSE: 750 break; 751 } 752 753 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 754 switch (SSELevel) { 755 case AVX512F: 756 case AVX2: 757 case AVX: 758 case SSE42: 759 case SSE41: 760 case SSSE3: 761 case SSE3: 762 case SSE2: 763 Builder.defineMacro("_M_IX86_FP", Twine(2)); 764 break; 765 case SSE1: 766 Builder.defineMacro("_M_IX86_FP", Twine(1)); 767 break; 768 default: 769 Builder.defineMacro("_M_IX86_FP", Twine(0)); 770 break; 771 } 772 } 773 774 // Each case falls through to the previous one here. 775 switch (MMX3DNowLevel) { 776 case AMD3DNowAthlon: 777 Builder.defineMacro("__3dNOW_A__"); 778 LLVM_FALLTHROUGH; 779 case AMD3DNow: 780 Builder.defineMacro("__3dNOW__"); 781 LLVM_FALLTHROUGH; 782 case MMX: 783 Builder.defineMacro("__MMX__"); 784 LLVM_FALLTHROUGH; 785 case NoMMX3DNow: 786 break; 787 } 788 789 if (CPU >= CK_i486 || CPU == CK_None) { 790 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 791 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 792 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 793 } 794 if (HasCX8) 795 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 796 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 797 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 798 799 if (HasFloat128) 800 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 801 } 802 803 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 804 return llvm::StringSwitch<bool>(Name) 805 .Case("3dnow", true) 806 .Case("3dnowa", true) 807 .Case("adx", true) 808 .Case("aes", true) 809 .Case("amx-bf16", true) 810 .Case("amx-int8", true) 811 .Case("amx-tile", true) 812 .Case("avx", true) 813 .Case("avx2", true) 814 .Case("avx512f", true) 815 .Case("avx512cd", true) 816 .Case("avx512vpopcntdq", true) 817 .Case("avx512vnni", true) 818 .Case("avx512bf16", true) 819 .Case("avx512er", true) 820 .Case("avx512pf", true) 821 .Case("avx512dq", true) 822 .Case("avx512bitalg", true) 823 .Case("avx512bw", true) 824 .Case("avx512vl", true) 825 .Case("avx512vbmi", true) 826 .Case("avx512vbmi2", true) 827 .Case("avx512ifma", true) 828 .Case("avx512vp2intersect", true) 829 .Case("bmi", true) 830 .Case("bmi2", true) 831 .Case("cldemote", true) 832 .Case("clflushopt", true) 833 .Case("clwb", true) 834 .Case("clzero", true) 835 .Case("cx16", true) 836 .Case("enqcmd", true) 837 .Case("f16c", true) 838 .Case("fma", true) 839 .Case("fma4", true) 840 .Case("fsgsbase", true) 841 .Case("fxsr", true) 842 .Case("gfni", true) 843 .Case("invpcid", true) 844 .Case("kl", true) 845 .Case("widekl", true) 846 .Case("lwp", true) 847 .Case("lzcnt", true) 848 .Case("mmx", true) 849 .Case("movbe", true) 850 .Case("movdiri", true) 851 .Case("movdir64b", true) 852 .Case("mwaitx", true) 853 .Case("pclmul", true) 854 .Case("pconfig", true) 855 .Case("pku", true) 856 .Case("popcnt", true) 857 .Case("prefetchwt1", true) 858 .Case("prfchw", true) 859 .Case("ptwrite", true) 860 .Case("rdpid", true) 861 .Case("rdrnd", true) 862 .Case("rdseed", true) 863 .Case("rtm", true) 864 .Case("sahf", true) 865 .Case("serialize", true) 866 .Case("sgx", true) 867 .Case("sha", true) 868 .Case("shstk", true) 869 .Case("sse", true) 870 .Case("sse2", true) 871 .Case("sse3", true) 872 .Case("ssse3", true) 873 .Case("sse4", true) 874 .Case("sse4.1", true) 875 .Case("sse4.2", true) 876 .Case("sse4a", true) 877 .Case("tbm", true) 878 .Case("tsxldtrk", true) 879 .Case("vaes", true) 880 .Case("vpclmulqdq", true) 881 .Case("wbnoinvd", true) 882 .Case("waitpkg", true) 883 .Case("x87", true) 884 .Case("xop", true) 885 .Case("xsave", true) 886 .Case("xsavec", true) 887 .Case("xsaves", true) 888 .Case("xsaveopt", true) 889 .Default(false); 890 } 891 892 bool X86TargetInfo::hasFeature(StringRef Feature) const { 893 return llvm::StringSwitch<bool>(Feature) 894 .Case("adx", HasADX) 895 .Case("aes", HasAES) 896 .Case("amx-bf16", HasAMXBF16) 897 .Case("amx-int8", HasAMXINT8) 898 .Case("amx-tile", HasAMXTILE) 899 .Case("avx", SSELevel >= AVX) 900 .Case("avx2", SSELevel >= AVX2) 901 .Case("avx512f", SSELevel >= AVX512F) 902 .Case("avx512cd", HasAVX512CD) 903 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 904 .Case("avx512vnni", HasAVX512VNNI) 905 .Case("avx512bf16", HasAVX512BF16) 906 .Case("avx512er", HasAVX512ER) 907 .Case("avx512pf", HasAVX512PF) 908 .Case("avx512dq", HasAVX512DQ) 909 .Case("avx512bitalg", HasAVX512BITALG) 910 .Case("avx512bw", HasAVX512BW) 911 .Case("avx512vl", HasAVX512VL) 912 .Case("avx512vbmi", HasAVX512VBMI) 913 .Case("avx512vbmi2", HasAVX512VBMI2) 914 .Case("avx512ifma", HasAVX512IFMA) 915 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 916 .Case("bmi", HasBMI) 917 .Case("bmi2", HasBMI2) 918 .Case("cldemote", HasCLDEMOTE) 919 .Case("clflushopt", HasCLFLUSHOPT) 920 .Case("clwb", HasCLWB) 921 .Case("clzero", HasCLZERO) 922 .Case("cx8", HasCX8) 923 .Case("cx16", HasCX16) 924 .Case("enqcmd", HasENQCMD) 925 .Case("f16c", HasF16C) 926 .Case("fma", HasFMA) 927 .Case("fma4", XOPLevel >= FMA4) 928 .Case("fsgsbase", HasFSGSBASE) 929 .Case("fxsr", HasFXSR) 930 .Case("gfni", HasGFNI) 931 .Case("invpcid", HasINVPCID) 932 .Case("kl", HasKL) 933 .Case("widekl", HasWIDEKL) 934 .Case("lwp", HasLWP) 935 .Case("lzcnt", HasLZCNT) 936 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 937 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 938 .Case("mmx", MMX3DNowLevel >= MMX) 939 .Case("movbe", HasMOVBE) 940 .Case("movdiri", HasMOVDIRI) 941 .Case("movdir64b", HasMOVDIR64B) 942 .Case("mwaitx", HasMWAITX) 943 .Case("pclmul", HasPCLMUL) 944 .Case("pconfig", HasPCONFIG) 945 .Case("pku", HasPKU) 946 .Case("popcnt", HasPOPCNT) 947 .Case("prefetchwt1", HasPREFETCHWT1) 948 .Case("prfchw", HasPRFCHW) 949 .Case("ptwrite", HasPTWRITE) 950 .Case("rdpid", HasRDPID) 951 .Case("rdrnd", HasRDRND) 952 .Case("rdseed", HasRDSEED) 953 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 954 .Case("rtm", HasRTM) 955 .Case("sahf", HasLAHFSAHF) 956 .Case("serialize", HasSERIALIZE) 957 .Case("sgx", HasSGX) 958 .Case("sha", HasSHA) 959 .Case("shstk", HasSHSTK) 960 .Case("sse", SSELevel >= SSE1) 961 .Case("sse2", SSELevel >= SSE2) 962 .Case("sse3", SSELevel >= SSE3) 963 .Case("ssse3", SSELevel >= SSSE3) 964 .Case("sse4.1", SSELevel >= SSE41) 965 .Case("sse4.2", SSELevel >= SSE42) 966 .Case("sse4a", XOPLevel >= SSE4A) 967 .Case("tbm", HasTBM) 968 .Case("tsxldtrk", HasTSXLDTRK) 969 .Case("vaes", HasVAES) 970 .Case("vpclmulqdq", HasVPCLMULQDQ) 971 .Case("wbnoinvd", HasWBNOINVD) 972 .Case("waitpkg", HasWAITPKG) 973 .Case("x86", true) 974 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 975 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 976 .Case("xop", XOPLevel >= XOP) 977 .Case("xsave", HasXSAVE) 978 .Case("xsavec", HasXSAVEC) 979 .Case("xsaves", HasXSAVES) 980 .Case("xsaveopt", HasXSAVEOPT) 981 .Default(false); 982 } 983 984 // We can't use a generic validation scheme for the features accepted here 985 // versus subtarget features accepted in the target attribute because the 986 // bitfield structure that's initialized in the runtime only supports the 987 // below currently rather than the full range of subtarget features. (See 988 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 989 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 990 return llvm::StringSwitch<bool>(FeatureStr) 991 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 992 #include "llvm/Support/X86TargetParser.def" 993 .Default(false); 994 } 995 996 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 997 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 998 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 999 #include "llvm/Support/X86TargetParser.def" 1000 ; 1001 // Note, this function should only be used after ensuring the value is 1002 // correct, so it asserts if the value is out of range. 1003 } 1004 1005 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1006 enum class FeatPriority { 1007 #define FEATURE(FEAT) FEAT, 1008 #include "clang/Basic/X86Target.def" 1009 }; 1010 switch (Feat) { 1011 #define FEATURE(FEAT) \ 1012 case llvm::X86::FEAT: \ 1013 return static_cast<unsigned>(FeatPriority::FEAT); 1014 #include "clang/Basic/X86Target.def" 1015 default: 1016 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1017 } 1018 } 1019 1020 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1021 // Valid CPUs have a 'key feature' that compares just better than its key 1022 // feature. 1023 using namespace llvm::X86; 1024 CPUKind Kind = parseArchX86(Name); 1025 if (Kind != CK_None) { 1026 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1027 return (getFeaturePriority(KeyFeature) << 1) + 1; 1028 } 1029 1030 // Now we know we have a feature, so get its priority and shift it a few so 1031 // that we have sufficient room for the CPUs (above). 1032 return getFeaturePriority(getFeature(Name)) << 1; 1033 } 1034 1035 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1036 return llvm::StringSwitch<bool>(Name) 1037 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1038 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1039 #include "clang/Basic/X86Target.def" 1040 .Default(false); 1041 } 1042 1043 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1044 return llvm::StringSwitch<StringRef>(Name) 1045 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1046 #include "clang/Basic/X86Target.def" 1047 .Default(Name); 1048 } 1049 1050 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1051 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1052 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1053 #include "clang/Basic/X86Target.def" 1054 .Default(0); 1055 } 1056 1057 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1058 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1059 StringRef WholeList = 1060 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1061 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1062 #include "clang/Basic/X86Target.def" 1063 .Default(""); 1064 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1065 } 1066 1067 // We can't use a generic validation scheme for the cpus accepted here 1068 // versus subtarget cpus accepted in the target attribute because the 1069 // variables intitialized by the runtime only support the below currently 1070 // rather than the full range of cpus. 1071 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1072 return llvm::StringSwitch<bool>(FeatureStr) 1073 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1074 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1075 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1076 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1077 #include "llvm/Support/X86TargetParser.def" 1078 .Default(false); 1079 } 1080 1081 static unsigned matchAsmCCConstraint(const char *&Name) { 1082 auto RV = llvm::StringSwitch<unsigned>(Name) 1083 .Case("@cca", 4) 1084 .Case("@ccae", 5) 1085 .Case("@ccb", 4) 1086 .Case("@ccbe", 5) 1087 .Case("@ccc", 4) 1088 .Case("@cce", 4) 1089 .Case("@ccz", 4) 1090 .Case("@ccg", 4) 1091 .Case("@ccge", 5) 1092 .Case("@ccl", 4) 1093 .Case("@ccle", 5) 1094 .Case("@ccna", 5) 1095 .Case("@ccnae", 6) 1096 .Case("@ccnb", 5) 1097 .Case("@ccnbe", 6) 1098 .Case("@ccnc", 5) 1099 .Case("@ccne", 5) 1100 .Case("@ccnz", 5) 1101 .Case("@ccng", 5) 1102 .Case("@ccnge", 6) 1103 .Case("@ccnl", 5) 1104 .Case("@ccnle", 6) 1105 .Case("@ccno", 5) 1106 .Case("@ccnp", 5) 1107 .Case("@ccns", 5) 1108 .Case("@cco", 4) 1109 .Case("@ccp", 4) 1110 .Case("@ccs", 4) 1111 .Default(0); 1112 return RV; 1113 } 1114 1115 bool X86TargetInfo::validateAsmConstraint( 1116 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1117 switch (*Name) { 1118 default: 1119 return false; 1120 // Constant constraints. 1121 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1122 // instructions. 1123 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1124 // x86_64 instructions. 1125 case 's': 1126 Info.setRequiresImmediate(); 1127 return true; 1128 case 'I': 1129 Info.setRequiresImmediate(0, 31); 1130 return true; 1131 case 'J': 1132 Info.setRequiresImmediate(0, 63); 1133 return true; 1134 case 'K': 1135 Info.setRequiresImmediate(-128, 127); 1136 return true; 1137 case 'L': 1138 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1139 return true; 1140 case 'M': 1141 Info.setRequiresImmediate(0, 3); 1142 return true; 1143 case 'N': 1144 Info.setRequiresImmediate(0, 255); 1145 return true; 1146 case 'O': 1147 Info.setRequiresImmediate(0, 127); 1148 return true; 1149 // Register constraints. 1150 case 'Y': // 'Y' is the first character for several 2-character constraints. 1151 // Shift the pointer to the second character of the constraint. 1152 Name++; 1153 switch (*Name) { 1154 default: 1155 return false; 1156 case 'z': // First SSE register. 1157 case '2': 1158 case 't': // Any SSE register, when SSE2 is enabled. 1159 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1160 case 'm': // Any MMX register, when inter-unit moves enabled. 1161 case 'k': // AVX512 arch mask registers: k1-k7. 1162 Info.setAllowsRegister(); 1163 return true; 1164 } 1165 case 'f': // Any x87 floating point stack register. 1166 // Constraint 'f' cannot be used for output operands. 1167 if (Info.ConstraintStr[0] == '=') 1168 return false; 1169 Info.setAllowsRegister(); 1170 return true; 1171 case 'a': // eax. 1172 case 'b': // ebx. 1173 case 'c': // ecx. 1174 case 'd': // edx. 1175 case 'S': // esi. 1176 case 'D': // edi. 1177 case 'A': // edx:eax. 1178 case 't': // Top of floating point stack. 1179 case 'u': // Second from top of floating point stack. 1180 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1181 case 'y': // Any MMX register. 1182 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1183 case 'x': // Any SSE register. 1184 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1185 // for intermideate k reg operations). 1186 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1187 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1188 case 'l': // "Index" registers: any general register that can be used as an 1189 // index in a base+index memory access. 1190 Info.setAllowsRegister(); 1191 return true; 1192 // Floating point constant constraints. 1193 case 'C': // SSE floating point constant. 1194 case 'G': // x87 floating point constant. 1195 return true; 1196 case '@': 1197 // CC condition changes. 1198 if (auto Len = matchAsmCCConstraint(Name)) { 1199 Name += Len - 1; 1200 Info.setAllowsRegister(); 1201 return true; 1202 } 1203 return false; 1204 } 1205 } 1206 1207 // Below is based on the following information: 1208 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1209 // | Processor Name | Cache Line Size (Bytes) | Source | 1210 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1211 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1212 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1213 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1214 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1215 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1216 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1217 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1218 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1219 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1220 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1221 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1222 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1223 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1224 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1225 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1226 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1227 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1228 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1229 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1230 using namespace llvm::X86; 1231 switch (CPU) { 1232 // i386 1233 case CK_i386: 1234 // i486 1235 case CK_i486: 1236 case CK_WinChipC6: 1237 case CK_WinChip2: 1238 case CK_C3: 1239 // Lakemont 1240 case CK_Lakemont: 1241 return 16; 1242 1243 // i586 1244 case CK_i586: 1245 case CK_Pentium: 1246 case CK_PentiumMMX: 1247 // i686 1248 case CK_PentiumPro: 1249 case CK_i686: 1250 case CK_Pentium2: 1251 case CK_Pentium3: 1252 case CK_PentiumM: 1253 case CK_C3_2: 1254 // K6 1255 case CK_K6: 1256 case CK_K6_2: 1257 case CK_K6_3: 1258 // Geode 1259 case CK_Geode: 1260 return 32; 1261 1262 // Netburst 1263 case CK_Pentium4: 1264 case CK_Prescott: 1265 case CK_Nocona: 1266 // Atom 1267 case CK_Bonnell: 1268 case CK_Silvermont: 1269 case CK_Goldmont: 1270 case CK_GoldmontPlus: 1271 case CK_Tremont: 1272 1273 case CK_Westmere: 1274 case CK_SandyBridge: 1275 case CK_IvyBridge: 1276 case CK_Haswell: 1277 case CK_Broadwell: 1278 case CK_SkylakeClient: 1279 case CK_SkylakeServer: 1280 case CK_Cascadelake: 1281 case CK_Nehalem: 1282 case CK_Cooperlake: 1283 case CK_Cannonlake: 1284 case CK_Tigerlake: 1285 case CK_SapphireRapids: 1286 case CK_IcelakeClient: 1287 case CK_IcelakeServer: 1288 case CK_KNL: 1289 case CK_KNM: 1290 // K7 1291 case CK_Athlon: 1292 case CK_AthlonXP: 1293 // K8 1294 case CK_K8: 1295 case CK_K8SSE3: 1296 case CK_AMDFAM10: 1297 // Bobcat 1298 case CK_BTVER1: 1299 case CK_BTVER2: 1300 // Bulldozer 1301 case CK_BDVER1: 1302 case CK_BDVER2: 1303 case CK_BDVER3: 1304 case CK_BDVER4: 1305 // Zen 1306 case CK_ZNVER1: 1307 case CK_ZNVER2: 1308 // Deprecated 1309 case CK_x86_64: 1310 case CK_Yonah: 1311 case CK_Penryn: 1312 case CK_Core2: 1313 return 64; 1314 1315 // The following currently have unknown cache line sizes (but they are probably all 64): 1316 // Core 1317 case CK_None: 1318 return None; 1319 } 1320 llvm_unreachable("Unknown CPU kind"); 1321 } 1322 1323 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1324 StringRef Constraint, 1325 unsigned Size) const { 1326 // Strip off constraint modifiers. 1327 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1328 Constraint = Constraint.substr(1); 1329 1330 return validateOperandSize(FeatureMap, Constraint, Size); 1331 } 1332 1333 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1334 StringRef Constraint, 1335 unsigned Size) const { 1336 return validateOperandSize(FeatureMap, Constraint, Size); 1337 } 1338 1339 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1340 StringRef Constraint, 1341 unsigned Size) const { 1342 switch (Constraint[0]) { 1343 default: 1344 break; 1345 case 'k': 1346 // Registers k0-k7 (AVX512) size limit is 64 bit. 1347 case 'y': 1348 return Size <= 64; 1349 case 'f': 1350 case 't': 1351 case 'u': 1352 return Size <= 128; 1353 case 'Y': 1354 // 'Y' is the first character for several 2-character constraints. 1355 switch (Constraint[1]) { 1356 default: 1357 return false; 1358 case 'm': 1359 // 'Ym' is synonymous with 'y'. 1360 case 'k': 1361 return Size <= 64; 1362 case 'z': 1363 // XMM0/YMM/ZMM0 1364 if (FeatureMap.lookup("avx512f")) 1365 // ZMM0 can be used if target supports AVX512F. 1366 return Size <= 512U; 1367 else if (FeatureMap.lookup("avx")) 1368 // YMM0 can be used if target supports AVX. 1369 return Size <= 256U; 1370 else if (FeatureMap.lookup("sse")) 1371 return Size <= 128U; 1372 return false; 1373 case 'i': 1374 case 't': 1375 case '2': 1376 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1377 if (SSELevel < SSE2) 1378 return false; 1379 break; 1380 } 1381 break; 1382 case 'v': 1383 case 'x': 1384 if (FeatureMap.lookup("avx512f")) 1385 // 512-bit zmm registers can be used if target supports AVX512F. 1386 return Size <= 512U; 1387 else if (FeatureMap.lookup("avx")) 1388 // 256-bit ymm registers can be used if target supports AVX. 1389 return Size <= 256U; 1390 return Size <= 128U; 1391 1392 } 1393 1394 return true; 1395 } 1396 1397 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1398 switch (*Constraint) { 1399 case '@': 1400 if (auto Len = matchAsmCCConstraint(Constraint)) { 1401 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1402 Constraint += Len - 1; 1403 return Converted; 1404 } 1405 return std::string(1, *Constraint); 1406 case 'a': 1407 return std::string("{ax}"); 1408 case 'b': 1409 return std::string("{bx}"); 1410 case 'c': 1411 return std::string("{cx}"); 1412 case 'd': 1413 return std::string("{dx}"); 1414 case 'S': 1415 return std::string("{si}"); 1416 case 'D': 1417 return std::string("{di}"); 1418 case 'p': // address 1419 return std::string("im"); 1420 case 't': // top of floating point stack. 1421 return std::string("{st}"); 1422 case 'u': // second from top of floating point stack. 1423 return std::string("{st(1)}"); // second from top of floating point stack. 1424 case 'Y': 1425 switch (Constraint[1]) { 1426 default: 1427 // Break from inner switch and fall through (copy single char), 1428 // continue parsing after copying the current constraint into 1429 // the return string. 1430 break; 1431 case 'k': 1432 case 'm': 1433 case 'i': 1434 case 't': 1435 case 'z': 1436 case '2': 1437 // "^" hints llvm that this is a 2 letter constraint. 1438 // "Constraint++" is used to promote the string iterator 1439 // to the next constraint. 1440 return std::string("^") + std::string(Constraint++, 2); 1441 } 1442 LLVM_FALLTHROUGH; 1443 default: 1444 return std::string(1, *Constraint); 1445 } 1446 } 1447 1448 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1449 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1450 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1451 } 1452 1453 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1454 llvm::X86::fillValidCPUArchList(Values); 1455 } 1456 1457 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1458 return llvm::makeArrayRef(GCCRegNames); 1459 } 1460 1461 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1462 return llvm::makeArrayRef(AddlRegNames); 1463 } 1464 1465 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1466 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1467 Builtin::FirstTSBuiltin + 1); 1468 } 1469 1470 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1471 return llvm::makeArrayRef(BuiltinInfoX86, 1472 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1473 } 1474