1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::checkCFProtectionReturnSupported( 106 DiagnosticsEngine &Diags) const { 107 if (HasSHSTK) 108 return true; 109 110 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 111 << "-mshstk"; 112 return false; 113 } 114 115 bool X86TargetInfo::checkCFProtectionBranchSupported( 116 DiagnosticsEngine &Diags) const { 117 if (HasIBT) 118 return true; 119 120 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 121 << "-mibt"; 122 return false; 123 } 124 125 bool X86TargetInfo::initFeatureMap( 126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 127 const std::vector<std::string> &FeaturesVec) const { 128 // FIXME: This *really* should not be here. 129 // X86_64 always has SSE2. 130 if (getTriple().getArch() == llvm::Triple::x86_64) 131 setFeatureEnabledImpl(Features, "sse2", true); 132 133 const CPUKind Kind = getCPUKind(CPU); 134 135 // Enable X87 for all X86 processors but Lakemont. 136 if (Kind != CK_Lakemont) 137 setFeatureEnabledImpl(Features, "x87", true); 138 139 switch (Kind) { 140 case CK_Generic: 141 case CK_i386: 142 case CK_i486: 143 case CK_i586: 144 case CK_Pentium: 145 case CK_PentiumPro: 146 case CK_Lakemont: 147 break; 148 149 case CK_PentiumMMX: 150 case CK_Pentium2: 151 case CK_K6: 152 case CK_WinChipC6: 153 setFeatureEnabledImpl(Features, "mmx", true); 154 break; 155 156 case CK_IcelakeServer: 157 setFeatureEnabledImpl(Features, "pconfig", true); 158 setFeatureEnabledImpl(Features, "wbnoinvd", true); 159 LLVM_FALLTHROUGH; 160 case CK_IcelakeClient: 161 setFeatureEnabledImpl(Features, "vaes", true); 162 setFeatureEnabledImpl(Features, "gfni", true); 163 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 164 setFeatureEnabledImpl(Features, "avx512bitalg", true); 165 setFeatureEnabledImpl(Features, "avx512vnni", true); 166 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 167 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 168 setFeatureEnabledImpl(Features, "rdpid", true); 169 LLVM_FALLTHROUGH; 170 case CK_Cannonlake: 171 setFeatureEnabledImpl(Features, "avx512ifma", true); 172 setFeatureEnabledImpl(Features, "avx512vbmi", true); 173 setFeatureEnabledImpl(Features, "sha", true); 174 LLVM_FALLTHROUGH; 175 case CK_SkylakeServer: 176 setFeatureEnabledImpl(Features, "avx512f", true); 177 setFeatureEnabledImpl(Features, "avx512cd", true); 178 setFeatureEnabledImpl(Features, "avx512dq", true); 179 setFeatureEnabledImpl(Features, "avx512bw", true); 180 setFeatureEnabledImpl(Features, "avx512vl", true); 181 setFeatureEnabledImpl(Features, "pku", true); 182 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 183 setFeatureEnabledImpl(Features, "clwb", true); 184 LLVM_FALLTHROUGH; 185 case CK_SkylakeClient: 186 setFeatureEnabledImpl(Features, "xsavec", true); 187 setFeatureEnabledImpl(Features, "xsaves", true); 188 setFeatureEnabledImpl(Features, "mpx", true); 189 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 190 setFeatureEnabledImpl(Features, "sgx", true); 191 setFeatureEnabledImpl(Features, "clflushopt", true); 192 setFeatureEnabledImpl(Features, "rtm", true); 193 LLVM_FALLTHROUGH; 194 case CK_Broadwell: 195 setFeatureEnabledImpl(Features, "rdseed", true); 196 setFeatureEnabledImpl(Features, "adx", true); 197 setFeatureEnabledImpl(Features, "prfchw", true); 198 LLVM_FALLTHROUGH; 199 case CK_Haswell: 200 setFeatureEnabledImpl(Features, "avx2", true); 201 setFeatureEnabledImpl(Features, "lzcnt", true); 202 setFeatureEnabledImpl(Features, "bmi", true); 203 setFeatureEnabledImpl(Features, "bmi2", true); 204 setFeatureEnabledImpl(Features, "fma", true); 205 setFeatureEnabledImpl(Features, "movbe", true); 206 LLVM_FALLTHROUGH; 207 case CK_IvyBridge: 208 setFeatureEnabledImpl(Features, "rdrnd", true); 209 setFeatureEnabledImpl(Features, "f16c", true); 210 setFeatureEnabledImpl(Features, "fsgsbase", true); 211 LLVM_FALLTHROUGH; 212 case CK_SandyBridge: 213 setFeatureEnabledImpl(Features, "avx", true); 214 setFeatureEnabledImpl(Features, "xsave", true); 215 setFeatureEnabledImpl(Features, "xsaveopt", true); 216 LLVM_FALLTHROUGH; 217 case CK_Westmere: 218 setFeatureEnabledImpl(Features, "aes", true); 219 setFeatureEnabledImpl(Features, "pclmul", true); 220 LLVM_FALLTHROUGH; 221 case CK_Nehalem: 222 setFeatureEnabledImpl(Features, "sse4.2", true); 223 LLVM_FALLTHROUGH; 224 case CK_Penryn: 225 setFeatureEnabledImpl(Features, "sse4.1", true); 226 LLVM_FALLTHROUGH; 227 case CK_Core2: 228 setFeatureEnabledImpl(Features, "ssse3", true); 229 setFeatureEnabledImpl(Features, "sahf", true); 230 LLVM_FALLTHROUGH; 231 case CK_Yonah: 232 case CK_Prescott: 233 case CK_Nocona: 234 setFeatureEnabledImpl(Features, "sse3", true); 235 setFeatureEnabledImpl(Features, "cx16", true); 236 LLVM_FALLTHROUGH; 237 case CK_PentiumM: 238 case CK_Pentium4: 239 case CK_x86_64: 240 setFeatureEnabledImpl(Features, "sse2", true); 241 LLVM_FALLTHROUGH; 242 case CK_Pentium3: 243 case CK_C3_2: 244 setFeatureEnabledImpl(Features, "sse", true); 245 setFeatureEnabledImpl(Features, "fxsr", true); 246 break; 247 248 case CK_Tremont: 249 setFeatureEnabledImpl(Features, "cldemote", true); 250 setFeatureEnabledImpl(Features, "movdiri", true); 251 setFeatureEnabledImpl(Features, "movdir64b", true); 252 setFeatureEnabledImpl(Features, "gfni", true); 253 setFeatureEnabledImpl(Features, "waitpkg", true); 254 LLVM_FALLTHROUGH; 255 case CK_GoldmontPlus: 256 setFeatureEnabledImpl(Features, "rdpid", true); 257 setFeatureEnabledImpl(Features, "sgx", true); 258 LLVM_FALLTHROUGH; 259 case CK_Goldmont: 260 setFeatureEnabledImpl(Features, "sha", true); 261 setFeatureEnabledImpl(Features, "rdseed", true); 262 setFeatureEnabledImpl(Features, "xsave", true); 263 setFeatureEnabledImpl(Features, "xsaveopt", true); 264 setFeatureEnabledImpl(Features, "xsavec", true); 265 setFeatureEnabledImpl(Features, "xsaves", true); 266 setFeatureEnabledImpl(Features, "clflushopt", true); 267 setFeatureEnabledImpl(Features, "mpx", true); 268 setFeatureEnabledImpl(Features, "fsgsbase", true); 269 LLVM_FALLTHROUGH; 270 case CK_Silvermont: 271 setFeatureEnabledImpl(Features, "rdrnd", true); 272 setFeatureEnabledImpl(Features, "aes", true); 273 setFeatureEnabledImpl(Features, "pclmul", true); 274 setFeatureEnabledImpl(Features, "sse4.2", true); 275 setFeatureEnabledImpl(Features, "prfchw", true); 276 LLVM_FALLTHROUGH; 277 case CK_Bonnell: 278 setFeatureEnabledImpl(Features, "movbe", true); 279 setFeatureEnabledImpl(Features, "ssse3", true); 280 setFeatureEnabledImpl(Features, "fxsr", true); 281 setFeatureEnabledImpl(Features, "cx16", true); 282 setFeatureEnabledImpl(Features, "sahf", true); 283 break; 284 285 case CK_KNM: 286 // TODO: Add avx5124fmaps/avx5124vnniw. 287 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 288 LLVM_FALLTHROUGH; 289 case CK_KNL: 290 setFeatureEnabledImpl(Features, "avx512f", true); 291 setFeatureEnabledImpl(Features, "avx512cd", true); 292 setFeatureEnabledImpl(Features, "avx512er", true); 293 setFeatureEnabledImpl(Features, "avx512pf", true); 294 setFeatureEnabledImpl(Features, "prfchw", true); 295 setFeatureEnabledImpl(Features, "prefetchwt1", true); 296 setFeatureEnabledImpl(Features, "fxsr", true); 297 setFeatureEnabledImpl(Features, "rdseed", true); 298 setFeatureEnabledImpl(Features, "adx", true); 299 setFeatureEnabledImpl(Features, "lzcnt", true); 300 setFeatureEnabledImpl(Features, "bmi", true); 301 setFeatureEnabledImpl(Features, "bmi2", true); 302 setFeatureEnabledImpl(Features, "rtm", true); 303 setFeatureEnabledImpl(Features, "fma", true); 304 setFeatureEnabledImpl(Features, "rdrnd", true); 305 setFeatureEnabledImpl(Features, "f16c", true); 306 setFeatureEnabledImpl(Features, "fsgsbase", true); 307 setFeatureEnabledImpl(Features, "aes", true); 308 setFeatureEnabledImpl(Features, "pclmul", true); 309 setFeatureEnabledImpl(Features, "cx16", true); 310 setFeatureEnabledImpl(Features, "xsaveopt", true); 311 setFeatureEnabledImpl(Features, "xsave", true); 312 setFeatureEnabledImpl(Features, "movbe", true); 313 setFeatureEnabledImpl(Features, "sahf", true); 314 break; 315 316 case CK_K6_2: 317 case CK_K6_3: 318 case CK_WinChip2: 319 case CK_C3: 320 setFeatureEnabledImpl(Features, "3dnow", true); 321 break; 322 323 case CK_AMDFAM10: 324 setFeatureEnabledImpl(Features, "sse4a", true); 325 setFeatureEnabledImpl(Features, "lzcnt", true); 326 setFeatureEnabledImpl(Features, "popcnt", true); 327 setFeatureEnabledImpl(Features, "sahf", true); 328 LLVM_FALLTHROUGH; 329 case CK_K8SSE3: 330 setFeatureEnabledImpl(Features, "sse3", true); 331 LLVM_FALLTHROUGH; 332 case CK_K8: 333 setFeatureEnabledImpl(Features, "sse2", true); 334 LLVM_FALLTHROUGH; 335 case CK_AthlonXP: 336 setFeatureEnabledImpl(Features, "sse", true); 337 setFeatureEnabledImpl(Features, "fxsr", true); 338 LLVM_FALLTHROUGH; 339 case CK_Athlon: 340 case CK_Geode: 341 setFeatureEnabledImpl(Features, "3dnowa", true); 342 break; 343 344 case CK_BTVER2: 345 setFeatureEnabledImpl(Features, "avx", true); 346 setFeatureEnabledImpl(Features, "aes", true); 347 setFeatureEnabledImpl(Features, "pclmul", true); 348 setFeatureEnabledImpl(Features, "bmi", true); 349 setFeatureEnabledImpl(Features, "f16c", true); 350 setFeatureEnabledImpl(Features, "xsaveopt", true); 351 setFeatureEnabledImpl(Features, "movbe", true); 352 LLVM_FALLTHROUGH; 353 case CK_BTVER1: 354 setFeatureEnabledImpl(Features, "ssse3", true); 355 setFeatureEnabledImpl(Features, "sse4a", true); 356 setFeatureEnabledImpl(Features, "lzcnt", true); 357 setFeatureEnabledImpl(Features, "popcnt", true); 358 setFeatureEnabledImpl(Features, "prfchw", true); 359 setFeatureEnabledImpl(Features, "cx16", true); 360 setFeatureEnabledImpl(Features, "fxsr", true); 361 setFeatureEnabledImpl(Features, "sahf", true); 362 break; 363 364 case CK_ZNVER1: 365 setFeatureEnabledImpl(Features, "adx", true); 366 setFeatureEnabledImpl(Features, "aes", true); 367 setFeatureEnabledImpl(Features, "avx2", true); 368 setFeatureEnabledImpl(Features, "bmi", true); 369 setFeatureEnabledImpl(Features, "bmi2", true); 370 setFeatureEnabledImpl(Features, "clflushopt", true); 371 setFeatureEnabledImpl(Features, "clzero", true); 372 setFeatureEnabledImpl(Features, "cx16", true); 373 setFeatureEnabledImpl(Features, "f16c", true); 374 setFeatureEnabledImpl(Features, "fma", true); 375 setFeatureEnabledImpl(Features, "fsgsbase", true); 376 setFeatureEnabledImpl(Features, "fxsr", true); 377 setFeatureEnabledImpl(Features, "lzcnt", true); 378 setFeatureEnabledImpl(Features, "mwaitx", true); 379 setFeatureEnabledImpl(Features, "movbe", true); 380 setFeatureEnabledImpl(Features, "pclmul", true); 381 setFeatureEnabledImpl(Features, "popcnt", true); 382 setFeatureEnabledImpl(Features, "prfchw", true); 383 setFeatureEnabledImpl(Features, "rdrnd", true); 384 setFeatureEnabledImpl(Features, "rdseed", true); 385 setFeatureEnabledImpl(Features, "sahf", true); 386 setFeatureEnabledImpl(Features, "sha", true); 387 setFeatureEnabledImpl(Features, "sse4a", true); 388 setFeatureEnabledImpl(Features, "xsave", true); 389 setFeatureEnabledImpl(Features, "xsavec", true); 390 setFeatureEnabledImpl(Features, "xsaveopt", true); 391 setFeatureEnabledImpl(Features, "xsaves", true); 392 break; 393 394 case CK_BDVER4: 395 setFeatureEnabledImpl(Features, "avx2", true); 396 setFeatureEnabledImpl(Features, "bmi2", true); 397 setFeatureEnabledImpl(Features, "mwaitx", true); 398 LLVM_FALLTHROUGH; 399 case CK_BDVER3: 400 setFeatureEnabledImpl(Features, "fsgsbase", true); 401 setFeatureEnabledImpl(Features, "xsaveopt", true); 402 LLVM_FALLTHROUGH; 403 case CK_BDVER2: 404 setFeatureEnabledImpl(Features, "bmi", true); 405 setFeatureEnabledImpl(Features, "fma", true); 406 setFeatureEnabledImpl(Features, "f16c", true); 407 setFeatureEnabledImpl(Features, "tbm", true); 408 LLVM_FALLTHROUGH; 409 case CK_BDVER1: 410 // xop implies avx, sse4a and fma4. 411 setFeatureEnabledImpl(Features, "xop", true); 412 setFeatureEnabledImpl(Features, "lwp", true); 413 setFeatureEnabledImpl(Features, "lzcnt", true); 414 setFeatureEnabledImpl(Features, "aes", true); 415 setFeatureEnabledImpl(Features, "pclmul", true); 416 setFeatureEnabledImpl(Features, "prfchw", true); 417 setFeatureEnabledImpl(Features, "cx16", true); 418 setFeatureEnabledImpl(Features, "fxsr", true); 419 setFeatureEnabledImpl(Features, "xsave", true); 420 setFeatureEnabledImpl(Features, "sahf", true); 421 break; 422 } 423 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 424 return false; 425 426 // Can't do this earlier because we need to be able to explicitly enable 427 // or disable these features and the things that they depend upon. 428 429 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 430 auto I = Features.find("sse4.2"); 431 if (I != Features.end() && I->getValue() && 432 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 433 FeaturesVec.end()) 434 Features["popcnt"] = true; 435 436 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 437 I = Features.find("3dnow"); 438 if (I != Features.end() && I->getValue() && 439 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 440 FeaturesVec.end()) 441 Features["prfchw"] = true; 442 443 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 444 // then enable MMX. 445 I = Features.find("sse"); 446 if (I != Features.end() && I->getValue() && 447 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 448 FeaturesVec.end()) 449 Features["mmx"] = true; 450 451 return true; 452 } 453 454 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 455 X86SSEEnum Level, bool Enabled) { 456 if (Enabled) { 457 switch (Level) { 458 case AVX512F: 459 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 460 LLVM_FALLTHROUGH; 461 case AVX2: 462 Features["avx2"] = true; 463 LLVM_FALLTHROUGH; 464 case AVX: 465 Features["avx"] = true; 466 Features["xsave"] = true; 467 LLVM_FALLTHROUGH; 468 case SSE42: 469 Features["sse4.2"] = true; 470 LLVM_FALLTHROUGH; 471 case SSE41: 472 Features["sse4.1"] = true; 473 LLVM_FALLTHROUGH; 474 case SSSE3: 475 Features["ssse3"] = true; 476 LLVM_FALLTHROUGH; 477 case SSE3: 478 Features["sse3"] = true; 479 LLVM_FALLTHROUGH; 480 case SSE2: 481 Features["sse2"] = true; 482 LLVM_FALLTHROUGH; 483 case SSE1: 484 Features["sse"] = true; 485 LLVM_FALLTHROUGH; 486 case NoSSE: 487 break; 488 } 489 return; 490 } 491 492 switch (Level) { 493 case NoSSE: 494 case SSE1: 495 Features["sse"] = false; 496 LLVM_FALLTHROUGH; 497 case SSE2: 498 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 499 Features["gfni"] = false; 500 LLVM_FALLTHROUGH; 501 case SSE3: 502 Features["sse3"] = false; 503 setXOPLevel(Features, NoXOP, false); 504 LLVM_FALLTHROUGH; 505 case SSSE3: 506 Features["ssse3"] = false; 507 LLVM_FALLTHROUGH; 508 case SSE41: 509 Features["sse4.1"] = false; 510 LLVM_FALLTHROUGH; 511 case SSE42: 512 Features["sse4.2"] = false; 513 LLVM_FALLTHROUGH; 514 case AVX: 515 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 516 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 517 setXOPLevel(Features, FMA4, false); 518 LLVM_FALLTHROUGH; 519 case AVX2: 520 Features["avx2"] = false; 521 LLVM_FALLTHROUGH; 522 case AVX512F: 523 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 524 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 525 Features["avx512vl"] = Features["avx512vbmi"] = 526 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 527 Features["avx512bitalg"] = Features["avx512vnni"] = 528 Features["avx512vbmi2"] = false; 529 break; 530 } 531 } 532 533 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 534 MMX3DNowEnum Level, bool Enabled) { 535 if (Enabled) { 536 switch (Level) { 537 case AMD3DNowAthlon: 538 Features["3dnowa"] = true; 539 LLVM_FALLTHROUGH; 540 case AMD3DNow: 541 Features["3dnow"] = true; 542 LLVM_FALLTHROUGH; 543 case MMX: 544 Features["mmx"] = true; 545 LLVM_FALLTHROUGH; 546 case NoMMX3DNow: 547 break; 548 } 549 return; 550 } 551 552 switch (Level) { 553 case NoMMX3DNow: 554 case MMX: 555 Features["mmx"] = false; 556 LLVM_FALLTHROUGH; 557 case AMD3DNow: 558 Features["3dnow"] = false; 559 LLVM_FALLTHROUGH; 560 case AMD3DNowAthlon: 561 Features["3dnowa"] = false; 562 break; 563 } 564 } 565 566 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 567 bool Enabled) { 568 if (Enabled) { 569 switch (Level) { 570 case XOP: 571 Features["xop"] = true; 572 LLVM_FALLTHROUGH; 573 case FMA4: 574 Features["fma4"] = true; 575 setSSELevel(Features, AVX, true); 576 LLVM_FALLTHROUGH; 577 case SSE4A: 578 Features["sse4a"] = true; 579 setSSELevel(Features, SSE3, true); 580 LLVM_FALLTHROUGH; 581 case NoXOP: 582 break; 583 } 584 return; 585 } 586 587 switch (Level) { 588 case NoXOP: 589 case SSE4A: 590 Features["sse4a"] = false; 591 LLVM_FALLTHROUGH; 592 case FMA4: 593 Features["fma4"] = false; 594 LLVM_FALLTHROUGH; 595 case XOP: 596 Features["xop"] = false; 597 break; 598 } 599 } 600 601 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 602 StringRef Name, bool Enabled) { 603 // This is a bit of a hack to deal with the sse4 target feature when used 604 // as part of the target attribute. We handle sse4 correctly everywhere 605 // else. See below for more information on how we handle the sse4 options. 606 if (Name != "sse4") 607 Features[Name] = Enabled; 608 609 if (Name == "mmx") { 610 setMMXLevel(Features, MMX, Enabled); 611 } else if (Name == "sse") { 612 setSSELevel(Features, SSE1, Enabled); 613 } else if (Name == "sse2") { 614 setSSELevel(Features, SSE2, Enabled); 615 } else if (Name == "sse3") { 616 setSSELevel(Features, SSE3, Enabled); 617 } else if (Name == "ssse3") { 618 setSSELevel(Features, SSSE3, Enabled); 619 } else if (Name == "sse4.2") { 620 setSSELevel(Features, SSE42, Enabled); 621 } else if (Name == "sse4.1") { 622 setSSELevel(Features, SSE41, Enabled); 623 } else if (Name == "3dnow") { 624 setMMXLevel(Features, AMD3DNow, Enabled); 625 } else if (Name == "3dnowa") { 626 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 627 } else if (Name == "aes") { 628 if (Enabled) 629 setSSELevel(Features, SSE2, Enabled); 630 else 631 Features["vaes"] = false; 632 } else if (Name == "vaes") { 633 if (Enabled) { 634 setSSELevel(Features, AVX, Enabled); 635 Features["aes"] = true; 636 } 637 } else if (Name == "pclmul") { 638 if (Enabled) 639 setSSELevel(Features, SSE2, Enabled); 640 else 641 Features["vpclmulqdq"] = false; 642 } else if (Name == "vpclmulqdq") { 643 if (Enabled) { 644 setSSELevel(Features, AVX, Enabled); 645 Features["pclmul"] = true; 646 } 647 } else if (Name == "gfni") { 648 if (Enabled) 649 setSSELevel(Features, SSE2, Enabled); 650 } else if (Name == "avx") { 651 setSSELevel(Features, AVX, Enabled); 652 } else if (Name == "avx2") { 653 setSSELevel(Features, AVX2, Enabled); 654 } else if (Name == "avx512f") { 655 setSSELevel(Features, AVX512F, Enabled); 656 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 657 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 658 Name == "avx512vbmi" || Name == "avx512ifma" || 659 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 660 Name == "avx512vnni" || Name == "avx512vbmi2") { 661 if (Enabled) 662 setSSELevel(Features, AVX512F, Enabled); 663 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 664 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 665 Features["avx512bw"] = true; 666 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 667 if (Name == "avx512bw" && !Enabled) 668 Features["avx512vbmi"] = Features["avx512vbmi2"] = 669 Features["avx512bitalg"] = false; 670 } else if (Name == "fma") { 671 if (Enabled) 672 setSSELevel(Features, AVX, Enabled); 673 else 674 setSSELevel(Features, AVX512F, Enabled); 675 } else if (Name == "fma4") { 676 setXOPLevel(Features, FMA4, Enabled); 677 } else if (Name == "xop") { 678 setXOPLevel(Features, XOP, Enabled); 679 } else if (Name == "sse4a") { 680 setXOPLevel(Features, SSE4A, Enabled); 681 } else if (Name == "f16c") { 682 if (Enabled) 683 setSSELevel(Features, AVX, Enabled); 684 else 685 setSSELevel(Features, AVX512F, Enabled); 686 } else if (Name == "sha") { 687 if (Enabled) 688 setSSELevel(Features, SSE2, Enabled); 689 } else if (Name == "sse4") { 690 // We can get here via the __target__ attribute since that's not controlled 691 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 692 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 693 // disabled. 694 if (Enabled) 695 setSSELevel(Features, SSE42, Enabled); 696 else 697 setSSELevel(Features, SSE41, Enabled); 698 } else if (Name == "xsave") { 699 if (!Enabled) 700 Features["xsaveopt"] = false; 701 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 702 if (Enabled) 703 Features["xsave"] = true; 704 } 705 } 706 707 /// handleTargetFeatures - Perform initialization based on the user 708 /// configured set of features. 709 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 710 DiagnosticsEngine &Diags) { 711 for (const auto &Feature : Features) { 712 if (Feature[0] != '+') 713 continue; 714 715 if (Feature == "+aes") { 716 HasAES = true; 717 } else if (Feature == "+vaes") { 718 HasVAES = true; 719 } else if (Feature == "+pclmul") { 720 HasPCLMUL = true; 721 } else if (Feature == "+vpclmulqdq") { 722 HasVPCLMULQDQ = true; 723 } else if (Feature == "+lzcnt") { 724 HasLZCNT = true; 725 } else if (Feature == "+rdrnd") { 726 HasRDRND = true; 727 } else if (Feature == "+fsgsbase") { 728 HasFSGSBASE = true; 729 } else if (Feature == "+bmi") { 730 HasBMI = true; 731 } else if (Feature == "+bmi2") { 732 HasBMI2 = true; 733 } else if (Feature == "+popcnt") { 734 HasPOPCNT = true; 735 } else if (Feature == "+rtm") { 736 HasRTM = true; 737 } else if (Feature == "+prfchw") { 738 HasPRFCHW = true; 739 } else if (Feature == "+rdseed") { 740 HasRDSEED = true; 741 } else if (Feature == "+adx") { 742 HasADX = true; 743 } else if (Feature == "+tbm") { 744 HasTBM = true; 745 } else if (Feature == "+lwp") { 746 HasLWP = true; 747 } else if (Feature == "+fma") { 748 HasFMA = true; 749 } else if (Feature == "+f16c") { 750 HasF16C = true; 751 } else if (Feature == "+gfni") { 752 HasGFNI = true; 753 } else if (Feature == "+avx512cd") { 754 HasAVX512CD = true; 755 } else if (Feature == "+avx512vpopcntdq") { 756 HasAVX512VPOPCNTDQ = true; 757 } else if (Feature == "+avx512vnni") { 758 HasAVX512VNNI = true; 759 } else if (Feature == "+avx512er") { 760 HasAVX512ER = true; 761 } else if (Feature == "+avx512pf") { 762 HasAVX512PF = true; 763 } else if (Feature == "+avx512dq") { 764 HasAVX512DQ = true; 765 } else if (Feature == "+avx512bitalg") { 766 HasAVX512BITALG = true; 767 } else if (Feature == "+avx512bw") { 768 HasAVX512BW = true; 769 } else if (Feature == "+avx512vl") { 770 HasAVX512VL = true; 771 } else if (Feature == "+avx512vbmi") { 772 HasAVX512VBMI = true; 773 } else if (Feature == "+avx512vbmi2") { 774 HasAVX512VBMI2 = true; 775 } else if (Feature == "+avx512ifma") { 776 HasAVX512IFMA = true; 777 } else if (Feature == "+sha") { 778 HasSHA = true; 779 } else if (Feature == "+mpx") { 780 HasMPX = true; 781 } else if (Feature == "+shstk") { 782 HasSHSTK = true; 783 } else if (Feature == "+ibt") { 784 HasIBT = true; 785 } else if (Feature == "+movbe") { 786 HasMOVBE = true; 787 } else if (Feature == "+sgx") { 788 HasSGX = true; 789 } else if (Feature == "+cx16") { 790 HasCX16 = true; 791 } else if (Feature == "+fxsr") { 792 HasFXSR = true; 793 } else if (Feature == "+xsave") { 794 HasXSAVE = true; 795 } else if (Feature == "+xsaveopt") { 796 HasXSAVEOPT = true; 797 } else if (Feature == "+xsavec") { 798 HasXSAVEC = true; 799 } else if (Feature == "+xsaves") { 800 HasXSAVES = true; 801 } else if (Feature == "+mwaitx") { 802 HasMWAITX = true; 803 } else if (Feature == "+pku") { 804 HasPKU = true; 805 } else if (Feature == "+clflushopt") { 806 HasCLFLUSHOPT = true; 807 } else if (Feature == "+clwb") { 808 HasCLWB = true; 809 } else if (Feature == "+wbnoinvd") { 810 HasWBNOINVD = true; 811 } else if (Feature == "+prefetchwt1") { 812 HasPREFETCHWT1 = true; 813 } else if (Feature == "+clzero") { 814 HasCLZERO = true; 815 } else if (Feature == "+cldemote") { 816 HasCLDEMOTE = true; 817 } else if (Feature == "+rdpid") { 818 HasRDPID = true; 819 } else if (Feature == "+retpoline") { 820 HasRetpoline = true; 821 } else if (Feature == "+retpoline-external-thunk") { 822 HasRetpolineExternalThunk = true; 823 } else if (Feature == "+sahf") { 824 HasLAHFSAHF = true; 825 } else if (Feature == "+waitpkg") { 826 HasWAITPKG = true; 827 } else if (Feature == "+movdiri") { 828 HasMOVDIRI = true; 829 } else if (Feature == "+movdir64b") { 830 HasMOVDIR64B = true; 831 } else if (Feature == "+pconfig") { 832 HasPCONFIG = true; 833 } 834 835 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 836 .Case("+avx512f", AVX512F) 837 .Case("+avx2", AVX2) 838 .Case("+avx", AVX) 839 .Case("+sse4.2", SSE42) 840 .Case("+sse4.1", SSE41) 841 .Case("+ssse3", SSSE3) 842 .Case("+sse3", SSE3) 843 .Case("+sse2", SSE2) 844 .Case("+sse", SSE1) 845 .Default(NoSSE); 846 SSELevel = std::max(SSELevel, Level); 847 848 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 849 .Case("+3dnowa", AMD3DNowAthlon) 850 .Case("+3dnow", AMD3DNow) 851 .Case("+mmx", MMX) 852 .Default(NoMMX3DNow); 853 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 854 855 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 856 .Case("+xop", XOP) 857 .Case("+fma4", FMA4) 858 .Case("+sse4a", SSE4A) 859 .Default(NoXOP); 860 XOPLevel = std::max(XOPLevel, XLevel); 861 } 862 863 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 864 // matches the selected sse level. 865 if ((FPMath == FP_SSE && SSELevel < SSE1) || 866 (FPMath == FP_387 && SSELevel >= SSE1)) { 867 Diags.Report(diag::err_target_unsupported_fpmath) 868 << (FPMath == FP_SSE ? "sse" : "387"); 869 return false; 870 } 871 872 SimdDefaultAlign = 873 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 874 return true; 875 } 876 877 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 878 /// definitions for this particular subtarget. 879 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 880 MacroBuilder &Builder) const { 881 // Target identification. 882 if (getTriple().getArch() == llvm::Triple::x86_64) { 883 Builder.defineMacro("__amd64__"); 884 Builder.defineMacro("__amd64"); 885 Builder.defineMacro("__x86_64"); 886 Builder.defineMacro("__x86_64__"); 887 if (getTriple().getArchName() == "x86_64h") { 888 Builder.defineMacro("__x86_64h"); 889 Builder.defineMacro("__x86_64h__"); 890 } 891 } else { 892 DefineStd(Builder, "i386", Opts); 893 } 894 895 // Subtarget options. 896 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 897 // truly should be based on -mtune options. 898 switch (CPU) { 899 case CK_Generic: 900 break; 901 case CK_i386: 902 // The rest are coming from the i386 define above. 903 Builder.defineMacro("__tune_i386__"); 904 break; 905 case CK_i486: 906 case CK_WinChipC6: 907 case CK_WinChip2: 908 case CK_C3: 909 defineCPUMacros(Builder, "i486"); 910 break; 911 case CK_PentiumMMX: 912 Builder.defineMacro("__pentium_mmx__"); 913 Builder.defineMacro("__tune_pentium_mmx__"); 914 LLVM_FALLTHROUGH; 915 case CK_i586: 916 case CK_Pentium: 917 defineCPUMacros(Builder, "i586"); 918 defineCPUMacros(Builder, "pentium"); 919 break; 920 case CK_Pentium3: 921 case CK_PentiumM: 922 Builder.defineMacro("__tune_pentium3__"); 923 LLVM_FALLTHROUGH; 924 case CK_Pentium2: 925 case CK_C3_2: 926 Builder.defineMacro("__tune_pentium2__"); 927 LLVM_FALLTHROUGH; 928 case CK_PentiumPro: 929 defineCPUMacros(Builder, "i686"); 930 defineCPUMacros(Builder, "pentiumpro"); 931 break; 932 case CK_Pentium4: 933 defineCPUMacros(Builder, "pentium4"); 934 break; 935 case CK_Yonah: 936 case CK_Prescott: 937 case CK_Nocona: 938 defineCPUMacros(Builder, "nocona"); 939 break; 940 case CK_Core2: 941 case CK_Penryn: 942 defineCPUMacros(Builder, "core2"); 943 break; 944 case CK_Bonnell: 945 defineCPUMacros(Builder, "atom"); 946 break; 947 case CK_Silvermont: 948 defineCPUMacros(Builder, "slm"); 949 break; 950 case CK_Goldmont: 951 defineCPUMacros(Builder, "goldmont"); 952 break; 953 case CK_GoldmontPlus: 954 defineCPUMacros(Builder, "goldmont_plus"); 955 break; 956 case CK_Tremont: 957 defineCPUMacros(Builder, "tremont"); 958 break; 959 case CK_Nehalem: 960 case CK_Westmere: 961 case CK_SandyBridge: 962 case CK_IvyBridge: 963 case CK_Haswell: 964 case CK_Broadwell: 965 case CK_SkylakeClient: 966 case CK_SkylakeServer: 967 case CK_Cannonlake: 968 case CK_IcelakeClient: 969 case CK_IcelakeServer: 970 // FIXME: Historically, we defined this legacy name, it would be nice to 971 // remove it at some point. We've never exposed fine-grained names for 972 // recent primary x86 CPUs, and we should keep it that way. 973 defineCPUMacros(Builder, "corei7"); 974 break; 975 case CK_KNL: 976 defineCPUMacros(Builder, "knl"); 977 break; 978 case CK_KNM: 979 break; 980 case CK_Lakemont: 981 defineCPUMacros(Builder, "i586", /*Tuning*/false); 982 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 983 Builder.defineMacro("__tune_lakemont__"); 984 break; 985 case CK_K6_2: 986 Builder.defineMacro("__k6_2__"); 987 Builder.defineMacro("__tune_k6_2__"); 988 LLVM_FALLTHROUGH; 989 case CK_K6_3: 990 if (CPU != CK_K6_2) { // In case of fallthrough 991 // FIXME: GCC may be enabling these in cases where some other k6 992 // architecture is specified but -m3dnow is explicitly provided. The 993 // exact semantics need to be determined and emulated here. 994 Builder.defineMacro("__k6_3__"); 995 Builder.defineMacro("__tune_k6_3__"); 996 } 997 LLVM_FALLTHROUGH; 998 case CK_K6: 999 defineCPUMacros(Builder, "k6"); 1000 break; 1001 case CK_Athlon: 1002 case CK_AthlonXP: 1003 defineCPUMacros(Builder, "athlon"); 1004 if (SSELevel != NoSSE) { 1005 Builder.defineMacro("__athlon_sse__"); 1006 Builder.defineMacro("__tune_athlon_sse__"); 1007 } 1008 break; 1009 case CK_K8: 1010 case CK_K8SSE3: 1011 case CK_x86_64: 1012 defineCPUMacros(Builder, "k8"); 1013 break; 1014 case CK_AMDFAM10: 1015 defineCPUMacros(Builder, "amdfam10"); 1016 break; 1017 case CK_BTVER1: 1018 defineCPUMacros(Builder, "btver1"); 1019 break; 1020 case CK_BTVER2: 1021 defineCPUMacros(Builder, "btver2"); 1022 break; 1023 case CK_BDVER1: 1024 defineCPUMacros(Builder, "bdver1"); 1025 break; 1026 case CK_BDVER2: 1027 defineCPUMacros(Builder, "bdver2"); 1028 break; 1029 case CK_BDVER3: 1030 defineCPUMacros(Builder, "bdver3"); 1031 break; 1032 case CK_BDVER4: 1033 defineCPUMacros(Builder, "bdver4"); 1034 break; 1035 case CK_ZNVER1: 1036 defineCPUMacros(Builder, "znver1"); 1037 break; 1038 case CK_Geode: 1039 defineCPUMacros(Builder, "geode"); 1040 break; 1041 } 1042 1043 // Target properties. 1044 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1045 1046 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1047 // functions in glibc header files that use FP Stack inline asm which the 1048 // backend can't deal with (PR879). 1049 Builder.defineMacro("__NO_MATH_INLINES"); 1050 1051 if (HasAES) 1052 Builder.defineMacro("__AES__"); 1053 1054 if (HasVAES) 1055 Builder.defineMacro("__VAES__"); 1056 1057 if (HasPCLMUL) 1058 Builder.defineMacro("__PCLMUL__"); 1059 1060 if (HasVPCLMULQDQ) 1061 Builder.defineMacro("__VPCLMULQDQ__"); 1062 1063 if (HasLZCNT) 1064 Builder.defineMacro("__LZCNT__"); 1065 1066 if (HasRDRND) 1067 Builder.defineMacro("__RDRND__"); 1068 1069 if (HasFSGSBASE) 1070 Builder.defineMacro("__FSGSBASE__"); 1071 1072 if (HasBMI) 1073 Builder.defineMacro("__BMI__"); 1074 1075 if (HasBMI2) 1076 Builder.defineMacro("__BMI2__"); 1077 1078 if (HasPOPCNT) 1079 Builder.defineMacro("__POPCNT__"); 1080 1081 if (HasRTM) 1082 Builder.defineMacro("__RTM__"); 1083 1084 if (HasPRFCHW) 1085 Builder.defineMacro("__PRFCHW__"); 1086 1087 if (HasRDSEED) 1088 Builder.defineMacro("__RDSEED__"); 1089 1090 if (HasADX) 1091 Builder.defineMacro("__ADX__"); 1092 1093 if (HasTBM) 1094 Builder.defineMacro("__TBM__"); 1095 1096 if (HasLWP) 1097 Builder.defineMacro("__LWP__"); 1098 1099 if (HasMWAITX) 1100 Builder.defineMacro("__MWAITX__"); 1101 1102 switch (XOPLevel) { 1103 case XOP: 1104 Builder.defineMacro("__XOP__"); 1105 LLVM_FALLTHROUGH; 1106 case FMA4: 1107 Builder.defineMacro("__FMA4__"); 1108 LLVM_FALLTHROUGH; 1109 case SSE4A: 1110 Builder.defineMacro("__SSE4A__"); 1111 LLVM_FALLTHROUGH; 1112 case NoXOP: 1113 break; 1114 } 1115 1116 if (HasFMA) 1117 Builder.defineMacro("__FMA__"); 1118 1119 if (HasF16C) 1120 Builder.defineMacro("__F16C__"); 1121 1122 if (HasGFNI) 1123 Builder.defineMacro("__GFNI__"); 1124 1125 if (HasAVX512CD) 1126 Builder.defineMacro("__AVX512CD__"); 1127 if (HasAVX512VPOPCNTDQ) 1128 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1129 if (HasAVX512VNNI) 1130 Builder.defineMacro("__AVX512VNNI__"); 1131 if (HasAVX512ER) 1132 Builder.defineMacro("__AVX512ER__"); 1133 if (HasAVX512PF) 1134 Builder.defineMacro("__AVX512PF__"); 1135 if (HasAVX512DQ) 1136 Builder.defineMacro("__AVX512DQ__"); 1137 if (HasAVX512BITALG) 1138 Builder.defineMacro("__AVX512BITALG__"); 1139 if (HasAVX512BW) 1140 Builder.defineMacro("__AVX512BW__"); 1141 if (HasAVX512VL) 1142 Builder.defineMacro("__AVX512VL__"); 1143 if (HasAVX512VBMI) 1144 Builder.defineMacro("__AVX512VBMI__"); 1145 if (HasAVX512VBMI2) 1146 Builder.defineMacro("__AVX512VBMI2__"); 1147 if (HasAVX512IFMA) 1148 Builder.defineMacro("__AVX512IFMA__"); 1149 1150 if (HasSHA) 1151 Builder.defineMacro("__SHA__"); 1152 1153 if (HasFXSR) 1154 Builder.defineMacro("__FXSR__"); 1155 if (HasXSAVE) 1156 Builder.defineMacro("__XSAVE__"); 1157 if (HasXSAVEOPT) 1158 Builder.defineMacro("__XSAVEOPT__"); 1159 if (HasXSAVEC) 1160 Builder.defineMacro("__XSAVEC__"); 1161 if (HasXSAVES) 1162 Builder.defineMacro("__XSAVES__"); 1163 if (HasPKU) 1164 Builder.defineMacro("__PKU__"); 1165 if (HasCLFLUSHOPT) 1166 Builder.defineMacro("__CLFLUSHOPT__"); 1167 if (HasCLWB) 1168 Builder.defineMacro("__CLWB__"); 1169 if (HasWBNOINVD) 1170 Builder.defineMacro("__WBNOINVD__"); 1171 if (HasMPX) 1172 Builder.defineMacro("__MPX__"); 1173 if (HasSHSTK) 1174 Builder.defineMacro("__SHSTK__"); 1175 if (HasIBT) 1176 Builder.defineMacro("__IBT__"); 1177 if (HasSGX) 1178 Builder.defineMacro("__SGX__"); 1179 if (HasPREFETCHWT1) 1180 Builder.defineMacro("__PREFETCHWT1__"); 1181 if (HasCLZERO) 1182 Builder.defineMacro("__CLZERO__"); 1183 if (HasRDPID) 1184 Builder.defineMacro("__RDPID__"); 1185 if (HasCLDEMOTE) 1186 Builder.defineMacro("__CLDEMOTE__"); 1187 if (HasWAITPKG) 1188 Builder.defineMacro("__WAITPKG__"); 1189 if (HasMOVDIRI) 1190 Builder.defineMacro("__MOVDIRI__"); 1191 if (HasMOVDIR64B) 1192 Builder.defineMacro("__MOVDIR64B__"); 1193 if (HasPCONFIG) 1194 Builder.defineMacro("__PCONFIG__"); 1195 1196 // Each case falls through to the previous one here. 1197 switch (SSELevel) { 1198 case AVX512F: 1199 Builder.defineMacro("__AVX512F__"); 1200 LLVM_FALLTHROUGH; 1201 case AVX2: 1202 Builder.defineMacro("__AVX2__"); 1203 LLVM_FALLTHROUGH; 1204 case AVX: 1205 Builder.defineMacro("__AVX__"); 1206 LLVM_FALLTHROUGH; 1207 case SSE42: 1208 Builder.defineMacro("__SSE4_2__"); 1209 LLVM_FALLTHROUGH; 1210 case SSE41: 1211 Builder.defineMacro("__SSE4_1__"); 1212 LLVM_FALLTHROUGH; 1213 case SSSE3: 1214 Builder.defineMacro("__SSSE3__"); 1215 LLVM_FALLTHROUGH; 1216 case SSE3: 1217 Builder.defineMacro("__SSE3__"); 1218 LLVM_FALLTHROUGH; 1219 case SSE2: 1220 Builder.defineMacro("__SSE2__"); 1221 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1222 LLVM_FALLTHROUGH; 1223 case SSE1: 1224 Builder.defineMacro("__SSE__"); 1225 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1226 LLVM_FALLTHROUGH; 1227 case NoSSE: 1228 break; 1229 } 1230 1231 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1232 switch (SSELevel) { 1233 case AVX512F: 1234 case AVX2: 1235 case AVX: 1236 case SSE42: 1237 case SSE41: 1238 case SSSE3: 1239 case SSE3: 1240 case SSE2: 1241 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1242 break; 1243 case SSE1: 1244 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1245 break; 1246 default: 1247 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1248 break; 1249 } 1250 } 1251 1252 // Each case falls through to the previous one here. 1253 switch (MMX3DNowLevel) { 1254 case AMD3DNowAthlon: 1255 Builder.defineMacro("__3dNOW_A__"); 1256 LLVM_FALLTHROUGH; 1257 case AMD3DNow: 1258 Builder.defineMacro("__3dNOW__"); 1259 LLVM_FALLTHROUGH; 1260 case MMX: 1261 Builder.defineMacro("__MMX__"); 1262 LLVM_FALLTHROUGH; 1263 case NoMMX3DNow: 1264 break; 1265 } 1266 1267 if (CPU >= CK_i486) { 1268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1270 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1271 } 1272 if (CPU >= CK_i586) 1273 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1274 if (HasCX16) 1275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1276 1277 if (HasFloat128) 1278 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1279 } 1280 1281 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1282 return llvm::StringSwitch<bool>(Name) 1283 .Case("3dnow", true) 1284 .Case("3dnowa", true) 1285 .Case("adx", true) 1286 .Case("aes", true) 1287 .Case("avx", true) 1288 .Case("avx2", true) 1289 .Case("avx512f", true) 1290 .Case("avx512cd", true) 1291 .Case("avx512vpopcntdq", true) 1292 .Case("avx512vnni", true) 1293 .Case("avx512er", true) 1294 .Case("avx512pf", true) 1295 .Case("avx512dq", true) 1296 .Case("avx512bitalg", true) 1297 .Case("avx512bw", true) 1298 .Case("avx512vl", true) 1299 .Case("avx512vbmi", true) 1300 .Case("avx512vbmi2", true) 1301 .Case("avx512ifma", true) 1302 .Case("bmi", true) 1303 .Case("bmi2", true) 1304 .Case("cldemote", true) 1305 .Case("clflushopt", true) 1306 .Case("clwb", true) 1307 .Case("clzero", true) 1308 .Case("cx16", true) 1309 .Case("f16c", true) 1310 .Case("fma", true) 1311 .Case("fma4", true) 1312 .Case("fsgsbase", true) 1313 .Case("fxsr", true) 1314 .Case("gfni", true) 1315 .Case("lwp", true) 1316 .Case("lzcnt", true) 1317 .Case("mmx", true) 1318 .Case("movbe", true) 1319 .Case("movdiri", true) 1320 .Case("movdir64b", true) 1321 .Case("mpx", true) 1322 .Case("mwaitx", true) 1323 .Case("pclmul", true) 1324 .Case("pconfig", true) 1325 .Case("pku", true) 1326 .Case("popcnt", true) 1327 .Case("prefetchwt1", true) 1328 .Case("prfchw", true) 1329 .Case("rdpid", true) 1330 .Case("rdrnd", true) 1331 .Case("rdseed", true) 1332 .Case("rtm", true) 1333 .Case("sahf", true) 1334 .Case("sgx", true) 1335 .Case("sha", true) 1336 .Case("shstk", true) 1337 .Case("sse", true) 1338 .Case("sse2", true) 1339 .Case("sse3", true) 1340 .Case("ssse3", true) 1341 .Case("sse4", true) 1342 .Case("sse4.1", true) 1343 .Case("sse4.2", true) 1344 .Case("sse4a", true) 1345 .Case("tbm", true) 1346 .Case("vaes", true) 1347 .Case("vpclmulqdq", true) 1348 .Case("wbnoinvd", true) 1349 .Case("waitpkg", true) 1350 .Case("x87", true) 1351 .Case("xop", true) 1352 .Case("xsave", true) 1353 .Case("xsavec", true) 1354 .Case("xsaves", true) 1355 .Case("xsaveopt", true) 1356 .Default(false); 1357 } 1358 1359 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1360 return llvm::StringSwitch<bool>(Feature) 1361 .Case("adx", HasADX) 1362 .Case("aes", HasAES) 1363 .Case("avx", SSELevel >= AVX) 1364 .Case("avx2", SSELevel >= AVX2) 1365 .Case("avx512f", SSELevel >= AVX512F) 1366 .Case("avx512cd", HasAVX512CD) 1367 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1368 .Case("avx512vnni", HasAVX512VNNI) 1369 .Case("avx512er", HasAVX512ER) 1370 .Case("avx512pf", HasAVX512PF) 1371 .Case("avx512dq", HasAVX512DQ) 1372 .Case("avx512bitalg", HasAVX512BITALG) 1373 .Case("avx512bw", HasAVX512BW) 1374 .Case("avx512vl", HasAVX512VL) 1375 .Case("avx512vbmi", HasAVX512VBMI) 1376 .Case("avx512vbmi2", HasAVX512VBMI2) 1377 .Case("avx512ifma", HasAVX512IFMA) 1378 .Case("bmi", HasBMI) 1379 .Case("bmi2", HasBMI2) 1380 .Case("cldemote", HasCLDEMOTE) 1381 .Case("clflushopt", HasCLFLUSHOPT) 1382 .Case("clwb", HasCLWB) 1383 .Case("clzero", HasCLZERO) 1384 .Case("cx16", HasCX16) 1385 .Case("f16c", HasF16C) 1386 .Case("fma", HasFMA) 1387 .Case("fma4", XOPLevel >= FMA4) 1388 .Case("fsgsbase", HasFSGSBASE) 1389 .Case("fxsr", HasFXSR) 1390 .Case("gfni", HasGFNI) 1391 .Case("ibt", HasIBT) 1392 .Case("lwp", HasLWP) 1393 .Case("lzcnt", HasLZCNT) 1394 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1395 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1396 .Case("mmx", MMX3DNowLevel >= MMX) 1397 .Case("movbe", HasMOVBE) 1398 .Case("movdiri", HasMOVDIRI) 1399 .Case("movdir64b", HasMOVDIR64B) 1400 .Case("mpx", HasMPX) 1401 .Case("mwaitx", HasMWAITX) 1402 .Case("pclmul", HasPCLMUL) 1403 .Case("pconfig", HasPCONFIG) 1404 .Case("pku", HasPKU) 1405 .Case("popcnt", HasPOPCNT) 1406 .Case("prefetchwt1", HasPREFETCHWT1) 1407 .Case("prfchw", HasPRFCHW) 1408 .Case("rdpid", HasRDPID) 1409 .Case("rdrnd", HasRDRND) 1410 .Case("rdseed", HasRDSEED) 1411 .Case("retpoline", HasRetpoline) 1412 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1413 .Case("rtm", HasRTM) 1414 .Case("sahf", HasLAHFSAHF) 1415 .Case("sgx", HasSGX) 1416 .Case("sha", HasSHA) 1417 .Case("shstk", HasSHSTK) 1418 .Case("sse", SSELevel >= SSE1) 1419 .Case("sse2", SSELevel >= SSE2) 1420 .Case("sse3", SSELevel >= SSE3) 1421 .Case("ssse3", SSELevel >= SSSE3) 1422 .Case("sse4.1", SSELevel >= SSE41) 1423 .Case("sse4.2", SSELevel >= SSE42) 1424 .Case("sse4a", XOPLevel >= SSE4A) 1425 .Case("tbm", HasTBM) 1426 .Case("vaes", HasVAES) 1427 .Case("vpclmulqdq", HasVPCLMULQDQ) 1428 .Case("wbnoinvd", HasWBNOINVD) 1429 .Case("waitpkg", HasWAITPKG) 1430 .Case("x86", true) 1431 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1432 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1433 .Case("xop", XOPLevel >= XOP) 1434 .Case("xsave", HasXSAVE) 1435 .Case("xsavec", HasXSAVEC) 1436 .Case("xsaves", HasXSAVES) 1437 .Case("xsaveopt", HasXSAVEOPT) 1438 .Default(false); 1439 } 1440 1441 // We can't use a generic validation scheme for the features accepted here 1442 // versus subtarget features accepted in the target attribute because the 1443 // bitfield structure that's initialized in the runtime only supports the 1444 // below currently rather than the full range of subtarget features. (See 1445 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1446 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1447 return llvm::StringSwitch<bool>(FeatureStr) 1448 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1449 #include "llvm/Support/X86TargetParser.def" 1450 .Default(false); 1451 } 1452 1453 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1454 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1455 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1456 #include "llvm/Support/X86TargetParser.def" 1457 ; 1458 // Note, this function should only be used after ensuring the value is 1459 // correct, so it asserts if the value is out of range. 1460 } 1461 1462 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1463 enum class FeatPriority { 1464 #define FEATURE(FEAT) FEAT, 1465 #include "clang/Basic/X86Target.def" 1466 }; 1467 switch (Feat) { 1468 #define FEATURE(FEAT) \ 1469 case llvm::X86::FEAT: \ 1470 return static_cast<unsigned>(FeatPriority::FEAT); 1471 #include "clang/Basic/X86Target.def" 1472 default: 1473 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1474 } 1475 } 1476 1477 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1478 // Valid CPUs have a 'key feature' that compares just better than its key 1479 // feature. 1480 CPUKind Kind = getCPUKind(Name); 1481 if (Kind != CK_Generic) { 1482 switch (Kind) { 1483 default: 1484 llvm_unreachable( 1485 "CPU Type without a key feature used in 'target' attribute"); 1486 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1487 case CK_##ENUM: \ 1488 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1489 #include "clang/Basic/X86Target.def" 1490 } 1491 } 1492 1493 // Now we know we have a feature, so get its priority and shift it a few so 1494 // that we have sufficient room for the CPUs (above). 1495 return getFeaturePriority(getFeature(Name)) << 1; 1496 } 1497 1498 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1499 switch (Kind) { 1500 case CK_Generic: 1501 return ""; 1502 #define PROC(ENUM, STRING, IS64BIT) \ 1503 case CK_##ENUM: \ 1504 return STRING; 1505 #include "clang/Basic/X86Target.def" 1506 } 1507 llvm_unreachable("Invalid CPUKind"); 1508 } 1509 1510 // We can't use a generic validation scheme for the cpus accepted here 1511 // versus subtarget cpus accepted in the target attribute because the 1512 // variables intitialized by the runtime only support the below currently 1513 // rather than the full range of cpus. 1514 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1515 return llvm::StringSwitch<bool>(FeatureStr) 1516 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1517 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1518 .Cases(STR, ALIAS, true) 1519 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1520 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1521 #include "llvm/Support/X86TargetParser.def" 1522 .Default(false); 1523 } 1524 1525 bool X86TargetInfo::validateAsmConstraint( 1526 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1527 switch (*Name) { 1528 default: 1529 return false; 1530 // Constant constraints. 1531 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1532 // instructions. 1533 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1534 // x86_64 instructions. 1535 case 's': 1536 Info.setRequiresImmediate(); 1537 return true; 1538 case 'I': 1539 Info.setRequiresImmediate(0, 31); 1540 return true; 1541 case 'J': 1542 Info.setRequiresImmediate(0, 63); 1543 return true; 1544 case 'K': 1545 Info.setRequiresImmediate(-128, 127); 1546 return true; 1547 case 'L': 1548 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1549 return true; 1550 case 'M': 1551 Info.setRequiresImmediate(0, 3); 1552 return true; 1553 case 'N': 1554 Info.setRequiresImmediate(0, 255); 1555 return true; 1556 case 'O': 1557 Info.setRequiresImmediate(0, 127); 1558 return true; 1559 // Register constraints. 1560 case 'Y': // 'Y' is the first character for several 2-character constraints. 1561 // Shift the pointer to the second character of the constraint. 1562 Name++; 1563 switch (*Name) { 1564 default: 1565 return false; 1566 case 'z': 1567 case '0': // First SSE register. 1568 case '2': 1569 case 't': // Any SSE register, when SSE2 is enabled. 1570 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1571 case 'm': // Any MMX register, when inter-unit moves enabled. 1572 case 'k': // AVX512 arch mask registers: k1-k7. 1573 Info.setAllowsRegister(); 1574 return true; 1575 } 1576 case 'f': // Any x87 floating point stack register. 1577 // Constraint 'f' cannot be used for output operands. 1578 if (Info.ConstraintStr[0] == '=') 1579 return false; 1580 Info.setAllowsRegister(); 1581 return true; 1582 case 'a': // eax. 1583 case 'b': // ebx. 1584 case 'c': // ecx. 1585 case 'd': // edx. 1586 case 'S': // esi. 1587 case 'D': // edi. 1588 case 'A': // edx:eax. 1589 case 't': // Top of floating point stack. 1590 case 'u': // Second from top of floating point stack. 1591 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1592 case 'y': // Any MMX register. 1593 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1594 case 'x': // Any SSE register. 1595 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1596 // for intermideate k reg operations). 1597 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1598 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1599 case 'l': // "Index" registers: any general register that can be used as an 1600 // index in a base+index memory access. 1601 Info.setAllowsRegister(); 1602 return true; 1603 // Floating point constant constraints. 1604 case 'C': // SSE floating point constant. 1605 case 'G': // x87 floating point constant. 1606 return true; 1607 } 1608 } 1609 1610 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1611 unsigned Size) const { 1612 // Strip off constraint modifiers. 1613 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1614 Constraint = Constraint.substr(1); 1615 1616 return validateOperandSize(Constraint, Size); 1617 } 1618 1619 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1620 unsigned Size) const { 1621 return validateOperandSize(Constraint, Size); 1622 } 1623 1624 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1625 unsigned Size) const { 1626 switch (Constraint[0]) { 1627 default: 1628 break; 1629 case 'k': 1630 // Registers k0-k7 (AVX512) size limit is 64 bit. 1631 case 'y': 1632 return Size <= 64; 1633 case 'f': 1634 case 't': 1635 case 'u': 1636 return Size <= 128; 1637 case 'Y': 1638 // 'Y' is the first character for several 2-character constraints. 1639 switch (Constraint[1]) { 1640 default: 1641 return false; 1642 case 'm': 1643 // 'Ym' is synonymous with 'y'. 1644 case 'k': 1645 return Size <= 64; 1646 case 'z': 1647 case '0': 1648 // XMM0 1649 if (SSELevel >= SSE1) 1650 return Size <= 128U; 1651 return false; 1652 case 'i': 1653 case 't': 1654 case '2': 1655 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1656 if (SSELevel < SSE2) 1657 return false; 1658 break; 1659 } 1660 case 'v': 1661 case 'x': 1662 if (SSELevel >= AVX512F) 1663 // 512-bit zmm registers can be used if target supports AVX512F. 1664 return Size <= 512U; 1665 else if (SSELevel >= AVX) 1666 // 256-bit ymm registers can be used if target supports AVX. 1667 return Size <= 256U; 1668 return Size <= 128U; 1669 1670 } 1671 1672 return true; 1673 } 1674 1675 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1676 switch (*Constraint) { 1677 case 'a': 1678 return std::string("{ax}"); 1679 case 'b': 1680 return std::string("{bx}"); 1681 case 'c': 1682 return std::string("{cx}"); 1683 case 'd': 1684 return std::string("{dx}"); 1685 case 'S': 1686 return std::string("{si}"); 1687 case 'D': 1688 return std::string("{di}"); 1689 case 'p': // address 1690 return std::string("im"); 1691 case 't': // top of floating point stack. 1692 return std::string("{st}"); 1693 case 'u': // second from top of floating point stack. 1694 return std::string("{st(1)}"); // second from top of floating point stack. 1695 case 'Y': 1696 switch (Constraint[1]) { 1697 default: 1698 // Break from inner switch and fall through (copy single char), 1699 // continue parsing after copying the current constraint into 1700 // the return string. 1701 break; 1702 case 'k': 1703 case 'm': 1704 case 'i': 1705 case 't': 1706 case 'z': 1707 case '0': 1708 case '2': 1709 // "^" hints llvm that this is a 2 letter constraint. 1710 // "Constraint++" is used to promote the string iterator 1711 // to the next constraint. 1712 return std::string("^") + std::string(Constraint++, 2); 1713 } 1714 LLVM_FALLTHROUGH; 1715 default: 1716 return std::string(1, *Constraint); 1717 } 1718 } 1719 1720 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1721 // Perform any per-CPU checks necessary to determine if this CPU is 1722 // acceptable. 1723 switch (Kind) { 1724 case CK_Generic: 1725 // No processor selected! 1726 return false; 1727 #define PROC(ENUM, STRING, IS64BIT) \ 1728 case CK_##ENUM: \ 1729 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1730 #include "clang/Basic/X86Target.def" 1731 } 1732 llvm_unreachable("Unhandled CPU kind"); 1733 } 1734 1735 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1736 #define PROC(ENUM, STRING, IS64BIT) \ 1737 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1738 Values.emplace_back(STRING); 1739 // Go through CPUKind checking to ensure that the alias is de-aliased and 1740 // 64 bit-ness is checked. 1741 #define PROC_ALIAS(ENUM, ALIAS) \ 1742 if (checkCPUKind(getCPUKind(ALIAS))) \ 1743 Values.emplace_back(ALIAS); 1744 #include "clang/Basic/X86Target.def" 1745 } 1746 1747 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1748 return llvm::StringSwitch<CPUKind>(CPU) 1749 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1750 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1751 #include "clang/Basic/X86Target.def" 1752 .Default(CK_Generic); 1753 } 1754 1755 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1756 return llvm::makeArrayRef(GCCRegNames); 1757 } 1758 1759 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1760 return llvm::makeArrayRef(AddlRegNames); 1761 } 1762 1763 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1764 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1765 Builtin::FirstTSBuiltin + 1); 1766 } 1767 1768 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1769 return llvm::makeArrayRef(BuiltinInfoX86, 1770 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1771 } 1772