1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 using namespace llvm::X86; 113 const enum CPUKind Kind = parseArchX86(CPU); 114 115 // Enable X87 for all X86 processors but Lakemont. 116 if (Kind != CK_Lakemont) 117 setFeatureEnabledImpl(Features, "x87", true); 118 119 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 120 // compatibility. 121 if (Kind >= CK_i586 || Kind == CK_None) 122 setFeatureEnabledImpl(Features, "cx8", true); 123 124 switch (Kind) { 125 case CK_None: 126 case CK_i386: 127 case CK_i486: 128 case CK_i586: 129 case CK_Pentium: 130 case CK_PentiumPro: 131 case CK_i686: 132 case CK_Lakemont: 133 break; 134 135 case CK_Cooperlake: 136 // CPX inherits all CLX features plus AVX512BF16 137 setFeatureEnabledImpl(Features, "avx512bf16", true); 138 LLVM_FALLTHROUGH; 139 case CK_Cascadelake: 140 // CLX inherits all SKX features plus AVX512VNNI 141 setFeatureEnabledImpl(Features, "avx512vnni", true); 142 LLVM_FALLTHROUGH; 143 case CK_SkylakeServer: 144 setFeatureEnabledImpl(Features, "avx512f", true); 145 setFeatureEnabledImpl(Features, "avx512cd", true); 146 setFeatureEnabledImpl(Features, "avx512dq", true); 147 setFeatureEnabledImpl(Features, "avx512bw", true); 148 setFeatureEnabledImpl(Features, "avx512vl", true); 149 setFeatureEnabledImpl(Features, "clwb", true); 150 setFeatureEnabledImpl(Features, "pku", true); 151 // SkylakeServer cores inherits all SKL features, except SGX 152 goto SkylakeCommon; 153 154 case CK_Tigerlake: 155 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 156 setFeatureEnabledImpl(Features, "movdiri", true); 157 setFeatureEnabledImpl(Features, "movdir64b", true); 158 setFeatureEnabledImpl(Features, "shstk", true); 159 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 160 goto IcelakeCommon; 161 162 case CK_IcelakeServer: 163 setFeatureEnabledImpl(Features, "pconfig", true); 164 setFeatureEnabledImpl(Features, "wbnoinvd", true); 165 LLVM_FALLTHROUGH; 166 case CK_IcelakeClient: 167 IcelakeCommon: 168 setFeatureEnabledImpl(Features, "vaes", true); 169 setFeatureEnabledImpl(Features, "gfni", true); 170 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 171 setFeatureEnabledImpl(Features, "avx512bitalg", true); 172 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 173 setFeatureEnabledImpl(Features, "avx512vnni", true); 174 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 175 setFeatureEnabledImpl(Features, "rdpid", true); 176 setFeatureEnabledImpl(Features, "clwb", true); 177 LLVM_FALLTHROUGH; 178 case CK_Cannonlake: 179 setFeatureEnabledImpl(Features, "avx512f", true); 180 setFeatureEnabledImpl(Features, "avx512cd", true); 181 setFeatureEnabledImpl(Features, "avx512dq", true); 182 setFeatureEnabledImpl(Features, "avx512bw", true); 183 setFeatureEnabledImpl(Features, "avx512vl", true); 184 setFeatureEnabledImpl(Features, "avx512ifma", true); 185 setFeatureEnabledImpl(Features, "avx512vbmi", true); 186 setFeatureEnabledImpl(Features, "pku", true); 187 setFeatureEnabledImpl(Features, "sha", true); 188 LLVM_FALLTHROUGH; 189 case CK_SkylakeClient: 190 setFeatureEnabledImpl(Features, "sgx", true); 191 // SkylakeServer cores inherits all SKL features, except SGX 192 SkylakeCommon: 193 setFeatureEnabledImpl(Features, "xsavec", true); 194 setFeatureEnabledImpl(Features, "xsaves", true); 195 setFeatureEnabledImpl(Features, "clflushopt", true); 196 setFeatureEnabledImpl(Features, "aes", true); 197 LLVM_FALLTHROUGH; 198 case CK_Broadwell: 199 setFeatureEnabledImpl(Features, "rdseed", true); 200 setFeatureEnabledImpl(Features, "adx", true); 201 setFeatureEnabledImpl(Features, "prfchw", true); 202 LLVM_FALLTHROUGH; 203 case CK_Haswell: 204 setFeatureEnabledImpl(Features, "avx2", true); 205 setFeatureEnabledImpl(Features, "lzcnt", true); 206 setFeatureEnabledImpl(Features, "bmi", true); 207 setFeatureEnabledImpl(Features, "bmi2", true); 208 setFeatureEnabledImpl(Features, "fma", true); 209 setFeatureEnabledImpl(Features, "invpcid", true); 210 setFeatureEnabledImpl(Features, "movbe", true); 211 LLVM_FALLTHROUGH; 212 case CK_IvyBridge: 213 setFeatureEnabledImpl(Features, "rdrnd", true); 214 setFeatureEnabledImpl(Features, "f16c", true); 215 setFeatureEnabledImpl(Features, "fsgsbase", true); 216 LLVM_FALLTHROUGH; 217 case CK_SandyBridge: 218 setFeatureEnabledImpl(Features, "avx", true); 219 setFeatureEnabledImpl(Features, "xsave", true); 220 setFeatureEnabledImpl(Features, "xsaveopt", true); 221 LLVM_FALLTHROUGH; 222 case CK_Westmere: 223 setFeatureEnabledImpl(Features, "pclmul", true); 224 LLVM_FALLTHROUGH; 225 case CK_Nehalem: 226 setFeatureEnabledImpl(Features, "sse4.2", true); 227 LLVM_FALLTHROUGH; 228 case CK_Penryn: 229 setFeatureEnabledImpl(Features, "sse4.1", true); 230 LLVM_FALLTHROUGH; 231 case CK_Core2: 232 setFeatureEnabledImpl(Features, "ssse3", true); 233 setFeatureEnabledImpl(Features, "sahf", true); 234 LLVM_FALLTHROUGH; 235 case CK_Nocona: 236 setFeatureEnabledImpl(Features, "cx16", true); 237 LLVM_FALLTHROUGH; 238 case CK_Yonah: 239 case CK_Prescott: 240 setFeatureEnabledImpl(Features, "sse3", true); 241 LLVM_FALLTHROUGH; 242 case CK_PentiumM: 243 case CK_Pentium4: 244 case CK_x86_64: 245 setFeatureEnabledImpl(Features, "sse2", true); 246 LLVM_FALLTHROUGH; 247 case CK_Pentium3: 248 case CK_C3_2: 249 setFeatureEnabledImpl(Features, "sse", true); 250 LLVM_FALLTHROUGH; 251 case CK_Pentium2: 252 setFeatureEnabledImpl(Features, "fxsr", true); 253 LLVM_FALLTHROUGH; 254 case CK_PentiumMMX: 255 case CK_K6: 256 case CK_WinChipC6: 257 setFeatureEnabledImpl(Features, "mmx", true); 258 break; 259 260 case CK_Tremont: 261 setFeatureEnabledImpl(Features, "clwb", true); 262 setFeatureEnabledImpl(Features, "gfni", true); 263 LLVM_FALLTHROUGH; 264 case CK_GoldmontPlus: 265 setFeatureEnabledImpl(Features, "ptwrite", true); 266 setFeatureEnabledImpl(Features, "rdpid", true); 267 setFeatureEnabledImpl(Features, "sgx", true); 268 LLVM_FALLTHROUGH; 269 case CK_Goldmont: 270 setFeatureEnabledImpl(Features, "sha", true); 271 setFeatureEnabledImpl(Features, "rdseed", true); 272 setFeatureEnabledImpl(Features, "xsave", true); 273 setFeatureEnabledImpl(Features, "xsaveopt", true); 274 setFeatureEnabledImpl(Features, "xsavec", true); 275 setFeatureEnabledImpl(Features, "xsaves", true); 276 setFeatureEnabledImpl(Features, "clflushopt", true); 277 setFeatureEnabledImpl(Features, "fsgsbase", true); 278 setFeatureEnabledImpl(Features, "aes", true); 279 LLVM_FALLTHROUGH; 280 case CK_Silvermont: 281 setFeatureEnabledImpl(Features, "rdrnd", true); 282 setFeatureEnabledImpl(Features, "pclmul", true); 283 setFeatureEnabledImpl(Features, "sse4.2", true); 284 setFeatureEnabledImpl(Features, "prfchw", true); 285 LLVM_FALLTHROUGH; 286 case CK_Bonnell: 287 setFeatureEnabledImpl(Features, "movbe", true); 288 setFeatureEnabledImpl(Features, "ssse3", true); 289 setFeatureEnabledImpl(Features, "fxsr", true); 290 setFeatureEnabledImpl(Features, "cx16", true); 291 setFeatureEnabledImpl(Features, "sahf", true); 292 setFeatureEnabledImpl(Features, "mmx", true); 293 break; 294 295 case CK_KNM: 296 // TODO: Add avx5124fmaps/avx5124vnniw. 297 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 298 LLVM_FALLTHROUGH; 299 case CK_KNL: 300 setFeatureEnabledImpl(Features, "avx512f", true); 301 setFeatureEnabledImpl(Features, "avx512cd", true); 302 setFeatureEnabledImpl(Features, "avx512er", true); 303 setFeatureEnabledImpl(Features, "avx512pf", true); 304 setFeatureEnabledImpl(Features, "prfchw", true); 305 setFeatureEnabledImpl(Features, "prefetchwt1", true); 306 setFeatureEnabledImpl(Features, "fxsr", true); 307 setFeatureEnabledImpl(Features, "rdseed", true); 308 setFeatureEnabledImpl(Features, "adx", true); 309 setFeatureEnabledImpl(Features, "lzcnt", true); 310 setFeatureEnabledImpl(Features, "bmi", true); 311 setFeatureEnabledImpl(Features, "bmi2", true); 312 setFeatureEnabledImpl(Features, "fma", true); 313 setFeatureEnabledImpl(Features, "rdrnd", true); 314 setFeatureEnabledImpl(Features, "f16c", true); 315 setFeatureEnabledImpl(Features, "fsgsbase", true); 316 setFeatureEnabledImpl(Features, "aes", true); 317 setFeatureEnabledImpl(Features, "pclmul", true); 318 setFeatureEnabledImpl(Features, "cx16", true); 319 setFeatureEnabledImpl(Features, "xsaveopt", true); 320 setFeatureEnabledImpl(Features, "xsave", true); 321 setFeatureEnabledImpl(Features, "movbe", true); 322 setFeatureEnabledImpl(Features, "sahf", true); 323 setFeatureEnabledImpl(Features, "mmx", true); 324 break; 325 326 case CK_K6_2: 327 case CK_K6_3: 328 case CK_WinChip2: 329 case CK_C3: 330 setFeatureEnabledImpl(Features, "3dnow", true); 331 break; 332 333 case CK_AMDFAM10: 334 setFeatureEnabledImpl(Features, "sse4a", true); 335 setFeatureEnabledImpl(Features, "lzcnt", true); 336 setFeatureEnabledImpl(Features, "popcnt", true); 337 setFeatureEnabledImpl(Features, "sahf", true); 338 setFeatureEnabledImpl(Features, "prfchw", true); 339 setFeatureEnabledImpl(Features, "cx16", true); 340 LLVM_FALLTHROUGH; 341 case CK_K8SSE3: 342 setFeatureEnabledImpl(Features, "sse3", true); 343 LLVM_FALLTHROUGH; 344 case CK_K8: 345 setFeatureEnabledImpl(Features, "sse2", true); 346 LLVM_FALLTHROUGH; 347 case CK_AthlonXP: 348 setFeatureEnabledImpl(Features, "sse", true); 349 setFeatureEnabledImpl(Features, "fxsr", true); 350 LLVM_FALLTHROUGH; 351 case CK_Athlon: 352 case CK_Geode: 353 setFeatureEnabledImpl(Features, "3dnowa", true); 354 break; 355 356 case CK_BTVER2: 357 setFeatureEnabledImpl(Features, "avx", true); 358 setFeatureEnabledImpl(Features, "aes", true); 359 setFeatureEnabledImpl(Features, "pclmul", true); 360 setFeatureEnabledImpl(Features, "bmi", true); 361 setFeatureEnabledImpl(Features, "f16c", true); 362 setFeatureEnabledImpl(Features, "xsaveopt", true); 363 setFeatureEnabledImpl(Features, "movbe", true); 364 LLVM_FALLTHROUGH; 365 case CK_BTVER1: 366 setFeatureEnabledImpl(Features, "ssse3", true); 367 setFeatureEnabledImpl(Features, "sse4a", true); 368 setFeatureEnabledImpl(Features, "lzcnt", true); 369 setFeatureEnabledImpl(Features, "popcnt", true); 370 setFeatureEnabledImpl(Features, "prfchw", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "fxsr", true); 373 setFeatureEnabledImpl(Features, "sahf", true); 374 setFeatureEnabledImpl(Features, "mmx", true); 375 break; 376 377 case CK_ZNVER2: 378 setFeatureEnabledImpl(Features, "clwb", true); 379 setFeatureEnabledImpl(Features, "rdpid", true); 380 setFeatureEnabledImpl(Features, "wbnoinvd", true); 381 LLVM_FALLTHROUGH; 382 case CK_ZNVER1: 383 setFeatureEnabledImpl(Features, "adx", true); 384 setFeatureEnabledImpl(Features, "aes", true); 385 setFeatureEnabledImpl(Features, "avx2", true); 386 setFeatureEnabledImpl(Features, "bmi", true); 387 setFeatureEnabledImpl(Features, "bmi2", true); 388 setFeatureEnabledImpl(Features, "clflushopt", true); 389 setFeatureEnabledImpl(Features, "clzero", true); 390 setFeatureEnabledImpl(Features, "cx16", true); 391 setFeatureEnabledImpl(Features, "f16c", true); 392 setFeatureEnabledImpl(Features, "fma", true); 393 setFeatureEnabledImpl(Features, "fsgsbase", true); 394 setFeatureEnabledImpl(Features, "fxsr", true); 395 setFeatureEnabledImpl(Features, "lzcnt", true); 396 setFeatureEnabledImpl(Features, "mmx", true); 397 setFeatureEnabledImpl(Features, "mwaitx", true); 398 setFeatureEnabledImpl(Features, "movbe", true); 399 setFeatureEnabledImpl(Features, "pclmul", true); 400 setFeatureEnabledImpl(Features, "popcnt", true); 401 setFeatureEnabledImpl(Features, "prfchw", true); 402 setFeatureEnabledImpl(Features, "rdrnd", true); 403 setFeatureEnabledImpl(Features, "rdseed", true); 404 setFeatureEnabledImpl(Features, "sahf", true); 405 setFeatureEnabledImpl(Features, "sha", true); 406 setFeatureEnabledImpl(Features, "sse4a", true); 407 setFeatureEnabledImpl(Features, "xsave", true); 408 setFeatureEnabledImpl(Features, "xsavec", true); 409 setFeatureEnabledImpl(Features, "xsaveopt", true); 410 setFeatureEnabledImpl(Features, "xsaves", true); 411 break; 412 413 case CK_BDVER4: 414 setFeatureEnabledImpl(Features, "avx2", true); 415 setFeatureEnabledImpl(Features, "bmi2", true); 416 setFeatureEnabledImpl(Features, "mwaitx", true); 417 LLVM_FALLTHROUGH; 418 case CK_BDVER3: 419 setFeatureEnabledImpl(Features, "fsgsbase", true); 420 setFeatureEnabledImpl(Features, "xsaveopt", true); 421 LLVM_FALLTHROUGH; 422 case CK_BDVER2: 423 setFeatureEnabledImpl(Features, "bmi", true); 424 setFeatureEnabledImpl(Features, "fma", true); 425 setFeatureEnabledImpl(Features, "f16c", true); 426 setFeatureEnabledImpl(Features, "tbm", true); 427 LLVM_FALLTHROUGH; 428 case CK_BDVER1: 429 // xop implies avx, sse4a and fma4. 430 setFeatureEnabledImpl(Features, "xop", true); 431 setFeatureEnabledImpl(Features, "lwp", true); 432 setFeatureEnabledImpl(Features, "lzcnt", true); 433 setFeatureEnabledImpl(Features, "aes", true); 434 setFeatureEnabledImpl(Features, "pclmul", true); 435 setFeatureEnabledImpl(Features, "prfchw", true); 436 setFeatureEnabledImpl(Features, "cx16", true); 437 setFeatureEnabledImpl(Features, "fxsr", true); 438 setFeatureEnabledImpl(Features, "xsave", true); 439 setFeatureEnabledImpl(Features, "sahf", true); 440 setFeatureEnabledImpl(Features, "mmx", true); 441 break; 442 } 443 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 444 return false; 445 446 // Can't do this earlier because we need to be able to explicitly enable 447 // or disable these features and the things that they depend upon. 448 449 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 450 auto I = Features.find("sse4.2"); 451 if (I != Features.end() && I->getValue() && 452 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 453 Features["popcnt"] = true; 454 455 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 456 // then enable MMX. 457 I = Features.find("sse"); 458 if (I != Features.end() && I->getValue() && 459 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 460 Features["mmx"] = true; 461 462 return true; 463 } 464 465 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 466 X86SSEEnum Level, bool Enabled) { 467 if (Enabled) { 468 switch (Level) { 469 case AVX512F: 470 Features["avx512f"] = true; 471 Features["fma"] = true; 472 Features["f16c"] = true; 473 LLVM_FALLTHROUGH; 474 case AVX2: 475 Features["avx2"] = true; 476 LLVM_FALLTHROUGH; 477 case AVX: 478 Features["avx"] = true; 479 Features["xsave"] = true; 480 LLVM_FALLTHROUGH; 481 case SSE42: 482 Features["sse4.2"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE41: 485 Features["sse4.1"] = true; 486 LLVM_FALLTHROUGH; 487 case SSSE3: 488 Features["ssse3"] = true; 489 LLVM_FALLTHROUGH; 490 case SSE3: 491 Features["sse3"] = true; 492 LLVM_FALLTHROUGH; 493 case SSE2: 494 Features["sse2"] = true; 495 LLVM_FALLTHROUGH; 496 case SSE1: 497 Features["sse"] = true; 498 LLVM_FALLTHROUGH; 499 case NoSSE: 500 break; 501 } 502 return; 503 } 504 505 switch (Level) { 506 case NoSSE: 507 case SSE1: 508 Features["sse"] = false; 509 LLVM_FALLTHROUGH; 510 case SSE2: 511 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 512 Features["sha"] = Features["gfni"] = false; 513 LLVM_FALLTHROUGH; 514 case SSE3: 515 Features["sse3"] = false; 516 setXOPLevel(Features, NoXOP, false); 517 LLVM_FALLTHROUGH; 518 case SSSE3: 519 Features["ssse3"] = false; 520 LLVM_FALLTHROUGH; 521 case SSE41: 522 Features["sse4.1"] = false; 523 LLVM_FALLTHROUGH; 524 case SSE42: 525 Features["sse4.2"] = false; 526 LLVM_FALLTHROUGH; 527 case AVX: 528 Features["fma"] = Features["avx"] = Features["f16c"] = false; 529 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 530 Features["vpclmulqdq"] = false; 531 setXOPLevel(Features, FMA4, false); 532 LLVM_FALLTHROUGH; 533 case AVX2: 534 Features["avx2"] = false; 535 LLVM_FALLTHROUGH; 536 case AVX512F: 537 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 538 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 539 Features["avx512vl"] = Features["avx512vbmi"] = false; 540 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 541 Features["avx512bitalg"] = Features["avx512vnni"] = false; 542 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 543 Features["avx512vp2intersect"] = false; 544 break; 545 } 546 } 547 548 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 549 MMX3DNowEnum Level, bool Enabled) { 550 if (Enabled) { 551 switch (Level) { 552 case AMD3DNowAthlon: 553 Features["3dnowa"] = true; 554 LLVM_FALLTHROUGH; 555 case AMD3DNow: 556 Features["3dnow"] = true; 557 LLVM_FALLTHROUGH; 558 case MMX: 559 Features["mmx"] = true; 560 LLVM_FALLTHROUGH; 561 case NoMMX3DNow: 562 break; 563 } 564 return; 565 } 566 567 switch (Level) { 568 case NoMMX3DNow: 569 case MMX: 570 Features["mmx"] = false; 571 LLVM_FALLTHROUGH; 572 case AMD3DNow: 573 Features["3dnow"] = false; 574 LLVM_FALLTHROUGH; 575 case AMD3DNowAthlon: 576 Features["3dnowa"] = false; 577 break; 578 } 579 } 580 581 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 582 bool Enabled) { 583 if (Enabled) { 584 switch (Level) { 585 case XOP: 586 Features["xop"] = true; 587 LLVM_FALLTHROUGH; 588 case FMA4: 589 Features["fma4"] = true; 590 setSSELevel(Features, AVX, true); 591 LLVM_FALLTHROUGH; 592 case SSE4A: 593 Features["sse4a"] = true; 594 setSSELevel(Features, SSE3, true); 595 LLVM_FALLTHROUGH; 596 case NoXOP: 597 break; 598 } 599 return; 600 } 601 602 switch (Level) { 603 case NoXOP: 604 case SSE4A: 605 Features["sse4a"] = false; 606 LLVM_FALLTHROUGH; 607 case FMA4: 608 Features["fma4"] = false; 609 LLVM_FALLTHROUGH; 610 case XOP: 611 Features["xop"] = false; 612 break; 613 } 614 } 615 616 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 617 StringRef Name, bool Enabled) { 618 // This is a bit of a hack to deal with the sse4 target feature when used 619 // as part of the target attribute. We handle sse4 correctly everywhere 620 // else. See below for more information on how we handle the sse4 options. 621 if (Name != "sse4") 622 Features[Name] = Enabled; 623 624 if (Name == "mmx") { 625 setMMXLevel(Features, MMX, Enabled); 626 } else if (Name == "sse") { 627 setSSELevel(Features, SSE1, Enabled); 628 } else if (Name == "sse2") { 629 setSSELevel(Features, SSE2, Enabled); 630 } else if (Name == "sse3") { 631 setSSELevel(Features, SSE3, Enabled); 632 } else if (Name == "ssse3") { 633 setSSELevel(Features, SSSE3, Enabled); 634 } else if (Name == "sse4.2") { 635 setSSELevel(Features, SSE42, Enabled); 636 } else if (Name == "sse4.1") { 637 setSSELevel(Features, SSE41, Enabled); 638 } else if (Name == "3dnow") { 639 setMMXLevel(Features, AMD3DNow, Enabled); 640 } else if (Name == "3dnowa") { 641 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 642 } else if (Name == "aes") { 643 if (Enabled) 644 setSSELevel(Features, SSE2, Enabled); 645 else 646 Features["vaes"] = false; 647 } else if (Name == "vaes") { 648 if (Enabled) { 649 setSSELevel(Features, AVX, Enabled); 650 Features["aes"] = true; 651 } 652 } else if (Name == "pclmul") { 653 if (Enabled) 654 setSSELevel(Features, SSE2, Enabled); 655 else 656 Features["vpclmulqdq"] = false; 657 } else if (Name == "vpclmulqdq") { 658 if (Enabled) { 659 setSSELevel(Features, AVX, Enabled); 660 Features["pclmul"] = true; 661 } 662 } else if (Name == "gfni") { 663 if (Enabled) 664 setSSELevel(Features, SSE2, Enabled); 665 } else if (Name == "avx") { 666 setSSELevel(Features, AVX, Enabled); 667 } else if (Name == "avx2") { 668 setSSELevel(Features, AVX2, Enabled); 669 } else if (Name == "avx512f") { 670 setSSELevel(Features, AVX512F, Enabled); 671 } else if (Name.startswith("avx512")) { 672 if (Enabled) 673 setSSELevel(Features, AVX512F, Enabled); 674 // Enable BWI instruction if certain features are being enabled. 675 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 676 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 677 Features["avx512bw"] = true; 678 // Also disable some features if BWI is being disabled. 679 if (Name == "avx512bw" && !Enabled) { 680 Features["avx512vbmi"] = false; 681 Features["avx512vbmi2"] = false; 682 Features["avx512bitalg"] = false; 683 Features["avx512bf16"] = false; 684 } 685 } else if (Name == "fma") { 686 if (Enabled) 687 setSSELevel(Features, AVX, Enabled); 688 else 689 setSSELevel(Features, AVX512F, Enabled); 690 } else if (Name == "fma4") { 691 setXOPLevel(Features, FMA4, Enabled); 692 } else if (Name == "xop") { 693 setXOPLevel(Features, XOP, Enabled); 694 } else if (Name == "sse4a") { 695 setXOPLevel(Features, SSE4A, Enabled); 696 } else if (Name == "f16c") { 697 if (Enabled) 698 setSSELevel(Features, AVX, Enabled); 699 else 700 setSSELevel(Features, AVX512F, Enabled); 701 } else if (Name == "sha") { 702 if (Enabled) 703 setSSELevel(Features, SSE2, Enabled); 704 } else if (Name == "sse4") { 705 // We can get here via the __target__ attribute since that's not controlled 706 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 707 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 708 // disabled. 709 if (Enabled) 710 setSSELevel(Features, SSE42, Enabled); 711 else 712 setSSELevel(Features, SSE41, Enabled); 713 } else if (Name == "xsave") { 714 if (!Enabled) 715 Features["xsaveopt"] = Features["xsavec"] = Features["xsaves"] = false; 716 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 717 if (Enabled) 718 Features["xsave"] = true; 719 } 720 } 721 722 /// handleTargetFeatures - Perform initialization based on the user 723 /// configured set of features. 724 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 725 DiagnosticsEngine &Diags) { 726 for (const auto &Feature : Features) { 727 if (Feature[0] != '+') 728 continue; 729 730 if (Feature == "+aes") { 731 HasAES = true; 732 } else if (Feature == "+vaes") { 733 HasVAES = true; 734 } else if (Feature == "+pclmul") { 735 HasPCLMUL = true; 736 } else if (Feature == "+vpclmulqdq") { 737 HasVPCLMULQDQ = true; 738 } else if (Feature == "+lzcnt") { 739 HasLZCNT = true; 740 } else if (Feature == "+rdrnd") { 741 HasRDRND = true; 742 } else if (Feature == "+fsgsbase") { 743 HasFSGSBASE = true; 744 } else if (Feature == "+bmi") { 745 HasBMI = true; 746 } else if (Feature == "+bmi2") { 747 HasBMI2 = true; 748 } else if (Feature == "+popcnt") { 749 HasPOPCNT = true; 750 } else if (Feature == "+rtm") { 751 HasRTM = true; 752 } else if (Feature == "+prfchw") { 753 HasPRFCHW = true; 754 } else if (Feature == "+rdseed") { 755 HasRDSEED = true; 756 } else if (Feature == "+adx") { 757 HasADX = true; 758 } else if (Feature == "+tbm") { 759 HasTBM = true; 760 } else if (Feature == "+lwp") { 761 HasLWP = true; 762 } else if (Feature == "+fma") { 763 HasFMA = true; 764 } else if (Feature == "+f16c") { 765 HasF16C = true; 766 } else if (Feature == "+gfni") { 767 HasGFNI = true; 768 } else if (Feature == "+avx512cd") { 769 HasAVX512CD = true; 770 } else if (Feature == "+avx512vpopcntdq") { 771 HasAVX512VPOPCNTDQ = true; 772 } else if (Feature == "+avx512vnni") { 773 HasAVX512VNNI = true; 774 } else if (Feature == "+avx512bf16") { 775 HasAVX512BF16 = true; 776 } else if (Feature == "+avx512er") { 777 HasAVX512ER = true; 778 } else if (Feature == "+avx512pf") { 779 HasAVX512PF = true; 780 } else if (Feature == "+avx512dq") { 781 HasAVX512DQ = true; 782 } else if (Feature == "+avx512bitalg") { 783 HasAVX512BITALG = true; 784 } else if (Feature == "+avx512bw") { 785 HasAVX512BW = true; 786 } else if (Feature == "+avx512vl") { 787 HasAVX512VL = true; 788 } else if (Feature == "+avx512vbmi") { 789 HasAVX512VBMI = true; 790 } else if (Feature == "+avx512vbmi2") { 791 HasAVX512VBMI2 = true; 792 } else if (Feature == "+avx512ifma") { 793 HasAVX512IFMA = true; 794 } else if (Feature == "+avx512vp2intersect") { 795 HasAVX512VP2INTERSECT = true; 796 } else if (Feature == "+sha") { 797 HasSHA = true; 798 } else if (Feature == "+shstk") { 799 HasSHSTK = true; 800 } else if (Feature == "+movbe") { 801 HasMOVBE = true; 802 } else if (Feature == "+sgx") { 803 HasSGX = true; 804 } else if (Feature == "+cx8") { 805 HasCX8 = true; 806 } else if (Feature == "+cx16") { 807 HasCX16 = true; 808 } else if (Feature == "+fxsr") { 809 HasFXSR = true; 810 } else if (Feature == "+xsave") { 811 HasXSAVE = true; 812 } else if (Feature == "+xsaveopt") { 813 HasXSAVEOPT = true; 814 } else if (Feature == "+xsavec") { 815 HasXSAVEC = true; 816 } else if (Feature == "+xsaves") { 817 HasXSAVES = true; 818 } else if (Feature == "+mwaitx") { 819 HasMWAITX = true; 820 } else if (Feature == "+pku") { 821 HasPKU = true; 822 } else if (Feature == "+clflushopt") { 823 HasCLFLUSHOPT = true; 824 } else if (Feature == "+clwb") { 825 HasCLWB = true; 826 } else if (Feature == "+wbnoinvd") { 827 HasWBNOINVD = true; 828 } else if (Feature == "+prefetchwt1") { 829 HasPREFETCHWT1 = true; 830 } else if (Feature == "+clzero") { 831 HasCLZERO = true; 832 } else if (Feature == "+cldemote") { 833 HasCLDEMOTE = true; 834 } else if (Feature == "+rdpid") { 835 HasRDPID = true; 836 } else if (Feature == "+retpoline-external-thunk") { 837 HasRetpolineExternalThunk = true; 838 } else if (Feature == "+sahf") { 839 HasLAHFSAHF = true; 840 } else if (Feature == "+waitpkg") { 841 HasWAITPKG = true; 842 } else if (Feature == "+movdiri") { 843 HasMOVDIRI = true; 844 } else if (Feature == "+movdir64b") { 845 HasMOVDIR64B = true; 846 } else if (Feature == "+pconfig") { 847 HasPCONFIG = true; 848 } else if (Feature == "+ptwrite") { 849 HasPTWRITE = true; 850 } else if (Feature == "+invpcid") { 851 HasINVPCID = true; 852 } else if (Feature == "+enqcmd") { 853 HasENQCMD = true; 854 } else if (Feature == "+serialize") { 855 HasSERIALIZE = true; 856 } else if (Feature == "+tsxldtrk") { 857 HasTSXLDTRK = true; 858 } 859 860 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 861 .Case("+avx512f", AVX512F) 862 .Case("+avx2", AVX2) 863 .Case("+avx", AVX) 864 .Case("+sse4.2", SSE42) 865 .Case("+sse4.1", SSE41) 866 .Case("+ssse3", SSSE3) 867 .Case("+sse3", SSE3) 868 .Case("+sse2", SSE2) 869 .Case("+sse", SSE1) 870 .Default(NoSSE); 871 SSELevel = std::max(SSELevel, Level); 872 873 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 874 .Case("+3dnowa", AMD3DNowAthlon) 875 .Case("+3dnow", AMD3DNow) 876 .Case("+mmx", MMX) 877 .Default(NoMMX3DNow); 878 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 879 880 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 881 .Case("+xop", XOP) 882 .Case("+fma4", FMA4) 883 .Case("+sse4a", SSE4A) 884 .Default(NoXOP); 885 XOPLevel = std::max(XOPLevel, XLevel); 886 } 887 888 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 889 // matches the selected sse level. 890 if ((FPMath == FP_SSE && SSELevel < SSE1) || 891 (FPMath == FP_387 && SSELevel >= SSE1)) { 892 Diags.Report(diag::err_target_unsupported_fpmath) 893 << (FPMath == FP_SSE ? "sse" : "387"); 894 return false; 895 } 896 897 SimdDefaultAlign = 898 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 899 return true; 900 } 901 902 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 903 /// definitions for this particular subtarget. 904 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 905 MacroBuilder &Builder) const { 906 // Inline assembly supports X86 flag outputs. 907 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 908 909 std::string CodeModel = getTargetOpts().CodeModel; 910 if (CodeModel == "default") 911 CodeModel = "small"; 912 Builder.defineMacro("__code_model_" + CodeModel + "__"); 913 914 // Target identification. 915 if (getTriple().getArch() == llvm::Triple::x86_64) { 916 Builder.defineMacro("__amd64__"); 917 Builder.defineMacro("__amd64"); 918 Builder.defineMacro("__x86_64"); 919 Builder.defineMacro("__x86_64__"); 920 if (getTriple().getArchName() == "x86_64h") { 921 Builder.defineMacro("__x86_64h"); 922 Builder.defineMacro("__x86_64h__"); 923 } 924 } else { 925 DefineStd(Builder, "i386", Opts); 926 } 927 928 Builder.defineMacro("__SEG_GS"); 929 Builder.defineMacro("__SEG_FS"); 930 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 931 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 932 933 // Subtarget options. 934 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 935 // truly should be based on -mtune options. 936 using namespace llvm::X86; 937 switch (CPU) { 938 case CK_None: 939 break; 940 case CK_i386: 941 // The rest are coming from the i386 define above. 942 Builder.defineMacro("__tune_i386__"); 943 break; 944 case CK_i486: 945 case CK_WinChipC6: 946 case CK_WinChip2: 947 case CK_C3: 948 defineCPUMacros(Builder, "i486"); 949 break; 950 case CK_PentiumMMX: 951 Builder.defineMacro("__pentium_mmx__"); 952 Builder.defineMacro("__tune_pentium_mmx__"); 953 LLVM_FALLTHROUGH; 954 case CK_i586: 955 case CK_Pentium: 956 defineCPUMacros(Builder, "i586"); 957 defineCPUMacros(Builder, "pentium"); 958 break; 959 case CK_Pentium3: 960 case CK_PentiumM: 961 Builder.defineMacro("__tune_pentium3__"); 962 LLVM_FALLTHROUGH; 963 case CK_Pentium2: 964 case CK_C3_2: 965 Builder.defineMacro("__tune_pentium2__"); 966 LLVM_FALLTHROUGH; 967 case CK_PentiumPro: 968 case CK_i686: 969 defineCPUMacros(Builder, "i686"); 970 defineCPUMacros(Builder, "pentiumpro"); 971 break; 972 case CK_Pentium4: 973 defineCPUMacros(Builder, "pentium4"); 974 break; 975 case CK_Yonah: 976 case CK_Prescott: 977 case CK_Nocona: 978 defineCPUMacros(Builder, "nocona"); 979 break; 980 case CK_Core2: 981 case CK_Penryn: 982 defineCPUMacros(Builder, "core2"); 983 break; 984 case CK_Bonnell: 985 defineCPUMacros(Builder, "atom"); 986 break; 987 case CK_Silvermont: 988 defineCPUMacros(Builder, "slm"); 989 break; 990 case CK_Goldmont: 991 defineCPUMacros(Builder, "goldmont"); 992 break; 993 case CK_GoldmontPlus: 994 defineCPUMacros(Builder, "goldmont_plus"); 995 break; 996 case CK_Tremont: 997 defineCPUMacros(Builder, "tremont"); 998 break; 999 case CK_Nehalem: 1000 case CK_Westmere: 1001 case CK_SandyBridge: 1002 case CK_IvyBridge: 1003 case CK_Haswell: 1004 case CK_Broadwell: 1005 case CK_SkylakeClient: 1006 case CK_SkylakeServer: 1007 case CK_Cascadelake: 1008 case CK_Cooperlake: 1009 case CK_Cannonlake: 1010 case CK_IcelakeClient: 1011 case CK_IcelakeServer: 1012 case CK_Tigerlake: 1013 // FIXME: Historically, we defined this legacy name, it would be nice to 1014 // remove it at some point. We've never exposed fine-grained names for 1015 // recent primary x86 CPUs, and we should keep it that way. 1016 defineCPUMacros(Builder, "corei7"); 1017 break; 1018 case CK_KNL: 1019 defineCPUMacros(Builder, "knl"); 1020 break; 1021 case CK_KNM: 1022 break; 1023 case CK_Lakemont: 1024 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1025 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1026 Builder.defineMacro("__tune_lakemont__"); 1027 break; 1028 case CK_K6_2: 1029 Builder.defineMacro("__k6_2__"); 1030 Builder.defineMacro("__tune_k6_2__"); 1031 LLVM_FALLTHROUGH; 1032 case CK_K6_3: 1033 if (CPU != CK_K6_2) { // In case of fallthrough 1034 // FIXME: GCC may be enabling these in cases where some other k6 1035 // architecture is specified but -m3dnow is explicitly provided. The 1036 // exact semantics need to be determined and emulated here. 1037 Builder.defineMacro("__k6_3__"); 1038 Builder.defineMacro("__tune_k6_3__"); 1039 } 1040 LLVM_FALLTHROUGH; 1041 case CK_K6: 1042 defineCPUMacros(Builder, "k6"); 1043 break; 1044 case CK_Athlon: 1045 case CK_AthlonXP: 1046 defineCPUMacros(Builder, "athlon"); 1047 if (SSELevel != NoSSE) { 1048 Builder.defineMacro("__athlon_sse__"); 1049 Builder.defineMacro("__tune_athlon_sse__"); 1050 } 1051 break; 1052 case CK_K8: 1053 case CK_K8SSE3: 1054 case CK_x86_64: 1055 defineCPUMacros(Builder, "k8"); 1056 break; 1057 case CK_AMDFAM10: 1058 defineCPUMacros(Builder, "amdfam10"); 1059 break; 1060 case CK_BTVER1: 1061 defineCPUMacros(Builder, "btver1"); 1062 break; 1063 case CK_BTVER2: 1064 defineCPUMacros(Builder, "btver2"); 1065 break; 1066 case CK_BDVER1: 1067 defineCPUMacros(Builder, "bdver1"); 1068 break; 1069 case CK_BDVER2: 1070 defineCPUMacros(Builder, "bdver2"); 1071 break; 1072 case CK_BDVER3: 1073 defineCPUMacros(Builder, "bdver3"); 1074 break; 1075 case CK_BDVER4: 1076 defineCPUMacros(Builder, "bdver4"); 1077 break; 1078 case CK_ZNVER1: 1079 defineCPUMacros(Builder, "znver1"); 1080 break; 1081 case CK_ZNVER2: 1082 defineCPUMacros(Builder, "znver2"); 1083 break; 1084 case CK_Geode: 1085 defineCPUMacros(Builder, "geode"); 1086 break; 1087 } 1088 1089 // Target properties. 1090 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1091 1092 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1093 // functions in glibc header files that use FP Stack inline asm which the 1094 // backend can't deal with (PR879). 1095 Builder.defineMacro("__NO_MATH_INLINES"); 1096 1097 if (HasAES) 1098 Builder.defineMacro("__AES__"); 1099 1100 if (HasVAES) 1101 Builder.defineMacro("__VAES__"); 1102 1103 if (HasPCLMUL) 1104 Builder.defineMacro("__PCLMUL__"); 1105 1106 if (HasVPCLMULQDQ) 1107 Builder.defineMacro("__VPCLMULQDQ__"); 1108 1109 if (HasLZCNT) 1110 Builder.defineMacro("__LZCNT__"); 1111 1112 if (HasRDRND) 1113 Builder.defineMacro("__RDRND__"); 1114 1115 if (HasFSGSBASE) 1116 Builder.defineMacro("__FSGSBASE__"); 1117 1118 if (HasBMI) 1119 Builder.defineMacro("__BMI__"); 1120 1121 if (HasBMI2) 1122 Builder.defineMacro("__BMI2__"); 1123 1124 if (HasPOPCNT) 1125 Builder.defineMacro("__POPCNT__"); 1126 1127 if (HasRTM) 1128 Builder.defineMacro("__RTM__"); 1129 1130 if (HasPRFCHW) 1131 Builder.defineMacro("__PRFCHW__"); 1132 1133 if (HasRDSEED) 1134 Builder.defineMacro("__RDSEED__"); 1135 1136 if (HasADX) 1137 Builder.defineMacro("__ADX__"); 1138 1139 if (HasTBM) 1140 Builder.defineMacro("__TBM__"); 1141 1142 if (HasLWP) 1143 Builder.defineMacro("__LWP__"); 1144 1145 if (HasMWAITX) 1146 Builder.defineMacro("__MWAITX__"); 1147 1148 if (HasMOVBE) 1149 Builder.defineMacro("__MOVBE__"); 1150 1151 switch (XOPLevel) { 1152 case XOP: 1153 Builder.defineMacro("__XOP__"); 1154 LLVM_FALLTHROUGH; 1155 case FMA4: 1156 Builder.defineMacro("__FMA4__"); 1157 LLVM_FALLTHROUGH; 1158 case SSE4A: 1159 Builder.defineMacro("__SSE4A__"); 1160 LLVM_FALLTHROUGH; 1161 case NoXOP: 1162 break; 1163 } 1164 1165 if (HasFMA) 1166 Builder.defineMacro("__FMA__"); 1167 1168 if (HasF16C) 1169 Builder.defineMacro("__F16C__"); 1170 1171 if (HasGFNI) 1172 Builder.defineMacro("__GFNI__"); 1173 1174 if (HasAVX512CD) 1175 Builder.defineMacro("__AVX512CD__"); 1176 if (HasAVX512VPOPCNTDQ) 1177 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1178 if (HasAVX512VNNI) 1179 Builder.defineMacro("__AVX512VNNI__"); 1180 if (HasAVX512BF16) 1181 Builder.defineMacro("__AVX512BF16__"); 1182 if (HasAVX512ER) 1183 Builder.defineMacro("__AVX512ER__"); 1184 if (HasAVX512PF) 1185 Builder.defineMacro("__AVX512PF__"); 1186 if (HasAVX512DQ) 1187 Builder.defineMacro("__AVX512DQ__"); 1188 if (HasAVX512BITALG) 1189 Builder.defineMacro("__AVX512BITALG__"); 1190 if (HasAVX512BW) 1191 Builder.defineMacro("__AVX512BW__"); 1192 if (HasAVX512VL) 1193 Builder.defineMacro("__AVX512VL__"); 1194 if (HasAVX512VBMI) 1195 Builder.defineMacro("__AVX512VBMI__"); 1196 if (HasAVX512VBMI2) 1197 Builder.defineMacro("__AVX512VBMI2__"); 1198 if (HasAVX512IFMA) 1199 Builder.defineMacro("__AVX512IFMA__"); 1200 if (HasAVX512VP2INTERSECT) 1201 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1202 if (HasSHA) 1203 Builder.defineMacro("__SHA__"); 1204 1205 if (HasFXSR) 1206 Builder.defineMacro("__FXSR__"); 1207 if (HasXSAVE) 1208 Builder.defineMacro("__XSAVE__"); 1209 if (HasXSAVEOPT) 1210 Builder.defineMacro("__XSAVEOPT__"); 1211 if (HasXSAVEC) 1212 Builder.defineMacro("__XSAVEC__"); 1213 if (HasXSAVES) 1214 Builder.defineMacro("__XSAVES__"); 1215 if (HasPKU) 1216 Builder.defineMacro("__PKU__"); 1217 if (HasCLFLUSHOPT) 1218 Builder.defineMacro("__CLFLUSHOPT__"); 1219 if (HasCLWB) 1220 Builder.defineMacro("__CLWB__"); 1221 if (HasWBNOINVD) 1222 Builder.defineMacro("__WBNOINVD__"); 1223 if (HasSHSTK) 1224 Builder.defineMacro("__SHSTK__"); 1225 if (HasSGX) 1226 Builder.defineMacro("__SGX__"); 1227 if (HasPREFETCHWT1) 1228 Builder.defineMacro("__PREFETCHWT1__"); 1229 if (HasCLZERO) 1230 Builder.defineMacro("__CLZERO__"); 1231 if (HasRDPID) 1232 Builder.defineMacro("__RDPID__"); 1233 if (HasCLDEMOTE) 1234 Builder.defineMacro("__CLDEMOTE__"); 1235 if (HasWAITPKG) 1236 Builder.defineMacro("__WAITPKG__"); 1237 if (HasMOVDIRI) 1238 Builder.defineMacro("__MOVDIRI__"); 1239 if (HasMOVDIR64B) 1240 Builder.defineMacro("__MOVDIR64B__"); 1241 if (HasPCONFIG) 1242 Builder.defineMacro("__PCONFIG__"); 1243 if (HasPTWRITE) 1244 Builder.defineMacro("__PTWRITE__"); 1245 if (HasINVPCID) 1246 Builder.defineMacro("__INVPCID__"); 1247 if (HasENQCMD) 1248 Builder.defineMacro("__ENQCMD__"); 1249 if (HasSERIALIZE) 1250 Builder.defineMacro("__SERIALIZE__"); 1251 if (HasTSXLDTRK) 1252 Builder.defineMacro("__TSXLDTRK__"); 1253 1254 // Each case falls through to the previous one here. 1255 switch (SSELevel) { 1256 case AVX512F: 1257 Builder.defineMacro("__AVX512F__"); 1258 LLVM_FALLTHROUGH; 1259 case AVX2: 1260 Builder.defineMacro("__AVX2__"); 1261 LLVM_FALLTHROUGH; 1262 case AVX: 1263 Builder.defineMacro("__AVX__"); 1264 LLVM_FALLTHROUGH; 1265 case SSE42: 1266 Builder.defineMacro("__SSE4_2__"); 1267 LLVM_FALLTHROUGH; 1268 case SSE41: 1269 Builder.defineMacro("__SSE4_1__"); 1270 LLVM_FALLTHROUGH; 1271 case SSSE3: 1272 Builder.defineMacro("__SSSE3__"); 1273 LLVM_FALLTHROUGH; 1274 case SSE3: 1275 Builder.defineMacro("__SSE3__"); 1276 LLVM_FALLTHROUGH; 1277 case SSE2: 1278 Builder.defineMacro("__SSE2__"); 1279 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1280 LLVM_FALLTHROUGH; 1281 case SSE1: 1282 Builder.defineMacro("__SSE__"); 1283 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1284 LLVM_FALLTHROUGH; 1285 case NoSSE: 1286 break; 1287 } 1288 1289 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1290 switch (SSELevel) { 1291 case AVX512F: 1292 case AVX2: 1293 case AVX: 1294 case SSE42: 1295 case SSE41: 1296 case SSSE3: 1297 case SSE3: 1298 case SSE2: 1299 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1300 break; 1301 case SSE1: 1302 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1303 break; 1304 default: 1305 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1306 break; 1307 } 1308 } 1309 1310 // Each case falls through to the previous one here. 1311 switch (MMX3DNowLevel) { 1312 case AMD3DNowAthlon: 1313 Builder.defineMacro("__3dNOW_A__"); 1314 LLVM_FALLTHROUGH; 1315 case AMD3DNow: 1316 Builder.defineMacro("__3dNOW__"); 1317 LLVM_FALLTHROUGH; 1318 case MMX: 1319 Builder.defineMacro("__MMX__"); 1320 LLVM_FALLTHROUGH; 1321 case NoMMX3DNow: 1322 break; 1323 } 1324 1325 if (CPU >= CK_i486 || CPU == CK_None) { 1326 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1329 } 1330 if (HasCX8) 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1332 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1334 1335 if (HasFloat128) 1336 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1337 } 1338 1339 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1340 return llvm::StringSwitch<bool>(Name) 1341 .Case("3dnow", true) 1342 .Case("3dnowa", true) 1343 .Case("adx", true) 1344 .Case("aes", true) 1345 .Case("avx", true) 1346 .Case("avx2", true) 1347 .Case("avx512f", true) 1348 .Case("avx512cd", true) 1349 .Case("avx512vpopcntdq", true) 1350 .Case("avx512vnni", true) 1351 .Case("avx512bf16", true) 1352 .Case("avx512er", true) 1353 .Case("avx512pf", true) 1354 .Case("avx512dq", true) 1355 .Case("avx512bitalg", true) 1356 .Case("avx512bw", true) 1357 .Case("avx512vl", true) 1358 .Case("avx512vbmi", true) 1359 .Case("avx512vbmi2", true) 1360 .Case("avx512ifma", true) 1361 .Case("avx512vp2intersect", true) 1362 .Case("bmi", true) 1363 .Case("bmi2", true) 1364 .Case("cldemote", true) 1365 .Case("clflushopt", true) 1366 .Case("clwb", true) 1367 .Case("clzero", true) 1368 .Case("cx16", true) 1369 .Case("enqcmd", true) 1370 .Case("f16c", true) 1371 .Case("fma", true) 1372 .Case("fma4", true) 1373 .Case("fsgsbase", true) 1374 .Case("fxsr", true) 1375 .Case("gfni", true) 1376 .Case("invpcid", true) 1377 .Case("lwp", true) 1378 .Case("lzcnt", true) 1379 .Case("mmx", true) 1380 .Case("movbe", true) 1381 .Case("movdiri", true) 1382 .Case("movdir64b", true) 1383 .Case("mwaitx", true) 1384 .Case("pclmul", true) 1385 .Case("pconfig", true) 1386 .Case("pku", true) 1387 .Case("popcnt", true) 1388 .Case("prefetchwt1", true) 1389 .Case("prfchw", true) 1390 .Case("ptwrite", true) 1391 .Case("rdpid", true) 1392 .Case("rdrnd", true) 1393 .Case("rdseed", true) 1394 .Case("rtm", true) 1395 .Case("sahf", true) 1396 .Case("serialize", true) 1397 .Case("sgx", true) 1398 .Case("sha", true) 1399 .Case("shstk", true) 1400 .Case("sse", true) 1401 .Case("sse2", true) 1402 .Case("sse3", true) 1403 .Case("ssse3", true) 1404 .Case("sse4", true) 1405 .Case("sse4.1", true) 1406 .Case("sse4.2", true) 1407 .Case("sse4a", true) 1408 .Case("tbm", true) 1409 .Case("tsxldtrk", true) 1410 .Case("vaes", true) 1411 .Case("vpclmulqdq", true) 1412 .Case("wbnoinvd", true) 1413 .Case("waitpkg", true) 1414 .Case("x87", true) 1415 .Case("xop", true) 1416 .Case("xsave", true) 1417 .Case("xsavec", true) 1418 .Case("xsaves", true) 1419 .Case("xsaveopt", true) 1420 .Default(false); 1421 } 1422 1423 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1424 return llvm::StringSwitch<bool>(Feature) 1425 .Case("adx", HasADX) 1426 .Case("aes", HasAES) 1427 .Case("avx", SSELevel >= AVX) 1428 .Case("avx2", SSELevel >= AVX2) 1429 .Case("avx512f", SSELevel >= AVX512F) 1430 .Case("avx512cd", HasAVX512CD) 1431 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1432 .Case("avx512vnni", HasAVX512VNNI) 1433 .Case("avx512bf16", HasAVX512BF16) 1434 .Case("avx512er", HasAVX512ER) 1435 .Case("avx512pf", HasAVX512PF) 1436 .Case("avx512dq", HasAVX512DQ) 1437 .Case("avx512bitalg", HasAVX512BITALG) 1438 .Case("avx512bw", HasAVX512BW) 1439 .Case("avx512vl", HasAVX512VL) 1440 .Case("avx512vbmi", HasAVX512VBMI) 1441 .Case("avx512vbmi2", HasAVX512VBMI2) 1442 .Case("avx512ifma", HasAVX512IFMA) 1443 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1444 .Case("bmi", HasBMI) 1445 .Case("bmi2", HasBMI2) 1446 .Case("cldemote", HasCLDEMOTE) 1447 .Case("clflushopt", HasCLFLUSHOPT) 1448 .Case("clwb", HasCLWB) 1449 .Case("clzero", HasCLZERO) 1450 .Case("cx8", HasCX8) 1451 .Case("cx16", HasCX16) 1452 .Case("enqcmd", HasENQCMD) 1453 .Case("f16c", HasF16C) 1454 .Case("fma", HasFMA) 1455 .Case("fma4", XOPLevel >= FMA4) 1456 .Case("fsgsbase", HasFSGSBASE) 1457 .Case("fxsr", HasFXSR) 1458 .Case("gfni", HasGFNI) 1459 .Case("invpcid", HasINVPCID) 1460 .Case("lwp", HasLWP) 1461 .Case("lzcnt", HasLZCNT) 1462 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1463 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1464 .Case("mmx", MMX3DNowLevel >= MMX) 1465 .Case("movbe", HasMOVBE) 1466 .Case("movdiri", HasMOVDIRI) 1467 .Case("movdir64b", HasMOVDIR64B) 1468 .Case("mwaitx", HasMWAITX) 1469 .Case("pclmul", HasPCLMUL) 1470 .Case("pconfig", HasPCONFIG) 1471 .Case("pku", HasPKU) 1472 .Case("popcnt", HasPOPCNT) 1473 .Case("prefetchwt1", HasPREFETCHWT1) 1474 .Case("prfchw", HasPRFCHW) 1475 .Case("ptwrite", HasPTWRITE) 1476 .Case("rdpid", HasRDPID) 1477 .Case("rdrnd", HasRDRND) 1478 .Case("rdseed", HasRDSEED) 1479 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1480 .Case("rtm", HasRTM) 1481 .Case("sahf", HasLAHFSAHF) 1482 .Case("serialize", HasSERIALIZE) 1483 .Case("sgx", HasSGX) 1484 .Case("sha", HasSHA) 1485 .Case("shstk", HasSHSTK) 1486 .Case("sse", SSELevel >= SSE1) 1487 .Case("sse2", SSELevel >= SSE2) 1488 .Case("sse3", SSELevel >= SSE3) 1489 .Case("ssse3", SSELevel >= SSSE3) 1490 .Case("sse4.1", SSELevel >= SSE41) 1491 .Case("sse4.2", SSELevel >= SSE42) 1492 .Case("sse4a", XOPLevel >= SSE4A) 1493 .Case("tbm", HasTBM) 1494 .Case("tsxldtrk", HasTSXLDTRK) 1495 .Case("vaes", HasVAES) 1496 .Case("vpclmulqdq", HasVPCLMULQDQ) 1497 .Case("wbnoinvd", HasWBNOINVD) 1498 .Case("waitpkg", HasWAITPKG) 1499 .Case("x86", true) 1500 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1501 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1502 .Case("xop", XOPLevel >= XOP) 1503 .Case("xsave", HasXSAVE) 1504 .Case("xsavec", HasXSAVEC) 1505 .Case("xsaves", HasXSAVES) 1506 .Case("xsaveopt", HasXSAVEOPT) 1507 .Default(false); 1508 } 1509 1510 // We can't use a generic validation scheme for the features accepted here 1511 // versus subtarget features accepted in the target attribute because the 1512 // bitfield structure that's initialized in the runtime only supports the 1513 // below currently rather than the full range of subtarget features. (See 1514 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1515 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1516 return llvm::StringSwitch<bool>(FeatureStr) 1517 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1518 #include "llvm/Support/X86TargetParser.def" 1519 .Default(false); 1520 } 1521 1522 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1523 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1524 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::ENUM) 1525 #include "llvm/Support/X86TargetParser.def" 1526 ; 1527 // Note, this function should only be used after ensuring the value is 1528 // correct, so it asserts if the value is out of range. 1529 } 1530 1531 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1532 enum class FeatPriority { 1533 #define FEATURE(FEAT) FEAT, 1534 #include "clang/Basic/X86Target.def" 1535 }; 1536 switch (Feat) { 1537 #define FEATURE(FEAT) \ 1538 case llvm::X86::FEAT: \ 1539 return static_cast<unsigned>(FeatPriority::FEAT); 1540 #include "clang/Basic/X86Target.def" 1541 default: 1542 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1543 } 1544 } 1545 1546 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1547 // Valid CPUs have a 'key feature' that compares just better than its key 1548 // feature. 1549 using namespace llvm::X86; 1550 CPUKind Kind = parseArchX86(Name); 1551 if (Kind != CK_None) { 1552 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1553 return (getFeaturePriority(KeyFeature) << 1) + 1; 1554 } 1555 1556 // Now we know we have a feature, so get its priority and shift it a few so 1557 // that we have sufficient room for the CPUs (above). 1558 return getFeaturePriority(getFeature(Name)) << 1; 1559 } 1560 1561 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1562 return llvm::StringSwitch<bool>(Name) 1563 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1564 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1565 #include "clang/Basic/X86Target.def" 1566 .Default(false); 1567 } 1568 1569 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1570 return llvm::StringSwitch<StringRef>(Name) 1571 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1572 #include "clang/Basic/X86Target.def" 1573 .Default(Name); 1574 } 1575 1576 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1577 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1578 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1579 #include "clang/Basic/X86Target.def" 1580 .Default(0); 1581 } 1582 1583 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1584 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1585 StringRef WholeList = 1586 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1587 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1588 #include "clang/Basic/X86Target.def" 1589 .Default(""); 1590 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1591 } 1592 1593 // We can't use a generic validation scheme for the cpus accepted here 1594 // versus subtarget cpus accepted in the target attribute because the 1595 // variables intitialized by the runtime only support the below currently 1596 // rather than the full range of cpus. 1597 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1598 return llvm::StringSwitch<bool>(FeatureStr) 1599 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1600 #define X86_CPU_TYPE_COMPAT_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1601 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1602 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1603 #include "llvm/Support/X86TargetParser.def" 1604 .Default(false); 1605 } 1606 1607 static unsigned matchAsmCCConstraint(const char *&Name) { 1608 auto RV = llvm::StringSwitch<unsigned>(Name) 1609 .Case("@cca", 4) 1610 .Case("@ccae", 5) 1611 .Case("@ccb", 4) 1612 .Case("@ccbe", 5) 1613 .Case("@ccc", 4) 1614 .Case("@cce", 4) 1615 .Case("@ccz", 4) 1616 .Case("@ccg", 4) 1617 .Case("@ccge", 5) 1618 .Case("@ccl", 4) 1619 .Case("@ccle", 5) 1620 .Case("@ccna", 5) 1621 .Case("@ccnae", 6) 1622 .Case("@ccnb", 5) 1623 .Case("@ccnbe", 6) 1624 .Case("@ccnc", 5) 1625 .Case("@ccne", 5) 1626 .Case("@ccnz", 5) 1627 .Case("@ccng", 5) 1628 .Case("@ccnge", 6) 1629 .Case("@ccnl", 5) 1630 .Case("@ccnle", 6) 1631 .Case("@ccno", 5) 1632 .Case("@ccnp", 5) 1633 .Case("@ccns", 5) 1634 .Case("@cco", 4) 1635 .Case("@ccp", 4) 1636 .Case("@ccs", 4) 1637 .Default(0); 1638 return RV; 1639 } 1640 1641 bool X86TargetInfo::validateAsmConstraint( 1642 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1643 switch (*Name) { 1644 default: 1645 return false; 1646 // Constant constraints. 1647 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1648 // instructions. 1649 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1650 // x86_64 instructions. 1651 case 's': 1652 Info.setRequiresImmediate(); 1653 return true; 1654 case 'I': 1655 Info.setRequiresImmediate(0, 31); 1656 return true; 1657 case 'J': 1658 Info.setRequiresImmediate(0, 63); 1659 return true; 1660 case 'K': 1661 Info.setRequiresImmediate(-128, 127); 1662 return true; 1663 case 'L': 1664 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1665 return true; 1666 case 'M': 1667 Info.setRequiresImmediate(0, 3); 1668 return true; 1669 case 'N': 1670 Info.setRequiresImmediate(0, 255); 1671 return true; 1672 case 'O': 1673 Info.setRequiresImmediate(0, 127); 1674 return true; 1675 // Register constraints. 1676 case 'Y': // 'Y' is the first character for several 2-character constraints. 1677 // Shift the pointer to the second character of the constraint. 1678 Name++; 1679 switch (*Name) { 1680 default: 1681 return false; 1682 case 'z': // First SSE register. 1683 case '2': 1684 case 't': // Any SSE register, when SSE2 is enabled. 1685 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1686 case 'm': // Any MMX register, when inter-unit moves enabled. 1687 case 'k': // AVX512 arch mask registers: k1-k7. 1688 Info.setAllowsRegister(); 1689 return true; 1690 } 1691 case 'f': // Any x87 floating point stack register. 1692 // Constraint 'f' cannot be used for output operands. 1693 if (Info.ConstraintStr[0] == '=') 1694 return false; 1695 Info.setAllowsRegister(); 1696 return true; 1697 case 'a': // eax. 1698 case 'b': // ebx. 1699 case 'c': // ecx. 1700 case 'd': // edx. 1701 case 'S': // esi. 1702 case 'D': // edi. 1703 case 'A': // edx:eax. 1704 case 't': // Top of floating point stack. 1705 case 'u': // Second from top of floating point stack. 1706 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1707 case 'y': // Any MMX register. 1708 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1709 case 'x': // Any SSE register. 1710 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1711 // for intermideate k reg operations). 1712 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1713 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1714 case 'l': // "Index" registers: any general register that can be used as an 1715 // index in a base+index memory access. 1716 Info.setAllowsRegister(); 1717 return true; 1718 // Floating point constant constraints. 1719 case 'C': // SSE floating point constant. 1720 case 'G': // x87 floating point constant. 1721 return true; 1722 case '@': 1723 // CC condition changes. 1724 if (auto Len = matchAsmCCConstraint(Name)) { 1725 Name += Len - 1; 1726 Info.setAllowsRegister(); 1727 return true; 1728 } 1729 return false; 1730 } 1731 } 1732 1733 // Below is based on the following information: 1734 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1735 // | Processor Name | Cache Line Size (Bytes) | Source | 1736 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1737 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1738 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1739 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1740 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1741 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1742 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1743 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1744 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1745 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1746 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1747 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1748 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1749 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1750 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1751 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1752 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1753 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1754 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1755 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1756 using namespace llvm::X86; 1757 switch (CPU) { 1758 // i386 1759 case CK_i386: 1760 // i486 1761 case CK_i486: 1762 case CK_WinChipC6: 1763 case CK_WinChip2: 1764 case CK_C3: 1765 // Lakemont 1766 case CK_Lakemont: 1767 return 16; 1768 1769 // i586 1770 case CK_i586: 1771 case CK_Pentium: 1772 case CK_PentiumMMX: 1773 // i686 1774 case CK_PentiumPro: 1775 case CK_i686: 1776 case CK_Pentium2: 1777 case CK_Pentium3: 1778 case CK_PentiumM: 1779 case CK_C3_2: 1780 // K6 1781 case CK_K6: 1782 case CK_K6_2: 1783 case CK_K6_3: 1784 // Geode 1785 case CK_Geode: 1786 return 32; 1787 1788 // Netburst 1789 case CK_Pentium4: 1790 case CK_Prescott: 1791 case CK_Nocona: 1792 // Atom 1793 case CK_Bonnell: 1794 case CK_Silvermont: 1795 case CK_Goldmont: 1796 case CK_GoldmontPlus: 1797 case CK_Tremont: 1798 1799 case CK_Westmere: 1800 case CK_SandyBridge: 1801 case CK_IvyBridge: 1802 case CK_Haswell: 1803 case CK_Broadwell: 1804 case CK_SkylakeClient: 1805 case CK_SkylakeServer: 1806 case CK_Cascadelake: 1807 case CK_Nehalem: 1808 case CK_Cooperlake: 1809 case CK_Cannonlake: 1810 case CK_Tigerlake: 1811 case CK_IcelakeClient: 1812 case CK_IcelakeServer: 1813 case CK_KNL: 1814 case CK_KNM: 1815 // K7 1816 case CK_Athlon: 1817 case CK_AthlonXP: 1818 // K8 1819 case CK_K8: 1820 case CK_K8SSE3: 1821 case CK_AMDFAM10: 1822 // Bobcat 1823 case CK_BTVER1: 1824 case CK_BTVER2: 1825 // Bulldozer 1826 case CK_BDVER1: 1827 case CK_BDVER2: 1828 case CK_BDVER3: 1829 case CK_BDVER4: 1830 // Zen 1831 case CK_ZNVER1: 1832 case CK_ZNVER2: 1833 // Deprecated 1834 case CK_x86_64: 1835 case CK_Yonah: 1836 case CK_Penryn: 1837 case CK_Core2: 1838 return 64; 1839 1840 // The following currently have unknown cache line sizes (but they are probably all 64): 1841 // Core 1842 case CK_None: 1843 return None; 1844 } 1845 llvm_unreachable("Unknown CPU kind"); 1846 } 1847 1848 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1849 StringRef Constraint, 1850 unsigned Size) const { 1851 // Strip off constraint modifiers. 1852 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1853 Constraint = Constraint.substr(1); 1854 1855 return validateOperandSize(FeatureMap, Constraint, Size); 1856 } 1857 1858 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1859 StringRef Constraint, 1860 unsigned Size) const { 1861 return validateOperandSize(FeatureMap, Constraint, Size); 1862 } 1863 1864 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1865 StringRef Constraint, 1866 unsigned Size) const { 1867 switch (Constraint[0]) { 1868 default: 1869 break; 1870 case 'k': 1871 // Registers k0-k7 (AVX512) size limit is 64 bit. 1872 case 'y': 1873 return Size <= 64; 1874 case 'f': 1875 case 't': 1876 case 'u': 1877 return Size <= 128; 1878 case 'Y': 1879 // 'Y' is the first character for several 2-character constraints. 1880 switch (Constraint[1]) { 1881 default: 1882 return false; 1883 case 'm': 1884 // 'Ym' is synonymous with 'y'. 1885 case 'k': 1886 return Size <= 64; 1887 case 'z': 1888 // XMM0/YMM/ZMM0 1889 if (FeatureMap.lookup("avx512f")) 1890 // ZMM0 can be used if target supports AVX512F. 1891 return Size <= 512U; 1892 else if (FeatureMap.lookup("avx")) 1893 // YMM0 can be used if target supports AVX. 1894 return Size <= 256U; 1895 else if (FeatureMap.lookup("sse")) 1896 return Size <= 128U; 1897 return false; 1898 case 'i': 1899 case 't': 1900 case '2': 1901 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1902 if (SSELevel < SSE2) 1903 return false; 1904 break; 1905 } 1906 break; 1907 case 'v': 1908 case 'x': 1909 if (FeatureMap.lookup("avx512f")) 1910 // 512-bit zmm registers can be used if target supports AVX512F. 1911 return Size <= 512U; 1912 else if (FeatureMap.lookup("avx")) 1913 // 256-bit ymm registers can be used if target supports AVX. 1914 return Size <= 256U; 1915 return Size <= 128U; 1916 1917 } 1918 1919 return true; 1920 } 1921 1922 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1923 switch (*Constraint) { 1924 case '@': 1925 if (auto Len = matchAsmCCConstraint(Constraint)) { 1926 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1927 Constraint += Len - 1; 1928 return Converted; 1929 } 1930 return std::string(1, *Constraint); 1931 case 'a': 1932 return std::string("{ax}"); 1933 case 'b': 1934 return std::string("{bx}"); 1935 case 'c': 1936 return std::string("{cx}"); 1937 case 'd': 1938 return std::string("{dx}"); 1939 case 'S': 1940 return std::string("{si}"); 1941 case 'D': 1942 return std::string("{di}"); 1943 case 'p': // address 1944 return std::string("im"); 1945 case 't': // top of floating point stack. 1946 return std::string("{st}"); 1947 case 'u': // second from top of floating point stack. 1948 return std::string("{st(1)}"); // second from top of floating point stack. 1949 case 'Y': 1950 switch (Constraint[1]) { 1951 default: 1952 // Break from inner switch and fall through (copy single char), 1953 // continue parsing after copying the current constraint into 1954 // the return string. 1955 break; 1956 case 'k': 1957 case 'm': 1958 case 'i': 1959 case 't': 1960 case 'z': 1961 case '2': 1962 // "^" hints llvm that this is a 2 letter constraint. 1963 // "Constraint++" is used to promote the string iterator 1964 // to the next constraint. 1965 return std::string("^") + std::string(Constraint++, 2); 1966 } 1967 LLVM_FALLTHROUGH; 1968 default: 1969 return std::string(1, *Constraint); 1970 } 1971 } 1972 1973 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1974 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1975 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1976 } 1977 1978 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1979 return llvm::makeArrayRef(GCCRegNames); 1980 } 1981 1982 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1983 return llvm::makeArrayRef(AddlRegNames); 1984 } 1985 1986 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1987 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1988 Builtin::FirstTSBuiltin + 1); 1989 } 1990 1991 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1992 return llvm::makeArrayRef(BuiltinInfoX86, 1993 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1994 } 1995