1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabledImpl(Features, "sse2", true); 112 113 const CPUKind Kind = getCPUKind(CPU); 114 115 // Enable X87 for all X86 processors but Lakemont. 116 if (Kind != CK_Lakemont) 117 setFeatureEnabledImpl(Features, "x87", true); 118 119 switch (Kind) { 120 case CK_Generic: 121 case CK_i386: 122 case CK_i486: 123 case CK_i586: 124 case CK_Pentium: 125 case CK_PentiumPro: 126 case CK_Lakemont: 127 break; 128 129 case CK_PentiumMMX: 130 case CK_Pentium2: 131 case CK_K6: 132 case CK_WinChipC6: 133 setFeatureEnabledImpl(Features, "mmx", true); 134 break; 135 136 case CK_IcelakeServer: 137 setFeatureEnabledImpl(Features, "pconfig", true); 138 setFeatureEnabledImpl(Features, "wbnoinvd", true); 139 LLVM_FALLTHROUGH; 140 case CK_IcelakeClient: 141 setFeatureEnabledImpl(Features, "vaes", true); 142 setFeatureEnabledImpl(Features, "gfni", true); 143 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 144 setFeatureEnabledImpl(Features, "avx512bitalg", true); 145 setFeatureEnabledImpl(Features, "avx512vnni", true); 146 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 147 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 148 setFeatureEnabledImpl(Features, "rdpid", true); 149 LLVM_FALLTHROUGH; 150 case CK_Cannonlake: 151 setFeatureEnabledImpl(Features, "avx512ifma", true); 152 setFeatureEnabledImpl(Features, "avx512vbmi", true); 153 setFeatureEnabledImpl(Features, "sha", true); 154 LLVM_FALLTHROUGH; 155 case CK_SkylakeServer: 156 setFeatureEnabledImpl(Features, "avx512f", true); 157 setFeatureEnabledImpl(Features, "avx512cd", true); 158 setFeatureEnabledImpl(Features, "avx512dq", true); 159 setFeatureEnabledImpl(Features, "avx512bw", true); 160 setFeatureEnabledImpl(Features, "avx512vl", true); 161 setFeatureEnabledImpl(Features, "pku", true); 162 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 163 setFeatureEnabledImpl(Features, "clwb", true); 164 LLVM_FALLTHROUGH; 165 case CK_SkylakeClient: 166 setFeatureEnabledImpl(Features, "xsavec", true); 167 setFeatureEnabledImpl(Features, "xsaves", true); 168 setFeatureEnabledImpl(Features, "mpx", true); 169 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 170 setFeatureEnabledImpl(Features, "sgx", true); 171 setFeatureEnabledImpl(Features, "clflushopt", true); 172 setFeatureEnabledImpl(Features, "aes", true); 173 LLVM_FALLTHROUGH; 174 case CK_Broadwell: 175 setFeatureEnabledImpl(Features, "rdseed", true); 176 setFeatureEnabledImpl(Features, "adx", true); 177 setFeatureEnabledImpl(Features, "prfchw", true); 178 LLVM_FALLTHROUGH; 179 case CK_Haswell: 180 setFeatureEnabledImpl(Features, "avx2", true); 181 setFeatureEnabledImpl(Features, "lzcnt", true); 182 setFeatureEnabledImpl(Features, "bmi", true); 183 setFeatureEnabledImpl(Features, "bmi2", true); 184 setFeatureEnabledImpl(Features, "fma", true); 185 setFeatureEnabledImpl(Features, "invpcid", true); 186 setFeatureEnabledImpl(Features, "movbe", true); 187 LLVM_FALLTHROUGH; 188 case CK_IvyBridge: 189 setFeatureEnabledImpl(Features, "rdrnd", true); 190 setFeatureEnabledImpl(Features, "f16c", true); 191 setFeatureEnabledImpl(Features, "fsgsbase", true); 192 LLVM_FALLTHROUGH; 193 case CK_SandyBridge: 194 setFeatureEnabledImpl(Features, "avx", true); 195 setFeatureEnabledImpl(Features, "xsave", true); 196 setFeatureEnabledImpl(Features, "xsaveopt", true); 197 LLVM_FALLTHROUGH; 198 case CK_Westmere: 199 setFeatureEnabledImpl(Features, "pclmul", true); 200 LLVM_FALLTHROUGH; 201 case CK_Nehalem: 202 setFeatureEnabledImpl(Features, "sse4.2", true); 203 LLVM_FALLTHROUGH; 204 case CK_Penryn: 205 setFeatureEnabledImpl(Features, "sse4.1", true); 206 LLVM_FALLTHROUGH; 207 case CK_Core2: 208 setFeatureEnabledImpl(Features, "ssse3", true); 209 setFeatureEnabledImpl(Features, "sahf", true); 210 LLVM_FALLTHROUGH; 211 case CK_Yonah: 212 case CK_Prescott: 213 case CK_Nocona: 214 setFeatureEnabledImpl(Features, "sse3", true); 215 setFeatureEnabledImpl(Features, "cx16", true); 216 LLVM_FALLTHROUGH; 217 case CK_PentiumM: 218 case CK_Pentium4: 219 case CK_x86_64: 220 setFeatureEnabledImpl(Features, "sse2", true); 221 LLVM_FALLTHROUGH; 222 case CK_Pentium3: 223 case CK_C3_2: 224 setFeatureEnabledImpl(Features, "sse", true); 225 setFeatureEnabledImpl(Features, "fxsr", true); 226 break; 227 228 case CK_Tremont: 229 setFeatureEnabledImpl(Features, "cldemote", true); 230 setFeatureEnabledImpl(Features, "movdiri", true); 231 setFeatureEnabledImpl(Features, "movdir64b", true); 232 setFeatureEnabledImpl(Features, "gfni", true); 233 setFeatureEnabledImpl(Features, "waitpkg", true); 234 LLVM_FALLTHROUGH; 235 case CK_GoldmontPlus: 236 setFeatureEnabledImpl(Features, "ptwrite", true); 237 setFeatureEnabledImpl(Features, "rdpid", true); 238 setFeatureEnabledImpl(Features, "sgx", true); 239 LLVM_FALLTHROUGH; 240 case CK_Goldmont: 241 setFeatureEnabledImpl(Features, "sha", true); 242 setFeatureEnabledImpl(Features, "rdseed", true); 243 setFeatureEnabledImpl(Features, "xsave", true); 244 setFeatureEnabledImpl(Features, "xsaveopt", true); 245 setFeatureEnabledImpl(Features, "xsavec", true); 246 setFeatureEnabledImpl(Features, "xsaves", true); 247 setFeatureEnabledImpl(Features, "clflushopt", true); 248 setFeatureEnabledImpl(Features, "mpx", true); 249 setFeatureEnabledImpl(Features, "fsgsbase", true); 250 setFeatureEnabledImpl(Features, "aes", true); 251 LLVM_FALLTHROUGH; 252 case CK_Silvermont: 253 setFeatureEnabledImpl(Features, "rdrnd", true); 254 setFeatureEnabledImpl(Features, "pclmul", true); 255 setFeatureEnabledImpl(Features, "sse4.2", true); 256 setFeatureEnabledImpl(Features, "prfchw", true); 257 LLVM_FALLTHROUGH; 258 case CK_Bonnell: 259 setFeatureEnabledImpl(Features, "movbe", true); 260 setFeatureEnabledImpl(Features, "ssse3", true); 261 setFeatureEnabledImpl(Features, "fxsr", true); 262 setFeatureEnabledImpl(Features, "cx16", true); 263 setFeatureEnabledImpl(Features, "sahf", true); 264 break; 265 266 case CK_KNM: 267 // TODO: Add avx5124fmaps/avx5124vnniw. 268 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 269 LLVM_FALLTHROUGH; 270 case CK_KNL: 271 setFeatureEnabledImpl(Features, "avx512f", true); 272 setFeatureEnabledImpl(Features, "avx512cd", true); 273 setFeatureEnabledImpl(Features, "avx512er", true); 274 setFeatureEnabledImpl(Features, "avx512pf", true); 275 setFeatureEnabledImpl(Features, "prfchw", true); 276 setFeatureEnabledImpl(Features, "prefetchwt1", true); 277 setFeatureEnabledImpl(Features, "fxsr", true); 278 setFeatureEnabledImpl(Features, "rdseed", true); 279 setFeatureEnabledImpl(Features, "adx", true); 280 setFeatureEnabledImpl(Features, "lzcnt", true); 281 setFeatureEnabledImpl(Features, "bmi", true); 282 setFeatureEnabledImpl(Features, "bmi2", true); 283 setFeatureEnabledImpl(Features, "fma", true); 284 setFeatureEnabledImpl(Features, "rdrnd", true); 285 setFeatureEnabledImpl(Features, "f16c", true); 286 setFeatureEnabledImpl(Features, "fsgsbase", true); 287 setFeatureEnabledImpl(Features, "aes", true); 288 setFeatureEnabledImpl(Features, "pclmul", true); 289 setFeatureEnabledImpl(Features, "cx16", true); 290 setFeatureEnabledImpl(Features, "xsaveopt", true); 291 setFeatureEnabledImpl(Features, "xsave", true); 292 setFeatureEnabledImpl(Features, "movbe", true); 293 setFeatureEnabledImpl(Features, "sahf", true); 294 break; 295 296 case CK_K6_2: 297 case CK_K6_3: 298 case CK_WinChip2: 299 case CK_C3: 300 setFeatureEnabledImpl(Features, "3dnow", true); 301 break; 302 303 case CK_AMDFAM10: 304 setFeatureEnabledImpl(Features, "sse4a", true); 305 setFeatureEnabledImpl(Features, "lzcnt", true); 306 setFeatureEnabledImpl(Features, "popcnt", true); 307 setFeatureEnabledImpl(Features, "sahf", true); 308 LLVM_FALLTHROUGH; 309 case CK_K8SSE3: 310 setFeatureEnabledImpl(Features, "sse3", true); 311 LLVM_FALLTHROUGH; 312 case CK_K8: 313 setFeatureEnabledImpl(Features, "sse2", true); 314 LLVM_FALLTHROUGH; 315 case CK_AthlonXP: 316 setFeatureEnabledImpl(Features, "sse", true); 317 setFeatureEnabledImpl(Features, "fxsr", true); 318 LLVM_FALLTHROUGH; 319 case CK_Athlon: 320 case CK_Geode: 321 setFeatureEnabledImpl(Features, "3dnowa", true); 322 break; 323 324 case CK_BTVER2: 325 setFeatureEnabledImpl(Features, "avx", true); 326 setFeatureEnabledImpl(Features, "aes", true); 327 setFeatureEnabledImpl(Features, "pclmul", true); 328 setFeatureEnabledImpl(Features, "bmi", true); 329 setFeatureEnabledImpl(Features, "f16c", true); 330 setFeatureEnabledImpl(Features, "xsaveopt", true); 331 setFeatureEnabledImpl(Features, "movbe", true); 332 LLVM_FALLTHROUGH; 333 case CK_BTVER1: 334 setFeatureEnabledImpl(Features, "ssse3", true); 335 setFeatureEnabledImpl(Features, "sse4a", true); 336 setFeatureEnabledImpl(Features, "lzcnt", true); 337 setFeatureEnabledImpl(Features, "popcnt", true); 338 setFeatureEnabledImpl(Features, "prfchw", true); 339 setFeatureEnabledImpl(Features, "cx16", true); 340 setFeatureEnabledImpl(Features, "fxsr", true); 341 setFeatureEnabledImpl(Features, "sahf", true); 342 break; 343 344 case CK_ZNVER1: 345 setFeatureEnabledImpl(Features, "adx", true); 346 setFeatureEnabledImpl(Features, "aes", true); 347 setFeatureEnabledImpl(Features, "avx2", true); 348 setFeatureEnabledImpl(Features, "bmi", true); 349 setFeatureEnabledImpl(Features, "bmi2", true); 350 setFeatureEnabledImpl(Features, "clflushopt", true); 351 setFeatureEnabledImpl(Features, "clzero", true); 352 setFeatureEnabledImpl(Features, "cx16", true); 353 setFeatureEnabledImpl(Features, "f16c", true); 354 setFeatureEnabledImpl(Features, "fma", true); 355 setFeatureEnabledImpl(Features, "fsgsbase", true); 356 setFeatureEnabledImpl(Features, "fxsr", true); 357 setFeatureEnabledImpl(Features, "lzcnt", true); 358 setFeatureEnabledImpl(Features, "mwaitx", true); 359 setFeatureEnabledImpl(Features, "movbe", true); 360 setFeatureEnabledImpl(Features, "pclmul", true); 361 setFeatureEnabledImpl(Features, "popcnt", true); 362 setFeatureEnabledImpl(Features, "prfchw", true); 363 setFeatureEnabledImpl(Features, "rdrnd", true); 364 setFeatureEnabledImpl(Features, "rdseed", true); 365 setFeatureEnabledImpl(Features, "sahf", true); 366 setFeatureEnabledImpl(Features, "sha", true); 367 setFeatureEnabledImpl(Features, "sse4a", true); 368 setFeatureEnabledImpl(Features, "xsave", true); 369 setFeatureEnabledImpl(Features, "xsavec", true); 370 setFeatureEnabledImpl(Features, "xsaveopt", true); 371 setFeatureEnabledImpl(Features, "xsaves", true); 372 break; 373 374 case CK_BDVER4: 375 setFeatureEnabledImpl(Features, "avx2", true); 376 setFeatureEnabledImpl(Features, "bmi2", true); 377 setFeatureEnabledImpl(Features, "mwaitx", true); 378 LLVM_FALLTHROUGH; 379 case CK_BDVER3: 380 setFeatureEnabledImpl(Features, "fsgsbase", true); 381 setFeatureEnabledImpl(Features, "xsaveopt", true); 382 LLVM_FALLTHROUGH; 383 case CK_BDVER2: 384 setFeatureEnabledImpl(Features, "bmi", true); 385 setFeatureEnabledImpl(Features, "fma", true); 386 setFeatureEnabledImpl(Features, "f16c", true); 387 setFeatureEnabledImpl(Features, "tbm", true); 388 LLVM_FALLTHROUGH; 389 case CK_BDVER1: 390 // xop implies avx, sse4a and fma4. 391 setFeatureEnabledImpl(Features, "xop", true); 392 setFeatureEnabledImpl(Features, "lwp", true); 393 setFeatureEnabledImpl(Features, "lzcnt", true); 394 setFeatureEnabledImpl(Features, "aes", true); 395 setFeatureEnabledImpl(Features, "pclmul", true); 396 setFeatureEnabledImpl(Features, "prfchw", true); 397 setFeatureEnabledImpl(Features, "cx16", true); 398 setFeatureEnabledImpl(Features, "fxsr", true); 399 setFeatureEnabledImpl(Features, "xsave", true); 400 setFeatureEnabledImpl(Features, "sahf", true); 401 break; 402 } 403 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 404 return false; 405 406 // Can't do this earlier because we need to be able to explicitly enable 407 // or disable these features and the things that they depend upon. 408 409 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 410 auto I = Features.find("sse4.2"); 411 if (I != Features.end() && I->getValue() && 412 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 413 FeaturesVec.end()) 414 Features["popcnt"] = true; 415 416 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 417 I = Features.find("3dnow"); 418 if (I != Features.end() && I->getValue() && 419 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 420 FeaturesVec.end()) 421 Features["prfchw"] = true; 422 423 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 424 // then enable MMX. 425 I = Features.find("sse"); 426 if (I != Features.end() && I->getValue() && 427 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 428 FeaturesVec.end()) 429 Features["mmx"] = true; 430 431 return true; 432 } 433 434 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 435 X86SSEEnum Level, bool Enabled) { 436 if (Enabled) { 437 switch (Level) { 438 case AVX512F: 439 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 440 LLVM_FALLTHROUGH; 441 case AVX2: 442 Features["avx2"] = true; 443 LLVM_FALLTHROUGH; 444 case AVX: 445 Features["avx"] = true; 446 Features["xsave"] = true; 447 LLVM_FALLTHROUGH; 448 case SSE42: 449 Features["sse4.2"] = true; 450 LLVM_FALLTHROUGH; 451 case SSE41: 452 Features["sse4.1"] = true; 453 LLVM_FALLTHROUGH; 454 case SSSE3: 455 Features["ssse3"] = true; 456 LLVM_FALLTHROUGH; 457 case SSE3: 458 Features["sse3"] = true; 459 LLVM_FALLTHROUGH; 460 case SSE2: 461 Features["sse2"] = true; 462 LLVM_FALLTHROUGH; 463 case SSE1: 464 Features["sse"] = true; 465 LLVM_FALLTHROUGH; 466 case NoSSE: 467 break; 468 } 469 return; 470 } 471 472 switch (Level) { 473 case NoSSE: 474 case SSE1: 475 Features["sse"] = false; 476 LLVM_FALLTHROUGH; 477 case SSE2: 478 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 479 Features["gfni"] = false; 480 LLVM_FALLTHROUGH; 481 case SSE3: 482 Features["sse3"] = false; 483 setXOPLevel(Features, NoXOP, false); 484 LLVM_FALLTHROUGH; 485 case SSSE3: 486 Features["ssse3"] = false; 487 LLVM_FALLTHROUGH; 488 case SSE41: 489 Features["sse4.1"] = false; 490 LLVM_FALLTHROUGH; 491 case SSE42: 492 Features["sse4.2"] = false; 493 LLVM_FALLTHROUGH; 494 case AVX: 495 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 496 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 497 setXOPLevel(Features, FMA4, false); 498 LLVM_FALLTHROUGH; 499 case AVX2: 500 Features["avx2"] = false; 501 LLVM_FALLTHROUGH; 502 case AVX512F: 503 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 504 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 505 Features["avx512vl"] = Features["avx512vbmi"] = 506 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 507 Features["avx512bitalg"] = Features["avx512vnni"] = 508 Features["avx512vbmi2"] = false; 509 break; 510 } 511 } 512 513 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 514 MMX3DNowEnum Level, bool Enabled) { 515 if (Enabled) { 516 switch (Level) { 517 case AMD3DNowAthlon: 518 Features["3dnowa"] = true; 519 LLVM_FALLTHROUGH; 520 case AMD3DNow: 521 Features["3dnow"] = true; 522 LLVM_FALLTHROUGH; 523 case MMX: 524 Features["mmx"] = true; 525 LLVM_FALLTHROUGH; 526 case NoMMX3DNow: 527 break; 528 } 529 return; 530 } 531 532 switch (Level) { 533 case NoMMX3DNow: 534 case MMX: 535 Features["mmx"] = false; 536 LLVM_FALLTHROUGH; 537 case AMD3DNow: 538 Features["3dnow"] = false; 539 LLVM_FALLTHROUGH; 540 case AMD3DNowAthlon: 541 Features["3dnowa"] = false; 542 break; 543 } 544 } 545 546 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 547 bool Enabled) { 548 if (Enabled) { 549 switch (Level) { 550 case XOP: 551 Features["xop"] = true; 552 LLVM_FALLTHROUGH; 553 case FMA4: 554 Features["fma4"] = true; 555 setSSELevel(Features, AVX, true); 556 LLVM_FALLTHROUGH; 557 case SSE4A: 558 Features["sse4a"] = true; 559 setSSELevel(Features, SSE3, true); 560 LLVM_FALLTHROUGH; 561 case NoXOP: 562 break; 563 } 564 return; 565 } 566 567 switch (Level) { 568 case NoXOP: 569 case SSE4A: 570 Features["sse4a"] = false; 571 LLVM_FALLTHROUGH; 572 case FMA4: 573 Features["fma4"] = false; 574 LLVM_FALLTHROUGH; 575 case XOP: 576 Features["xop"] = false; 577 break; 578 } 579 } 580 581 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 582 StringRef Name, bool Enabled) { 583 // This is a bit of a hack to deal with the sse4 target feature when used 584 // as part of the target attribute. We handle sse4 correctly everywhere 585 // else. See below for more information on how we handle the sse4 options. 586 if (Name != "sse4") 587 Features[Name] = Enabled; 588 589 if (Name == "mmx") { 590 setMMXLevel(Features, MMX, Enabled); 591 } else if (Name == "sse") { 592 setSSELevel(Features, SSE1, Enabled); 593 } else if (Name == "sse2") { 594 setSSELevel(Features, SSE2, Enabled); 595 } else if (Name == "sse3") { 596 setSSELevel(Features, SSE3, Enabled); 597 } else if (Name == "ssse3") { 598 setSSELevel(Features, SSSE3, Enabled); 599 } else if (Name == "sse4.2") { 600 setSSELevel(Features, SSE42, Enabled); 601 } else if (Name == "sse4.1") { 602 setSSELevel(Features, SSE41, Enabled); 603 } else if (Name == "3dnow") { 604 setMMXLevel(Features, AMD3DNow, Enabled); 605 } else if (Name == "3dnowa") { 606 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 607 } else if (Name == "aes") { 608 if (Enabled) 609 setSSELevel(Features, SSE2, Enabled); 610 else 611 Features["vaes"] = false; 612 } else if (Name == "vaes") { 613 if (Enabled) { 614 setSSELevel(Features, AVX, Enabled); 615 Features["aes"] = true; 616 } 617 } else if (Name == "pclmul") { 618 if (Enabled) 619 setSSELevel(Features, SSE2, Enabled); 620 else 621 Features["vpclmulqdq"] = false; 622 } else if (Name == "vpclmulqdq") { 623 if (Enabled) { 624 setSSELevel(Features, AVX, Enabled); 625 Features["pclmul"] = true; 626 } 627 } else if (Name == "gfni") { 628 if (Enabled) 629 setSSELevel(Features, SSE2, Enabled); 630 } else if (Name == "avx") { 631 setSSELevel(Features, AVX, Enabled); 632 } else if (Name == "avx2") { 633 setSSELevel(Features, AVX2, Enabled); 634 } else if (Name == "avx512f") { 635 setSSELevel(Features, AVX512F, Enabled); 636 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 637 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 638 Name == "avx512vbmi" || Name == "avx512ifma" || 639 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 640 Name == "avx512vnni" || Name == "avx512vbmi2") { 641 if (Enabled) 642 setSSELevel(Features, AVX512F, Enabled); 643 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 644 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 645 Features["avx512bw"] = true; 646 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 647 if (Name == "avx512bw" && !Enabled) 648 Features["avx512vbmi"] = Features["avx512vbmi2"] = 649 Features["avx512bitalg"] = false; 650 } else if (Name == "fma") { 651 if (Enabled) 652 setSSELevel(Features, AVX, Enabled); 653 else 654 setSSELevel(Features, AVX512F, Enabled); 655 } else if (Name == "fma4") { 656 setXOPLevel(Features, FMA4, Enabled); 657 } else if (Name == "xop") { 658 setXOPLevel(Features, XOP, Enabled); 659 } else if (Name == "sse4a") { 660 setXOPLevel(Features, SSE4A, Enabled); 661 } else if (Name == "f16c") { 662 if (Enabled) 663 setSSELevel(Features, AVX, Enabled); 664 else 665 setSSELevel(Features, AVX512F, Enabled); 666 } else if (Name == "sha") { 667 if (Enabled) 668 setSSELevel(Features, SSE2, Enabled); 669 } else if (Name == "sse4") { 670 // We can get here via the __target__ attribute since that's not controlled 671 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 672 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 673 // disabled. 674 if (Enabled) 675 setSSELevel(Features, SSE42, Enabled); 676 else 677 setSSELevel(Features, SSE41, Enabled); 678 } else if (Name == "xsave") { 679 if (!Enabled) 680 Features["xsaveopt"] = false; 681 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 682 if (Enabled) 683 Features["xsave"] = true; 684 } 685 } 686 687 /// handleTargetFeatures - Perform initialization based on the user 688 /// configured set of features. 689 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 690 DiagnosticsEngine &Diags) { 691 for (const auto &Feature : Features) { 692 if (Feature[0] != '+') 693 continue; 694 695 if (Feature == "+aes") { 696 HasAES = true; 697 } else if (Feature == "+vaes") { 698 HasVAES = true; 699 } else if (Feature == "+pclmul") { 700 HasPCLMUL = true; 701 } else if (Feature == "+vpclmulqdq") { 702 HasVPCLMULQDQ = true; 703 } else if (Feature == "+lzcnt") { 704 HasLZCNT = true; 705 } else if (Feature == "+rdrnd") { 706 HasRDRND = true; 707 } else if (Feature == "+fsgsbase") { 708 HasFSGSBASE = true; 709 } else if (Feature == "+bmi") { 710 HasBMI = true; 711 } else if (Feature == "+bmi2") { 712 HasBMI2 = true; 713 } else if (Feature == "+popcnt") { 714 HasPOPCNT = true; 715 } else if (Feature == "+rtm") { 716 HasRTM = true; 717 } else if (Feature == "+prfchw") { 718 HasPRFCHW = true; 719 } else if (Feature == "+rdseed") { 720 HasRDSEED = true; 721 } else if (Feature == "+adx") { 722 HasADX = true; 723 } else if (Feature == "+tbm") { 724 HasTBM = true; 725 } else if (Feature == "+lwp") { 726 HasLWP = true; 727 } else if (Feature == "+fma") { 728 HasFMA = true; 729 } else if (Feature == "+f16c") { 730 HasF16C = true; 731 } else if (Feature == "+gfni") { 732 HasGFNI = true; 733 } else if (Feature == "+avx512cd") { 734 HasAVX512CD = true; 735 } else if (Feature == "+avx512vpopcntdq") { 736 HasAVX512VPOPCNTDQ = true; 737 } else if (Feature == "+avx512vnni") { 738 HasAVX512VNNI = true; 739 } else if (Feature == "+avx512er") { 740 HasAVX512ER = true; 741 } else if (Feature == "+avx512pf") { 742 HasAVX512PF = true; 743 } else if (Feature == "+avx512dq") { 744 HasAVX512DQ = true; 745 } else if (Feature == "+avx512bitalg") { 746 HasAVX512BITALG = true; 747 } else if (Feature == "+avx512bw") { 748 HasAVX512BW = true; 749 } else if (Feature == "+avx512vl") { 750 HasAVX512VL = true; 751 } else if (Feature == "+avx512vbmi") { 752 HasAVX512VBMI = true; 753 } else if (Feature == "+avx512vbmi2") { 754 HasAVX512VBMI2 = true; 755 } else if (Feature == "+avx512ifma") { 756 HasAVX512IFMA = true; 757 } else if (Feature == "+sha") { 758 HasSHA = true; 759 } else if (Feature == "+mpx") { 760 HasMPX = true; 761 } else if (Feature == "+shstk") { 762 HasSHSTK = true; 763 } else if (Feature == "+movbe") { 764 HasMOVBE = true; 765 } else if (Feature == "+sgx") { 766 HasSGX = true; 767 } else if (Feature == "+cx16") { 768 HasCX16 = true; 769 } else if (Feature == "+fxsr") { 770 HasFXSR = true; 771 } else if (Feature == "+xsave") { 772 HasXSAVE = true; 773 } else if (Feature == "+xsaveopt") { 774 HasXSAVEOPT = true; 775 } else if (Feature == "+xsavec") { 776 HasXSAVEC = true; 777 } else if (Feature == "+xsaves") { 778 HasXSAVES = true; 779 } else if (Feature == "+mwaitx") { 780 HasMWAITX = true; 781 } else if (Feature == "+pku") { 782 HasPKU = true; 783 } else if (Feature == "+clflushopt") { 784 HasCLFLUSHOPT = true; 785 } else if (Feature == "+clwb") { 786 HasCLWB = true; 787 } else if (Feature == "+wbnoinvd") { 788 HasWBNOINVD = true; 789 } else if (Feature == "+prefetchwt1") { 790 HasPREFETCHWT1 = true; 791 } else if (Feature == "+clzero") { 792 HasCLZERO = true; 793 } else if (Feature == "+cldemote") { 794 HasCLDEMOTE = true; 795 } else if (Feature == "+rdpid") { 796 HasRDPID = true; 797 } else if (Feature == "+retpoline-external-thunk") { 798 HasRetpolineExternalThunk = true; 799 } else if (Feature == "+sahf") { 800 HasLAHFSAHF = true; 801 } else if (Feature == "+waitpkg") { 802 HasWAITPKG = true; 803 } else if (Feature == "+movdiri") { 804 HasMOVDIRI = true; 805 } else if (Feature == "+movdir64b") { 806 HasMOVDIR64B = true; 807 } else if (Feature == "+pconfig") { 808 HasPCONFIG = true; 809 } else if (Feature == "+ptwrite") { 810 HasPTWRITE = true; 811 } else if (Feature == "+invpcid") { 812 HasINVPCID = true; 813 } 814 815 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 816 .Case("+avx512f", AVX512F) 817 .Case("+avx2", AVX2) 818 .Case("+avx", AVX) 819 .Case("+sse4.2", SSE42) 820 .Case("+sse4.1", SSE41) 821 .Case("+ssse3", SSSE3) 822 .Case("+sse3", SSE3) 823 .Case("+sse2", SSE2) 824 .Case("+sse", SSE1) 825 .Default(NoSSE); 826 SSELevel = std::max(SSELevel, Level); 827 828 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 829 .Case("+3dnowa", AMD3DNowAthlon) 830 .Case("+3dnow", AMD3DNow) 831 .Case("+mmx", MMX) 832 .Default(NoMMX3DNow); 833 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 834 835 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 836 .Case("+xop", XOP) 837 .Case("+fma4", FMA4) 838 .Case("+sse4a", SSE4A) 839 .Default(NoXOP); 840 XOPLevel = std::max(XOPLevel, XLevel); 841 } 842 843 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 844 // matches the selected sse level. 845 if ((FPMath == FP_SSE && SSELevel < SSE1) || 846 (FPMath == FP_387 && SSELevel >= SSE1)) { 847 Diags.Report(diag::err_target_unsupported_fpmath) 848 << (FPMath == FP_SSE ? "sse" : "387"); 849 return false; 850 } 851 852 SimdDefaultAlign = 853 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 854 return true; 855 } 856 857 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 858 /// definitions for this particular subtarget. 859 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 860 MacroBuilder &Builder) const { 861 std::string CodeModel = getTargetOpts().CodeModel; 862 if (CodeModel == "default") 863 CodeModel = "small"; 864 Builder.defineMacro("__code_model_" + CodeModel + "_"); 865 866 // Target identification. 867 if (getTriple().getArch() == llvm::Triple::x86_64) { 868 Builder.defineMacro("__amd64__"); 869 Builder.defineMacro("__amd64"); 870 Builder.defineMacro("__x86_64"); 871 Builder.defineMacro("__x86_64__"); 872 if (getTriple().getArchName() == "x86_64h") { 873 Builder.defineMacro("__x86_64h"); 874 Builder.defineMacro("__x86_64h__"); 875 } 876 } else { 877 DefineStd(Builder, "i386", Opts); 878 } 879 880 // Subtarget options. 881 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 882 // truly should be based on -mtune options. 883 switch (CPU) { 884 case CK_Generic: 885 break; 886 case CK_i386: 887 // The rest are coming from the i386 define above. 888 Builder.defineMacro("__tune_i386__"); 889 break; 890 case CK_i486: 891 case CK_WinChipC6: 892 case CK_WinChip2: 893 case CK_C3: 894 defineCPUMacros(Builder, "i486"); 895 break; 896 case CK_PentiumMMX: 897 Builder.defineMacro("__pentium_mmx__"); 898 Builder.defineMacro("__tune_pentium_mmx__"); 899 LLVM_FALLTHROUGH; 900 case CK_i586: 901 case CK_Pentium: 902 defineCPUMacros(Builder, "i586"); 903 defineCPUMacros(Builder, "pentium"); 904 break; 905 case CK_Pentium3: 906 case CK_PentiumM: 907 Builder.defineMacro("__tune_pentium3__"); 908 LLVM_FALLTHROUGH; 909 case CK_Pentium2: 910 case CK_C3_2: 911 Builder.defineMacro("__tune_pentium2__"); 912 LLVM_FALLTHROUGH; 913 case CK_PentiumPro: 914 defineCPUMacros(Builder, "i686"); 915 defineCPUMacros(Builder, "pentiumpro"); 916 break; 917 case CK_Pentium4: 918 defineCPUMacros(Builder, "pentium4"); 919 break; 920 case CK_Yonah: 921 case CK_Prescott: 922 case CK_Nocona: 923 defineCPUMacros(Builder, "nocona"); 924 break; 925 case CK_Core2: 926 case CK_Penryn: 927 defineCPUMacros(Builder, "core2"); 928 break; 929 case CK_Bonnell: 930 defineCPUMacros(Builder, "atom"); 931 break; 932 case CK_Silvermont: 933 defineCPUMacros(Builder, "slm"); 934 break; 935 case CK_Goldmont: 936 defineCPUMacros(Builder, "goldmont"); 937 break; 938 case CK_GoldmontPlus: 939 defineCPUMacros(Builder, "goldmont_plus"); 940 break; 941 case CK_Tremont: 942 defineCPUMacros(Builder, "tremont"); 943 break; 944 case CK_Nehalem: 945 case CK_Westmere: 946 case CK_SandyBridge: 947 case CK_IvyBridge: 948 case CK_Haswell: 949 case CK_Broadwell: 950 case CK_SkylakeClient: 951 case CK_SkylakeServer: 952 case CK_Cannonlake: 953 case CK_IcelakeClient: 954 case CK_IcelakeServer: 955 // FIXME: Historically, we defined this legacy name, it would be nice to 956 // remove it at some point. We've never exposed fine-grained names for 957 // recent primary x86 CPUs, and we should keep it that way. 958 defineCPUMacros(Builder, "corei7"); 959 break; 960 case CK_KNL: 961 defineCPUMacros(Builder, "knl"); 962 break; 963 case CK_KNM: 964 break; 965 case CK_Lakemont: 966 defineCPUMacros(Builder, "i586", /*Tuning*/false); 967 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 968 Builder.defineMacro("__tune_lakemont__"); 969 break; 970 case CK_K6_2: 971 Builder.defineMacro("__k6_2__"); 972 Builder.defineMacro("__tune_k6_2__"); 973 LLVM_FALLTHROUGH; 974 case CK_K6_3: 975 if (CPU != CK_K6_2) { // In case of fallthrough 976 // FIXME: GCC may be enabling these in cases where some other k6 977 // architecture is specified but -m3dnow is explicitly provided. The 978 // exact semantics need to be determined and emulated here. 979 Builder.defineMacro("__k6_3__"); 980 Builder.defineMacro("__tune_k6_3__"); 981 } 982 LLVM_FALLTHROUGH; 983 case CK_K6: 984 defineCPUMacros(Builder, "k6"); 985 break; 986 case CK_Athlon: 987 case CK_AthlonXP: 988 defineCPUMacros(Builder, "athlon"); 989 if (SSELevel != NoSSE) { 990 Builder.defineMacro("__athlon_sse__"); 991 Builder.defineMacro("__tune_athlon_sse__"); 992 } 993 break; 994 case CK_K8: 995 case CK_K8SSE3: 996 case CK_x86_64: 997 defineCPUMacros(Builder, "k8"); 998 break; 999 case CK_AMDFAM10: 1000 defineCPUMacros(Builder, "amdfam10"); 1001 break; 1002 case CK_BTVER1: 1003 defineCPUMacros(Builder, "btver1"); 1004 break; 1005 case CK_BTVER2: 1006 defineCPUMacros(Builder, "btver2"); 1007 break; 1008 case CK_BDVER1: 1009 defineCPUMacros(Builder, "bdver1"); 1010 break; 1011 case CK_BDVER2: 1012 defineCPUMacros(Builder, "bdver2"); 1013 break; 1014 case CK_BDVER3: 1015 defineCPUMacros(Builder, "bdver3"); 1016 break; 1017 case CK_BDVER4: 1018 defineCPUMacros(Builder, "bdver4"); 1019 break; 1020 case CK_ZNVER1: 1021 defineCPUMacros(Builder, "znver1"); 1022 break; 1023 case CK_Geode: 1024 defineCPUMacros(Builder, "geode"); 1025 break; 1026 } 1027 1028 // Target properties. 1029 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1030 1031 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1032 // functions in glibc header files that use FP Stack inline asm which the 1033 // backend can't deal with (PR879). 1034 Builder.defineMacro("__NO_MATH_INLINES"); 1035 1036 if (HasAES) 1037 Builder.defineMacro("__AES__"); 1038 1039 if (HasVAES) 1040 Builder.defineMacro("__VAES__"); 1041 1042 if (HasPCLMUL) 1043 Builder.defineMacro("__PCLMUL__"); 1044 1045 if (HasVPCLMULQDQ) 1046 Builder.defineMacro("__VPCLMULQDQ__"); 1047 1048 if (HasLZCNT) 1049 Builder.defineMacro("__LZCNT__"); 1050 1051 if (HasRDRND) 1052 Builder.defineMacro("__RDRND__"); 1053 1054 if (HasFSGSBASE) 1055 Builder.defineMacro("__FSGSBASE__"); 1056 1057 if (HasBMI) 1058 Builder.defineMacro("__BMI__"); 1059 1060 if (HasBMI2) 1061 Builder.defineMacro("__BMI2__"); 1062 1063 if (HasPOPCNT) 1064 Builder.defineMacro("__POPCNT__"); 1065 1066 if (HasRTM) 1067 Builder.defineMacro("__RTM__"); 1068 1069 if (HasPRFCHW) 1070 Builder.defineMacro("__PRFCHW__"); 1071 1072 if (HasRDSEED) 1073 Builder.defineMacro("__RDSEED__"); 1074 1075 if (HasADX) 1076 Builder.defineMacro("__ADX__"); 1077 1078 if (HasTBM) 1079 Builder.defineMacro("__TBM__"); 1080 1081 if (HasLWP) 1082 Builder.defineMacro("__LWP__"); 1083 1084 if (HasMWAITX) 1085 Builder.defineMacro("__MWAITX__"); 1086 1087 if (HasMOVBE) 1088 Builder.defineMacro("__MOVBE__"); 1089 1090 switch (XOPLevel) { 1091 case XOP: 1092 Builder.defineMacro("__XOP__"); 1093 LLVM_FALLTHROUGH; 1094 case FMA4: 1095 Builder.defineMacro("__FMA4__"); 1096 LLVM_FALLTHROUGH; 1097 case SSE4A: 1098 Builder.defineMacro("__SSE4A__"); 1099 LLVM_FALLTHROUGH; 1100 case NoXOP: 1101 break; 1102 } 1103 1104 if (HasFMA) 1105 Builder.defineMacro("__FMA__"); 1106 1107 if (HasF16C) 1108 Builder.defineMacro("__F16C__"); 1109 1110 if (HasGFNI) 1111 Builder.defineMacro("__GFNI__"); 1112 1113 if (HasAVX512CD) 1114 Builder.defineMacro("__AVX512CD__"); 1115 if (HasAVX512VPOPCNTDQ) 1116 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1117 if (HasAVX512VNNI) 1118 Builder.defineMacro("__AVX512VNNI__"); 1119 if (HasAVX512ER) 1120 Builder.defineMacro("__AVX512ER__"); 1121 if (HasAVX512PF) 1122 Builder.defineMacro("__AVX512PF__"); 1123 if (HasAVX512DQ) 1124 Builder.defineMacro("__AVX512DQ__"); 1125 if (HasAVX512BITALG) 1126 Builder.defineMacro("__AVX512BITALG__"); 1127 if (HasAVX512BW) 1128 Builder.defineMacro("__AVX512BW__"); 1129 if (HasAVX512VL) 1130 Builder.defineMacro("__AVX512VL__"); 1131 if (HasAVX512VBMI) 1132 Builder.defineMacro("__AVX512VBMI__"); 1133 if (HasAVX512VBMI2) 1134 Builder.defineMacro("__AVX512VBMI2__"); 1135 if (HasAVX512IFMA) 1136 Builder.defineMacro("__AVX512IFMA__"); 1137 1138 if (HasSHA) 1139 Builder.defineMacro("__SHA__"); 1140 1141 if (HasFXSR) 1142 Builder.defineMacro("__FXSR__"); 1143 if (HasXSAVE) 1144 Builder.defineMacro("__XSAVE__"); 1145 if (HasXSAVEOPT) 1146 Builder.defineMacro("__XSAVEOPT__"); 1147 if (HasXSAVEC) 1148 Builder.defineMacro("__XSAVEC__"); 1149 if (HasXSAVES) 1150 Builder.defineMacro("__XSAVES__"); 1151 if (HasPKU) 1152 Builder.defineMacro("__PKU__"); 1153 if (HasCLFLUSHOPT) 1154 Builder.defineMacro("__CLFLUSHOPT__"); 1155 if (HasCLWB) 1156 Builder.defineMacro("__CLWB__"); 1157 if (HasWBNOINVD) 1158 Builder.defineMacro("__WBNOINVD__"); 1159 if (HasMPX) 1160 Builder.defineMacro("__MPX__"); 1161 if (HasSHSTK) 1162 Builder.defineMacro("__SHSTK__"); 1163 if (HasSGX) 1164 Builder.defineMacro("__SGX__"); 1165 if (HasPREFETCHWT1) 1166 Builder.defineMacro("__PREFETCHWT1__"); 1167 if (HasCLZERO) 1168 Builder.defineMacro("__CLZERO__"); 1169 if (HasRDPID) 1170 Builder.defineMacro("__RDPID__"); 1171 if (HasCLDEMOTE) 1172 Builder.defineMacro("__CLDEMOTE__"); 1173 if (HasWAITPKG) 1174 Builder.defineMacro("__WAITPKG__"); 1175 if (HasMOVDIRI) 1176 Builder.defineMacro("__MOVDIRI__"); 1177 if (HasMOVDIR64B) 1178 Builder.defineMacro("__MOVDIR64B__"); 1179 if (HasPCONFIG) 1180 Builder.defineMacro("__PCONFIG__"); 1181 if (HasPTWRITE) 1182 Builder.defineMacro("__PTWRITE__"); 1183 if (HasINVPCID) 1184 Builder.defineMacro("__INVPCID__"); 1185 1186 // Each case falls through to the previous one here. 1187 switch (SSELevel) { 1188 case AVX512F: 1189 Builder.defineMacro("__AVX512F__"); 1190 LLVM_FALLTHROUGH; 1191 case AVX2: 1192 Builder.defineMacro("__AVX2__"); 1193 LLVM_FALLTHROUGH; 1194 case AVX: 1195 Builder.defineMacro("__AVX__"); 1196 LLVM_FALLTHROUGH; 1197 case SSE42: 1198 Builder.defineMacro("__SSE4_2__"); 1199 LLVM_FALLTHROUGH; 1200 case SSE41: 1201 Builder.defineMacro("__SSE4_1__"); 1202 LLVM_FALLTHROUGH; 1203 case SSSE3: 1204 Builder.defineMacro("__SSSE3__"); 1205 LLVM_FALLTHROUGH; 1206 case SSE3: 1207 Builder.defineMacro("__SSE3__"); 1208 LLVM_FALLTHROUGH; 1209 case SSE2: 1210 Builder.defineMacro("__SSE2__"); 1211 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1212 LLVM_FALLTHROUGH; 1213 case SSE1: 1214 Builder.defineMacro("__SSE__"); 1215 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1216 LLVM_FALLTHROUGH; 1217 case NoSSE: 1218 break; 1219 } 1220 1221 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1222 switch (SSELevel) { 1223 case AVX512F: 1224 case AVX2: 1225 case AVX: 1226 case SSE42: 1227 case SSE41: 1228 case SSSE3: 1229 case SSE3: 1230 case SSE2: 1231 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1232 break; 1233 case SSE1: 1234 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1235 break; 1236 default: 1237 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1238 break; 1239 } 1240 } 1241 1242 // Each case falls through to the previous one here. 1243 switch (MMX3DNowLevel) { 1244 case AMD3DNowAthlon: 1245 Builder.defineMacro("__3dNOW_A__"); 1246 LLVM_FALLTHROUGH; 1247 case AMD3DNow: 1248 Builder.defineMacro("__3dNOW__"); 1249 LLVM_FALLTHROUGH; 1250 case MMX: 1251 Builder.defineMacro("__MMX__"); 1252 LLVM_FALLTHROUGH; 1253 case NoMMX3DNow: 1254 break; 1255 } 1256 1257 if (CPU >= CK_i486) { 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1259 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1260 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1261 } 1262 if (CPU >= CK_i586) 1263 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1264 if (HasCX16) 1265 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1266 1267 if (HasFloat128) 1268 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1269 } 1270 1271 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1272 return llvm::StringSwitch<bool>(Name) 1273 .Case("3dnow", true) 1274 .Case("3dnowa", true) 1275 .Case("adx", true) 1276 .Case("aes", true) 1277 .Case("avx", true) 1278 .Case("avx2", true) 1279 .Case("avx512f", true) 1280 .Case("avx512cd", true) 1281 .Case("avx512vpopcntdq", true) 1282 .Case("avx512vnni", true) 1283 .Case("avx512er", true) 1284 .Case("avx512pf", true) 1285 .Case("avx512dq", true) 1286 .Case("avx512bitalg", true) 1287 .Case("avx512bw", true) 1288 .Case("avx512vl", true) 1289 .Case("avx512vbmi", true) 1290 .Case("avx512vbmi2", true) 1291 .Case("avx512ifma", true) 1292 .Case("bmi", true) 1293 .Case("bmi2", true) 1294 .Case("cldemote", true) 1295 .Case("clflushopt", true) 1296 .Case("clwb", true) 1297 .Case("clzero", true) 1298 .Case("cx16", true) 1299 .Case("f16c", true) 1300 .Case("fma", true) 1301 .Case("fma4", true) 1302 .Case("fsgsbase", true) 1303 .Case("fxsr", true) 1304 .Case("gfni", true) 1305 .Case("invpcid", true) 1306 .Case("lwp", true) 1307 .Case("lzcnt", true) 1308 .Case("mmx", true) 1309 .Case("movbe", true) 1310 .Case("movdiri", true) 1311 .Case("movdir64b", true) 1312 .Case("mpx", true) 1313 .Case("mwaitx", true) 1314 .Case("pclmul", true) 1315 .Case("pconfig", true) 1316 .Case("pku", true) 1317 .Case("popcnt", true) 1318 .Case("prefetchwt1", true) 1319 .Case("prfchw", true) 1320 .Case("ptwrite", true) 1321 .Case("rdpid", true) 1322 .Case("rdrnd", true) 1323 .Case("rdseed", true) 1324 .Case("rtm", true) 1325 .Case("sahf", true) 1326 .Case("sgx", true) 1327 .Case("sha", true) 1328 .Case("shstk", true) 1329 .Case("sse", true) 1330 .Case("sse2", true) 1331 .Case("sse3", true) 1332 .Case("ssse3", true) 1333 .Case("sse4", true) 1334 .Case("sse4.1", true) 1335 .Case("sse4.2", true) 1336 .Case("sse4a", true) 1337 .Case("tbm", true) 1338 .Case("vaes", true) 1339 .Case("vpclmulqdq", true) 1340 .Case("wbnoinvd", true) 1341 .Case("waitpkg", true) 1342 .Case("x87", true) 1343 .Case("xop", true) 1344 .Case("xsave", true) 1345 .Case("xsavec", true) 1346 .Case("xsaves", true) 1347 .Case("xsaveopt", true) 1348 .Default(false); 1349 } 1350 1351 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1352 return llvm::StringSwitch<bool>(Feature) 1353 .Case("adx", HasADX) 1354 .Case("aes", HasAES) 1355 .Case("avx", SSELevel >= AVX) 1356 .Case("avx2", SSELevel >= AVX2) 1357 .Case("avx512f", SSELevel >= AVX512F) 1358 .Case("avx512cd", HasAVX512CD) 1359 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1360 .Case("avx512vnni", HasAVX512VNNI) 1361 .Case("avx512er", HasAVX512ER) 1362 .Case("avx512pf", HasAVX512PF) 1363 .Case("avx512dq", HasAVX512DQ) 1364 .Case("avx512bitalg", HasAVX512BITALG) 1365 .Case("avx512bw", HasAVX512BW) 1366 .Case("avx512vl", HasAVX512VL) 1367 .Case("avx512vbmi", HasAVX512VBMI) 1368 .Case("avx512vbmi2", HasAVX512VBMI2) 1369 .Case("avx512ifma", HasAVX512IFMA) 1370 .Case("bmi", HasBMI) 1371 .Case("bmi2", HasBMI2) 1372 .Case("cldemote", HasCLDEMOTE) 1373 .Case("clflushopt", HasCLFLUSHOPT) 1374 .Case("clwb", HasCLWB) 1375 .Case("clzero", HasCLZERO) 1376 .Case("cx16", HasCX16) 1377 .Case("f16c", HasF16C) 1378 .Case("fma", HasFMA) 1379 .Case("fma4", XOPLevel >= FMA4) 1380 .Case("fsgsbase", HasFSGSBASE) 1381 .Case("fxsr", HasFXSR) 1382 .Case("gfni", HasGFNI) 1383 .Case("invpcid", HasINVPCID) 1384 .Case("lwp", HasLWP) 1385 .Case("lzcnt", HasLZCNT) 1386 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1387 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1388 .Case("mmx", MMX3DNowLevel >= MMX) 1389 .Case("movbe", HasMOVBE) 1390 .Case("movdiri", HasMOVDIRI) 1391 .Case("movdir64b", HasMOVDIR64B) 1392 .Case("mpx", HasMPX) 1393 .Case("mwaitx", HasMWAITX) 1394 .Case("pclmul", HasPCLMUL) 1395 .Case("pconfig", HasPCONFIG) 1396 .Case("pku", HasPKU) 1397 .Case("popcnt", HasPOPCNT) 1398 .Case("prefetchwt1", HasPREFETCHWT1) 1399 .Case("prfchw", HasPRFCHW) 1400 .Case("ptwrite", HasPTWRITE) 1401 .Case("rdpid", HasRDPID) 1402 .Case("rdrnd", HasRDRND) 1403 .Case("rdseed", HasRDSEED) 1404 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1405 .Case("rtm", HasRTM) 1406 .Case("sahf", HasLAHFSAHF) 1407 .Case("sgx", HasSGX) 1408 .Case("sha", HasSHA) 1409 .Case("shstk", HasSHSTK) 1410 .Case("sse", SSELevel >= SSE1) 1411 .Case("sse2", SSELevel >= SSE2) 1412 .Case("sse3", SSELevel >= SSE3) 1413 .Case("ssse3", SSELevel >= SSSE3) 1414 .Case("sse4.1", SSELevel >= SSE41) 1415 .Case("sse4.2", SSELevel >= SSE42) 1416 .Case("sse4a", XOPLevel >= SSE4A) 1417 .Case("tbm", HasTBM) 1418 .Case("vaes", HasVAES) 1419 .Case("vpclmulqdq", HasVPCLMULQDQ) 1420 .Case("wbnoinvd", HasWBNOINVD) 1421 .Case("waitpkg", HasWAITPKG) 1422 .Case("x86", true) 1423 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1424 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1425 .Case("xop", XOPLevel >= XOP) 1426 .Case("xsave", HasXSAVE) 1427 .Case("xsavec", HasXSAVEC) 1428 .Case("xsaves", HasXSAVES) 1429 .Case("xsaveopt", HasXSAVEOPT) 1430 .Default(false); 1431 } 1432 1433 // We can't use a generic validation scheme for the features accepted here 1434 // versus subtarget features accepted in the target attribute because the 1435 // bitfield structure that's initialized in the runtime only supports the 1436 // below currently rather than the full range of subtarget features. (See 1437 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1438 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1439 return llvm::StringSwitch<bool>(FeatureStr) 1440 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1441 #include "llvm/Support/X86TargetParser.def" 1442 .Default(false); 1443 } 1444 1445 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1446 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1447 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1448 #include "llvm/Support/X86TargetParser.def" 1449 ; 1450 // Note, this function should only be used after ensuring the value is 1451 // correct, so it asserts if the value is out of range. 1452 } 1453 1454 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1455 enum class FeatPriority { 1456 #define FEATURE(FEAT) FEAT, 1457 #include "clang/Basic/X86Target.def" 1458 }; 1459 switch (Feat) { 1460 #define FEATURE(FEAT) \ 1461 case llvm::X86::FEAT: \ 1462 return static_cast<unsigned>(FeatPriority::FEAT); 1463 #include "clang/Basic/X86Target.def" 1464 default: 1465 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1466 } 1467 } 1468 1469 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1470 // Valid CPUs have a 'key feature' that compares just better than its key 1471 // feature. 1472 CPUKind Kind = getCPUKind(Name); 1473 if (Kind != CK_Generic) { 1474 switch (Kind) { 1475 default: 1476 llvm_unreachable( 1477 "CPU Type without a key feature used in 'target' attribute"); 1478 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1479 case CK_##ENUM: \ 1480 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1481 #include "clang/Basic/X86Target.def" 1482 } 1483 } 1484 1485 // Now we know we have a feature, so get its priority and shift it a few so 1486 // that we have sufficient room for the CPUs (above). 1487 return getFeaturePriority(getFeature(Name)) << 1; 1488 } 1489 1490 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1491 return llvm::StringSwitch<bool>(Name) 1492 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1493 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1494 #include "clang/Basic/X86Target.def" 1495 .Default(false); 1496 } 1497 1498 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1499 return llvm::StringSwitch<StringRef>(Name) 1500 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1501 #include "clang/Basic/X86Target.def" 1502 .Default(Name); 1503 } 1504 1505 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1506 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1507 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1508 #include "clang/Basic/X86Target.def" 1509 .Default(0); 1510 } 1511 1512 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1513 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1514 StringRef WholeList = 1515 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1516 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1517 #include "clang/Basic/X86Target.def" 1518 .Default(""); 1519 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1520 } 1521 1522 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1523 switch (Kind) { 1524 case CK_Generic: 1525 return ""; 1526 #define PROC(ENUM, STRING, IS64BIT) \ 1527 case CK_##ENUM: \ 1528 return STRING; 1529 #include "clang/Basic/X86Target.def" 1530 } 1531 llvm_unreachable("Invalid CPUKind"); 1532 } 1533 1534 // We can't use a generic validation scheme for the cpus accepted here 1535 // versus subtarget cpus accepted in the target attribute because the 1536 // variables intitialized by the runtime only support the below currently 1537 // rather than the full range of cpus. 1538 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1539 return llvm::StringSwitch<bool>(FeatureStr) 1540 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1541 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1542 .Cases(STR, ALIAS, true) 1543 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1544 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1545 #include "llvm/Support/X86TargetParser.def" 1546 .Default(false); 1547 } 1548 1549 bool X86TargetInfo::validateAsmConstraint( 1550 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1551 switch (*Name) { 1552 default: 1553 return false; 1554 // Constant constraints. 1555 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1556 // instructions. 1557 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1558 // x86_64 instructions. 1559 case 's': 1560 Info.setRequiresImmediate(); 1561 return true; 1562 case 'I': 1563 Info.setRequiresImmediate(0, 31); 1564 return true; 1565 case 'J': 1566 Info.setRequiresImmediate(0, 63); 1567 return true; 1568 case 'K': 1569 Info.setRequiresImmediate(-128, 127); 1570 return true; 1571 case 'L': 1572 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1573 return true; 1574 case 'M': 1575 Info.setRequiresImmediate(0, 3); 1576 return true; 1577 case 'N': 1578 Info.setRequiresImmediate(0, 255); 1579 return true; 1580 case 'O': 1581 Info.setRequiresImmediate(0, 127); 1582 return true; 1583 // Register constraints. 1584 case 'Y': // 'Y' is the first character for several 2-character constraints. 1585 // Shift the pointer to the second character of the constraint. 1586 Name++; 1587 switch (*Name) { 1588 default: 1589 return false; 1590 case 'z': 1591 case '0': // First SSE register. 1592 case '2': 1593 case 't': // Any SSE register, when SSE2 is enabled. 1594 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1595 case 'm': // Any MMX register, when inter-unit moves enabled. 1596 case 'k': // AVX512 arch mask registers: k1-k7. 1597 Info.setAllowsRegister(); 1598 return true; 1599 } 1600 case 'f': // Any x87 floating point stack register. 1601 // Constraint 'f' cannot be used for output operands. 1602 if (Info.ConstraintStr[0] == '=') 1603 return false; 1604 Info.setAllowsRegister(); 1605 return true; 1606 case 'a': // eax. 1607 case 'b': // ebx. 1608 case 'c': // ecx. 1609 case 'd': // edx. 1610 case 'S': // esi. 1611 case 'D': // edi. 1612 case 'A': // edx:eax. 1613 case 't': // Top of floating point stack. 1614 case 'u': // Second from top of floating point stack. 1615 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1616 case 'y': // Any MMX register. 1617 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1618 case 'x': // Any SSE register. 1619 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1620 // for intermideate k reg operations). 1621 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1622 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1623 case 'l': // "Index" registers: any general register that can be used as an 1624 // index in a base+index memory access. 1625 Info.setAllowsRegister(); 1626 return true; 1627 // Floating point constant constraints. 1628 case 'C': // SSE floating point constant. 1629 case 'G': // x87 floating point constant. 1630 return true; 1631 } 1632 } 1633 1634 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1635 unsigned Size) const { 1636 // Strip off constraint modifiers. 1637 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1638 Constraint = Constraint.substr(1); 1639 1640 return validateOperandSize(Constraint, Size); 1641 } 1642 1643 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1644 unsigned Size) const { 1645 return validateOperandSize(Constraint, Size); 1646 } 1647 1648 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1649 unsigned Size) const { 1650 switch (Constraint[0]) { 1651 default: 1652 break; 1653 case 'k': 1654 // Registers k0-k7 (AVX512) size limit is 64 bit. 1655 case 'y': 1656 return Size <= 64; 1657 case 'f': 1658 case 't': 1659 case 'u': 1660 return Size <= 128; 1661 case 'Y': 1662 // 'Y' is the first character for several 2-character constraints. 1663 switch (Constraint[1]) { 1664 default: 1665 return false; 1666 case 'm': 1667 // 'Ym' is synonymous with 'y'. 1668 case 'k': 1669 return Size <= 64; 1670 case 'z': 1671 case '0': 1672 // XMM0 1673 if (SSELevel >= SSE1) 1674 return Size <= 128U; 1675 return false; 1676 case 'i': 1677 case 't': 1678 case '2': 1679 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1680 if (SSELevel < SSE2) 1681 return false; 1682 break; 1683 } 1684 case 'v': 1685 case 'x': 1686 if (SSELevel >= AVX512F) 1687 // 512-bit zmm registers can be used if target supports AVX512F. 1688 return Size <= 512U; 1689 else if (SSELevel >= AVX) 1690 // 256-bit ymm registers can be used if target supports AVX. 1691 return Size <= 256U; 1692 return Size <= 128U; 1693 1694 } 1695 1696 return true; 1697 } 1698 1699 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1700 switch (*Constraint) { 1701 case 'a': 1702 return std::string("{ax}"); 1703 case 'b': 1704 return std::string("{bx}"); 1705 case 'c': 1706 return std::string("{cx}"); 1707 case 'd': 1708 return std::string("{dx}"); 1709 case 'S': 1710 return std::string("{si}"); 1711 case 'D': 1712 return std::string("{di}"); 1713 case 'p': // address 1714 return std::string("im"); 1715 case 't': // top of floating point stack. 1716 return std::string("{st}"); 1717 case 'u': // second from top of floating point stack. 1718 return std::string("{st(1)}"); // second from top of floating point stack. 1719 case 'Y': 1720 switch (Constraint[1]) { 1721 default: 1722 // Break from inner switch and fall through (copy single char), 1723 // continue parsing after copying the current constraint into 1724 // the return string. 1725 break; 1726 case 'k': 1727 case 'm': 1728 case 'i': 1729 case 't': 1730 case 'z': 1731 case '0': 1732 case '2': 1733 // "^" hints llvm that this is a 2 letter constraint. 1734 // "Constraint++" is used to promote the string iterator 1735 // to the next constraint. 1736 return std::string("^") + std::string(Constraint++, 2); 1737 } 1738 LLVM_FALLTHROUGH; 1739 default: 1740 return std::string(1, *Constraint); 1741 } 1742 } 1743 1744 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1745 // Perform any per-CPU checks necessary to determine if this CPU is 1746 // acceptable. 1747 switch (Kind) { 1748 case CK_Generic: 1749 // No processor selected! 1750 return false; 1751 #define PROC(ENUM, STRING, IS64BIT) \ 1752 case CK_##ENUM: \ 1753 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1754 #include "clang/Basic/X86Target.def" 1755 } 1756 llvm_unreachable("Unhandled CPU kind"); 1757 } 1758 1759 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1760 #define PROC(ENUM, STRING, IS64BIT) \ 1761 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1762 Values.emplace_back(STRING); 1763 // Go through CPUKind checking to ensure that the alias is de-aliased and 1764 // 64 bit-ness is checked. 1765 #define PROC_ALIAS(ENUM, ALIAS) \ 1766 if (checkCPUKind(getCPUKind(ALIAS))) \ 1767 Values.emplace_back(ALIAS); 1768 #include "clang/Basic/X86Target.def" 1769 } 1770 1771 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1772 return llvm::StringSwitch<CPUKind>(CPU) 1773 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1774 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1775 #include "clang/Basic/X86Target.def" 1776 .Default(CK_Generic); 1777 } 1778 1779 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1780 return llvm::makeArrayRef(GCCRegNames); 1781 } 1782 1783 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1784 return llvm::makeArrayRef(AddlRegNames); 1785 } 1786 1787 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1788 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1789 Builtin::FirstTSBuiltin + 1); 1790 } 1791 1792 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1793 return llvm::makeArrayRef(BuiltinInfoX86, 1794 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1795 } 1796