1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 "bnd0", "bnd1", "bnd2", "bnd3", 64 }; 65 66 const TargetInfo::AddlRegName AddlRegNames[] = { 67 {{"al", "ah", "eax", "rax"}, 0}, 68 {{"bl", "bh", "ebx", "rbx"}, 3}, 69 {{"cl", "ch", "ecx", "rcx"}, 2}, 70 {{"dl", "dh", "edx", "rdx"}, 1}, 71 {{"esi", "rsi"}, 4}, 72 {{"edi", "rdi"}, 5}, 73 {{"esp", "rsp"}, 7}, 74 {{"ebp", "rbp"}, 6}, 75 {{"r8d", "r8w", "r8b"}, 38}, 76 {{"r9d", "r9w", "r9b"}, 39}, 77 {{"r10d", "r10w", "r10b"}, 40}, 78 {{"r11d", "r11w", "r11b"}, 41}, 79 {{"r12d", "r12w", "r12b"}, 42}, 80 {{"r13d", "r13w", "r13b"}, 43}, 81 {{"r14d", "r14w", "r14b"}, 44}, 82 {{"r15d", "r15w", "r15b"}, 45}, 83 }; 84 85 } // namespace targets 86 } // namespace clang 87 88 using namespace clang; 89 using namespace clang::targets; 90 91 bool X86TargetInfo::setFPMath(StringRef Name) { 92 if (Name == "387") { 93 FPMath = FP_387; 94 return true; 95 } 96 if (Name == "sse") { 97 FPMath = FP_SSE; 98 return true; 99 } 100 return false; 101 } 102 103 bool X86TargetInfo::initFeatureMap( 104 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 105 const std::vector<std::string> &FeaturesVec) const { 106 // FIXME: This *really* should not be here. 107 // X86_64 always has SSE2. 108 if (getTriple().getArch() == llvm::Triple::x86_64) 109 setFeatureEnabledImpl(Features, "sse2", true); 110 111 const CPUKind Kind = getCPUKind(CPU); 112 113 // Enable X87 for all X86 processors but Lakemont. 114 if (Kind != CK_Lakemont) 115 setFeatureEnabledImpl(Features, "x87", true); 116 117 switch (Kind) { 118 case CK_Generic: 119 case CK_i386: 120 case CK_i486: 121 case CK_i586: 122 case CK_Pentium: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 127 case CK_PentiumMMX: 128 case CK_Pentium2: 129 case CK_K6: 130 case CK_WinChipC6: 131 setFeatureEnabledImpl(Features, "mmx", true); 132 break; 133 134 case CK_Icelake: 135 setFeatureEnabledImpl(Features, "vaes", true); 136 setFeatureEnabledImpl(Features, "gfni", true); 137 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 138 setFeatureEnabledImpl(Features, "avx512bitalg", true); 139 setFeatureEnabledImpl(Features, "avx512vnni", true); 140 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 141 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 142 LLVM_FALLTHROUGH; 143 case CK_Cannonlake: 144 setFeatureEnabledImpl(Features, "avx512ifma", true); 145 setFeatureEnabledImpl(Features, "avx512vbmi", true); 146 setFeatureEnabledImpl(Features, "sha", true); 147 LLVM_FALLTHROUGH; 148 case CK_SkylakeServer: 149 setFeatureEnabledImpl(Features, "avx512f", true); 150 setFeatureEnabledImpl(Features, "avx512cd", true); 151 setFeatureEnabledImpl(Features, "avx512dq", true); 152 setFeatureEnabledImpl(Features, "avx512bw", true); 153 setFeatureEnabledImpl(Features, "avx512vl", true); 154 setFeatureEnabledImpl(Features, "pku", true); 155 setFeatureEnabledImpl(Features, "clwb", true); 156 LLVM_FALLTHROUGH; 157 case CK_SkylakeClient: 158 setFeatureEnabledImpl(Features, "xsavec", true); 159 setFeatureEnabledImpl(Features, "xsaves", true); 160 setFeatureEnabledImpl(Features, "mpx", true); 161 setFeatureEnabledImpl(Features, "sgx", true); 162 setFeatureEnabledImpl(Features, "clflushopt", true); 163 setFeatureEnabledImpl(Features, "rtm", true); 164 LLVM_FALLTHROUGH; 165 case CK_Broadwell: 166 setFeatureEnabledImpl(Features, "rdseed", true); 167 setFeatureEnabledImpl(Features, "adx", true); 168 setFeatureEnabledImpl(Features, "prfchw", true); 169 LLVM_FALLTHROUGH; 170 case CK_Haswell: 171 setFeatureEnabledImpl(Features, "avx2", true); 172 setFeatureEnabledImpl(Features, "lzcnt", true); 173 setFeatureEnabledImpl(Features, "bmi", true); 174 setFeatureEnabledImpl(Features, "bmi2", true); 175 setFeatureEnabledImpl(Features, "fma", true); 176 setFeatureEnabledImpl(Features, "movbe", true); 177 LLVM_FALLTHROUGH; 178 case CK_IvyBridge: 179 setFeatureEnabledImpl(Features, "rdrnd", true); 180 setFeatureEnabledImpl(Features, "f16c", true); 181 setFeatureEnabledImpl(Features, "fsgsbase", true); 182 LLVM_FALLTHROUGH; 183 case CK_SandyBridge: 184 setFeatureEnabledImpl(Features, "avx", true); 185 setFeatureEnabledImpl(Features, "xsave", true); 186 setFeatureEnabledImpl(Features, "xsaveopt", true); 187 LLVM_FALLTHROUGH; 188 case CK_Westmere: 189 setFeatureEnabledImpl(Features, "aes", true); 190 setFeatureEnabledImpl(Features, "pclmul", true); 191 LLVM_FALLTHROUGH; 192 case CK_Nehalem: 193 setFeatureEnabledImpl(Features, "sse4.2", true); 194 LLVM_FALLTHROUGH; 195 case CK_Penryn: 196 setFeatureEnabledImpl(Features, "sse4.1", true); 197 LLVM_FALLTHROUGH; 198 case CK_Core2: 199 setFeatureEnabledImpl(Features, "ssse3", true); 200 LLVM_FALLTHROUGH; 201 case CK_Yonah: 202 case CK_Prescott: 203 case CK_Nocona: 204 setFeatureEnabledImpl(Features, "sse3", true); 205 setFeatureEnabledImpl(Features, "cx16", true); 206 LLVM_FALLTHROUGH; 207 case CK_PentiumM: 208 case CK_Pentium4: 209 case CK_x86_64: 210 setFeatureEnabledImpl(Features, "sse2", true); 211 LLVM_FALLTHROUGH; 212 case CK_Pentium3: 213 case CK_C3_2: 214 setFeatureEnabledImpl(Features, "sse", true); 215 setFeatureEnabledImpl(Features, "fxsr", true); 216 break; 217 218 case CK_Goldmont: 219 setFeatureEnabledImpl(Features, "sha", true); 220 setFeatureEnabledImpl(Features, "rdrnd", true); 221 setFeatureEnabledImpl(Features, "rdseed", true); 222 setFeatureEnabledImpl(Features, "xsave", true); 223 setFeatureEnabledImpl(Features, "xsaveopt", true); 224 setFeatureEnabledImpl(Features, "xsavec", true); 225 setFeatureEnabledImpl(Features, "xsaves", true); 226 setFeatureEnabledImpl(Features, "clflushopt", true); 227 setFeatureEnabledImpl(Features, "mpx", true); 228 setFeatureEnabledImpl(Features, "fsgsbase", true); 229 LLVM_FALLTHROUGH; 230 case CK_Silvermont: 231 setFeatureEnabledImpl(Features, "aes", true); 232 setFeatureEnabledImpl(Features, "pclmul", true); 233 setFeatureEnabledImpl(Features, "sse4.2", true); 234 setFeatureEnabledImpl(Features, "prfchw", true); 235 LLVM_FALLTHROUGH; 236 case CK_Bonnell: 237 setFeatureEnabledImpl(Features, "movbe", true); 238 setFeatureEnabledImpl(Features, "ssse3", true); 239 setFeatureEnabledImpl(Features, "fxsr", true); 240 setFeatureEnabledImpl(Features, "cx16", true); 241 break; 242 243 case CK_KNM: 244 // TODO: Add avx5124fmaps/avx5124vnniw. 245 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 246 LLVM_FALLTHROUGH; 247 case CK_KNL: 248 setFeatureEnabledImpl(Features, "avx512f", true); 249 setFeatureEnabledImpl(Features, "avx512cd", true); 250 setFeatureEnabledImpl(Features, "avx512er", true); 251 setFeatureEnabledImpl(Features, "avx512pf", true); 252 setFeatureEnabledImpl(Features, "prfchw", true); 253 setFeatureEnabledImpl(Features, "prefetchwt1", true); 254 setFeatureEnabledImpl(Features, "fxsr", true); 255 setFeatureEnabledImpl(Features, "rdseed", true); 256 setFeatureEnabledImpl(Features, "adx", true); 257 setFeatureEnabledImpl(Features, "lzcnt", true); 258 setFeatureEnabledImpl(Features, "bmi", true); 259 setFeatureEnabledImpl(Features, "bmi2", true); 260 setFeatureEnabledImpl(Features, "rtm", true); 261 setFeatureEnabledImpl(Features, "fma", true); 262 setFeatureEnabledImpl(Features, "rdrnd", true); 263 setFeatureEnabledImpl(Features, "f16c", true); 264 setFeatureEnabledImpl(Features, "fsgsbase", true); 265 setFeatureEnabledImpl(Features, "aes", true); 266 setFeatureEnabledImpl(Features, "pclmul", true); 267 setFeatureEnabledImpl(Features, "cx16", true); 268 setFeatureEnabledImpl(Features, "xsaveopt", true); 269 setFeatureEnabledImpl(Features, "xsave", true); 270 setFeatureEnabledImpl(Features, "movbe", true); 271 break; 272 273 case CK_K6_2: 274 case CK_K6_3: 275 case CK_WinChip2: 276 case CK_C3: 277 setFeatureEnabledImpl(Features, "3dnow", true); 278 break; 279 280 case CK_AMDFAM10: 281 setFeatureEnabledImpl(Features, "sse4a", true); 282 setFeatureEnabledImpl(Features, "lzcnt", true); 283 setFeatureEnabledImpl(Features, "popcnt", true); 284 LLVM_FALLTHROUGH; 285 case CK_K8SSE3: 286 setFeatureEnabledImpl(Features, "sse3", true); 287 LLVM_FALLTHROUGH; 288 case CK_K8: 289 setFeatureEnabledImpl(Features, "sse2", true); 290 LLVM_FALLTHROUGH; 291 case CK_AthlonXP: 292 setFeatureEnabledImpl(Features, "sse", true); 293 setFeatureEnabledImpl(Features, "fxsr", true); 294 LLVM_FALLTHROUGH; 295 case CK_Athlon: 296 case CK_Geode: 297 setFeatureEnabledImpl(Features, "3dnowa", true); 298 break; 299 300 case CK_BTVER2: 301 setFeatureEnabledImpl(Features, "avx", true); 302 setFeatureEnabledImpl(Features, "aes", true); 303 setFeatureEnabledImpl(Features, "pclmul", true); 304 setFeatureEnabledImpl(Features, "bmi", true); 305 setFeatureEnabledImpl(Features, "f16c", true); 306 setFeatureEnabledImpl(Features, "xsaveopt", true); 307 setFeatureEnabledImpl(Features, "movbe", true); 308 LLVM_FALLTHROUGH; 309 case CK_BTVER1: 310 setFeatureEnabledImpl(Features, "ssse3", true); 311 setFeatureEnabledImpl(Features, "sse4a", true); 312 setFeatureEnabledImpl(Features, "lzcnt", true); 313 setFeatureEnabledImpl(Features, "popcnt", true); 314 setFeatureEnabledImpl(Features, "prfchw", true); 315 setFeatureEnabledImpl(Features, "cx16", true); 316 setFeatureEnabledImpl(Features, "fxsr", true); 317 break; 318 319 case CK_ZNVER1: 320 setFeatureEnabledImpl(Features, "adx", true); 321 setFeatureEnabledImpl(Features, "aes", true); 322 setFeatureEnabledImpl(Features, "avx2", true); 323 setFeatureEnabledImpl(Features, "bmi", true); 324 setFeatureEnabledImpl(Features, "bmi2", true); 325 setFeatureEnabledImpl(Features, "clflushopt", true); 326 setFeatureEnabledImpl(Features, "clzero", true); 327 setFeatureEnabledImpl(Features, "cx16", true); 328 setFeatureEnabledImpl(Features, "f16c", true); 329 setFeatureEnabledImpl(Features, "fma", true); 330 setFeatureEnabledImpl(Features, "fsgsbase", true); 331 setFeatureEnabledImpl(Features, "fxsr", true); 332 setFeatureEnabledImpl(Features, "lzcnt", true); 333 setFeatureEnabledImpl(Features, "mwaitx", true); 334 setFeatureEnabledImpl(Features, "movbe", true); 335 setFeatureEnabledImpl(Features, "pclmul", true); 336 setFeatureEnabledImpl(Features, "popcnt", true); 337 setFeatureEnabledImpl(Features, "prfchw", true); 338 setFeatureEnabledImpl(Features, "rdrnd", true); 339 setFeatureEnabledImpl(Features, "rdseed", true); 340 setFeatureEnabledImpl(Features, "sha", true); 341 setFeatureEnabledImpl(Features, "sse4a", true); 342 setFeatureEnabledImpl(Features, "xsave", true); 343 setFeatureEnabledImpl(Features, "xsavec", true); 344 setFeatureEnabledImpl(Features, "xsaveopt", true); 345 setFeatureEnabledImpl(Features, "xsaves", true); 346 break; 347 348 case CK_BDVER4: 349 setFeatureEnabledImpl(Features, "avx2", true); 350 setFeatureEnabledImpl(Features, "bmi2", true); 351 setFeatureEnabledImpl(Features, "mwaitx", true); 352 LLVM_FALLTHROUGH; 353 case CK_BDVER3: 354 setFeatureEnabledImpl(Features, "fsgsbase", true); 355 setFeatureEnabledImpl(Features, "xsaveopt", true); 356 LLVM_FALLTHROUGH; 357 case CK_BDVER2: 358 setFeatureEnabledImpl(Features, "bmi", true); 359 setFeatureEnabledImpl(Features, "fma", true); 360 setFeatureEnabledImpl(Features, "f16c", true); 361 setFeatureEnabledImpl(Features, "tbm", true); 362 LLVM_FALLTHROUGH; 363 case CK_BDVER1: 364 // xop implies avx, sse4a and fma4. 365 setFeatureEnabledImpl(Features, "xop", true); 366 setFeatureEnabledImpl(Features, "lwp", true); 367 setFeatureEnabledImpl(Features, "lzcnt", true); 368 setFeatureEnabledImpl(Features, "aes", true); 369 setFeatureEnabledImpl(Features, "pclmul", true); 370 setFeatureEnabledImpl(Features, "prfchw", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "fxsr", true); 373 setFeatureEnabledImpl(Features, "xsave", true); 374 break; 375 } 376 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 377 return false; 378 379 // Can't do this earlier because we need to be able to explicitly enable 380 // or disable these features and the things that they depend upon. 381 382 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 383 auto I = Features.find("sse4.2"); 384 if (I != Features.end() && I->getValue() && 385 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 386 FeaturesVec.end()) 387 Features["popcnt"] = true; 388 389 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 390 I = Features.find("3dnow"); 391 if (I != Features.end() && I->getValue() && 392 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 393 FeaturesVec.end()) 394 Features["prfchw"] = true; 395 396 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 397 // then enable MMX. 398 I = Features.find("sse"); 399 if (I != Features.end() && I->getValue() && 400 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 401 FeaturesVec.end()) 402 Features["mmx"] = true; 403 404 return true; 405 } 406 407 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 408 X86SSEEnum Level, bool Enabled) { 409 if (Enabled) { 410 switch (Level) { 411 case AVX512F: 412 Features["avx512f"] = true; 413 LLVM_FALLTHROUGH; 414 case AVX2: 415 Features["avx2"] = true; 416 LLVM_FALLTHROUGH; 417 case AVX: 418 Features["avx"] = true; 419 Features["xsave"] = true; 420 LLVM_FALLTHROUGH; 421 case SSE42: 422 Features["sse4.2"] = true; 423 LLVM_FALLTHROUGH; 424 case SSE41: 425 Features["sse4.1"] = true; 426 LLVM_FALLTHROUGH; 427 case SSSE3: 428 Features["ssse3"] = true; 429 LLVM_FALLTHROUGH; 430 case SSE3: 431 Features["sse3"] = true; 432 LLVM_FALLTHROUGH; 433 case SSE2: 434 Features["sse2"] = true; 435 LLVM_FALLTHROUGH; 436 case SSE1: 437 Features["sse"] = true; 438 LLVM_FALLTHROUGH; 439 case NoSSE: 440 break; 441 } 442 return; 443 } 444 445 switch (Level) { 446 case NoSSE: 447 case SSE1: 448 Features["sse"] = false; 449 LLVM_FALLTHROUGH; 450 case SSE2: 451 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 452 Features["gfni"] = false; 453 LLVM_FALLTHROUGH; 454 case SSE3: 455 Features["sse3"] = false; 456 setXOPLevel(Features, NoXOP, false); 457 LLVM_FALLTHROUGH; 458 case SSSE3: 459 Features["ssse3"] = false; 460 LLVM_FALLTHROUGH; 461 case SSE41: 462 Features["sse4.1"] = false; 463 LLVM_FALLTHROUGH; 464 case SSE42: 465 Features["sse4.2"] = false; 466 LLVM_FALLTHROUGH; 467 case AVX: 468 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 469 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 470 setXOPLevel(Features, FMA4, false); 471 LLVM_FALLTHROUGH; 472 case AVX2: 473 Features["avx2"] = false; 474 LLVM_FALLTHROUGH; 475 case AVX512F: 476 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 477 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 478 Features["avx512vl"] = Features["avx512vbmi"] = 479 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 480 Features["avx512bitalg"] = Features["avx512vnni"] = 481 Features["avx512vbmi2"] = false; 482 break; 483 } 484 } 485 486 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 487 MMX3DNowEnum Level, bool Enabled) { 488 if (Enabled) { 489 switch (Level) { 490 case AMD3DNowAthlon: 491 Features["3dnowa"] = true; 492 LLVM_FALLTHROUGH; 493 case AMD3DNow: 494 Features["3dnow"] = true; 495 LLVM_FALLTHROUGH; 496 case MMX: 497 Features["mmx"] = true; 498 LLVM_FALLTHROUGH; 499 case NoMMX3DNow: 500 break; 501 } 502 return; 503 } 504 505 switch (Level) { 506 case NoMMX3DNow: 507 case MMX: 508 Features["mmx"] = false; 509 LLVM_FALLTHROUGH; 510 case AMD3DNow: 511 Features["3dnow"] = false; 512 LLVM_FALLTHROUGH; 513 case AMD3DNowAthlon: 514 Features["3dnowa"] = false; 515 break; 516 } 517 } 518 519 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 520 bool Enabled) { 521 if (Enabled) { 522 switch (Level) { 523 case XOP: 524 Features["xop"] = true; 525 LLVM_FALLTHROUGH; 526 case FMA4: 527 Features["fma4"] = true; 528 setSSELevel(Features, AVX, true); 529 LLVM_FALLTHROUGH; 530 case SSE4A: 531 Features["sse4a"] = true; 532 setSSELevel(Features, SSE3, true); 533 LLVM_FALLTHROUGH; 534 case NoXOP: 535 break; 536 } 537 return; 538 } 539 540 switch (Level) { 541 case NoXOP: 542 case SSE4A: 543 Features["sse4a"] = false; 544 LLVM_FALLTHROUGH; 545 case FMA4: 546 Features["fma4"] = false; 547 LLVM_FALLTHROUGH; 548 case XOP: 549 Features["xop"] = false; 550 break; 551 } 552 } 553 554 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 555 StringRef Name, bool Enabled) { 556 // This is a bit of a hack to deal with the sse4 target feature when used 557 // as part of the target attribute. We handle sse4 correctly everywhere 558 // else. See below for more information on how we handle the sse4 options. 559 if (Name != "sse4") 560 Features[Name] = Enabled; 561 562 if (Name == "mmx") { 563 setMMXLevel(Features, MMX, Enabled); 564 } else if (Name == "sse") { 565 setSSELevel(Features, SSE1, Enabled); 566 } else if (Name == "sse2") { 567 setSSELevel(Features, SSE2, Enabled); 568 } else if (Name == "sse3") { 569 setSSELevel(Features, SSE3, Enabled); 570 } else if (Name == "ssse3") { 571 setSSELevel(Features, SSSE3, Enabled); 572 } else if (Name == "sse4.2") { 573 setSSELevel(Features, SSE42, Enabled); 574 } else if (Name == "sse4.1") { 575 setSSELevel(Features, SSE41, Enabled); 576 } else if (Name == "3dnow") { 577 setMMXLevel(Features, AMD3DNow, Enabled); 578 } else if (Name == "3dnowa") { 579 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 580 } else if (Name == "aes") { 581 if (Enabled) 582 setSSELevel(Features, SSE2, Enabled); 583 else 584 Features["vaes"] = false; 585 } else if (Name == "vaes") { 586 if (Enabled) { 587 setSSELevel(Features, AVX, Enabled); 588 Features["aes"] = true; 589 } 590 } else if (Name == "pclmul") { 591 if (Enabled) 592 setSSELevel(Features, SSE2, Enabled); 593 else 594 Features["vpclmulqdq"] = false; 595 } else if (Name == "vpclmulqdq") { 596 if (Enabled) { 597 setSSELevel(Features, AVX, Enabled); 598 Features["pclmul"] = true; 599 } 600 } else if (Name == "gfni") { 601 if (Enabled) 602 setSSELevel(Features, SSE2, Enabled); 603 } else if (Name == "avx") { 604 setSSELevel(Features, AVX, Enabled); 605 } else if (Name == "avx2") { 606 setSSELevel(Features, AVX2, Enabled); 607 } else if (Name == "avx512f") { 608 setSSELevel(Features, AVX512F, Enabled); 609 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 610 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 611 Name == "avx512vbmi" || Name == "avx512ifma" || 612 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 613 Name == "avx512vnni" || Name == "avx512vbmi2") { 614 if (Enabled) 615 setSSELevel(Features, AVX512F, Enabled); 616 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 617 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 618 Features["avx512bw"] = true; 619 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 620 if (Name == "avx512bw" && !Enabled) 621 Features["avx512vbmi"] = Features["avx512vbmi2"] = 622 Features["avx512bitalg"] = false; 623 } else if (Name == "fma") { 624 if (Enabled) 625 setSSELevel(Features, AVX, Enabled); 626 } else if (Name == "fma4") { 627 setXOPLevel(Features, FMA4, Enabled); 628 } else if (Name == "xop") { 629 setXOPLevel(Features, XOP, Enabled); 630 } else if (Name == "sse4a") { 631 setXOPLevel(Features, SSE4A, Enabled); 632 } else if (Name == "f16c") { 633 if (Enabled) 634 setSSELevel(Features, AVX, Enabled); 635 } else if (Name == "sha") { 636 if (Enabled) 637 setSSELevel(Features, SSE2, Enabled); 638 } else if (Name == "sse4") { 639 // We can get here via the __target__ attribute since that's not controlled 640 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 641 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 642 // disabled. 643 if (Enabled) 644 setSSELevel(Features, SSE42, Enabled); 645 else 646 setSSELevel(Features, SSE41, Enabled); 647 } else if (Name == "xsave") { 648 if (!Enabled) 649 Features["xsaveopt"] = false; 650 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 651 if (Enabled) 652 Features["xsave"] = true; 653 } 654 } 655 656 /// handleTargetFeatures - Perform initialization based on the user 657 /// configured set of features. 658 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 659 DiagnosticsEngine &Diags) { 660 for (const auto &Feature : Features) { 661 if (Feature[0] != '+') 662 continue; 663 664 if (Feature == "+aes") { 665 HasAES = true; 666 } else if (Feature == "+vaes") { 667 HasVAES = true; 668 } else if (Feature == "+pclmul") { 669 HasPCLMUL = true; 670 } else if (Feature == "+vpclmulqdq") { 671 HasVPCLMULQDQ = true; 672 } else if (Feature == "+lzcnt") { 673 HasLZCNT = true; 674 } else if (Feature == "+rdrnd") { 675 HasRDRND = true; 676 } else if (Feature == "+fsgsbase") { 677 HasFSGSBASE = true; 678 } else if (Feature == "+bmi") { 679 HasBMI = true; 680 } else if (Feature == "+bmi2") { 681 HasBMI2 = true; 682 } else if (Feature == "+popcnt") { 683 HasPOPCNT = true; 684 } else if (Feature == "+rtm") { 685 HasRTM = true; 686 } else if (Feature == "+prfchw") { 687 HasPRFCHW = true; 688 } else if (Feature == "+rdseed") { 689 HasRDSEED = true; 690 } else if (Feature == "+adx") { 691 HasADX = true; 692 } else if (Feature == "+tbm") { 693 HasTBM = true; 694 } else if (Feature == "+lwp") { 695 HasLWP = true; 696 } else if (Feature == "+fma") { 697 HasFMA = true; 698 } else if (Feature == "+f16c") { 699 HasF16C = true; 700 } else if (Feature == "+gfni") { 701 HasGFNI = true; 702 } else if (Feature == "+avx512cd") { 703 HasAVX512CD = true; 704 } else if (Feature == "+avx512vpopcntdq") { 705 HasAVX512VPOPCNTDQ = true; 706 } else if (Feature == "+avx512vnni") { 707 HasAVX512VNNI = true; 708 } else if (Feature == "+avx512er") { 709 HasAVX512ER = true; 710 } else if (Feature == "+avx512pf") { 711 HasAVX512PF = true; 712 } else if (Feature == "+avx512dq") { 713 HasAVX512DQ = true; 714 } else if (Feature == "+avx512bitalg") { 715 HasAVX512BITALG = true; 716 } else if (Feature == "+avx512bw") { 717 HasAVX512BW = true; 718 } else if (Feature == "+avx512vl") { 719 HasAVX512VL = true; 720 } else if (Feature == "+avx512vbmi") { 721 HasAVX512VBMI = true; 722 } else if (Feature == "+avx512vbmi2") { 723 HasAVX512VBMI2 = true; 724 } else if (Feature == "+avx512ifma") { 725 HasAVX512IFMA = true; 726 } else if (Feature == "+sha") { 727 HasSHA = true; 728 } else if (Feature == "+mpx") { 729 HasMPX = true; 730 } else if (Feature == "+shstk") { 731 HasSHSTK = true; 732 } else if (Feature == "+ibt") { 733 HasIBT = true; 734 } else if (Feature == "+movbe") { 735 HasMOVBE = true; 736 } else if (Feature == "+sgx") { 737 HasSGX = true; 738 } else if (Feature == "+cx16") { 739 HasCX16 = true; 740 } else if (Feature == "+fxsr") { 741 HasFXSR = true; 742 } else if (Feature == "+xsave") { 743 HasXSAVE = true; 744 } else if (Feature == "+xsaveopt") { 745 HasXSAVEOPT = true; 746 } else if (Feature == "+xsavec") { 747 HasXSAVEC = true; 748 } else if (Feature == "+xsaves") { 749 HasXSAVES = true; 750 } else if (Feature == "+mwaitx") { 751 HasMWAITX = true; 752 } else if (Feature == "+pku") { 753 HasPKU = true; 754 } else if (Feature == "+clflushopt") { 755 HasCLFLUSHOPT = true; 756 } else if (Feature == "+clwb") { 757 HasCLWB = true; 758 } else if (Feature == "+prefetchwt1") { 759 HasPREFETCHWT1 = true; 760 } else if (Feature == "+clzero") { 761 HasCLZERO = true; 762 } 763 764 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 765 .Case("+avx512f", AVX512F) 766 .Case("+avx2", AVX2) 767 .Case("+avx", AVX) 768 .Case("+sse4.2", SSE42) 769 .Case("+sse4.1", SSE41) 770 .Case("+ssse3", SSSE3) 771 .Case("+sse3", SSE3) 772 .Case("+sse2", SSE2) 773 .Case("+sse", SSE1) 774 .Default(NoSSE); 775 SSELevel = std::max(SSELevel, Level); 776 777 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 778 .Case("+3dnowa", AMD3DNowAthlon) 779 .Case("+3dnow", AMD3DNow) 780 .Case("+mmx", MMX) 781 .Default(NoMMX3DNow); 782 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 783 784 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 785 .Case("+xop", XOP) 786 .Case("+fma4", FMA4) 787 .Case("+sse4a", SSE4A) 788 .Default(NoXOP); 789 XOPLevel = std::max(XOPLevel, XLevel); 790 } 791 792 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 793 // matches the selected sse level. 794 if ((FPMath == FP_SSE && SSELevel < SSE1) || 795 (FPMath == FP_387 && SSELevel >= SSE1)) { 796 Diags.Report(diag::err_target_unsupported_fpmath) 797 << (FPMath == FP_SSE ? "sse" : "387"); 798 return false; 799 } 800 801 SimdDefaultAlign = 802 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 803 return true; 804 } 805 806 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 807 /// definitions for this particular subtarget. 808 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 809 MacroBuilder &Builder) const { 810 // Target identification. 811 if (getTriple().getArch() == llvm::Triple::x86_64) { 812 Builder.defineMacro("__amd64__"); 813 Builder.defineMacro("__amd64"); 814 Builder.defineMacro("__x86_64"); 815 Builder.defineMacro("__x86_64__"); 816 if (getTriple().getArchName() == "x86_64h") { 817 Builder.defineMacro("__x86_64h"); 818 Builder.defineMacro("__x86_64h__"); 819 } 820 } else { 821 DefineStd(Builder, "i386", Opts); 822 } 823 824 // Subtarget options. 825 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 826 // truly should be based on -mtune options. 827 switch (CPU) { 828 case CK_Generic: 829 break; 830 case CK_i386: 831 // The rest are coming from the i386 define above. 832 Builder.defineMacro("__tune_i386__"); 833 break; 834 case CK_i486: 835 case CK_WinChipC6: 836 case CK_WinChip2: 837 case CK_C3: 838 defineCPUMacros(Builder, "i486"); 839 break; 840 case CK_PentiumMMX: 841 Builder.defineMacro("__pentium_mmx__"); 842 Builder.defineMacro("__tune_pentium_mmx__"); 843 LLVM_FALLTHROUGH; 844 case CK_i586: 845 case CK_Pentium: 846 defineCPUMacros(Builder, "i586"); 847 defineCPUMacros(Builder, "pentium"); 848 break; 849 case CK_Pentium3: 850 case CK_PentiumM: 851 Builder.defineMacro("__tune_pentium3__"); 852 LLVM_FALLTHROUGH; 853 case CK_Pentium2: 854 case CK_C3_2: 855 Builder.defineMacro("__tune_pentium2__"); 856 LLVM_FALLTHROUGH; 857 case CK_PentiumPro: 858 defineCPUMacros(Builder, "i686"); 859 defineCPUMacros(Builder, "pentiumpro"); 860 break; 861 case CK_Pentium4: 862 defineCPUMacros(Builder, "pentium4"); 863 break; 864 case CK_Yonah: 865 case CK_Prescott: 866 case CK_Nocona: 867 defineCPUMacros(Builder, "nocona"); 868 break; 869 case CK_Core2: 870 case CK_Penryn: 871 defineCPUMacros(Builder, "core2"); 872 break; 873 case CK_Bonnell: 874 defineCPUMacros(Builder, "atom"); 875 break; 876 case CK_Silvermont: 877 defineCPUMacros(Builder, "slm"); 878 break; 879 case CK_Goldmont: 880 defineCPUMacros(Builder, "goldmont"); 881 break; 882 case CK_Nehalem: 883 case CK_Westmere: 884 case CK_SandyBridge: 885 case CK_IvyBridge: 886 case CK_Haswell: 887 case CK_Broadwell: 888 case CK_SkylakeClient: 889 case CK_SkylakeServer: 890 case CK_Cannonlake: 891 case CK_Icelake: 892 // FIXME: Historically, we defined this legacy name, it would be nice to 893 // remove it at some point. We've never exposed fine-grained names for 894 // recent primary x86 CPUs, and we should keep it that way. 895 defineCPUMacros(Builder, "corei7"); 896 break; 897 case CK_KNL: 898 defineCPUMacros(Builder, "knl"); 899 break; 900 case CK_KNM: 901 break; 902 case CK_Lakemont: 903 defineCPUMacros(Builder, "i586", /*Tuning*/false); 904 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 905 Builder.defineMacro("__tune_lakemont__"); 906 break; 907 case CK_K6_2: 908 Builder.defineMacro("__k6_2__"); 909 Builder.defineMacro("__tune_k6_2__"); 910 LLVM_FALLTHROUGH; 911 case CK_K6_3: 912 if (CPU != CK_K6_2) { // In case of fallthrough 913 // FIXME: GCC may be enabling these in cases where some other k6 914 // architecture is specified but -m3dnow is explicitly provided. The 915 // exact semantics need to be determined and emulated here. 916 Builder.defineMacro("__k6_3__"); 917 Builder.defineMacro("__tune_k6_3__"); 918 } 919 LLVM_FALLTHROUGH; 920 case CK_K6: 921 defineCPUMacros(Builder, "k6"); 922 break; 923 case CK_Athlon: 924 case CK_AthlonXP: 925 defineCPUMacros(Builder, "athlon"); 926 if (SSELevel != NoSSE) { 927 Builder.defineMacro("__athlon_sse__"); 928 Builder.defineMacro("__tune_athlon_sse__"); 929 } 930 break; 931 case CK_K8: 932 case CK_K8SSE3: 933 case CK_x86_64: 934 defineCPUMacros(Builder, "k8"); 935 break; 936 case CK_AMDFAM10: 937 defineCPUMacros(Builder, "amdfam10"); 938 break; 939 case CK_BTVER1: 940 defineCPUMacros(Builder, "btver1"); 941 break; 942 case CK_BTVER2: 943 defineCPUMacros(Builder, "btver2"); 944 break; 945 case CK_BDVER1: 946 defineCPUMacros(Builder, "bdver1"); 947 break; 948 case CK_BDVER2: 949 defineCPUMacros(Builder, "bdver2"); 950 break; 951 case CK_BDVER3: 952 defineCPUMacros(Builder, "bdver3"); 953 break; 954 case CK_BDVER4: 955 defineCPUMacros(Builder, "bdver4"); 956 break; 957 case CK_ZNVER1: 958 defineCPUMacros(Builder, "znver1"); 959 break; 960 case CK_Geode: 961 defineCPUMacros(Builder, "geode"); 962 break; 963 } 964 965 // Target properties. 966 Builder.defineMacro("__REGISTER_PREFIX__", ""); 967 968 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 969 // functions in glibc header files that use FP Stack inline asm which the 970 // backend can't deal with (PR879). 971 Builder.defineMacro("__NO_MATH_INLINES"); 972 973 if (HasAES) 974 Builder.defineMacro("__AES__"); 975 976 if (HasVAES) 977 Builder.defineMacro("__VAES__"); 978 979 if (HasPCLMUL) 980 Builder.defineMacro("__PCLMUL__"); 981 982 if (HasVPCLMULQDQ) 983 Builder.defineMacro("__VPCLMULQDQ__"); 984 985 if (HasLZCNT) 986 Builder.defineMacro("__LZCNT__"); 987 988 if (HasRDRND) 989 Builder.defineMacro("__RDRND__"); 990 991 if (HasFSGSBASE) 992 Builder.defineMacro("__FSGSBASE__"); 993 994 if (HasBMI) 995 Builder.defineMacro("__BMI__"); 996 997 if (HasBMI2) 998 Builder.defineMacro("__BMI2__"); 999 1000 if (HasPOPCNT) 1001 Builder.defineMacro("__POPCNT__"); 1002 1003 if (HasRTM) 1004 Builder.defineMacro("__RTM__"); 1005 1006 if (HasPRFCHW) 1007 Builder.defineMacro("__PRFCHW__"); 1008 1009 if (HasRDSEED) 1010 Builder.defineMacro("__RDSEED__"); 1011 1012 if (HasADX) 1013 Builder.defineMacro("__ADX__"); 1014 1015 if (HasTBM) 1016 Builder.defineMacro("__TBM__"); 1017 1018 if (HasLWP) 1019 Builder.defineMacro("__LWP__"); 1020 1021 if (HasMWAITX) 1022 Builder.defineMacro("__MWAITX__"); 1023 1024 switch (XOPLevel) { 1025 case XOP: 1026 Builder.defineMacro("__XOP__"); 1027 LLVM_FALLTHROUGH; 1028 case FMA4: 1029 Builder.defineMacro("__FMA4__"); 1030 LLVM_FALLTHROUGH; 1031 case SSE4A: 1032 Builder.defineMacro("__SSE4A__"); 1033 LLVM_FALLTHROUGH; 1034 case NoXOP: 1035 break; 1036 } 1037 1038 if (HasFMA) 1039 Builder.defineMacro("__FMA__"); 1040 1041 if (HasF16C) 1042 Builder.defineMacro("__F16C__"); 1043 1044 if (HasGFNI) 1045 Builder.defineMacro("__GFNI__"); 1046 1047 if (HasAVX512CD) 1048 Builder.defineMacro("__AVX512CD__"); 1049 if (HasAVX512VPOPCNTDQ) 1050 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1051 if (HasAVX512VNNI) 1052 Builder.defineMacro("__AVX512VNNI__"); 1053 if (HasAVX512ER) 1054 Builder.defineMacro("__AVX512ER__"); 1055 if (HasAVX512PF) 1056 Builder.defineMacro("__AVX512PF__"); 1057 if (HasAVX512DQ) 1058 Builder.defineMacro("__AVX512DQ__"); 1059 if (HasAVX512BITALG) 1060 Builder.defineMacro("__AVX512BITALG__"); 1061 if (HasAVX512BW) 1062 Builder.defineMacro("__AVX512BW__"); 1063 if (HasAVX512VL) 1064 Builder.defineMacro("__AVX512VL__"); 1065 if (HasAVX512VBMI) 1066 Builder.defineMacro("__AVX512VBMI__"); 1067 if (HasAVX512VBMI2) 1068 Builder.defineMacro("__AVX512VBMI2__"); 1069 if (HasAVX512IFMA) 1070 Builder.defineMacro("__AVX512IFMA__"); 1071 1072 if (HasSHA) 1073 Builder.defineMacro("__SHA__"); 1074 1075 if (HasFXSR) 1076 Builder.defineMacro("__FXSR__"); 1077 if (HasXSAVE) 1078 Builder.defineMacro("__XSAVE__"); 1079 if (HasXSAVEOPT) 1080 Builder.defineMacro("__XSAVEOPT__"); 1081 if (HasXSAVEC) 1082 Builder.defineMacro("__XSAVEC__"); 1083 if (HasXSAVES) 1084 Builder.defineMacro("__XSAVES__"); 1085 if (HasPKU) 1086 Builder.defineMacro("__PKU__"); 1087 if (HasCX16) 1088 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1089 if (HasCLFLUSHOPT) 1090 Builder.defineMacro("__CLFLUSHOPT__"); 1091 if (HasCLWB) 1092 Builder.defineMacro("__CLWB__"); 1093 if (HasMPX) 1094 Builder.defineMacro("__MPX__"); 1095 if (HasSHSTK) 1096 Builder.defineMacro("__SHSTK__"); 1097 if (HasSGX) 1098 Builder.defineMacro("__SGX__"); 1099 if (HasPREFETCHWT1) 1100 Builder.defineMacro("__PREFETCHWT1__"); 1101 if (HasCLZERO) 1102 Builder.defineMacro("__CLZERO__"); 1103 1104 // Each case falls through to the previous one here. 1105 switch (SSELevel) { 1106 case AVX512F: 1107 Builder.defineMacro("__AVX512F__"); 1108 LLVM_FALLTHROUGH; 1109 case AVX2: 1110 Builder.defineMacro("__AVX2__"); 1111 LLVM_FALLTHROUGH; 1112 case AVX: 1113 Builder.defineMacro("__AVX__"); 1114 LLVM_FALLTHROUGH; 1115 case SSE42: 1116 Builder.defineMacro("__SSE4_2__"); 1117 LLVM_FALLTHROUGH; 1118 case SSE41: 1119 Builder.defineMacro("__SSE4_1__"); 1120 LLVM_FALLTHROUGH; 1121 case SSSE3: 1122 Builder.defineMacro("__SSSE3__"); 1123 LLVM_FALLTHROUGH; 1124 case SSE3: 1125 Builder.defineMacro("__SSE3__"); 1126 LLVM_FALLTHROUGH; 1127 case SSE2: 1128 Builder.defineMacro("__SSE2__"); 1129 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1130 LLVM_FALLTHROUGH; 1131 case SSE1: 1132 Builder.defineMacro("__SSE__"); 1133 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1134 LLVM_FALLTHROUGH; 1135 case NoSSE: 1136 break; 1137 } 1138 1139 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1140 switch (SSELevel) { 1141 case AVX512F: 1142 case AVX2: 1143 case AVX: 1144 case SSE42: 1145 case SSE41: 1146 case SSSE3: 1147 case SSE3: 1148 case SSE2: 1149 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1150 break; 1151 case SSE1: 1152 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1153 break; 1154 default: 1155 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1156 break; 1157 } 1158 } 1159 1160 // Each case falls through to the previous one here. 1161 switch (MMX3DNowLevel) { 1162 case AMD3DNowAthlon: 1163 Builder.defineMacro("__3dNOW_A__"); 1164 LLVM_FALLTHROUGH; 1165 case AMD3DNow: 1166 Builder.defineMacro("__3dNOW__"); 1167 LLVM_FALLTHROUGH; 1168 case MMX: 1169 Builder.defineMacro("__MMX__"); 1170 LLVM_FALLTHROUGH; 1171 case NoMMX3DNow: 1172 break; 1173 } 1174 1175 if (CPU >= CK_i486) { 1176 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1177 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1178 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1179 } 1180 if (CPU >= CK_i586) 1181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1182 1183 if (HasFloat128) 1184 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1185 } 1186 1187 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1188 return llvm::StringSwitch<bool>(Name) 1189 .Case("3dnow", true) 1190 .Case("3dnowa", true) 1191 .Case("adx", true) 1192 .Case("aes", true) 1193 .Case("avx", true) 1194 .Case("avx2", true) 1195 .Case("avx512f", true) 1196 .Case("avx512cd", true) 1197 .Case("avx512vpopcntdq", true) 1198 .Case("avx512vnni", true) 1199 .Case("avx512er", true) 1200 .Case("avx512pf", true) 1201 .Case("avx512dq", true) 1202 .Case("avx512bitalg", true) 1203 .Case("avx512bw", true) 1204 .Case("avx512vl", true) 1205 .Case("avx512vbmi", true) 1206 .Case("avx512vbmi2", true) 1207 .Case("avx512ifma", true) 1208 .Case("bmi", true) 1209 .Case("bmi2", true) 1210 .Case("clflushopt", true) 1211 .Case("clwb", true) 1212 .Case("clzero", true) 1213 .Case("cx16", true) 1214 .Case("f16c", true) 1215 .Case("fma", true) 1216 .Case("fma4", true) 1217 .Case("fsgsbase", true) 1218 .Case("fxsr", true) 1219 .Case("gfni", true) 1220 .Case("lwp", true) 1221 .Case("lzcnt", true) 1222 .Case("mmx", true) 1223 .Case("movbe", true) 1224 .Case("mpx", true) 1225 .Case("mwaitx", true) 1226 .Case("pclmul", true) 1227 .Case("pku", true) 1228 .Case("popcnt", true) 1229 .Case("prefetchwt1", true) 1230 .Case("prfchw", true) 1231 .Case("rdrnd", true) 1232 .Case("rdseed", true) 1233 .Case("rtm", true) 1234 .Case("sgx", true) 1235 .Case("sha", true) 1236 .Case("shstk", true) 1237 .Case("sse", true) 1238 .Case("sse2", true) 1239 .Case("sse3", true) 1240 .Case("ssse3", true) 1241 .Case("sse4", true) 1242 .Case("sse4.1", true) 1243 .Case("sse4.2", true) 1244 .Case("sse4a", true) 1245 .Case("tbm", true) 1246 .Case("vaes", true) 1247 .Case("vpclmulqdq", true) 1248 .Case("x87", true) 1249 .Case("xop", true) 1250 .Case("xsave", true) 1251 .Case("xsavec", true) 1252 .Case("xsaves", true) 1253 .Case("xsaveopt", true) 1254 .Default(false); 1255 } 1256 1257 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1258 return llvm::StringSwitch<bool>(Feature) 1259 .Case("adx", HasADX) 1260 .Case("aes", HasAES) 1261 .Case("avx", SSELevel >= AVX) 1262 .Case("avx2", SSELevel >= AVX2) 1263 .Case("avx512f", SSELevel >= AVX512F) 1264 .Case("avx512cd", HasAVX512CD) 1265 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1266 .Case("avx512vnni", HasAVX512VNNI) 1267 .Case("avx512er", HasAVX512ER) 1268 .Case("avx512pf", HasAVX512PF) 1269 .Case("avx512dq", HasAVX512DQ) 1270 .Case("avx512bitalg", HasAVX512BITALG) 1271 .Case("avx512bw", HasAVX512BW) 1272 .Case("avx512vl", HasAVX512VL) 1273 .Case("avx512vbmi", HasAVX512VBMI) 1274 .Case("avx512vbmi2", HasAVX512VBMI2) 1275 .Case("avx512ifma", HasAVX512IFMA) 1276 .Case("bmi", HasBMI) 1277 .Case("bmi2", HasBMI2) 1278 .Case("clflushopt", HasCLFLUSHOPT) 1279 .Case("clwb", HasCLWB) 1280 .Case("clzero", HasCLZERO) 1281 .Case("cx16", HasCX16) 1282 .Case("f16c", HasF16C) 1283 .Case("fma", HasFMA) 1284 .Case("fma4", XOPLevel >= FMA4) 1285 .Case("fsgsbase", HasFSGSBASE) 1286 .Case("fxsr", HasFXSR) 1287 .Case("gfni", HasGFNI) 1288 .Case("ibt", HasIBT) 1289 .Case("lwp", HasLWP) 1290 .Case("lzcnt", HasLZCNT) 1291 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1292 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1293 .Case("mmx", MMX3DNowLevel >= MMX) 1294 .Case("movbe", HasMOVBE) 1295 .Case("mpx", HasMPX) 1296 .Case("mwaitx", HasMWAITX) 1297 .Case("pclmul", HasPCLMUL) 1298 .Case("pku", HasPKU) 1299 .Case("popcnt", HasPOPCNT) 1300 .Case("prefetchwt1", HasPREFETCHWT1) 1301 .Case("prfchw", HasPRFCHW) 1302 .Case("rdrnd", HasRDRND) 1303 .Case("rdseed", HasRDSEED) 1304 .Case("rtm", HasRTM) 1305 .Case("sgx", HasSGX) 1306 .Case("sha", HasSHA) 1307 .Case("shstk", HasSHSTK) 1308 .Case("sse", SSELevel >= SSE1) 1309 .Case("sse2", SSELevel >= SSE2) 1310 .Case("sse3", SSELevel >= SSE3) 1311 .Case("ssse3", SSELevel >= SSSE3) 1312 .Case("sse4.1", SSELevel >= SSE41) 1313 .Case("sse4.2", SSELevel >= SSE42) 1314 .Case("sse4a", XOPLevel >= SSE4A) 1315 .Case("tbm", HasTBM) 1316 .Case("vaes", HasVAES) 1317 .Case("vpclmulqdq", HasVPCLMULQDQ) 1318 .Case("x86", true) 1319 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1320 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1321 .Case("xop", XOPLevel >= XOP) 1322 .Case("xsave", HasXSAVE) 1323 .Case("xsavec", HasXSAVEC) 1324 .Case("xsaves", HasXSAVES) 1325 .Case("xsaveopt", HasXSAVEOPT) 1326 .Default(false); 1327 } 1328 1329 // We can't use a generic validation scheme for the features accepted here 1330 // versus subtarget features accepted in the target attribute because the 1331 // bitfield structure that's initialized in the runtime only supports the 1332 // below currently rather than the full range of subtarget features. (See 1333 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1334 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1335 return llvm::StringSwitch<bool>(FeatureStr) 1336 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1337 #include "llvm/Support/X86TargetParser.def" 1338 .Default(false); 1339 } 1340 1341 // We can't use a generic validation scheme for the cpus accepted here 1342 // versus subtarget cpus accepted in the target attribute because the 1343 // variables intitialized by the runtime only support the below currently 1344 // rather than the full range of cpus. 1345 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1346 return llvm::StringSwitch<bool>(FeatureStr) 1347 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1348 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1349 .Cases(STR, ALIAS, true) 1350 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1351 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1352 #include "llvm/Support/X86TargetParser.def" 1353 .Default(false); 1354 } 1355 1356 bool X86TargetInfo::validateAsmConstraint( 1357 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1358 switch (*Name) { 1359 default: 1360 return false; 1361 // Constant constraints. 1362 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1363 // instructions. 1364 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1365 // x86_64 instructions. 1366 case 's': 1367 Info.setRequiresImmediate(); 1368 return true; 1369 case 'I': 1370 Info.setRequiresImmediate(0, 31); 1371 return true; 1372 case 'J': 1373 Info.setRequiresImmediate(0, 63); 1374 return true; 1375 case 'K': 1376 Info.setRequiresImmediate(-128, 127); 1377 return true; 1378 case 'L': 1379 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1380 return true; 1381 case 'M': 1382 Info.setRequiresImmediate(0, 3); 1383 return true; 1384 case 'N': 1385 Info.setRequiresImmediate(0, 255); 1386 return true; 1387 case 'O': 1388 Info.setRequiresImmediate(0, 127); 1389 return true; 1390 // Register constraints. 1391 case 'Y': // 'Y' is the first character for several 2-character constraints. 1392 // Shift the pointer to the second character of the constraint. 1393 Name++; 1394 switch (*Name) { 1395 default: 1396 return false; 1397 case 'z': 1398 case '0': // First SSE register. 1399 case '2': 1400 case 't': // Any SSE register, when SSE2 is enabled. 1401 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1402 case 'm': // Any MMX register, when inter-unit moves enabled. 1403 case 'k': // AVX512 arch mask registers: k1-k7. 1404 Info.setAllowsRegister(); 1405 return true; 1406 } 1407 case 'f': // Any x87 floating point stack register. 1408 // Constraint 'f' cannot be used for output operands. 1409 if (Info.ConstraintStr[0] == '=') 1410 return false; 1411 Info.setAllowsRegister(); 1412 return true; 1413 case 'a': // eax. 1414 case 'b': // ebx. 1415 case 'c': // ecx. 1416 case 'd': // edx. 1417 case 'S': // esi. 1418 case 'D': // edi. 1419 case 'A': // edx:eax. 1420 case 't': // Top of floating point stack. 1421 case 'u': // Second from top of floating point stack. 1422 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1423 case 'y': // Any MMX register. 1424 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1425 case 'x': // Any SSE register. 1426 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1427 // for intermideate k reg operations). 1428 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1429 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1430 case 'l': // "Index" registers: any general register that can be used as an 1431 // index in a base+index memory access. 1432 Info.setAllowsRegister(); 1433 return true; 1434 // Floating point constant constraints. 1435 case 'C': // SSE floating point constant. 1436 case 'G': // x87 floating point constant. 1437 return true; 1438 } 1439 } 1440 1441 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1442 unsigned Size) const { 1443 // Strip off constraint modifiers. 1444 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1445 Constraint = Constraint.substr(1); 1446 1447 return validateOperandSize(Constraint, Size); 1448 } 1449 1450 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1451 unsigned Size) const { 1452 return validateOperandSize(Constraint, Size); 1453 } 1454 1455 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1456 unsigned Size) const { 1457 switch (Constraint[0]) { 1458 default: 1459 break; 1460 case 'k': 1461 // Registers k0-k7 (AVX512) size limit is 64 bit. 1462 case 'y': 1463 return Size <= 64; 1464 case 'f': 1465 case 't': 1466 case 'u': 1467 return Size <= 128; 1468 case 'Y': 1469 // 'Y' is the first character for several 2-character constraints. 1470 switch (Constraint[1]) { 1471 default: 1472 return false; 1473 case 'm': 1474 // 'Ym' is synonymous with 'y'. 1475 case 'k': 1476 return Size <= 64; 1477 case 'z': 1478 case '0': 1479 // XMM0 1480 if (SSELevel >= SSE1) 1481 return Size <= 128U; 1482 return false; 1483 case 'i': 1484 case 't': 1485 case '2': 1486 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1487 if (SSELevel < SSE2) 1488 return false; 1489 break; 1490 } 1491 case 'v': 1492 case 'x': 1493 if (SSELevel >= AVX512F) 1494 // 512-bit zmm registers can be used if target supports AVX512F. 1495 return Size <= 512U; 1496 else if (SSELevel >= AVX) 1497 // 256-bit ymm registers can be used if target supports AVX. 1498 return Size <= 256U; 1499 return Size <= 128U; 1500 1501 } 1502 1503 return true; 1504 } 1505 1506 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1507 switch (*Constraint) { 1508 case 'a': 1509 return std::string("{ax}"); 1510 case 'b': 1511 return std::string("{bx}"); 1512 case 'c': 1513 return std::string("{cx}"); 1514 case 'd': 1515 return std::string("{dx}"); 1516 case 'S': 1517 return std::string("{si}"); 1518 case 'D': 1519 return std::string("{di}"); 1520 case 'p': // address 1521 return std::string("im"); 1522 case 't': // top of floating point stack. 1523 return std::string("{st}"); 1524 case 'u': // second from top of floating point stack. 1525 return std::string("{st(1)}"); // second from top of floating point stack. 1526 case 'Y': 1527 switch (Constraint[1]) { 1528 default: 1529 // Break from inner switch and fall through (copy single char), 1530 // continue parsing after copying the current constraint into 1531 // the return string. 1532 break; 1533 case 'k': 1534 case 'm': 1535 case 'i': 1536 case 't': 1537 case 'z': 1538 case '0': 1539 case '2': 1540 // "^" hints llvm that this is a 2 letter constraint. 1541 // "Constraint++" is used to promote the string iterator 1542 // to the next constraint. 1543 return std::string("^") + std::string(Constraint++, 2); 1544 } 1545 LLVM_FALLTHROUGH; 1546 default: 1547 return std::string(1, *Constraint); 1548 } 1549 } 1550 1551 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1552 // Perform any per-CPU checks necessary to determine if this CPU is 1553 // acceptable. 1554 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1555 // invalid without explaining *why*. 1556 switch (Kind) { 1557 case CK_Generic: 1558 // No processor selected! 1559 return false; 1560 #define PROC(ENUM, STRING, IS64BIT) \ 1561 case CK_##ENUM: \ 1562 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1563 #include "clang/Basic/X86Target.def" 1564 } 1565 llvm_unreachable("Unhandled CPU kind"); 1566 } 1567 1568 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1569 return llvm::StringSwitch<CPUKind>(CPU) 1570 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1571 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1572 #include "clang/Basic/X86Target.def" 1573 .Default(CK_Generic); 1574 } 1575 1576 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1577 return llvm::makeArrayRef(GCCRegNames); 1578 } 1579 1580 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1581 return llvm::makeArrayRef(AddlRegNames); 1582 } 1583 1584 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1585 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1586 Builtin::FirstTSBuiltin + 1); 1587 } 1588 1589 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1590 return llvm::makeArrayRef(BuiltinInfoX86, 1591 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1592 } 1593