1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 }; 64 65 const TargetInfo::AddlRegName AddlRegNames[] = { 66 {{"al", "ah", "eax", "rax"}, 0}, 67 {{"bl", "bh", "ebx", "rbx"}, 3}, 68 {{"cl", "ch", "ecx", "rcx"}, 2}, 69 {{"dl", "dh", "edx", "rdx"}, 1}, 70 {{"esi", "rsi"}, 4}, 71 {{"edi", "rdi"}, 5}, 72 {{"esp", "rsp"}, 7}, 73 {{"ebp", "rbp"}, 6}, 74 {{"r8d", "r8w", "r8b"}, 38}, 75 {{"r9d", "r9w", "r9b"}, 39}, 76 {{"r10d", "r10w", "r10b"}, 40}, 77 {{"r11d", "r11w", "r11b"}, 41}, 78 {{"r12d", "r12w", "r12b"}, 42}, 79 {{"r13d", "r13w", "r13b"}, 43}, 80 {{"r14d", "r14w", "r14b"}, 44}, 81 {{"r15d", "r15w", "r15b"}, 45}, 82 }; 83 84 } // namespace targets 85 } // namespace clang 86 87 using namespace clang; 88 using namespace clang::targets; 89 90 bool X86TargetInfo::setFPMath(StringRef Name) { 91 if (Name == "387") { 92 FPMath = FP_387; 93 return true; 94 } 95 if (Name == "sse") { 96 FPMath = FP_SSE; 97 return true; 98 } 99 return false; 100 } 101 102 bool X86TargetInfo::initFeatureMap( 103 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 104 const std::vector<std::string> &FeaturesVec) const { 105 // FIXME: This *really* should not be here. 106 // X86_64 always has SSE2. 107 if (getTriple().getArch() == llvm::Triple::x86_64) 108 setFeatureEnabledImpl(Features, "sse2", true); 109 110 const CPUKind Kind = getCPUKind(CPU); 111 112 // Enable X87 for all X86 processors but Lakemont. 113 if (Kind != CK_Lakemont) 114 setFeatureEnabledImpl(Features, "x87", true); 115 116 switch (Kind) { 117 case CK_Generic: 118 case CK_i386: 119 case CK_i486: 120 case CK_i586: 121 case CK_Pentium: 122 case CK_i686: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 case CK_PentiumMMX: 127 case CK_Pentium2: 128 case CK_K6: 129 case CK_WinChipC6: 130 setFeatureEnabledImpl(Features, "mmx", true); 131 break; 132 case CK_Pentium3: 133 case CK_Pentium3M: 134 case CK_C3_2: 135 setFeatureEnabledImpl(Features, "sse", true); 136 setFeatureEnabledImpl(Features, "fxsr", true); 137 break; 138 case CK_PentiumM: 139 case CK_Pentium4: 140 case CK_Pentium4M: 141 case CK_x86_64: 142 setFeatureEnabledImpl(Features, "sse2", true); 143 setFeatureEnabledImpl(Features, "fxsr", true); 144 break; 145 case CK_Yonah: 146 case CK_Prescott: 147 case CK_Nocona: 148 setFeatureEnabledImpl(Features, "sse3", true); 149 setFeatureEnabledImpl(Features, "fxsr", true); 150 setFeatureEnabledImpl(Features, "cx16", true); 151 break; 152 case CK_Core2: 153 setFeatureEnabledImpl(Features, "ssse3", true); 154 setFeatureEnabledImpl(Features, "fxsr", true); 155 setFeatureEnabledImpl(Features, "cx16", true); 156 break; 157 case CK_Penryn: 158 setFeatureEnabledImpl(Features, "sse4.1", true); 159 setFeatureEnabledImpl(Features, "fxsr", true); 160 setFeatureEnabledImpl(Features, "cx16", true); 161 break; 162 case CK_Cannonlake: 163 setFeatureEnabledImpl(Features, "avx512ifma", true); 164 setFeatureEnabledImpl(Features, "avx512vbmi", true); 165 setFeatureEnabledImpl(Features, "sha", true); 166 LLVM_FALLTHROUGH; 167 case CK_SkylakeServer: 168 setFeatureEnabledImpl(Features, "avx512f", true); 169 setFeatureEnabledImpl(Features, "avx512cd", true); 170 setFeatureEnabledImpl(Features, "avx512dq", true); 171 setFeatureEnabledImpl(Features, "avx512bw", true); 172 setFeatureEnabledImpl(Features, "avx512vl", true); 173 setFeatureEnabledImpl(Features, "pku", true); 174 setFeatureEnabledImpl(Features, "clwb", true); 175 LLVM_FALLTHROUGH; 176 case CK_SkylakeClient: 177 setFeatureEnabledImpl(Features, "xsavec", true); 178 setFeatureEnabledImpl(Features, "xsaves", true); 179 setFeatureEnabledImpl(Features, "mpx", true); 180 setFeatureEnabledImpl(Features, "sgx", true); 181 setFeatureEnabledImpl(Features, "clflushopt", true); 182 setFeatureEnabledImpl(Features, "rtm", true); 183 LLVM_FALLTHROUGH; 184 case CK_Broadwell: 185 setFeatureEnabledImpl(Features, "rdseed", true); 186 setFeatureEnabledImpl(Features, "adx", true); 187 LLVM_FALLTHROUGH; 188 case CK_Haswell: 189 setFeatureEnabledImpl(Features, "avx2", true); 190 setFeatureEnabledImpl(Features, "lzcnt", true); 191 setFeatureEnabledImpl(Features, "bmi", true); 192 setFeatureEnabledImpl(Features, "bmi2", true); 193 setFeatureEnabledImpl(Features, "fma", true); 194 setFeatureEnabledImpl(Features, "movbe", true); 195 LLVM_FALLTHROUGH; 196 case CK_IvyBridge: 197 setFeatureEnabledImpl(Features, "rdrnd", true); 198 setFeatureEnabledImpl(Features, "f16c", true); 199 setFeatureEnabledImpl(Features, "fsgsbase", true); 200 LLVM_FALLTHROUGH; 201 case CK_SandyBridge: 202 setFeatureEnabledImpl(Features, "avx", true); 203 setFeatureEnabledImpl(Features, "xsave", true); 204 setFeatureEnabledImpl(Features, "xsaveopt", true); 205 LLVM_FALLTHROUGH; 206 case CK_Westmere: 207 setFeatureEnabledImpl(Features, "aes", true); 208 setFeatureEnabledImpl(Features, "pclmul", true); 209 LLVM_FALLTHROUGH; 210 case CK_Nehalem: 211 setFeatureEnabledImpl(Features, "sse4.2", true); 212 setFeatureEnabledImpl(Features, "fxsr", true); 213 setFeatureEnabledImpl(Features, "cx16", true); 214 break; 215 case CK_Goldmont: 216 setFeatureEnabledImpl(Features, "sha", true); 217 setFeatureEnabledImpl(Features, "rdrnd", true); 218 setFeatureEnabledImpl(Features, "rdseed", true); 219 setFeatureEnabledImpl(Features, "xsave", true); 220 setFeatureEnabledImpl(Features, "xsaveopt", true); 221 setFeatureEnabledImpl(Features, "xsavec", true); 222 setFeatureEnabledImpl(Features, "xsaves", true); 223 setFeatureEnabledImpl(Features, "clflushopt", true); 224 setFeatureEnabledImpl(Features, "mpx", true); 225 LLVM_FALLTHROUGH; 226 case CK_Silvermont: 227 setFeatureEnabledImpl(Features, "aes", true); 228 setFeatureEnabledImpl(Features, "pclmul", true); 229 setFeatureEnabledImpl(Features, "sse4.2", true); 230 LLVM_FALLTHROUGH; 231 case CK_Bonnell: 232 setFeatureEnabledImpl(Features, "movbe", true); 233 setFeatureEnabledImpl(Features, "ssse3", true); 234 setFeatureEnabledImpl(Features, "fxsr", true); 235 setFeatureEnabledImpl(Features, "cx16", true); 236 break; 237 case CK_KNL: 238 setFeatureEnabledImpl(Features, "avx512f", true); 239 setFeatureEnabledImpl(Features, "avx512cd", true); 240 setFeatureEnabledImpl(Features, "avx512er", true); 241 setFeatureEnabledImpl(Features, "avx512pf", true); 242 setFeatureEnabledImpl(Features, "prefetchwt1", true); 243 setFeatureEnabledImpl(Features, "fxsr", true); 244 setFeatureEnabledImpl(Features, "rdseed", true); 245 setFeatureEnabledImpl(Features, "adx", true); 246 setFeatureEnabledImpl(Features, "lzcnt", true); 247 setFeatureEnabledImpl(Features, "bmi", true); 248 setFeatureEnabledImpl(Features, "bmi2", true); 249 setFeatureEnabledImpl(Features, "rtm", true); 250 setFeatureEnabledImpl(Features, "fma", true); 251 setFeatureEnabledImpl(Features, "rdrnd", true); 252 setFeatureEnabledImpl(Features, "f16c", true); 253 setFeatureEnabledImpl(Features, "fsgsbase", true); 254 setFeatureEnabledImpl(Features, "aes", true); 255 setFeatureEnabledImpl(Features, "pclmul", true); 256 setFeatureEnabledImpl(Features, "cx16", true); 257 setFeatureEnabledImpl(Features, "xsaveopt", true); 258 setFeatureEnabledImpl(Features, "xsave", true); 259 setFeatureEnabledImpl(Features, "movbe", true); 260 break; 261 case CK_K6_2: 262 case CK_K6_3: 263 case CK_WinChip2: 264 case CK_C3: 265 setFeatureEnabledImpl(Features, "3dnow", true); 266 break; 267 case CK_Athlon: 268 case CK_AthlonThunderbird: 269 case CK_Geode: 270 setFeatureEnabledImpl(Features, "3dnowa", true); 271 break; 272 case CK_Athlon4: 273 case CK_AthlonXP: 274 case CK_AthlonMP: 275 setFeatureEnabledImpl(Features, "sse", true); 276 setFeatureEnabledImpl(Features, "3dnowa", true); 277 setFeatureEnabledImpl(Features, "fxsr", true); 278 break; 279 case CK_K8: 280 case CK_Opteron: 281 case CK_Athlon64: 282 case CK_AthlonFX: 283 setFeatureEnabledImpl(Features, "sse2", true); 284 setFeatureEnabledImpl(Features, "3dnowa", true); 285 setFeatureEnabledImpl(Features, "fxsr", true); 286 break; 287 case CK_AMDFAM10: 288 setFeatureEnabledImpl(Features, "sse4a", true); 289 setFeatureEnabledImpl(Features, "lzcnt", true); 290 setFeatureEnabledImpl(Features, "popcnt", true); 291 LLVM_FALLTHROUGH; 292 case CK_K8SSE3: 293 case CK_OpteronSSE3: 294 case CK_Athlon64SSE3: 295 setFeatureEnabledImpl(Features, "sse3", true); 296 setFeatureEnabledImpl(Features, "3dnowa", true); 297 setFeatureEnabledImpl(Features, "fxsr", true); 298 break; 299 case CK_BTVER2: 300 setFeatureEnabledImpl(Features, "avx", true); 301 setFeatureEnabledImpl(Features, "aes", true); 302 setFeatureEnabledImpl(Features, "pclmul", true); 303 setFeatureEnabledImpl(Features, "bmi", true); 304 setFeatureEnabledImpl(Features, "f16c", true); 305 setFeatureEnabledImpl(Features, "xsaveopt", true); 306 setFeatureEnabledImpl(Features, "movbe", true); 307 LLVM_FALLTHROUGH; 308 case CK_BTVER1: 309 setFeatureEnabledImpl(Features, "ssse3", true); 310 setFeatureEnabledImpl(Features, "sse4a", true); 311 setFeatureEnabledImpl(Features, "lzcnt", true); 312 setFeatureEnabledImpl(Features, "popcnt", true); 313 setFeatureEnabledImpl(Features, "prfchw", true); 314 setFeatureEnabledImpl(Features, "cx16", true); 315 setFeatureEnabledImpl(Features, "fxsr", true); 316 break; 317 case CK_ZNVER1: 318 setFeatureEnabledImpl(Features, "adx", true); 319 setFeatureEnabledImpl(Features, "aes", true); 320 setFeatureEnabledImpl(Features, "avx2", true); 321 setFeatureEnabledImpl(Features, "bmi", true); 322 setFeatureEnabledImpl(Features, "bmi2", true); 323 setFeatureEnabledImpl(Features, "clflushopt", true); 324 setFeatureEnabledImpl(Features, "clzero", true); 325 setFeatureEnabledImpl(Features, "cx16", true); 326 setFeatureEnabledImpl(Features, "f16c", true); 327 setFeatureEnabledImpl(Features, "fma", true); 328 setFeatureEnabledImpl(Features, "fsgsbase", true); 329 setFeatureEnabledImpl(Features, "fxsr", true); 330 setFeatureEnabledImpl(Features, "lzcnt", true); 331 setFeatureEnabledImpl(Features, "mwaitx", true); 332 setFeatureEnabledImpl(Features, "movbe", true); 333 setFeatureEnabledImpl(Features, "pclmul", true); 334 setFeatureEnabledImpl(Features, "popcnt", true); 335 setFeatureEnabledImpl(Features, "prfchw", true); 336 setFeatureEnabledImpl(Features, "rdrnd", true); 337 setFeatureEnabledImpl(Features, "rdseed", true); 338 setFeatureEnabledImpl(Features, "sha", true); 339 setFeatureEnabledImpl(Features, "sse4a", true); 340 setFeatureEnabledImpl(Features, "xsave", true); 341 setFeatureEnabledImpl(Features, "xsavec", true); 342 setFeatureEnabledImpl(Features, "xsaveopt", true); 343 setFeatureEnabledImpl(Features, "xsaves", true); 344 break; 345 case CK_BDVER4: 346 setFeatureEnabledImpl(Features, "avx2", true); 347 setFeatureEnabledImpl(Features, "bmi2", true); 348 setFeatureEnabledImpl(Features, "mwaitx", true); 349 LLVM_FALLTHROUGH; 350 case CK_BDVER3: 351 setFeatureEnabledImpl(Features, "fsgsbase", true); 352 setFeatureEnabledImpl(Features, "xsaveopt", true); 353 LLVM_FALLTHROUGH; 354 case CK_BDVER2: 355 setFeatureEnabledImpl(Features, "bmi", true); 356 setFeatureEnabledImpl(Features, "fma", true); 357 setFeatureEnabledImpl(Features, "f16c", true); 358 setFeatureEnabledImpl(Features, "tbm", true); 359 LLVM_FALLTHROUGH; 360 case CK_BDVER1: 361 // xop implies avx, sse4a and fma4. 362 setFeatureEnabledImpl(Features, "xop", true); 363 setFeatureEnabledImpl(Features, "lwp", true); 364 setFeatureEnabledImpl(Features, "lzcnt", true); 365 setFeatureEnabledImpl(Features, "aes", true); 366 setFeatureEnabledImpl(Features, "pclmul", true); 367 setFeatureEnabledImpl(Features, "prfchw", true); 368 setFeatureEnabledImpl(Features, "cx16", true); 369 setFeatureEnabledImpl(Features, "fxsr", true); 370 setFeatureEnabledImpl(Features, "xsave", true); 371 break; 372 } 373 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 374 return false; 375 376 // Can't do this earlier because we need to be able to explicitly enable 377 // or disable these features and the things that they depend upon. 378 379 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 380 auto I = Features.find("sse4.2"); 381 if (I != Features.end() && I->getValue() && 382 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 383 FeaturesVec.end()) 384 Features["popcnt"] = true; 385 386 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 387 I = Features.find("3dnow"); 388 if (I != Features.end() && I->getValue() && 389 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 390 FeaturesVec.end()) 391 Features["prfchw"] = true; 392 393 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 394 // then enable MMX. 395 I = Features.find("sse"); 396 if (I != Features.end() && I->getValue() && 397 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 398 FeaturesVec.end()) 399 Features["mmx"] = true; 400 401 return true; 402 } 403 404 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 405 X86SSEEnum Level, bool Enabled) { 406 if (Enabled) { 407 switch (Level) { 408 case AVX512F: 409 Features["avx512f"] = true; 410 LLVM_FALLTHROUGH; 411 case AVX2: 412 Features["avx2"] = true; 413 LLVM_FALLTHROUGH; 414 case AVX: 415 Features["avx"] = true; 416 Features["xsave"] = true; 417 LLVM_FALLTHROUGH; 418 case SSE42: 419 Features["sse4.2"] = true; 420 LLVM_FALLTHROUGH; 421 case SSE41: 422 Features["sse4.1"] = true; 423 LLVM_FALLTHROUGH; 424 case SSSE3: 425 Features["ssse3"] = true; 426 LLVM_FALLTHROUGH; 427 case SSE3: 428 Features["sse3"] = true; 429 LLVM_FALLTHROUGH; 430 case SSE2: 431 Features["sse2"] = true; 432 LLVM_FALLTHROUGH; 433 case SSE1: 434 Features["sse"] = true; 435 LLVM_FALLTHROUGH; 436 case NoSSE: 437 break; 438 } 439 return; 440 } 441 442 switch (Level) { 443 case NoSSE: 444 case SSE1: 445 Features["sse"] = false; 446 LLVM_FALLTHROUGH; 447 case SSE2: 448 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 449 false; 450 LLVM_FALLTHROUGH; 451 case SSE3: 452 Features["sse3"] = false; 453 setXOPLevel(Features, NoXOP, false); 454 LLVM_FALLTHROUGH; 455 case SSSE3: 456 Features["ssse3"] = false; 457 LLVM_FALLTHROUGH; 458 case SSE41: 459 Features["sse4.1"] = false; 460 LLVM_FALLTHROUGH; 461 case SSE42: 462 Features["sse4.2"] = false; 463 LLVM_FALLTHROUGH; 464 case AVX: 465 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 466 Features["xsaveopt"] = false; 467 setXOPLevel(Features, FMA4, false); 468 LLVM_FALLTHROUGH; 469 case AVX2: 470 Features["avx2"] = false; 471 LLVM_FALLTHROUGH; 472 case AVX512F: 473 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 474 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 475 Features["avx512vl"] = Features["avx512vbmi"] = 476 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 477 break; 478 } 479 } 480 481 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 482 MMX3DNowEnum Level, bool Enabled) { 483 if (Enabled) { 484 switch (Level) { 485 case AMD3DNowAthlon: 486 Features["3dnowa"] = true; 487 LLVM_FALLTHROUGH; 488 case AMD3DNow: 489 Features["3dnow"] = true; 490 LLVM_FALLTHROUGH; 491 case MMX: 492 Features["mmx"] = true; 493 LLVM_FALLTHROUGH; 494 case NoMMX3DNow: 495 break; 496 } 497 return; 498 } 499 500 switch (Level) { 501 case NoMMX3DNow: 502 case MMX: 503 Features["mmx"] = false; 504 LLVM_FALLTHROUGH; 505 case AMD3DNow: 506 Features["3dnow"] = false; 507 LLVM_FALLTHROUGH; 508 case AMD3DNowAthlon: 509 Features["3dnowa"] = false; 510 break; 511 } 512 } 513 514 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 515 bool Enabled) { 516 if (Enabled) { 517 switch (Level) { 518 case XOP: 519 Features["xop"] = true; 520 LLVM_FALLTHROUGH; 521 case FMA4: 522 Features["fma4"] = true; 523 setSSELevel(Features, AVX, true); 524 LLVM_FALLTHROUGH; 525 case SSE4A: 526 Features["sse4a"] = true; 527 setSSELevel(Features, SSE3, true); 528 LLVM_FALLTHROUGH; 529 case NoXOP: 530 break; 531 } 532 return; 533 } 534 535 switch (Level) { 536 case NoXOP: 537 case SSE4A: 538 Features["sse4a"] = false; 539 LLVM_FALLTHROUGH; 540 case FMA4: 541 Features["fma4"] = false; 542 LLVM_FALLTHROUGH; 543 case XOP: 544 Features["xop"] = false; 545 break; 546 } 547 } 548 549 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 550 StringRef Name, bool Enabled) { 551 // This is a bit of a hack to deal with the sse4 target feature when used 552 // as part of the target attribute. We handle sse4 correctly everywhere 553 // else. See below for more information on how we handle the sse4 options. 554 if (Name != "sse4") 555 Features[Name] = Enabled; 556 557 if (Name == "mmx") { 558 setMMXLevel(Features, MMX, Enabled); 559 } else if (Name == "sse") { 560 setSSELevel(Features, SSE1, Enabled); 561 } else if (Name == "sse2") { 562 setSSELevel(Features, SSE2, Enabled); 563 } else if (Name == "sse3") { 564 setSSELevel(Features, SSE3, Enabled); 565 } else if (Name == "ssse3") { 566 setSSELevel(Features, SSSE3, Enabled); 567 } else if (Name == "sse4.2") { 568 setSSELevel(Features, SSE42, Enabled); 569 } else if (Name == "sse4.1") { 570 setSSELevel(Features, SSE41, Enabled); 571 } else if (Name == "3dnow") { 572 setMMXLevel(Features, AMD3DNow, Enabled); 573 } else if (Name == "3dnowa") { 574 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 575 } else if (Name == "aes") { 576 if (Enabled) 577 setSSELevel(Features, SSE2, Enabled); 578 } else if (Name == "pclmul") { 579 if (Enabled) 580 setSSELevel(Features, SSE2, Enabled); 581 } else if (Name == "avx") { 582 setSSELevel(Features, AVX, Enabled); 583 } else if (Name == "avx2") { 584 setSSELevel(Features, AVX2, Enabled); 585 } else if (Name == "avx512f") { 586 setSSELevel(Features, AVX512F, Enabled); 587 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 588 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 589 Name == "avx512vbmi" || Name == "avx512ifma" || 590 Name == "avx512vpopcntdq") { 591 if (Enabled) 592 setSSELevel(Features, AVX512F, Enabled); 593 // Enable BWI instruction if VBMI is being enabled. 594 if (Name == "avx512vbmi" && Enabled) 595 Features["avx512bw"] = true; 596 // Also disable VBMI if BWI is being disabled. 597 if (Name == "avx512bw" && !Enabled) 598 Features["avx512vbmi"] = false; 599 } else if (Name == "fma") { 600 if (Enabled) 601 setSSELevel(Features, AVX, Enabled); 602 } else if (Name == "fma4") { 603 setXOPLevel(Features, FMA4, Enabled); 604 } else if (Name == "xop") { 605 setXOPLevel(Features, XOP, Enabled); 606 } else if (Name == "sse4a") { 607 setXOPLevel(Features, SSE4A, Enabled); 608 } else if (Name == "f16c") { 609 if (Enabled) 610 setSSELevel(Features, AVX, Enabled); 611 } else if (Name == "sha") { 612 if (Enabled) 613 setSSELevel(Features, SSE2, Enabled); 614 } else if (Name == "sse4") { 615 // We can get here via the __target__ attribute since that's not controlled 616 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 617 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 618 // disabled. 619 if (Enabled) 620 setSSELevel(Features, SSE42, Enabled); 621 else 622 setSSELevel(Features, SSE41, Enabled); 623 } else if (Name == "xsave") { 624 if (!Enabled) 625 Features["xsaveopt"] = false; 626 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 627 if (Enabled) 628 Features["xsave"] = true; 629 } 630 } 631 632 /// handleTargetFeatures - Perform initialization based on the user 633 /// configured set of features. 634 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 635 DiagnosticsEngine &Diags) { 636 for (const auto &Feature : Features) { 637 if (Feature[0] != '+') 638 continue; 639 640 if (Feature == "+aes") { 641 HasAES = true; 642 } else if (Feature == "+pclmul") { 643 HasPCLMUL = true; 644 } else if (Feature == "+lzcnt") { 645 HasLZCNT = true; 646 } else if (Feature == "+rdrnd") { 647 HasRDRND = true; 648 } else if (Feature == "+fsgsbase") { 649 HasFSGSBASE = true; 650 } else if (Feature == "+bmi") { 651 HasBMI = true; 652 } else if (Feature == "+bmi2") { 653 HasBMI2 = true; 654 } else if (Feature == "+popcnt") { 655 HasPOPCNT = true; 656 } else if (Feature == "+rtm") { 657 HasRTM = true; 658 } else if (Feature == "+prfchw") { 659 HasPRFCHW = true; 660 } else if (Feature == "+rdseed") { 661 HasRDSEED = true; 662 } else if (Feature == "+adx") { 663 HasADX = true; 664 } else if (Feature == "+tbm") { 665 HasTBM = true; 666 } else if (Feature == "+lwp") { 667 HasLWP = true; 668 } else if (Feature == "+fma") { 669 HasFMA = true; 670 } else if (Feature == "+f16c") { 671 HasF16C = true; 672 } else if (Feature == "+avx512cd") { 673 HasAVX512CD = true; 674 } else if (Feature == "+avx512vpopcntdq") { 675 HasAVX512VPOPCNTDQ = true; 676 } else if (Feature == "+avx512er") { 677 HasAVX512ER = true; 678 } else if (Feature == "+avx512pf") { 679 HasAVX512PF = true; 680 } else if (Feature == "+avx512dq") { 681 HasAVX512DQ = true; 682 } else if (Feature == "+avx512bw") { 683 HasAVX512BW = true; 684 } else if (Feature == "+avx512vl") { 685 HasAVX512VL = true; 686 } else if (Feature == "+avx512vbmi") { 687 HasAVX512VBMI = true; 688 } else if (Feature == "+avx512ifma") { 689 HasAVX512IFMA = true; 690 } else if (Feature == "+sha") { 691 HasSHA = true; 692 } else if (Feature == "+mpx") { 693 HasMPX = true; 694 } else if (Feature == "+movbe") { 695 HasMOVBE = true; 696 } else if (Feature == "+sgx") { 697 HasSGX = true; 698 } else if (Feature == "+cx16") { 699 HasCX16 = true; 700 } else if (Feature == "+fxsr") { 701 HasFXSR = true; 702 } else if (Feature == "+xsave") { 703 HasXSAVE = true; 704 } else if (Feature == "+xsaveopt") { 705 HasXSAVEOPT = true; 706 } else if (Feature == "+xsavec") { 707 HasXSAVEC = true; 708 } else if (Feature == "+xsaves") { 709 HasXSAVES = true; 710 } else if (Feature == "+mwaitx") { 711 HasMWAITX = true; 712 } else if (Feature == "+pku") { 713 HasPKU = true; 714 } else if (Feature == "+clflushopt") { 715 HasCLFLUSHOPT = true; 716 } else if (Feature == "+clwb") { 717 HasCLWB = true; 718 } else if (Feature == "+prefetchwt1") { 719 HasPREFETCHWT1 = true; 720 } else if (Feature == "+clzero") { 721 HasCLZERO = true; 722 } 723 724 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 725 .Case("+avx512f", AVX512F) 726 .Case("+avx2", AVX2) 727 .Case("+avx", AVX) 728 .Case("+sse4.2", SSE42) 729 .Case("+sse4.1", SSE41) 730 .Case("+ssse3", SSSE3) 731 .Case("+sse3", SSE3) 732 .Case("+sse2", SSE2) 733 .Case("+sse", SSE1) 734 .Default(NoSSE); 735 SSELevel = std::max(SSELevel, Level); 736 737 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 738 .Case("+3dnowa", AMD3DNowAthlon) 739 .Case("+3dnow", AMD3DNow) 740 .Case("+mmx", MMX) 741 .Default(NoMMX3DNow); 742 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 743 744 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 745 .Case("+xop", XOP) 746 .Case("+fma4", FMA4) 747 .Case("+sse4a", SSE4A) 748 .Default(NoXOP); 749 XOPLevel = std::max(XOPLevel, XLevel); 750 } 751 752 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 753 // matches the selected sse level. 754 if ((FPMath == FP_SSE && SSELevel < SSE1) || 755 (FPMath == FP_387 && SSELevel >= SSE1)) { 756 Diags.Report(diag::err_target_unsupported_fpmath) 757 << (FPMath == FP_SSE ? "sse" : "387"); 758 return false; 759 } 760 761 SimdDefaultAlign = 762 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 763 return true; 764 } 765 766 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 767 /// definitions for this particular subtarget. 768 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 769 MacroBuilder &Builder) const { 770 // Target identification. 771 if (getTriple().getArch() == llvm::Triple::x86_64) { 772 Builder.defineMacro("__amd64__"); 773 Builder.defineMacro("__amd64"); 774 Builder.defineMacro("__x86_64"); 775 Builder.defineMacro("__x86_64__"); 776 if (getTriple().getArchName() == "x86_64h") { 777 Builder.defineMacro("__x86_64h"); 778 Builder.defineMacro("__x86_64h__"); 779 } 780 } else { 781 DefineStd(Builder, "i386", Opts); 782 } 783 784 // Subtarget options. 785 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 786 // truly should be based on -mtune options. 787 switch (CPU) { 788 case CK_Generic: 789 break; 790 case CK_i386: 791 // The rest are coming from the i386 define above. 792 Builder.defineMacro("__tune_i386__"); 793 break; 794 case CK_i486: 795 case CK_WinChipC6: 796 case CK_WinChip2: 797 case CK_C3: 798 defineCPUMacros(Builder, "i486"); 799 break; 800 case CK_PentiumMMX: 801 Builder.defineMacro("__pentium_mmx__"); 802 Builder.defineMacro("__tune_pentium_mmx__"); 803 LLVM_FALLTHROUGH; 804 case CK_i586: 805 case CK_Pentium: 806 defineCPUMacros(Builder, "i586"); 807 defineCPUMacros(Builder, "pentium"); 808 break; 809 case CK_Pentium3: 810 case CK_Pentium3M: 811 case CK_PentiumM: 812 Builder.defineMacro("__tune_pentium3__"); 813 LLVM_FALLTHROUGH; 814 case CK_Pentium2: 815 case CK_C3_2: 816 Builder.defineMacro("__tune_pentium2__"); 817 LLVM_FALLTHROUGH; 818 case CK_PentiumPro: 819 Builder.defineMacro("__tune_i686__"); 820 Builder.defineMacro("__tune_pentiumpro__"); 821 LLVM_FALLTHROUGH; 822 case CK_i686: 823 Builder.defineMacro("__i686"); 824 Builder.defineMacro("__i686__"); 825 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 826 Builder.defineMacro("__pentiumpro"); 827 Builder.defineMacro("__pentiumpro__"); 828 break; 829 case CK_Pentium4: 830 case CK_Pentium4M: 831 defineCPUMacros(Builder, "pentium4"); 832 break; 833 case CK_Yonah: 834 case CK_Prescott: 835 case CK_Nocona: 836 defineCPUMacros(Builder, "nocona"); 837 break; 838 case CK_Core2: 839 case CK_Penryn: 840 defineCPUMacros(Builder, "core2"); 841 break; 842 case CK_Bonnell: 843 defineCPUMacros(Builder, "atom"); 844 break; 845 case CK_Silvermont: 846 defineCPUMacros(Builder, "slm"); 847 break; 848 case CK_Goldmont: 849 defineCPUMacros(Builder, "goldmont"); 850 break; 851 case CK_Nehalem: 852 case CK_Westmere: 853 case CK_SandyBridge: 854 case CK_IvyBridge: 855 case CK_Haswell: 856 case CK_Broadwell: 857 case CK_SkylakeClient: 858 // FIXME: Historically, we defined this legacy name, it would be nice to 859 // remove it at some point. We've never exposed fine-grained names for 860 // recent primary x86 CPUs, and we should keep it that way. 861 defineCPUMacros(Builder, "corei7"); 862 break; 863 case CK_SkylakeServer: 864 defineCPUMacros(Builder, "skx"); 865 break; 866 case CK_Cannonlake: 867 break; 868 case CK_KNL: 869 defineCPUMacros(Builder, "knl"); 870 break; 871 case CK_Lakemont: 872 Builder.defineMacro("__tune_lakemont__"); 873 break; 874 case CK_K6_2: 875 Builder.defineMacro("__k6_2__"); 876 Builder.defineMacro("__tune_k6_2__"); 877 LLVM_FALLTHROUGH; 878 case CK_K6_3: 879 if (CPU != CK_K6_2) { // In case of fallthrough 880 // FIXME: GCC may be enabling these in cases where some other k6 881 // architecture is specified but -m3dnow is explicitly provided. The 882 // exact semantics need to be determined and emulated here. 883 Builder.defineMacro("__k6_3__"); 884 Builder.defineMacro("__tune_k6_3__"); 885 } 886 LLVM_FALLTHROUGH; 887 case CK_K6: 888 defineCPUMacros(Builder, "k6"); 889 break; 890 case CK_Athlon: 891 case CK_AthlonThunderbird: 892 case CK_Athlon4: 893 case CK_AthlonXP: 894 case CK_AthlonMP: 895 defineCPUMacros(Builder, "athlon"); 896 if (SSELevel != NoSSE) { 897 Builder.defineMacro("__athlon_sse__"); 898 Builder.defineMacro("__tune_athlon_sse__"); 899 } 900 break; 901 case CK_K8: 902 case CK_K8SSE3: 903 case CK_x86_64: 904 case CK_Opteron: 905 case CK_OpteronSSE3: 906 case CK_Athlon64: 907 case CK_Athlon64SSE3: 908 case CK_AthlonFX: 909 defineCPUMacros(Builder, "k8"); 910 break; 911 case CK_AMDFAM10: 912 defineCPUMacros(Builder, "amdfam10"); 913 break; 914 case CK_BTVER1: 915 defineCPUMacros(Builder, "btver1"); 916 break; 917 case CK_BTVER2: 918 defineCPUMacros(Builder, "btver2"); 919 break; 920 case CK_BDVER1: 921 defineCPUMacros(Builder, "bdver1"); 922 break; 923 case CK_BDVER2: 924 defineCPUMacros(Builder, "bdver2"); 925 break; 926 case CK_BDVER3: 927 defineCPUMacros(Builder, "bdver3"); 928 break; 929 case CK_BDVER4: 930 defineCPUMacros(Builder, "bdver4"); 931 break; 932 case CK_ZNVER1: 933 defineCPUMacros(Builder, "znver1"); 934 break; 935 case CK_Geode: 936 defineCPUMacros(Builder, "geode"); 937 break; 938 } 939 940 // Target properties. 941 Builder.defineMacro("__REGISTER_PREFIX__", ""); 942 943 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 944 // functions in glibc header files that use FP Stack inline asm which the 945 // backend can't deal with (PR879). 946 Builder.defineMacro("__NO_MATH_INLINES"); 947 948 if (HasAES) 949 Builder.defineMacro("__AES__"); 950 951 if (HasPCLMUL) 952 Builder.defineMacro("__PCLMUL__"); 953 954 if (HasLZCNT) 955 Builder.defineMacro("__LZCNT__"); 956 957 if (HasRDRND) 958 Builder.defineMacro("__RDRND__"); 959 960 if (HasFSGSBASE) 961 Builder.defineMacro("__FSGSBASE__"); 962 963 if (HasBMI) 964 Builder.defineMacro("__BMI__"); 965 966 if (HasBMI2) 967 Builder.defineMacro("__BMI2__"); 968 969 if (HasPOPCNT) 970 Builder.defineMacro("__POPCNT__"); 971 972 if (HasRTM) 973 Builder.defineMacro("__RTM__"); 974 975 if (HasPRFCHW) 976 Builder.defineMacro("__PRFCHW__"); 977 978 if (HasRDSEED) 979 Builder.defineMacro("__RDSEED__"); 980 981 if (HasADX) 982 Builder.defineMacro("__ADX__"); 983 984 if (HasTBM) 985 Builder.defineMacro("__TBM__"); 986 987 if (HasLWP) 988 Builder.defineMacro("__LWP__"); 989 990 if (HasMWAITX) 991 Builder.defineMacro("__MWAITX__"); 992 993 switch (XOPLevel) { 994 case XOP: 995 Builder.defineMacro("__XOP__"); 996 LLVM_FALLTHROUGH; 997 case FMA4: 998 Builder.defineMacro("__FMA4__"); 999 LLVM_FALLTHROUGH; 1000 case SSE4A: 1001 Builder.defineMacro("__SSE4A__"); 1002 LLVM_FALLTHROUGH; 1003 case NoXOP: 1004 break; 1005 } 1006 1007 if (HasFMA) 1008 Builder.defineMacro("__FMA__"); 1009 1010 if (HasF16C) 1011 Builder.defineMacro("__F16C__"); 1012 1013 if (HasAVX512CD) 1014 Builder.defineMacro("__AVX512CD__"); 1015 if (HasAVX512VPOPCNTDQ) 1016 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1017 if (HasAVX512ER) 1018 Builder.defineMacro("__AVX512ER__"); 1019 if (HasAVX512PF) 1020 Builder.defineMacro("__AVX512PF__"); 1021 if (HasAVX512DQ) 1022 Builder.defineMacro("__AVX512DQ__"); 1023 if (HasAVX512BW) 1024 Builder.defineMacro("__AVX512BW__"); 1025 if (HasAVX512VL) 1026 Builder.defineMacro("__AVX512VL__"); 1027 if (HasAVX512VBMI) 1028 Builder.defineMacro("__AVX512VBMI__"); 1029 if (HasAVX512IFMA) 1030 Builder.defineMacro("__AVX512IFMA__"); 1031 1032 if (HasSHA) 1033 Builder.defineMacro("__SHA__"); 1034 1035 if (HasFXSR) 1036 Builder.defineMacro("__FXSR__"); 1037 if (HasXSAVE) 1038 Builder.defineMacro("__XSAVE__"); 1039 if (HasXSAVEOPT) 1040 Builder.defineMacro("__XSAVEOPT__"); 1041 if (HasXSAVEC) 1042 Builder.defineMacro("__XSAVEC__"); 1043 if (HasXSAVES) 1044 Builder.defineMacro("__XSAVES__"); 1045 if (HasPKU) 1046 Builder.defineMacro("__PKU__"); 1047 if (HasCX16) 1048 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1049 if (HasCLFLUSHOPT) 1050 Builder.defineMacro("__CLFLUSHOPT__"); 1051 if (HasCLWB) 1052 Builder.defineMacro("__CLWB__"); 1053 if (HasMPX) 1054 Builder.defineMacro("__MPX__"); 1055 if (HasSGX) 1056 Builder.defineMacro("__SGX__"); 1057 if (HasPREFETCHWT1) 1058 Builder.defineMacro("__PREFETCHWT1__"); 1059 if (HasCLZERO) 1060 Builder.defineMacro("__CLZERO__"); 1061 1062 // Each case falls through to the previous one here. 1063 switch (SSELevel) { 1064 case AVX512F: 1065 Builder.defineMacro("__AVX512F__"); 1066 LLVM_FALLTHROUGH; 1067 case AVX2: 1068 Builder.defineMacro("__AVX2__"); 1069 LLVM_FALLTHROUGH; 1070 case AVX: 1071 Builder.defineMacro("__AVX__"); 1072 LLVM_FALLTHROUGH; 1073 case SSE42: 1074 Builder.defineMacro("__SSE4_2__"); 1075 LLVM_FALLTHROUGH; 1076 case SSE41: 1077 Builder.defineMacro("__SSE4_1__"); 1078 LLVM_FALLTHROUGH; 1079 case SSSE3: 1080 Builder.defineMacro("__SSSE3__"); 1081 LLVM_FALLTHROUGH; 1082 case SSE3: 1083 Builder.defineMacro("__SSE3__"); 1084 LLVM_FALLTHROUGH; 1085 case SSE2: 1086 Builder.defineMacro("__SSE2__"); 1087 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1088 LLVM_FALLTHROUGH; 1089 case SSE1: 1090 Builder.defineMacro("__SSE__"); 1091 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1092 LLVM_FALLTHROUGH; 1093 case NoSSE: 1094 break; 1095 } 1096 1097 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1098 switch (SSELevel) { 1099 case AVX512F: 1100 case AVX2: 1101 case AVX: 1102 case SSE42: 1103 case SSE41: 1104 case SSSE3: 1105 case SSE3: 1106 case SSE2: 1107 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1108 break; 1109 case SSE1: 1110 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1111 break; 1112 default: 1113 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1114 break; 1115 } 1116 } 1117 1118 // Each case falls through to the previous one here. 1119 switch (MMX3DNowLevel) { 1120 case AMD3DNowAthlon: 1121 Builder.defineMacro("__3dNOW_A__"); 1122 LLVM_FALLTHROUGH; 1123 case AMD3DNow: 1124 Builder.defineMacro("__3dNOW__"); 1125 LLVM_FALLTHROUGH; 1126 case MMX: 1127 Builder.defineMacro("__MMX__"); 1128 LLVM_FALLTHROUGH; 1129 case NoMMX3DNow: 1130 break; 1131 } 1132 1133 if (CPU >= CK_i486) { 1134 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1135 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1136 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1137 } 1138 if (CPU >= CK_i586) 1139 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1140 1141 if (HasFloat128) 1142 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1143 } 1144 1145 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1146 return llvm::StringSwitch<bool>(Name) 1147 .Case("aes", true) 1148 .Case("avx", true) 1149 .Case("avx2", true) 1150 .Case("avx512f", true) 1151 .Case("avx512cd", true) 1152 .Case("avx512vpopcntdq", true) 1153 .Case("avx512er", true) 1154 .Case("avx512pf", true) 1155 .Case("avx512dq", true) 1156 .Case("avx512bw", true) 1157 .Case("avx512vl", true) 1158 .Case("avx512vbmi", true) 1159 .Case("avx512ifma", true) 1160 .Case("bmi", true) 1161 .Case("bmi2", true) 1162 .Case("clflushopt", true) 1163 .Case("clwb", true) 1164 .Case("clzero", true) 1165 .Case("cx16", true) 1166 .Case("f16c", true) 1167 .Case("fma", true) 1168 .Case("fma4", true) 1169 .Case("fsgsbase", true) 1170 .Case("fxsr", true) 1171 .Case("lwp", true) 1172 .Case("lzcnt", true) 1173 .Case("mm3dnow", true) 1174 .Case("mm3dnowa", true) 1175 .Case("mmx", true) 1176 .Case("movbe", true) 1177 .Case("mpx", true) 1178 .Case("pclmul", true) 1179 .Case("pku", true) 1180 .Case("popcnt", true) 1181 .Case("prefetchwt1", true) 1182 .Case("prfchw", true) 1183 .Case("rdrnd", true) 1184 .Case("rdseed", true) 1185 .Case("rtm", true) 1186 .Case("sgx", true) 1187 .Case("sha", true) 1188 .Case("sse", true) 1189 .Case("sse2", true) 1190 .Case("sse3", true) 1191 .Case("ssse3", true) 1192 .Case("sse4.1", true) 1193 .Case("sse4.2", true) 1194 .Case("sse4a", true) 1195 .Case("tbm", true) 1196 .Case("x86", true) 1197 .Case("x86_32", true) 1198 .Case("x86_64", true) 1199 .Case("xop", true) 1200 .Case("xsave", true) 1201 .Case("xsavec", true) 1202 .Case("xsaves", true) 1203 .Case("xsaveopt", true) 1204 .Default(false); 1205 } 1206 1207 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1208 return llvm::StringSwitch<bool>(Feature) 1209 .Case("aes", HasAES) 1210 .Case("avx", SSELevel >= AVX) 1211 .Case("avx2", SSELevel >= AVX2) 1212 .Case("avx512f", SSELevel >= AVX512F) 1213 .Case("avx512cd", HasAVX512CD) 1214 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1215 .Case("avx512er", HasAVX512ER) 1216 .Case("avx512pf", HasAVX512PF) 1217 .Case("avx512dq", HasAVX512DQ) 1218 .Case("avx512bw", HasAVX512BW) 1219 .Case("avx512vl", HasAVX512VL) 1220 .Case("avx512vbmi", HasAVX512VBMI) 1221 .Case("avx512ifma", HasAVX512IFMA) 1222 .Case("bmi", HasBMI) 1223 .Case("bmi2", HasBMI2) 1224 .Case("clflushopt", HasCLFLUSHOPT) 1225 .Case("clwb", HasCLWB) 1226 .Case("clzero", HasCLZERO) 1227 .Case("cx16", HasCX16) 1228 .Case("f16c", HasF16C) 1229 .Case("fma", HasFMA) 1230 .Case("fma4", XOPLevel >= FMA4) 1231 .Case("fsgsbase", HasFSGSBASE) 1232 .Case("fxsr", HasFXSR) 1233 .Case("lwp", HasLWP) 1234 .Case("lzcnt", HasLZCNT) 1235 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1236 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1237 .Case("mmx", MMX3DNowLevel >= MMX) 1238 .Case("movbe", HasMOVBE) 1239 .Case("mpx", HasMPX) 1240 .Case("pclmul", HasPCLMUL) 1241 .Case("pku", HasPKU) 1242 .Case("popcnt", HasPOPCNT) 1243 .Case("prefetchwt1", HasPREFETCHWT1) 1244 .Case("prfchw", HasPRFCHW) 1245 .Case("rdrnd", HasRDRND) 1246 .Case("rdseed", HasRDSEED) 1247 .Case("rtm", HasRTM) 1248 .Case("sgx", HasSGX) 1249 .Case("sha", HasSHA) 1250 .Case("sse", SSELevel >= SSE1) 1251 .Case("sse2", SSELevel >= SSE2) 1252 .Case("sse3", SSELevel >= SSE3) 1253 .Case("ssse3", SSELevel >= SSSE3) 1254 .Case("sse4.1", SSELevel >= SSE41) 1255 .Case("sse4.2", SSELevel >= SSE42) 1256 .Case("sse4a", XOPLevel >= SSE4A) 1257 .Case("tbm", HasTBM) 1258 .Case("x86", true) 1259 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1260 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1261 .Case("xop", XOPLevel >= XOP) 1262 .Case("xsave", HasXSAVE) 1263 .Case("xsavec", HasXSAVEC) 1264 .Case("xsaves", HasXSAVES) 1265 .Case("xsaveopt", HasXSAVEOPT) 1266 .Default(false); 1267 } 1268 1269 // We can't use a generic validation scheme for the features accepted here 1270 // versus subtarget features accepted in the target attribute because the 1271 // bitfield structure that's initialized in the runtime only supports the 1272 // below currently rather than the full range of subtarget features. (See 1273 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1274 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1275 return llvm::StringSwitch<bool>(FeatureStr) 1276 .Case("cmov", true) 1277 .Case("mmx", true) 1278 .Case("popcnt", true) 1279 .Case("sse", true) 1280 .Case("sse2", true) 1281 .Case("sse3", true) 1282 .Case("ssse3", true) 1283 .Case("sse4.1", true) 1284 .Case("sse4.2", true) 1285 .Case("avx", true) 1286 .Case("avx2", true) 1287 .Case("sse4a", true) 1288 .Case("fma4", true) 1289 .Case("xop", true) 1290 .Case("fma", true) 1291 .Case("avx512f", true) 1292 .Case("bmi", true) 1293 .Case("bmi2", true) 1294 .Case("aes", true) 1295 .Case("pclmul", true) 1296 .Case("avx512vl", true) 1297 .Case("avx512bw", true) 1298 .Case("avx512dq", true) 1299 .Case("avx512cd", true) 1300 .Case("avx512er", true) 1301 .Case("avx512pf", true) 1302 .Case("avx512vbmi", true) 1303 .Case("avx512ifma", true) 1304 .Case("avx5124vnniw", true) 1305 .Case("avx5124fmaps", true) 1306 .Case("avx512vpopcntdq", true) 1307 .Default(false); 1308 } 1309 1310 // We can't use a generic validation scheme for the cpus accepted here 1311 // versus subtarget cpus accepted in the target attribute because the 1312 // variables intitialized by the runtime only support the below currently 1313 // rather than the full range of cpus. 1314 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1315 return llvm::StringSwitch<bool>(FeatureStr) 1316 .Case("amd", true) 1317 .Case("amdfam10h", true) 1318 .Case("amdfam15h", true) 1319 .Case("atom", true) 1320 .Case("barcelona", true) 1321 .Case("bdver1", true) 1322 .Case("bdver2", true) 1323 .Case("bdver3", true) 1324 .Case("bdver4", true) 1325 .Case("bonnell", true) 1326 .Case("broadwell", true) 1327 .Case("btver1", true) 1328 .Case("btver2", true) 1329 .Case("core2", true) 1330 .Case("corei7", true) 1331 .Case("haswell", true) 1332 .Case("intel", true) 1333 .Case("istanbul", true) 1334 .Case("ivybridge", true) 1335 .Case("knl", true) 1336 .Case("nehalem", true) 1337 .Case("sandybridge", true) 1338 .Case("shanghai", true) 1339 .Case("silvermont", true) 1340 .Case("skylake", true) 1341 .Case("skylake-avx512", true) 1342 .Case("slm", true) 1343 .Case("westmere", true) 1344 .Case("znver1", true) 1345 .Default(false); 1346 } 1347 1348 bool X86TargetInfo::validateAsmConstraint( 1349 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1350 switch (*Name) { 1351 default: 1352 return false; 1353 // Constant constraints. 1354 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1355 // instructions. 1356 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1357 // x86_64 instructions. 1358 case 's': 1359 Info.setRequiresImmediate(); 1360 return true; 1361 case 'I': 1362 Info.setRequiresImmediate(0, 31); 1363 return true; 1364 case 'J': 1365 Info.setRequiresImmediate(0, 63); 1366 return true; 1367 case 'K': 1368 Info.setRequiresImmediate(-128, 127); 1369 return true; 1370 case 'L': 1371 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1372 return true; 1373 case 'M': 1374 Info.setRequiresImmediate(0, 3); 1375 return true; 1376 case 'N': 1377 Info.setRequiresImmediate(0, 255); 1378 return true; 1379 case 'O': 1380 Info.setRequiresImmediate(0, 127); 1381 return true; 1382 // Register constraints. 1383 case 'Y': // 'Y' is the first character for several 2-character constraints. 1384 // Shift the pointer to the second character of the constraint. 1385 Name++; 1386 switch (*Name) { 1387 default: 1388 return false; 1389 case '0': // First SSE register. 1390 case 't': // Any SSE register, when SSE2 is enabled. 1391 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1392 case 'm': // Any MMX register, when inter-unit moves enabled. 1393 case 'k': // AVX512 arch mask registers: k1-k7. 1394 Info.setAllowsRegister(); 1395 return true; 1396 } 1397 case 'f': // Any x87 floating point stack register. 1398 // Constraint 'f' cannot be used for output operands. 1399 if (Info.ConstraintStr[0] == '=') 1400 return false; 1401 Info.setAllowsRegister(); 1402 return true; 1403 case 'a': // eax. 1404 case 'b': // ebx. 1405 case 'c': // ecx. 1406 case 'd': // edx. 1407 case 'S': // esi. 1408 case 'D': // edi. 1409 case 'A': // edx:eax. 1410 case 't': // Top of floating point stack. 1411 case 'u': // Second from top of floating point stack. 1412 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1413 case 'y': // Any MMX register. 1414 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1415 case 'x': // Any SSE register. 1416 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1417 // for intermideate k reg operations). 1418 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1419 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1420 case 'l': // "Index" registers: any general register that can be used as an 1421 // index in a base+index memory access. 1422 Info.setAllowsRegister(); 1423 return true; 1424 // Floating point constant constraints. 1425 case 'C': // SSE floating point constant. 1426 case 'G': // x87 floating point constant. 1427 return true; 1428 } 1429 } 1430 1431 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1432 unsigned Size) const { 1433 // Strip off constraint modifiers. 1434 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1435 Constraint = Constraint.substr(1); 1436 1437 return validateOperandSize(Constraint, Size); 1438 } 1439 1440 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1441 unsigned Size) const { 1442 return validateOperandSize(Constraint, Size); 1443 } 1444 1445 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1446 unsigned Size) const { 1447 switch (Constraint[0]) { 1448 default: 1449 break; 1450 case 'k': 1451 // Registers k0-k7 (AVX512) size limit is 64 bit. 1452 case 'y': 1453 return Size <= 64; 1454 case 'f': 1455 case 't': 1456 case 'u': 1457 return Size <= 128; 1458 case 'v': 1459 case 'x': 1460 if (SSELevel >= AVX512F) 1461 // 512-bit zmm registers can be used if target supports AVX512F. 1462 return Size <= 512U; 1463 else if (SSELevel >= AVX) 1464 // 256-bit ymm registers can be used if target supports AVX. 1465 return Size <= 256U; 1466 return Size <= 128U; 1467 case 'Y': 1468 // 'Y' is the first character for several 2-character constraints. 1469 switch (Constraint[1]) { 1470 default: 1471 break; 1472 case 'm': 1473 // 'Ym' is synonymous with 'y'. 1474 case 'k': 1475 return Size <= 64; 1476 case 'i': 1477 case 't': 1478 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 1479 if (SSELevel >= AVX512F) 1480 return Size <= 512U; 1481 else if (SSELevel >= AVX) 1482 return Size <= 256U; 1483 return SSELevel >= SSE2 && Size <= 128U; 1484 } 1485 } 1486 1487 return true; 1488 } 1489 1490 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1491 switch (*Constraint) { 1492 case 'a': 1493 return std::string("{ax}"); 1494 case 'b': 1495 return std::string("{bx}"); 1496 case 'c': 1497 return std::string("{cx}"); 1498 case 'd': 1499 return std::string("{dx}"); 1500 case 'S': 1501 return std::string("{si}"); 1502 case 'D': 1503 return std::string("{di}"); 1504 case 'p': // address 1505 return std::string("im"); 1506 case 't': // top of floating point stack. 1507 return std::string("{st}"); 1508 case 'u': // second from top of floating point stack. 1509 return std::string("{st(1)}"); // second from top of floating point stack. 1510 case 'Y': 1511 switch (Constraint[1]) { 1512 default: 1513 // Break from inner switch and fall through (copy single char), 1514 // continue parsing after copying the current constraint into 1515 // the return string. 1516 break; 1517 case 'k': 1518 // "^" hints llvm that this is a 2 letter constraint. 1519 // "Constraint++" is used to promote the string iterator 1520 // to the next constraint. 1521 return std::string("^") + std::string(Constraint++, 2); 1522 } 1523 LLVM_FALLTHROUGH; 1524 default: 1525 return std::string(1, *Constraint); 1526 } 1527 } 1528 1529 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1530 return llvm::StringSwitch<CPUKind>(CPU) 1531 .Case("i386", CK_i386) 1532 .Case("i486", CK_i486) 1533 .Case("winchip-c6", CK_WinChipC6) 1534 .Case("winchip2", CK_WinChip2) 1535 .Case("c3", CK_C3) 1536 .Case("i586", CK_i586) 1537 .Case("pentium", CK_Pentium) 1538 .Case("pentium-mmx", CK_PentiumMMX) 1539 .Case("i686", CK_i686) 1540 .Case("pentiumpro", CK_PentiumPro) 1541 .Case("pentium2", CK_Pentium2) 1542 .Case("pentium3", CK_Pentium3) 1543 .Case("pentium3m", CK_Pentium3M) 1544 .Case("pentium-m", CK_PentiumM) 1545 .Case("c3-2", CK_C3_2) 1546 .Case("yonah", CK_Yonah) 1547 .Case("pentium4", CK_Pentium4) 1548 .Case("pentium4m", CK_Pentium4M) 1549 .Case("prescott", CK_Prescott) 1550 .Case("nocona", CK_Nocona) 1551 .Case("core2", CK_Core2) 1552 .Case("penryn", CK_Penryn) 1553 .Case("bonnell", CK_Bonnell) 1554 .Case("atom", CK_Bonnell) // Legacy name. 1555 .Case("silvermont", CK_Silvermont) 1556 .Case("slm", CK_Silvermont) // Legacy name. 1557 .Case("goldmont", CK_Goldmont) 1558 .Case("nehalem", CK_Nehalem) 1559 .Case("corei7", CK_Nehalem) // Legacy name. 1560 .Case("westmere", CK_Westmere) 1561 .Case("sandybridge", CK_SandyBridge) 1562 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 1563 .Case("ivybridge", CK_IvyBridge) 1564 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 1565 .Case("haswell", CK_Haswell) 1566 .Case("core-avx2", CK_Haswell) // Legacy name. 1567 .Case("broadwell", CK_Broadwell) 1568 .Case("skylake", CK_SkylakeClient) 1569 .Case("skylake-avx512", CK_SkylakeServer) 1570 .Case("skx", CK_SkylakeServer) // Legacy name. 1571 .Case("cannonlake", CK_Cannonlake) 1572 .Case("knl", CK_KNL) 1573 .Case("lakemont", CK_Lakemont) 1574 .Case("k6", CK_K6) 1575 .Case("k6-2", CK_K6_2) 1576 .Case("k6-3", CK_K6_3) 1577 .Case("athlon", CK_Athlon) 1578 .Case("athlon-tbird", CK_AthlonThunderbird) 1579 .Case("athlon-4", CK_Athlon4) 1580 .Case("athlon-xp", CK_AthlonXP) 1581 .Case("athlon-mp", CK_AthlonMP) 1582 .Case("athlon64", CK_Athlon64) 1583 .Case("athlon64-sse3", CK_Athlon64SSE3) 1584 .Case("athlon-fx", CK_AthlonFX) 1585 .Case("k8", CK_K8) 1586 .Case("k8-sse3", CK_K8SSE3) 1587 .Case("opteron", CK_Opteron) 1588 .Case("opteron-sse3", CK_OpteronSSE3) 1589 .Case("barcelona", CK_AMDFAM10) 1590 .Case("amdfam10", CK_AMDFAM10) 1591 .Case("btver1", CK_BTVER1) 1592 .Case("btver2", CK_BTVER2) 1593 .Case("bdver1", CK_BDVER1) 1594 .Case("bdver2", CK_BDVER2) 1595 .Case("bdver3", CK_BDVER3) 1596 .Case("bdver4", CK_BDVER4) 1597 .Case("znver1", CK_ZNVER1) 1598 .Case("x86-64", CK_x86_64) 1599 .Case("geode", CK_Geode) 1600 .Default(CK_Generic); 1601 } 1602 1603 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1604 return llvm::makeArrayRef(GCCRegNames); 1605 } 1606 1607 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1608 return llvm::makeArrayRef(AddlRegNames); 1609 } 1610 1611 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1612 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1613 Builtin::FirstTSBuiltin + 1); 1614 } 1615 1616 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1617 return llvm::makeArrayRef(BuiltinInfoX86, 1618 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1619 } 1620