1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+serialize") { 310 HasSERIALIZE = true; 311 } else if (Feature == "+tsxldtrk") { 312 HasTSXLDTRK = true; 313 } else if (Feature == "+uintr") { 314 HasUINTR = true; 315 } 316 317 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 318 .Case("+avx512f", AVX512F) 319 .Case("+avx2", AVX2) 320 .Case("+avx", AVX) 321 .Case("+sse4.2", SSE42) 322 .Case("+sse4.1", SSE41) 323 .Case("+ssse3", SSSE3) 324 .Case("+sse3", SSE3) 325 .Case("+sse2", SSE2) 326 .Case("+sse", SSE1) 327 .Default(NoSSE); 328 SSELevel = std::max(SSELevel, Level); 329 330 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 331 .Case("+3dnowa", AMD3DNowAthlon) 332 .Case("+3dnow", AMD3DNow) 333 .Case("+mmx", MMX) 334 .Default(NoMMX3DNow); 335 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 336 337 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 338 .Case("+xop", XOP) 339 .Case("+fma4", FMA4) 340 .Case("+sse4a", SSE4A) 341 .Default(NoXOP); 342 XOPLevel = std::max(XOPLevel, XLevel); 343 } 344 345 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 346 // matches the selected sse level. 347 if ((FPMath == FP_SSE && SSELevel < SSE1) || 348 (FPMath == FP_387 && SSELevel >= SSE1)) { 349 Diags.Report(diag::err_target_unsupported_fpmath) 350 << (FPMath == FP_SSE ? "sse" : "387"); 351 return false; 352 } 353 354 SimdDefaultAlign = 355 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 356 return true; 357 } 358 359 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 360 /// definitions for this particular subtarget. 361 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 362 MacroBuilder &Builder) const { 363 // Inline assembly supports X86 flag outputs. 364 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 365 366 std::string CodeModel = getTargetOpts().CodeModel; 367 if (CodeModel == "default") 368 CodeModel = "small"; 369 Builder.defineMacro("__code_model_" + CodeModel + "__"); 370 371 // Target identification. 372 if (getTriple().getArch() == llvm::Triple::x86_64) { 373 Builder.defineMacro("__amd64__"); 374 Builder.defineMacro("__amd64"); 375 Builder.defineMacro("__x86_64"); 376 Builder.defineMacro("__x86_64__"); 377 if (getTriple().getArchName() == "x86_64h") { 378 Builder.defineMacro("__x86_64h"); 379 Builder.defineMacro("__x86_64h__"); 380 } 381 } else { 382 DefineStd(Builder, "i386", Opts); 383 } 384 385 Builder.defineMacro("__SEG_GS"); 386 Builder.defineMacro("__SEG_FS"); 387 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 388 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 389 390 // Subtarget options. 391 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 392 // truly should be based on -mtune options. 393 using namespace llvm::X86; 394 switch (CPU) { 395 case CK_None: 396 break; 397 case CK_i386: 398 // The rest are coming from the i386 define above. 399 Builder.defineMacro("__tune_i386__"); 400 break; 401 case CK_i486: 402 case CK_WinChipC6: 403 case CK_WinChip2: 404 case CK_C3: 405 defineCPUMacros(Builder, "i486"); 406 break; 407 case CK_PentiumMMX: 408 Builder.defineMacro("__pentium_mmx__"); 409 Builder.defineMacro("__tune_pentium_mmx__"); 410 LLVM_FALLTHROUGH; 411 case CK_i586: 412 case CK_Pentium: 413 defineCPUMacros(Builder, "i586"); 414 defineCPUMacros(Builder, "pentium"); 415 break; 416 case CK_Pentium3: 417 case CK_PentiumM: 418 Builder.defineMacro("__tune_pentium3__"); 419 LLVM_FALLTHROUGH; 420 case CK_Pentium2: 421 case CK_C3_2: 422 Builder.defineMacro("__tune_pentium2__"); 423 LLVM_FALLTHROUGH; 424 case CK_PentiumPro: 425 case CK_i686: 426 defineCPUMacros(Builder, "i686"); 427 defineCPUMacros(Builder, "pentiumpro"); 428 break; 429 case CK_Pentium4: 430 defineCPUMacros(Builder, "pentium4"); 431 break; 432 case CK_Yonah: 433 case CK_Prescott: 434 case CK_Nocona: 435 defineCPUMacros(Builder, "nocona"); 436 break; 437 case CK_Core2: 438 case CK_Penryn: 439 defineCPUMacros(Builder, "core2"); 440 break; 441 case CK_Bonnell: 442 defineCPUMacros(Builder, "atom"); 443 break; 444 case CK_Silvermont: 445 defineCPUMacros(Builder, "slm"); 446 break; 447 case CK_Goldmont: 448 defineCPUMacros(Builder, "goldmont"); 449 break; 450 case CK_GoldmontPlus: 451 defineCPUMacros(Builder, "goldmont_plus"); 452 break; 453 case CK_Tremont: 454 defineCPUMacros(Builder, "tremont"); 455 break; 456 case CK_Nehalem: 457 case CK_Westmere: 458 case CK_SandyBridge: 459 case CK_IvyBridge: 460 case CK_Haswell: 461 case CK_Broadwell: 462 case CK_SkylakeClient: 463 case CK_SkylakeServer: 464 case CK_Cascadelake: 465 case CK_Cooperlake: 466 case CK_Cannonlake: 467 case CK_IcelakeClient: 468 case CK_IcelakeServer: 469 case CK_Tigerlake: 470 case CK_SapphireRapids: 471 case CK_Alderlake: 472 // FIXME: Historically, we defined this legacy name, it would be nice to 473 // remove it at some point. We've never exposed fine-grained names for 474 // recent primary x86 CPUs, and we should keep it that way. 475 defineCPUMacros(Builder, "corei7"); 476 break; 477 case CK_KNL: 478 defineCPUMacros(Builder, "knl"); 479 break; 480 case CK_KNM: 481 break; 482 case CK_Lakemont: 483 defineCPUMacros(Builder, "i586", /*Tuning*/false); 484 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 485 Builder.defineMacro("__tune_lakemont__"); 486 break; 487 case CK_K6_2: 488 Builder.defineMacro("__k6_2__"); 489 Builder.defineMacro("__tune_k6_2__"); 490 LLVM_FALLTHROUGH; 491 case CK_K6_3: 492 if (CPU != CK_K6_2) { // In case of fallthrough 493 // FIXME: GCC may be enabling these in cases where some other k6 494 // architecture is specified but -m3dnow is explicitly provided. The 495 // exact semantics need to be determined and emulated here. 496 Builder.defineMacro("__k6_3__"); 497 Builder.defineMacro("__tune_k6_3__"); 498 } 499 LLVM_FALLTHROUGH; 500 case CK_K6: 501 defineCPUMacros(Builder, "k6"); 502 break; 503 case CK_Athlon: 504 case CK_AthlonXP: 505 defineCPUMacros(Builder, "athlon"); 506 if (SSELevel != NoSSE) { 507 Builder.defineMacro("__athlon_sse__"); 508 Builder.defineMacro("__tune_athlon_sse__"); 509 } 510 break; 511 case CK_K8: 512 case CK_K8SSE3: 513 case CK_x86_64: 514 case CK_x86_64_v2: 515 case CK_x86_64_v3: 516 case CK_x86_64_v4: 517 defineCPUMacros(Builder, "k8"); 518 break; 519 case CK_AMDFAM10: 520 defineCPUMacros(Builder, "amdfam10"); 521 break; 522 case CK_BTVER1: 523 defineCPUMacros(Builder, "btver1"); 524 break; 525 case CK_BTVER2: 526 defineCPUMacros(Builder, "btver2"); 527 break; 528 case CK_BDVER1: 529 defineCPUMacros(Builder, "bdver1"); 530 break; 531 case CK_BDVER2: 532 defineCPUMacros(Builder, "bdver2"); 533 break; 534 case CK_BDVER3: 535 defineCPUMacros(Builder, "bdver3"); 536 break; 537 case CK_BDVER4: 538 defineCPUMacros(Builder, "bdver4"); 539 break; 540 case CK_ZNVER1: 541 defineCPUMacros(Builder, "znver1"); 542 break; 543 case CK_ZNVER2: 544 defineCPUMacros(Builder, "znver2"); 545 break; 546 case CK_ZNVER3: 547 defineCPUMacros(Builder, "znver3"); 548 break; 549 case CK_Geode: 550 defineCPUMacros(Builder, "geode"); 551 break; 552 } 553 554 // Target properties. 555 Builder.defineMacro("__REGISTER_PREFIX__", ""); 556 557 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 558 // functions in glibc header files that use FP Stack inline asm which the 559 // backend can't deal with (PR879). 560 Builder.defineMacro("__NO_MATH_INLINES"); 561 562 if (HasAES) 563 Builder.defineMacro("__AES__"); 564 565 if (HasVAES) 566 Builder.defineMacro("__VAES__"); 567 568 if (HasPCLMUL) 569 Builder.defineMacro("__PCLMUL__"); 570 571 if (HasVPCLMULQDQ) 572 Builder.defineMacro("__VPCLMULQDQ__"); 573 574 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 575 // the feature flag only applies to 64-bit mode. 576 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 577 Builder.defineMacro("__LAHF_SAHF__"); 578 579 if (HasLZCNT) 580 Builder.defineMacro("__LZCNT__"); 581 582 if (HasRDRND) 583 Builder.defineMacro("__RDRND__"); 584 585 if (HasFSGSBASE) 586 Builder.defineMacro("__FSGSBASE__"); 587 588 if (HasBMI) 589 Builder.defineMacro("__BMI__"); 590 591 if (HasBMI2) 592 Builder.defineMacro("__BMI2__"); 593 594 if (HasPOPCNT) 595 Builder.defineMacro("__POPCNT__"); 596 597 if (HasRTM) 598 Builder.defineMacro("__RTM__"); 599 600 if (HasPRFCHW) 601 Builder.defineMacro("__PRFCHW__"); 602 603 if (HasRDSEED) 604 Builder.defineMacro("__RDSEED__"); 605 606 if (HasADX) 607 Builder.defineMacro("__ADX__"); 608 609 if (HasTBM) 610 Builder.defineMacro("__TBM__"); 611 612 if (HasLWP) 613 Builder.defineMacro("__LWP__"); 614 615 if (HasMWAITX) 616 Builder.defineMacro("__MWAITX__"); 617 618 if (HasMOVBE) 619 Builder.defineMacro("__MOVBE__"); 620 621 switch (XOPLevel) { 622 case XOP: 623 Builder.defineMacro("__XOP__"); 624 LLVM_FALLTHROUGH; 625 case FMA4: 626 Builder.defineMacro("__FMA4__"); 627 LLVM_FALLTHROUGH; 628 case SSE4A: 629 Builder.defineMacro("__SSE4A__"); 630 LLVM_FALLTHROUGH; 631 case NoXOP: 632 break; 633 } 634 635 if (HasFMA) 636 Builder.defineMacro("__FMA__"); 637 638 if (HasF16C) 639 Builder.defineMacro("__F16C__"); 640 641 if (HasGFNI) 642 Builder.defineMacro("__GFNI__"); 643 644 if (HasAVX512CD) 645 Builder.defineMacro("__AVX512CD__"); 646 if (HasAVX512VPOPCNTDQ) 647 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 648 if (HasAVX512VNNI) 649 Builder.defineMacro("__AVX512VNNI__"); 650 if (HasAVX512BF16) 651 Builder.defineMacro("__AVX512BF16__"); 652 if (HasAVX512ER) 653 Builder.defineMacro("__AVX512ER__"); 654 if (HasAVX512PF) 655 Builder.defineMacro("__AVX512PF__"); 656 if (HasAVX512DQ) 657 Builder.defineMacro("__AVX512DQ__"); 658 if (HasAVX512BITALG) 659 Builder.defineMacro("__AVX512BITALG__"); 660 if (HasAVX512BW) 661 Builder.defineMacro("__AVX512BW__"); 662 if (HasAVX512VL) 663 Builder.defineMacro("__AVX512VL__"); 664 if (HasAVX512VBMI) 665 Builder.defineMacro("__AVX512VBMI__"); 666 if (HasAVX512VBMI2) 667 Builder.defineMacro("__AVX512VBMI2__"); 668 if (HasAVX512IFMA) 669 Builder.defineMacro("__AVX512IFMA__"); 670 if (HasAVX512VP2INTERSECT) 671 Builder.defineMacro("__AVX512VP2INTERSECT__"); 672 if (HasSHA) 673 Builder.defineMacro("__SHA__"); 674 675 if (HasFXSR) 676 Builder.defineMacro("__FXSR__"); 677 if (HasXSAVE) 678 Builder.defineMacro("__XSAVE__"); 679 if (HasXSAVEOPT) 680 Builder.defineMacro("__XSAVEOPT__"); 681 if (HasXSAVEC) 682 Builder.defineMacro("__XSAVEC__"); 683 if (HasXSAVES) 684 Builder.defineMacro("__XSAVES__"); 685 if (HasPKU) 686 Builder.defineMacro("__PKU__"); 687 if (HasCLFLUSHOPT) 688 Builder.defineMacro("__CLFLUSHOPT__"); 689 if (HasCLWB) 690 Builder.defineMacro("__CLWB__"); 691 if (HasWBNOINVD) 692 Builder.defineMacro("__WBNOINVD__"); 693 if (HasSHSTK) 694 Builder.defineMacro("__SHSTK__"); 695 if (HasSGX) 696 Builder.defineMacro("__SGX__"); 697 if (HasPREFETCHWT1) 698 Builder.defineMacro("__PREFETCHWT1__"); 699 if (HasCLZERO) 700 Builder.defineMacro("__CLZERO__"); 701 if (HasKL) 702 Builder.defineMacro("__KL__"); 703 if (HasWIDEKL) 704 Builder.defineMacro("__WIDEKL__"); 705 if (HasRDPID) 706 Builder.defineMacro("__RDPID__"); 707 if (HasCLDEMOTE) 708 Builder.defineMacro("__CLDEMOTE__"); 709 if (HasWAITPKG) 710 Builder.defineMacro("__WAITPKG__"); 711 if (HasMOVDIRI) 712 Builder.defineMacro("__MOVDIRI__"); 713 if (HasMOVDIR64B) 714 Builder.defineMacro("__MOVDIR64B__"); 715 if (HasPCONFIG) 716 Builder.defineMacro("__PCONFIG__"); 717 if (HasPTWRITE) 718 Builder.defineMacro("__PTWRITE__"); 719 if (HasINVPCID) 720 Builder.defineMacro("__INVPCID__"); 721 if (HasENQCMD) 722 Builder.defineMacro("__ENQCMD__"); 723 if (HasHRESET) 724 Builder.defineMacro("__HRESET__"); 725 if (HasAMXTILE) 726 Builder.defineMacro("__AMXTILE__"); 727 if (HasAMXINT8) 728 Builder.defineMacro("__AMXINT8__"); 729 if (HasAMXBF16) 730 Builder.defineMacro("__AMXBF16__"); 731 if (HasSERIALIZE) 732 Builder.defineMacro("__SERIALIZE__"); 733 if (HasTSXLDTRK) 734 Builder.defineMacro("__TSXLDTRK__"); 735 if (HasUINTR) 736 Builder.defineMacro("__UINTR__"); 737 738 // Each case falls through to the previous one here. 739 switch (SSELevel) { 740 case AVX512F: 741 Builder.defineMacro("__AVX512F__"); 742 LLVM_FALLTHROUGH; 743 case AVX2: 744 Builder.defineMacro("__AVX2__"); 745 LLVM_FALLTHROUGH; 746 case AVX: 747 Builder.defineMacro("__AVX__"); 748 LLVM_FALLTHROUGH; 749 case SSE42: 750 Builder.defineMacro("__SSE4_2__"); 751 LLVM_FALLTHROUGH; 752 case SSE41: 753 Builder.defineMacro("__SSE4_1__"); 754 LLVM_FALLTHROUGH; 755 case SSSE3: 756 Builder.defineMacro("__SSSE3__"); 757 LLVM_FALLTHROUGH; 758 case SSE3: 759 Builder.defineMacro("__SSE3__"); 760 LLVM_FALLTHROUGH; 761 case SSE2: 762 Builder.defineMacro("__SSE2__"); 763 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 764 LLVM_FALLTHROUGH; 765 case SSE1: 766 Builder.defineMacro("__SSE__"); 767 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 768 LLVM_FALLTHROUGH; 769 case NoSSE: 770 break; 771 } 772 773 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 774 switch (SSELevel) { 775 case AVX512F: 776 case AVX2: 777 case AVX: 778 case SSE42: 779 case SSE41: 780 case SSSE3: 781 case SSE3: 782 case SSE2: 783 Builder.defineMacro("_M_IX86_FP", Twine(2)); 784 break; 785 case SSE1: 786 Builder.defineMacro("_M_IX86_FP", Twine(1)); 787 break; 788 default: 789 Builder.defineMacro("_M_IX86_FP", Twine(0)); 790 break; 791 } 792 } 793 794 // Each case falls through to the previous one here. 795 switch (MMX3DNowLevel) { 796 case AMD3DNowAthlon: 797 Builder.defineMacro("__3dNOW_A__"); 798 LLVM_FALLTHROUGH; 799 case AMD3DNow: 800 Builder.defineMacro("__3dNOW__"); 801 LLVM_FALLTHROUGH; 802 case MMX: 803 Builder.defineMacro("__MMX__"); 804 LLVM_FALLTHROUGH; 805 case NoMMX3DNow: 806 break; 807 } 808 809 if (CPU >= CK_i486 || CPU == CK_None) { 810 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 813 } 814 if (HasCX8) 815 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 816 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 817 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 818 819 if (HasFloat128) 820 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 821 } 822 823 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 824 return llvm::StringSwitch<bool>(Name) 825 .Case("3dnow", true) 826 .Case("3dnowa", true) 827 .Case("adx", true) 828 .Case("aes", true) 829 .Case("amx-bf16", true) 830 .Case("amx-int8", true) 831 .Case("amx-tile", true) 832 .Case("avx", true) 833 .Case("avx2", true) 834 .Case("avx512f", true) 835 .Case("avx512cd", true) 836 .Case("avx512vpopcntdq", true) 837 .Case("avx512vnni", true) 838 .Case("avx512bf16", true) 839 .Case("avx512er", true) 840 .Case("avx512pf", true) 841 .Case("avx512dq", true) 842 .Case("avx512bitalg", true) 843 .Case("avx512bw", true) 844 .Case("avx512vl", true) 845 .Case("avx512vbmi", true) 846 .Case("avx512vbmi2", true) 847 .Case("avx512ifma", true) 848 .Case("avx512vp2intersect", true) 849 .Case("bmi", true) 850 .Case("bmi2", true) 851 .Case("cldemote", true) 852 .Case("clflushopt", true) 853 .Case("clwb", true) 854 .Case("clzero", true) 855 .Case("cx16", true) 856 .Case("enqcmd", true) 857 .Case("f16c", true) 858 .Case("fma", true) 859 .Case("fma4", true) 860 .Case("fsgsbase", true) 861 .Case("fxsr", true) 862 .Case("gfni", true) 863 .Case("hreset", true) 864 .Case("invpcid", true) 865 .Case("kl", true) 866 .Case("widekl", true) 867 .Case("lwp", true) 868 .Case("lzcnt", true) 869 .Case("mmx", true) 870 .Case("movbe", true) 871 .Case("movdiri", true) 872 .Case("movdir64b", true) 873 .Case("mwaitx", true) 874 .Case("pclmul", true) 875 .Case("pconfig", true) 876 .Case("pku", true) 877 .Case("popcnt", true) 878 .Case("prefetchwt1", true) 879 .Case("prfchw", true) 880 .Case("ptwrite", true) 881 .Case("rdpid", true) 882 .Case("rdrnd", true) 883 .Case("rdseed", true) 884 .Case("rtm", true) 885 .Case("sahf", true) 886 .Case("serialize", true) 887 .Case("sgx", true) 888 .Case("sha", true) 889 .Case("shstk", true) 890 .Case("sse", true) 891 .Case("sse2", true) 892 .Case("sse3", true) 893 .Case("ssse3", true) 894 .Case("sse4", true) 895 .Case("sse4.1", true) 896 .Case("sse4.2", true) 897 .Case("sse4a", true) 898 .Case("tbm", true) 899 .Case("tsxldtrk", true) 900 .Case("uintr", true) 901 .Case("vaes", true) 902 .Case("vpclmulqdq", true) 903 .Case("wbnoinvd", true) 904 .Case("waitpkg", true) 905 .Case("x87", true) 906 .Case("xop", true) 907 .Case("xsave", true) 908 .Case("xsavec", true) 909 .Case("xsaves", true) 910 .Case("xsaveopt", true) 911 .Default(false); 912 } 913 914 bool X86TargetInfo::hasFeature(StringRef Feature) const { 915 return llvm::StringSwitch<bool>(Feature) 916 .Case("adx", HasADX) 917 .Case("aes", HasAES) 918 .Case("amx-bf16", HasAMXBF16) 919 .Case("amx-int8", HasAMXINT8) 920 .Case("amx-tile", HasAMXTILE) 921 .Case("avx", SSELevel >= AVX) 922 .Case("avx2", SSELevel >= AVX2) 923 .Case("avx512f", SSELevel >= AVX512F) 924 .Case("avx512cd", HasAVX512CD) 925 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 926 .Case("avx512vnni", HasAVX512VNNI) 927 .Case("avx512bf16", HasAVX512BF16) 928 .Case("avx512er", HasAVX512ER) 929 .Case("avx512pf", HasAVX512PF) 930 .Case("avx512dq", HasAVX512DQ) 931 .Case("avx512bitalg", HasAVX512BITALG) 932 .Case("avx512bw", HasAVX512BW) 933 .Case("avx512vl", HasAVX512VL) 934 .Case("avx512vbmi", HasAVX512VBMI) 935 .Case("avx512vbmi2", HasAVX512VBMI2) 936 .Case("avx512ifma", HasAVX512IFMA) 937 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 938 .Case("bmi", HasBMI) 939 .Case("bmi2", HasBMI2) 940 .Case("cldemote", HasCLDEMOTE) 941 .Case("clflushopt", HasCLFLUSHOPT) 942 .Case("clwb", HasCLWB) 943 .Case("clzero", HasCLZERO) 944 .Case("cx8", HasCX8) 945 .Case("cx16", HasCX16) 946 .Case("enqcmd", HasENQCMD) 947 .Case("f16c", HasF16C) 948 .Case("fma", HasFMA) 949 .Case("fma4", XOPLevel >= FMA4) 950 .Case("fsgsbase", HasFSGSBASE) 951 .Case("fxsr", HasFXSR) 952 .Case("gfni", HasGFNI) 953 .Case("hreset", HasHRESET) 954 .Case("invpcid", HasINVPCID) 955 .Case("kl", HasKL) 956 .Case("widekl", HasWIDEKL) 957 .Case("lwp", HasLWP) 958 .Case("lzcnt", HasLZCNT) 959 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 960 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 961 .Case("mmx", MMX3DNowLevel >= MMX) 962 .Case("movbe", HasMOVBE) 963 .Case("movdiri", HasMOVDIRI) 964 .Case("movdir64b", HasMOVDIR64B) 965 .Case("mwaitx", HasMWAITX) 966 .Case("pclmul", HasPCLMUL) 967 .Case("pconfig", HasPCONFIG) 968 .Case("pku", HasPKU) 969 .Case("popcnt", HasPOPCNT) 970 .Case("prefetchwt1", HasPREFETCHWT1) 971 .Case("prfchw", HasPRFCHW) 972 .Case("ptwrite", HasPTWRITE) 973 .Case("rdpid", HasRDPID) 974 .Case("rdrnd", HasRDRND) 975 .Case("rdseed", HasRDSEED) 976 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 977 .Case("rtm", HasRTM) 978 .Case("sahf", HasLAHFSAHF) 979 .Case("serialize", HasSERIALIZE) 980 .Case("sgx", HasSGX) 981 .Case("sha", HasSHA) 982 .Case("shstk", HasSHSTK) 983 .Case("sse", SSELevel >= SSE1) 984 .Case("sse2", SSELevel >= SSE2) 985 .Case("sse3", SSELevel >= SSE3) 986 .Case("ssse3", SSELevel >= SSSE3) 987 .Case("sse4.1", SSELevel >= SSE41) 988 .Case("sse4.2", SSELevel >= SSE42) 989 .Case("sse4a", XOPLevel >= SSE4A) 990 .Case("tbm", HasTBM) 991 .Case("tsxldtrk", HasTSXLDTRK) 992 .Case("uintr", HasUINTR) 993 .Case("vaes", HasVAES) 994 .Case("vpclmulqdq", HasVPCLMULQDQ) 995 .Case("wbnoinvd", HasWBNOINVD) 996 .Case("waitpkg", HasWAITPKG) 997 .Case("x86", true) 998 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 999 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1000 .Case("xop", XOPLevel >= XOP) 1001 .Case("xsave", HasXSAVE) 1002 .Case("xsavec", HasXSAVEC) 1003 .Case("xsaves", HasXSAVES) 1004 .Case("xsaveopt", HasXSAVEOPT) 1005 .Default(false); 1006 } 1007 1008 // We can't use a generic validation scheme for the features accepted here 1009 // versus subtarget features accepted in the target attribute because the 1010 // bitfield structure that's initialized in the runtime only supports the 1011 // below currently rather than the full range of subtarget features. (See 1012 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1013 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1014 return llvm::StringSwitch<bool>(FeatureStr) 1015 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1016 #include "llvm/Support/X86TargetParser.def" 1017 .Default(false); 1018 } 1019 1020 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1021 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1022 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1023 #include "llvm/Support/X86TargetParser.def" 1024 ; 1025 // Note, this function should only be used after ensuring the value is 1026 // correct, so it asserts if the value is out of range. 1027 } 1028 1029 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1030 enum class FeatPriority { 1031 #define FEATURE(FEAT) FEAT, 1032 #include "clang/Basic/X86Target.def" 1033 }; 1034 switch (Feat) { 1035 #define FEATURE(FEAT) \ 1036 case llvm::X86::FEAT: \ 1037 return static_cast<unsigned>(FeatPriority::FEAT); 1038 #include "clang/Basic/X86Target.def" 1039 default: 1040 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1041 } 1042 } 1043 1044 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1045 // Valid CPUs have a 'key feature' that compares just better than its key 1046 // feature. 1047 using namespace llvm::X86; 1048 CPUKind Kind = parseArchX86(Name); 1049 if (Kind != CK_None) { 1050 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1051 return (getFeaturePriority(KeyFeature) << 1) + 1; 1052 } 1053 1054 // Now we know we have a feature, so get its priority and shift it a few so 1055 // that we have sufficient room for the CPUs (above). 1056 return getFeaturePriority(getFeature(Name)) << 1; 1057 } 1058 1059 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1060 return llvm::StringSwitch<bool>(Name) 1061 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1062 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1063 #include "clang/Basic/X86Target.def" 1064 .Default(false); 1065 } 1066 1067 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1068 return llvm::StringSwitch<StringRef>(Name) 1069 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1070 #include "clang/Basic/X86Target.def" 1071 .Default(Name); 1072 } 1073 1074 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1075 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1076 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1077 #include "clang/Basic/X86Target.def" 1078 .Default(0); 1079 } 1080 1081 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1082 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1083 StringRef WholeList = 1084 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1085 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1086 #include "clang/Basic/X86Target.def" 1087 .Default(""); 1088 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1089 } 1090 1091 // We can't use a generic validation scheme for the cpus accepted here 1092 // versus subtarget cpus accepted in the target attribute because the 1093 // variables intitialized by the runtime only support the below currently 1094 // rather than the full range of cpus. 1095 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1096 return llvm::StringSwitch<bool>(FeatureStr) 1097 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1098 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1099 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1100 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1101 #include "llvm/Support/X86TargetParser.def" 1102 .Default(false); 1103 } 1104 1105 static unsigned matchAsmCCConstraint(const char *&Name) { 1106 auto RV = llvm::StringSwitch<unsigned>(Name) 1107 .Case("@cca", 4) 1108 .Case("@ccae", 5) 1109 .Case("@ccb", 4) 1110 .Case("@ccbe", 5) 1111 .Case("@ccc", 4) 1112 .Case("@cce", 4) 1113 .Case("@ccz", 4) 1114 .Case("@ccg", 4) 1115 .Case("@ccge", 5) 1116 .Case("@ccl", 4) 1117 .Case("@ccle", 5) 1118 .Case("@ccna", 5) 1119 .Case("@ccnae", 6) 1120 .Case("@ccnb", 5) 1121 .Case("@ccnbe", 6) 1122 .Case("@ccnc", 5) 1123 .Case("@ccne", 5) 1124 .Case("@ccnz", 5) 1125 .Case("@ccng", 5) 1126 .Case("@ccnge", 6) 1127 .Case("@ccnl", 5) 1128 .Case("@ccnle", 6) 1129 .Case("@ccno", 5) 1130 .Case("@ccnp", 5) 1131 .Case("@ccns", 5) 1132 .Case("@cco", 4) 1133 .Case("@ccp", 4) 1134 .Case("@ccs", 4) 1135 .Default(0); 1136 return RV; 1137 } 1138 1139 bool X86TargetInfo::validateAsmConstraint( 1140 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1141 switch (*Name) { 1142 default: 1143 return false; 1144 // Constant constraints. 1145 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1146 // instructions. 1147 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1148 // x86_64 instructions. 1149 case 's': 1150 Info.setRequiresImmediate(); 1151 return true; 1152 case 'I': 1153 Info.setRequiresImmediate(0, 31); 1154 return true; 1155 case 'J': 1156 Info.setRequiresImmediate(0, 63); 1157 return true; 1158 case 'K': 1159 Info.setRequiresImmediate(-128, 127); 1160 return true; 1161 case 'L': 1162 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1163 return true; 1164 case 'M': 1165 Info.setRequiresImmediate(0, 3); 1166 return true; 1167 case 'N': 1168 Info.setRequiresImmediate(0, 255); 1169 return true; 1170 case 'O': 1171 Info.setRequiresImmediate(0, 127); 1172 return true; 1173 // Register constraints. 1174 case 'Y': // 'Y' is the first character for several 2-character constraints. 1175 // Shift the pointer to the second character of the constraint. 1176 Name++; 1177 switch (*Name) { 1178 default: 1179 return false; 1180 case 'z': // First SSE register. 1181 case '2': 1182 case 't': // Any SSE register, when SSE2 is enabled. 1183 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1184 case 'm': // Any MMX register, when inter-unit moves enabled. 1185 case 'k': // AVX512 arch mask registers: k1-k7. 1186 Info.setAllowsRegister(); 1187 return true; 1188 } 1189 case 'f': // Any x87 floating point stack register. 1190 // Constraint 'f' cannot be used for output operands. 1191 if (Info.ConstraintStr[0] == '=') 1192 return false; 1193 Info.setAllowsRegister(); 1194 return true; 1195 case 'a': // eax. 1196 case 'b': // ebx. 1197 case 'c': // ecx. 1198 case 'd': // edx. 1199 case 'S': // esi. 1200 case 'D': // edi. 1201 case 'A': // edx:eax. 1202 case 't': // Top of floating point stack. 1203 case 'u': // Second from top of floating point stack. 1204 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1205 case 'y': // Any MMX register. 1206 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1207 case 'x': // Any SSE register. 1208 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1209 // for intermideate k reg operations). 1210 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1211 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1212 case 'l': // "Index" registers: any general register that can be used as an 1213 // index in a base+index memory access. 1214 Info.setAllowsRegister(); 1215 return true; 1216 // Floating point constant constraints. 1217 case 'C': // SSE floating point constant. 1218 case 'G': // x87 floating point constant. 1219 return true; 1220 case '@': 1221 // CC condition changes. 1222 if (auto Len = matchAsmCCConstraint(Name)) { 1223 Name += Len - 1; 1224 Info.setAllowsRegister(); 1225 return true; 1226 } 1227 return false; 1228 } 1229 } 1230 1231 // Below is based on the following information: 1232 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1233 // | Processor Name | Cache Line Size (Bytes) | Source | 1234 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1235 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1236 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1237 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1238 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1239 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1240 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1241 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1242 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1243 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1244 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1245 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1246 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1247 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1248 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1249 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1250 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1251 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1252 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1253 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1254 using namespace llvm::X86; 1255 switch (CPU) { 1256 // i386 1257 case CK_i386: 1258 // i486 1259 case CK_i486: 1260 case CK_WinChipC6: 1261 case CK_WinChip2: 1262 case CK_C3: 1263 // Lakemont 1264 case CK_Lakemont: 1265 return 16; 1266 1267 // i586 1268 case CK_i586: 1269 case CK_Pentium: 1270 case CK_PentiumMMX: 1271 // i686 1272 case CK_PentiumPro: 1273 case CK_i686: 1274 case CK_Pentium2: 1275 case CK_Pentium3: 1276 case CK_PentiumM: 1277 case CK_C3_2: 1278 // K6 1279 case CK_K6: 1280 case CK_K6_2: 1281 case CK_K6_3: 1282 // Geode 1283 case CK_Geode: 1284 return 32; 1285 1286 // Netburst 1287 case CK_Pentium4: 1288 case CK_Prescott: 1289 case CK_Nocona: 1290 // Atom 1291 case CK_Bonnell: 1292 case CK_Silvermont: 1293 case CK_Goldmont: 1294 case CK_GoldmontPlus: 1295 case CK_Tremont: 1296 1297 case CK_Westmere: 1298 case CK_SandyBridge: 1299 case CK_IvyBridge: 1300 case CK_Haswell: 1301 case CK_Broadwell: 1302 case CK_SkylakeClient: 1303 case CK_SkylakeServer: 1304 case CK_Cascadelake: 1305 case CK_Nehalem: 1306 case CK_Cooperlake: 1307 case CK_Cannonlake: 1308 case CK_Tigerlake: 1309 case CK_SapphireRapids: 1310 case CK_IcelakeClient: 1311 case CK_IcelakeServer: 1312 case CK_Alderlake: 1313 case CK_KNL: 1314 case CK_KNM: 1315 // K7 1316 case CK_Athlon: 1317 case CK_AthlonXP: 1318 // K8 1319 case CK_K8: 1320 case CK_K8SSE3: 1321 case CK_AMDFAM10: 1322 // Bobcat 1323 case CK_BTVER1: 1324 case CK_BTVER2: 1325 // Bulldozer 1326 case CK_BDVER1: 1327 case CK_BDVER2: 1328 case CK_BDVER3: 1329 case CK_BDVER4: 1330 // Zen 1331 case CK_ZNVER1: 1332 case CK_ZNVER2: 1333 case CK_ZNVER3: 1334 // Deprecated 1335 case CK_x86_64: 1336 case CK_x86_64_v2: 1337 case CK_x86_64_v3: 1338 case CK_x86_64_v4: 1339 case CK_Yonah: 1340 case CK_Penryn: 1341 case CK_Core2: 1342 return 64; 1343 1344 // The following currently have unknown cache line sizes (but they are probably all 64): 1345 // Core 1346 case CK_None: 1347 return None; 1348 } 1349 llvm_unreachable("Unknown CPU kind"); 1350 } 1351 1352 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1353 StringRef Constraint, 1354 unsigned Size) const { 1355 // Strip off constraint modifiers. 1356 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1357 Constraint = Constraint.substr(1); 1358 1359 return validateOperandSize(FeatureMap, Constraint, Size); 1360 } 1361 1362 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1363 StringRef Constraint, 1364 unsigned Size) const { 1365 return validateOperandSize(FeatureMap, Constraint, Size); 1366 } 1367 1368 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1369 StringRef Constraint, 1370 unsigned Size) const { 1371 switch (Constraint[0]) { 1372 default: 1373 break; 1374 case 'k': 1375 // Registers k0-k7 (AVX512) size limit is 64 bit. 1376 case 'y': 1377 return Size <= 64; 1378 case 'f': 1379 case 't': 1380 case 'u': 1381 return Size <= 128; 1382 case 'Y': 1383 // 'Y' is the first character for several 2-character constraints. 1384 switch (Constraint[1]) { 1385 default: 1386 return false; 1387 case 'm': 1388 // 'Ym' is synonymous with 'y'. 1389 case 'k': 1390 return Size <= 64; 1391 case 'z': 1392 // XMM0/YMM/ZMM0 1393 if (FeatureMap.lookup("avx512f")) 1394 // ZMM0 can be used if target supports AVX512F. 1395 return Size <= 512U; 1396 else if (FeatureMap.lookup("avx")) 1397 // YMM0 can be used if target supports AVX. 1398 return Size <= 256U; 1399 else if (FeatureMap.lookup("sse")) 1400 return Size <= 128U; 1401 return false; 1402 case 'i': 1403 case 't': 1404 case '2': 1405 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1406 if (SSELevel < SSE2) 1407 return false; 1408 break; 1409 } 1410 break; 1411 case 'v': 1412 case 'x': 1413 if (FeatureMap.lookup("avx512f")) 1414 // 512-bit zmm registers can be used if target supports AVX512F. 1415 return Size <= 512U; 1416 else if (FeatureMap.lookup("avx")) 1417 // 256-bit ymm registers can be used if target supports AVX. 1418 return Size <= 256U; 1419 return Size <= 128U; 1420 1421 } 1422 1423 return true; 1424 } 1425 1426 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1427 switch (*Constraint) { 1428 case '@': 1429 if (auto Len = matchAsmCCConstraint(Constraint)) { 1430 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1431 Constraint += Len - 1; 1432 return Converted; 1433 } 1434 return std::string(1, *Constraint); 1435 case 'a': 1436 return std::string("{ax}"); 1437 case 'b': 1438 return std::string("{bx}"); 1439 case 'c': 1440 return std::string("{cx}"); 1441 case 'd': 1442 return std::string("{dx}"); 1443 case 'S': 1444 return std::string("{si}"); 1445 case 'D': 1446 return std::string("{di}"); 1447 case 'p': // address 1448 return std::string("im"); 1449 case 't': // top of floating point stack. 1450 return std::string("{st}"); 1451 case 'u': // second from top of floating point stack. 1452 return std::string("{st(1)}"); // second from top of floating point stack. 1453 case 'Y': 1454 switch (Constraint[1]) { 1455 default: 1456 // Break from inner switch and fall through (copy single char), 1457 // continue parsing after copying the current constraint into 1458 // the return string. 1459 break; 1460 case 'k': 1461 case 'm': 1462 case 'i': 1463 case 't': 1464 case 'z': 1465 case '2': 1466 // "^" hints llvm that this is a 2 letter constraint. 1467 // "Constraint++" is used to promote the string iterator 1468 // to the next constraint. 1469 return std::string("^") + std::string(Constraint++, 2); 1470 } 1471 LLVM_FALLTHROUGH; 1472 default: 1473 return std::string(1, *Constraint); 1474 } 1475 } 1476 1477 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1478 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1479 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1480 } 1481 1482 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1483 llvm::X86::fillValidTuneCPUList(Values); 1484 } 1485 1486 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1487 return llvm::makeArrayRef(GCCRegNames); 1488 } 1489 1490 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1491 return llvm::makeArrayRef(AddlRegNames); 1492 } 1493 1494 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1495 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1496 Builtin::FirstTSBuiltin + 1); 1497 } 1498 1499 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1500 return llvm::makeArrayRef(BuiltinInfoX86, 1501 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1502 } 1503