1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_Cooperlake: 142 // CPX inherits all CLX features plus AVX512BF16 143 setFeatureEnabledImpl(Features, "avx512bf16", true); 144 LLVM_FALLTHROUGH; 145 case CK_Cascadelake: 146 // CLX inherits all SKX features plus AVX512VNNI 147 setFeatureEnabledImpl(Features, "avx512vnni", true); 148 LLVM_FALLTHROUGH; 149 case CK_SkylakeServer: 150 setFeatureEnabledImpl(Features, "avx512f", true); 151 setFeatureEnabledImpl(Features, "avx512cd", true); 152 setFeatureEnabledImpl(Features, "avx512dq", true); 153 setFeatureEnabledImpl(Features, "avx512bw", true); 154 setFeatureEnabledImpl(Features, "avx512vl", true); 155 setFeatureEnabledImpl(Features, "clwb", true); 156 setFeatureEnabledImpl(Features, "pku", true); 157 // SkylakeServer cores inherits all SKL features, except SGX 158 goto SkylakeCommon; 159 160 case CK_Tigerlake: 161 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 162 setFeatureEnabledImpl(Features, "movdiri", true); 163 setFeatureEnabledImpl(Features, "movdir64b", true); 164 setFeatureEnabledImpl(Features, "shstk", true); 165 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 166 goto IcelakeCommon; 167 168 case CK_IcelakeServer: 169 setFeatureEnabledImpl(Features, "pconfig", true); 170 setFeatureEnabledImpl(Features, "wbnoinvd", true); 171 LLVM_FALLTHROUGH; 172 case CK_IcelakeClient: 173 IcelakeCommon: 174 setFeatureEnabledImpl(Features, "vaes", true); 175 setFeatureEnabledImpl(Features, "gfni", true); 176 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 177 setFeatureEnabledImpl(Features, "avx512bitalg", true); 178 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 179 setFeatureEnabledImpl(Features, "avx512vnni", true); 180 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 181 setFeatureEnabledImpl(Features, "rdpid", true); 182 setFeatureEnabledImpl(Features, "clwb", true); 183 LLVM_FALLTHROUGH; 184 case CK_Cannonlake: 185 setFeatureEnabledImpl(Features, "avx512f", true); 186 setFeatureEnabledImpl(Features, "avx512cd", true); 187 setFeatureEnabledImpl(Features, "avx512dq", true); 188 setFeatureEnabledImpl(Features, "avx512bw", true); 189 setFeatureEnabledImpl(Features, "avx512vl", true); 190 setFeatureEnabledImpl(Features, "avx512ifma", true); 191 setFeatureEnabledImpl(Features, "avx512vbmi", true); 192 setFeatureEnabledImpl(Features, "pku", true); 193 setFeatureEnabledImpl(Features, "sha", true); 194 LLVM_FALLTHROUGH; 195 case CK_SkylakeClient: 196 setFeatureEnabledImpl(Features, "sgx", true); 197 // SkylakeServer cores inherits all SKL features, except SGX 198 SkylakeCommon: 199 setFeatureEnabledImpl(Features, "xsavec", true); 200 setFeatureEnabledImpl(Features, "xsaves", true); 201 setFeatureEnabledImpl(Features, "mpx", true); 202 setFeatureEnabledImpl(Features, "clflushopt", true); 203 setFeatureEnabledImpl(Features, "aes", true); 204 LLVM_FALLTHROUGH; 205 case CK_Broadwell: 206 setFeatureEnabledImpl(Features, "rdseed", true); 207 setFeatureEnabledImpl(Features, "adx", true); 208 setFeatureEnabledImpl(Features, "prfchw", true); 209 LLVM_FALLTHROUGH; 210 case CK_Haswell: 211 setFeatureEnabledImpl(Features, "avx2", true); 212 setFeatureEnabledImpl(Features, "lzcnt", true); 213 setFeatureEnabledImpl(Features, "bmi", true); 214 setFeatureEnabledImpl(Features, "bmi2", true); 215 setFeatureEnabledImpl(Features, "fma", true); 216 setFeatureEnabledImpl(Features, "invpcid", true); 217 setFeatureEnabledImpl(Features, "movbe", true); 218 LLVM_FALLTHROUGH; 219 case CK_IvyBridge: 220 setFeatureEnabledImpl(Features, "rdrnd", true); 221 setFeatureEnabledImpl(Features, "f16c", true); 222 setFeatureEnabledImpl(Features, "fsgsbase", true); 223 LLVM_FALLTHROUGH; 224 case CK_SandyBridge: 225 setFeatureEnabledImpl(Features, "avx", true); 226 setFeatureEnabledImpl(Features, "xsave", true); 227 setFeatureEnabledImpl(Features, "xsaveopt", true); 228 LLVM_FALLTHROUGH; 229 case CK_Westmere: 230 setFeatureEnabledImpl(Features, "pclmul", true); 231 LLVM_FALLTHROUGH; 232 case CK_Nehalem: 233 setFeatureEnabledImpl(Features, "sse4.2", true); 234 LLVM_FALLTHROUGH; 235 case CK_Penryn: 236 setFeatureEnabledImpl(Features, "sse4.1", true); 237 LLVM_FALLTHROUGH; 238 case CK_Core2: 239 setFeatureEnabledImpl(Features, "ssse3", true); 240 setFeatureEnabledImpl(Features, "sahf", true); 241 LLVM_FALLTHROUGH; 242 case CK_Nocona: 243 setFeatureEnabledImpl(Features, "cx16", true); 244 LLVM_FALLTHROUGH; 245 case CK_Yonah: 246 case CK_Prescott: 247 setFeatureEnabledImpl(Features, "sse3", true); 248 LLVM_FALLTHROUGH; 249 case CK_PentiumM: 250 case CK_Pentium4: 251 case CK_x86_64: 252 setFeatureEnabledImpl(Features, "sse2", true); 253 LLVM_FALLTHROUGH; 254 case CK_Pentium3: 255 case CK_C3_2: 256 setFeatureEnabledImpl(Features, "sse", true); 257 setFeatureEnabledImpl(Features, "fxsr", true); 258 break; 259 260 case CK_Tremont: 261 setFeatureEnabledImpl(Features, "cldemote", true); 262 setFeatureEnabledImpl(Features, "movdiri", true); 263 setFeatureEnabledImpl(Features, "movdir64b", true); 264 setFeatureEnabledImpl(Features, "gfni", true); 265 setFeatureEnabledImpl(Features, "waitpkg", true); 266 LLVM_FALLTHROUGH; 267 case CK_GoldmontPlus: 268 setFeatureEnabledImpl(Features, "ptwrite", true); 269 setFeatureEnabledImpl(Features, "rdpid", true); 270 setFeatureEnabledImpl(Features, "sgx", true); 271 LLVM_FALLTHROUGH; 272 case CK_Goldmont: 273 setFeatureEnabledImpl(Features, "sha", true); 274 setFeatureEnabledImpl(Features, "rdseed", true); 275 setFeatureEnabledImpl(Features, "xsave", true); 276 setFeatureEnabledImpl(Features, "xsaveopt", true); 277 setFeatureEnabledImpl(Features, "xsavec", true); 278 setFeatureEnabledImpl(Features, "xsaves", true); 279 setFeatureEnabledImpl(Features, "clflushopt", true); 280 setFeatureEnabledImpl(Features, "mpx", true); 281 setFeatureEnabledImpl(Features, "fsgsbase", true); 282 setFeatureEnabledImpl(Features, "aes", true); 283 LLVM_FALLTHROUGH; 284 case CK_Silvermont: 285 setFeatureEnabledImpl(Features, "rdrnd", true); 286 setFeatureEnabledImpl(Features, "pclmul", true); 287 setFeatureEnabledImpl(Features, "sse4.2", true); 288 setFeatureEnabledImpl(Features, "prfchw", true); 289 LLVM_FALLTHROUGH; 290 case CK_Bonnell: 291 setFeatureEnabledImpl(Features, "movbe", true); 292 setFeatureEnabledImpl(Features, "ssse3", true); 293 setFeatureEnabledImpl(Features, "fxsr", true); 294 setFeatureEnabledImpl(Features, "cx16", true); 295 setFeatureEnabledImpl(Features, "sahf", true); 296 break; 297 298 case CK_KNM: 299 // TODO: Add avx5124fmaps/avx5124vnniw. 300 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 301 LLVM_FALLTHROUGH; 302 case CK_KNL: 303 setFeatureEnabledImpl(Features, "avx512f", true); 304 setFeatureEnabledImpl(Features, "avx512cd", true); 305 setFeatureEnabledImpl(Features, "avx512er", true); 306 setFeatureEnabledImpl(Features, "avx512pf", true); 307 setFeatureEnabledImpl(Features, "prfchw", true); 308 setFeatureEnabledImpl(Features, "prefetchwt1", true); 309 setFeatureEnabledImpl(Features, "fxsr", true); 310 setFeatureEnabledImpl(Features, "rdseed", true); 311 setFeatureEnabledImpl(Features, "adx", true); 312 setFeatureEnabledImpl(Features, "lzcnt", true); 313 setFeatureEnabledImpl(Features, "bmi", true); 314 setFeatureEnabledImpl(Features, "bmi2", true); 315 setFeatureEnabledImpl(Features, "fma", true); 316 setFeatureEnabledImpl(Features, "rdrnd", true); 317 setFeatureEnabledImpl(Features, "f16c", true); 318 setFeatureEnabledImpl(Features, "fsgsbase", true); 319 setFeatureEnabledImpl(Features, "aes", true); 320 setFeatureEnabledImpl(Features, "pclmul", true); 321 setFeatureEnabledImpl(Features, "cx16", true); 322 setFeatureEnabledImpl(Features, "xsaveopt", true); 323 setFeatureEnabledImpl(Features, "xsave", true); 324 setFeatureEnabledImpl(Features, "movbe", true); 325 setFeatureEnabledImpl(Features, "sahf", true); 326 break; 327 328 case CK_K6_2: 329 case CK_K6_3: 330 case CK_WinChip2: 331 case CK_C3: 332 setFeatureEnabledImpl(Features, "3dnow", true); 333 break; 334 335 case CK_AMDFAM10: 336 setFeatureEnabledImpl(Features, "sse4a", true); 337 setFeatureEnabledImpl(Features, "lzcnt", true); 338 setFeatureEnabledImpl(Features, "popcnt", true); 339 setFeatureEnabledImpl(Features, "sahf", true); 340 LLVM_FALLTHROUGH; 341 case CK_K8SSE3: 342 setFeatureEnabledImpl(Features, "sse3", true); 343 LLVM_FALLTHROUGH; 344 case CK_K8: 345 setFeatureEnabledImpl(Features, "sse2", true); 346 LLVM_FALLTHROUGH; 347 case CK_AthlonXP: 348 setFeatureEnabledImpl(Features, "sse", true); 349 setFeatureEnabledImpl(Features, "fxsr", true); 350 LLVM_FALLTHROUGH; 351 case CK_Athlon: 352 case CK_Geode: 353 setFeatureEnabledImpl(Features, "3dnowa", true); 354 break; 355 356 case CK_BTVER2: 357 setFeatureEnabledImpl(Features, "avx", true); 358 setFeatureEnabledImpl(Features, "aes", true); 359 setFeatureEnabledImpl(Features, "pclmul", true); 360 setFeatureEnabledImpl(Features, "bmi", true); 361 setFeatureEnabledImpl(Features, "f16c", true); 362 setFeatureEnabledImpl(Features, "xsaveopt", true); 363 setFeatureEnabledImpl(Features, "movbe", true); 364 LLVM_FALLTHROUGH; 365 case CK_BTVER1: 366 setFeatureEnabledImpl(Features, "ssse3", true); 367 setFeatureEnabledImpl(Features, "sse4a", true); 368 setFeatureEnabledImpl(Features, "lzcnt", true); 369 setFeatureEnabledImpl(Features, "popcnt", true); 370 setFeatureEnabledImpl(Features, "prfchw", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "fxsr", true); 373 setFeatureEnabledImpl(Features, "sahf", true); 374 break; 375 376 case CK_ZNVER2: 377 setFeatureEnabledImpl(Features, "clwb", true); 378 setFeatureEnabledImpl(Features, "rdpid", true); 379 setFeatureEnabledImpl(Features, "wbnoinvd", true); 380 LLVM_FALLTHROUGH; 381 case CK_ZNVER1: 382 setFeatureEnabledImpl(Features, "adx", true); 383 setFeatureEnabledImpl(Features, "aes", true); 384 setFeatureEnabledImpl(Features, "avx2", true); 385 setFeatureEnabledImpl(Features, "bmi", true); 386 setFeatureEnabledImpl(Features, "bmi2", true); 387 setFeatureEnabledImpl(Features, "clflushopt", true); 388 setFeatureEnabledImpl(Features, "clzero", true); 389 setFeatureEnabledImpl(Features, "cx16", true); 390 setFeatureEnabledImpl(Features, "f16c", true); 391 setFeatureEnabledImpl(Features, "fma", true); 392 setFeatureEnabledImpl(Features, "fsgsbase", true); 393 setFeatureEnabledImpl(Features, "fxsr", true); 394 setFeatureEnabledImpl(Features, "lzcnt", true); 395 setFeatureEnabledImpl(Features, "mwaitx", true); 396 setFeatureEnabledImpl(Features, "movbe", true); 397 setFeatureEnabledImpl(Features, "pclmul", true); 398 setFeatureEnabledImpl(Features, "popcnt", true); 399 setFeatureEnabledImpl(Features, "prfchw", true); 400 setFeatureEnabledImpl(Features, "rdrnd", true); 401 setFeatureEnabledImpl(Features, "rdseed", true); 402 setFeatureEnabledImpl(Features, "sahf", true); 403 setFeatureEnabledImpl(Features, "sha", true); 404 setFeatureEnabledImpl(Features, "sse4a", true); 405 setFeatureEnabledImpl(Features, "xsave", true); 406 setFeatureEnabledImpl(Features, "xsavec", true); 407 setFeatureEnabledImpl(Features, "xsaveopt", true); 408 setFeatureEnabledImpl(Features, "xsaves", true); 409 break; 410 411 case CK_BDVER4: 412 setFeatureEnabledImpl(Features, "avx2", true); 413 setFeatureEnabledImpl(Features, "bmi2", true); 414 setFeatureEnabledImpl(Features, "mwaitx", true); 415 LLVM_FALLTHROUGH; 416 case CK_BDVER3: 417 setFeatureEnabledImpl(Features, "fsgsbase", true); 418 setFeatureEnabledImpl(Features, "xsaveopt", true); 419 LLVM_FALLTHROUGH; 420 case CK_BDVER2: 421 setFeatureEnabledImpl(Features, "bmi", true); 422 setFeatureEnabledImpl(Features, "fma", true); 423 setFeatureEnabledImpl(Features, "f16c", true); 424 setFeatureEnabledImpl(Features, "tbm", true); 425 LLVM_FALLTHROUGH; 426 case CK_BDVER1: 427 // xop implies avx, sse4a and fma4. 428 setFeatureEnabledImpl(Features, "xop", true); 429 setFeatureEnabledImpl(Features, "lwp", true); 430 setFeatureEnabledImpl(Features, "lzcnt", true); 431 setFeatureEnabledImpl(Features, "aes", true); 432 setFeatureEnabledImpl(Features, "pclmul", true); 433 setFeatureEnabledImpl(Features, "prfchw", true); 434 setFeatureEnabledImpl(Features, "cx16", true); 435 setFeatureEnabledImpl(Features, "fxsr", true); 436 setFeatureEnabledImpl(Features, "xsave", true); 437 setFeatureEnabledImpl(Features, "sahf", true); 438 break; 439 } 440 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 441 return false; 442 443 // Can't do this earlier because we need to be able to explicitly enable 444 // or disable these features and the things that they depend upon. 445 446 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 447 auto I = Features.find("sse4.2"); 448 if (I != Features.end() && I->getValue() && 449 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 450 Features["popcnt"] = true; 451 452 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 453 I = Features.find("3dnow"); 454 if (I != Features.end() && I->getValue() && 455 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 456 Features["prfchw"] = true; 457 458 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 459 // then enable MMX. 460 I = Features.find("sse"); 461 if (I != Features.end() && I->getValue() && 462 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 463 Features["mmx"] = true; 464 465 return true; 466 } 467 468 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 469 X86SSEEnum Level, bool Enabled) { 470 if (Enabled) { 471 switch (Level) { 472 case AVX512F: 473 Features["avx512f"] = true; 474 Features["fma"] = true; 475 Features["f16c"] = true; 476 LLVM_FALLTHROUGH; 477 case AVX2: 478 Features["avx2"] = true; 479 LLVM_FALLTHROUGH; 480 case AVX: 481 Features["avx"] = true; 482 Features["xsave"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE42: 485 Features["sse4.2"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE41: 488 Features["sse4.1"] = true; 489 LLVM_FALLTHROUGH; 490 case SSSE3: 491 Features["ssse3"] = true; 492 LLVM_FALLTHROUGH; 493 case SSE3: 494 Features["sse3"] = true; 495 LLVM_FALLTHROUGH; 496 case SSE2: 497 Features["sse2"] = true; 498 LLVM_FALLTHROUGH; 499 case SSE1: 500 Features["sse"] = true; 501 LLVM_FALLTHROUGH; 502 case NoSSE: 503 break; 504 } 505 return; 506 } 507 508 switch (Level) { 509 case NoSSE: 510 case SSE1: 511 Features["sse"] = false; 512 LLVM_FALLTHROUGH; 513 case SSE2: 514 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 515 Features["sha"] = Features["gfni"] = false; 516 LLVM_FALLTHROUGH; 517 case SSE3: 518 Features["sse3"] = false; 519 setXOPLevel(Features, NoXOP, false); 520 LLVM_FALLTHROUGH; 521 case SSSE3: 522 Features["ssse3"] = false; 523 LLVM_FALLTHROUGH; 524 case SSE41: 525 Features["sse4.1"] = false; 526 LLVM_FALLTHROUGH; 527 case SSE42: 528 Features["sse4.2"] = false; 529 LLVM_FALLTHROUGH; 530 case AVX: 531 Features["fma"] = Features["avx"] = Features["f16c"] = false; 532 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 533 Features["vpclmulqdq"] = false; 534 setXOPLevel(Features, FMA4, false); 535 LLVM_FALLTHROUGH; 536 case AVX2: 537 Features["avx2"] = false; 538 LLVM_FALLTHROUGH; 539 case AVX512F: 540 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 541 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 542 Features["avx512vl"] = Features["avx512vbmi"] = false; 543 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 544 Features["avx512bitalg"] = Features["avx512vnni"] = false; 545 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 546 Features["avx512vp2intersect"] = false; 547 break; 548 } 549 } 550 551 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 552 MMX3DNowEnum Level, bool Enabled) { 553 if (Enabled) { 554 switch (Level) { 555 case AMD3DNowAthlon: 556 Features["3dnowa"] = true; 557 LLVM_FALLTHROUGH; 558 case AMD3DNow: 559 Features["3dnow"] = true; 560 LLVM_FALLTHROUGH; 561 case MMX: 562 Features["mmx"] = true; 563 LLVM_FALLTHROUGH; 564 case NoMMX3DNow: 565 break; 566 } 567 return; 568 } 569 570 switch (Level) { 571 case NoMMX3DNow: 572 case MMX: 573 Features["mmx"] = false; 574 LLVM_FALLTHROUGH; 575 case AMD3DNow: 576 Features["3dnow"] = false; 577 LLVM_FALLTHROUGH; 578 case AMD3DNowAthlon: 579 Features["3dnowa"] = false; 580 break; 581 } 582 } 583 584 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 585 bool Enabled) { 586 if (Enabled) { 587 switch (Level) { 588 case XOP: 589 Features["xop"] = true; 590 LLVM_FALLTHROUGH; 591 case FMA4: 592 Features["fma4"] = true; 593 setSSELevel(Features, AVX, true); 594 LLVM_FALLTHROUGH; 595 case SSE4A: 596 Features["sse4a"] = true; 597 setSSELevel(Features, SSE3, true); 598 LLVM_FALLTHROUGH; 599 case NoXOP: 600 break; 601 } 602 return; 603 } 604 605 switch (Level) { 606 case NoXOP: 607 case SSE4A: 608 Features["sse4a"] = false; 609 LLVM_FALLTHROUGH; 610 case FMA4: 611 Features["fma4"] = false; 612 LLVM_FALLTHROUGH; 613 case XOP: 614 Features["xop"] = false; 615 break; 616 } 617 } 618 619 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 620 StringRef Name, bool Enabled) { 621 // This is a bit of a hack to deal with the sse4 target feature when used 622 // as part of the target attribute. We handle sse4 correctly everywhere 623 // else. See below for more information on how we handle the sse4 options. 624 if (Name != "sse4") 625 Features[Name] = Enabled; 626 627 if (Name == "mmx") { 628 setMMXLevel(Features, MMX, Enabled); 629 } else if (Name == "sse") { 630 setSSELevel(Features, SSE1, Enabled); 631 } else if (Name == "sse2") { 632 setSSELevel(Features, SSE2, Enabled); 633 } else if (Name == "sse3") { 634 setSSELevel(Features, SSE3, Enabled); 635 } else if (Name == "ssse3") { 636 setSSELevel(Features, SSSE3, Enabled); 637 } else if (Name == "sse4.2") { 638 setSSELevel(Features, SSE42, Enabled); 639 } else if (Name == "sse4.1") { 640 setSSELevel(Features, SSE41, Enabled); 641 } else if (Name == "3dnow") { 642 setMMXLevel(Features, AMD3DNow, Enabled); 643 } else if (Name == "3dnowa") { 644 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 645 } else if (Name == "aes") { 646 if (Enabled) 647 setSSELevel(Features, SSE2, Enabled); 648 else 649 Features["vaes"] = false; 650 } else if (Name == "vaes") { 651 if (Enabled) { 652 setSSELevel(Features, AVX, Enabled); 653 Features["aes"] = true; 654 } 655 } else if (Name == "pclmul") { 656 if (Enabled) 657 setSSELevel(Features, SSE2, Enabled); 658 else 659 Features["vpclmulqdq"] = false; 660 } else if (Name == "vpclmulqdq") { 661 if (Enabled) { 662 setSSELevel(Features, AVX, Enabled); 663 Features["pclmul"] = true; 664 } 665 } else if (Name == "gfni") { 666 if (Enabled) 667 setSSELevel(Features, SSE2, Enabled); 668 } else if (Name == "avx") { 669 setSSELevel(Features, AVX, Enabled); 670 } else if (Name == "avx2") { 671 setSSELevel(Features, AVX2, Enabled); 672 } else if (Name == "avx512f") { 673 setSSELevel(Features, AVX512F, Enabled); 674 } else if (Name.startswith("avx512")) { 675 if (Enabled) 676 setSSELevel(Features, AVX512F, Enabled); 677 // Enable BWI instruction if certain features are being enabled. 678 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 679 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 680 Features["avx512bw"] = true; 681 // Also disable some features if BWI is being disabled. 682 if (Name == "avx512bw" && !Enabled) { 683 Features["avx512vbmi"] = false; 684 Features["avx512vbmi2"] = false; 685 Features["avx512bitalg"] = false; 686 Features["avx512bf16"] = false; 687 } 688 } else if (Name == "fma") { 689 if (Enabled) 690 setSSELevel(Features, AVX, Enabled); 691 else 692 setSSELevel(Features, AVX512F, Enabled); 693 } else if (Name == "fma4") { 694 setXOPLevel(Features, FMA4, Enabled); 695 } else if (Name == "xop") { 696 setXOPLevel(Features, XOP, Enabled); 697 } else if (Name == "sse4a") { 698 setXOPLevel(Features, SSE4A, Enabled); 699 } else if (Name == "f16c") { 700 if (Enabled) 701 setSSELevel(Features, AVX, Enabled); 702 else 703 setSSELevel(Features, AVX512F, Enabled); 704 } else if (Name == "sha") { 705 if (Enabled) 706 setSSELevel(Features, SSE2, Enabled); 707 } else if (Name == "sse4") { 708 // We can get here via the __target__ attribute since that's not controlled 709 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 710 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 711 // disabled. 712 if (Enabled) 713 setSSELevel(Features, SSE42, Enabled); 714 else 715 setSSELevel(Features, SSE41, Enabled); 716 } else if (Name == "xsave") { 717 if (!Enabled) 718 Features["xsaveopt"] = false; 719 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 720 if (Enabled) 721 Features["xsave"] = true; 722 } 723 } 724 725 /// handleTargetFeatures - Perform initialization based on the user 726 /// configured set of features. 727 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 728 DiagnosticsEngine &Diags) { 729 for (const auto &Feature : Features) { 730 if (Feature[0] != '+') 731 continue; 732 733 if (Feature == "+aes") { 734 HasAES = true; 735 } else if (Feature == "+vaes") { 736 HasVAES = true; 737 } else if (Feature == "+pclmul") { 738 HasPCLMUL = true; 739 } else if (Feature == "+vpclmulqdq") { 740 HasVPCLMULQDQ = true; 741 } else if (Feature == "+lzcnt") { 742 HasLZCNT = true; 743 } else if (Feature == "+rdrnd") { 744 HasRDRND = true; 745 } else if (Feature == "+fsgsbase") { 746 HasFSGSBASE = true; 747 } else if (Feature == "+bmi") { 748 HasBMI = true; 749 } else if (Feature == "+bmi2") { 750 HasBMI2 = true; 751 } else if (Feature == "+popcnt") { 752 HasPOPCNT = true; 753 } else if (Feature == "+rtm") { 754 HasRTM = true; 755 } else if (Feature == "+prfchw") { 756 HasPRFCHW = true; 757 } else if (Feature == "+rdseed") { 758 HasRDSEED = true; 759 } else if (Feature == "+adx") { 760 HasADX = true; 761 } else if (Feature == "+tbm") { 762 HasTBM = true; 763 } else if (Feature == "+lwp") { 764 HasLWP = true; 765 } else if (Feature == "+fma") { 766 HasFMA = true; 767 } else if (Feature == "+f16c") { 768 HasF16C = true; 769 } else if (Feature == "+gfni") { 770 HasGFNI = true; 771 } else if (Feature == "+avx512cd") { 772 HasAVX512CD = true; 773 } else if (Feature == "+avx512vpopcntdq") { 774 HasAVX512VPOPCNTDQ = true; 775 } else if (Feature == "+avx512vnni") { 776 HasAVX512VNNI = true; 777 } else if (Feature == "+avx512bf16") { 778 HasAVX512BF16 = true; 779 } else if (Feature == "+avx512er") { 780 HasAVX512ER = true; 781 } else if (Feature == "+avx512pf") { 782 HasAVX512PF = true; 783 } else if (Feature == "+avx512dq") { 784 HasAVX512DQ = true; 785 } else if (Feature == "+avx512bitalg") { 786 HasAVX512BITALG = true; 787 } else if (Feature == "+avx512bw") { 788 HasAVX512BW = true; 789 } else if (Feature == "+avx512vl") { 790 HasAVX512VL = true; 791 } else if (Feature == "+avx512vbmi") { 792 HasAVX512VBMI = true; 793 } else if (Feature == "+avx512vbmi2") { 794 HasAVX512VBMI2 = true; 795 } else if (Feature == "+avx512ifma") { 796 HasAVX512IFMA = true; 797 } else if (Feature == "+avx512vp2intersect") { 798 HasAVX512VP2INTERSECT = true; 799 } else if (Feature == "+sha") { 800 HasSHA = true; 801 } else if (Feature == "+mpx") { 802 HasMPX = true; 803 } else if (Feature == "+shstk") { 804 HasSHSTK = true; 805 } else if (Feature == "+movbe") { 806 HasMOVBE = true; 807 } else if (Feature == "+sgx") { 808 HasSGX = true; 809 } else if (Feature == "+cx8") { 810 HasCX8 = true; 811 } else if (Feature == "+cx16") { 812 HasCX16 = true; 813 } else if (Feature == "+fxsr") { 814 HasFXSR = true; 815 } else if (Feature == "+xsave") { 816 HasXSAVE = true; 817 } else if (Feature == "+xsaveopt") { 818 HasXSAVEOPT = true; 819 } else if (Feature == "+xsavec") { 820 HasXSAVEC = true; 821 } else if (Feature == "+xsaves") { 822 HasXSAVES = true; 823 } else if (Feature == "+mwaitx") { 824 HasMWAITX = true; 825 } else if (Feature == "+pku") { 826 HasPKU = true; 827 } else if (Feature == "+clflushopt") { 828 HasCLFLUSHOPT = true; 829 } else if (Feature == "+clwb") { 830 HasCLWB = true; 831 } else if (Feature == "+wbnoinvd") { 832 HasWBNOINVD = true; 833 } else if (Feature == "+prefetchwt1") { 834 HasPREFETCHWT1 = true; 835 } else if (Feature == "+clzero") { 836 HasCLZERO = true; 837 } else if (Feature == "+cldemote") { 838 HasCLDEMOTE = true; 839 } else if (Feature == "+rdpid") { 840 HasRDPID = true; 841 } else if (Feature == "+retpoline-external-thunk") { 842 HasRetpolineExternalThunk = true; 843 } else if (Feature == "+sahf") { 844 HasLAHFSAHF = true; 845 } else if (Feature == "+waitpkg") { 846 HasWAITPKG = true; 847 } else if (Feature == "+movdiri") { 848 HasMOVDIRI = true; 849 } else if (Feature == "+movdir64b") { 850 HasMOVDIR64B = true; 851 } else if (Feature == "+pconfig") { 852 HasPCONFIG = true; 853 } else if (Feature == "+ptwrite") { 854 HasPTWRITE = true; 855 } else if (Feature == "+invpcid") { 856 HasINVPCID = true; 857 } else if (Feature == "+enqcmd") { 858 HasENQCMD = true; 859 } 860 861 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 862 .Case("+avx512f", AVX512F) 863 .Case("+avx2", AVX2) 864 .Case("+avx", AVX) 865 .Case("+sse4.2", SSE42) 866 .Case("+sse4.1", SSE41) 867 .Case("+ssse3", SSSE3) 868 .Case("+sse3", SSE3) 869 .Case("+sse2", SSE2) 870 .Case("+sse", SSE1) 871 .Default(NoSSE); 872 SSELevel = std::max(SSELevel, Level); 873 874 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 875 .Case("+3dnowa", AMD3DNowAthlon) 876 .Case("+3dnow", AMD3DNow) 877 .Case("+mmx", MMX) 878 .Default(NoMMX3DNow); 879 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 880 881 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 882 .Case("+xop", XOP) 883 .Case("+fma4", FMA4) 884 .Case("+sse4a", SSE4A) 885 .Default(NoXOP); 886 XOPLevel = std::max(XOPLevel, XLevel); 887 } 888 889 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 890 // matches the selected sse level. 891 if ((FPMath == FP_SSE && SSELevel < SSE1) || 892 (FPMath == FP_387 && SSELevel >= SSE1)) { 893 Diags.Report(diag::err_target_unsupported_fpmath) 894 << (FPMath == FP_SSE ? "sse" : "387"); 895 return false; 896 } 897 898 SimdDefaultAlign = 899 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 900 return true; 901 } 902 903 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 904 /// definitions for this particular subtarget. 905 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 906 MacroBuilder &Builder) const { 907 // Inline assembly supports X86 flag outputs. 908 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 909 910 std::string CodeModel = getTargetOpts().CodeModel; 911 if (CodeModel == "default") 912 CodeModel = "small"; 913 Builder.defineMacro("__code_model_" + CodeModel + "_"); 914 915 // Target identification. 916 if (getTriple().getArch() == llvm::Triple::x86_64) { 917 Builder.defineMacro("__amd64__"); 918 Builder.defineMacro("__amd64"); 919 Builder.defineMacro("__x86_64"); 920 Builder.defineMacro("__x86_64__"); 921 if (getTriple().getArchName() == "x86_64h") { 922 Builder.defineMacro("__x86_64h"); 923 Builder.defineMacro("__x86_64h__"); 924 } 925 } else { 926 DefineStd(Builder, "i386", Opts); 927 } 928 929 Builder.defineMacro("__SEG_GS"); 930 Builder.defineMacro("__SEG_FS"); 931 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 932 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 933 934 // Subtarget options. 935 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 936 // truly should be based on -mtune options. 937 switch (CPU) { 938 case CK_Generic: 939 break; 940 case CK_i386: 941 // The rest are coming from the i386 define above. 942 Builder.defineMacro("__tune_i386__"); 943 break; 944 case CK_i486: 945 case CK_WinChipC6: 946 case CK_WinChip2: 947 case CK_C3: 948 defineCPUMacros(Builder, "i486"); 949 break; 950 case CK_PentiumMMX: 951 Builder.defineMacro("__pentium_mmx__"); 952 Builder.defineMacro("__tune_pentium_mmx__"); 953 LLVM_FALLTHROUGH; 954 case CK_i586: 955 case CK_Pentium: 956 defineCPUMacros(Builder, "i586"); 957 defineCPUMacros(Builder, "pentium"); 958 break; 959 case CK_Pentium3: 960 case CK_PentiumM: 961 Builder.defineMacro("__tune_pentium3__"); 962 LLVM_FALLTHROUGH; 963 case CK_Pentium2: 964 case CK_C3_2: 965 Builder.defineMacro("__tune_pentium2__"); 966 LLVM_FALLTHROUGH; 967 case CK_PentiumPro: 968 case CK_i686: 969 defineCPUMacros(Builder, "i686"); 970 defineCPUMacros(Builder, "pentiumpro"); 971 break; 972 case CK_Pentium4: 973 defineCPUMacros(Builder, "pentium4"); 974 break; 975 case CK_Yonah: 976 case CK_Prescott: 977 case CK_Nocona: 978 defineCPUMacros(Builder, "nocona"); 979 break; 980 case CK_Core2: 981 case CK_Penryn: 982 defineCPUMacros(Builder, "core2"); 983 break; 984 case CK_Bonnell: 985 defineCPUMacros(Builder, "atom"); 986 break; 987 case CK_Silvermont: 988 defineCPUMacros(Builder, "slm"); 989 break; 990 case CK_Goldmont: 991 defineCPUMacros(Builder, "goldmont"); 992 break; 993 case CK_GoldmontPlus: 994 defineCPUMacros(Builder, "goldmont_plus"); 995 break; 996 case CK_Tremont: 997 defineCPUMacros(Builder, "tremont"); 998 break; 999 case CK_Nehalem: 1000 case CK_Westmere: 1001 case CK_SandyBridge: 1002 case CK_IvyBridge: 1003 case CK_Haswell: 1004 case CK_Broadwell: 1005 case CK_SkylakeClient: 1006 case CK_SkylakeServer: 1007 case CK_Cascadelake: 1008 case CK_Cooperlake: 1009 case CK_Cannonlake: 1010 case CK_IcelakeClient: 1011 case CK_IcelakeServer: 1012 case CK_Tigerlake: 1013 // FIXME: Historically, we defined this legacy name, it would be nice to 1014 // remove it at some point. We've never exposed fine-grained names for 1015 // recent primary x86 CPUs, and we should keep it that way. 1016 defineCPUMacros(Builder, "corei7"); 1017 break; 1018 case CK_KNL: 1019 defineCPUMacros(Builder, "knl"); 1020 break; 1021 case CK_KNM: 1022 break; 1023 case CK_Lakemont: 1024 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1025 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1026 Builder.defineMacro("__tune_lakemont__"); 1027 break; 1028 case CK_K6_2: 1029 Builder.defineMacro("__k6_2__"); 1030 Builder.defineMacro("__tune_k6_2__"); 1031 LLVM_FALLTHROUGH; 1032 case CK_K6_3: 1033 if (CPU != CK_K6_2) { // In case of fallthrough 1034 // FIXME: GCC may be enabling these in cases where some other k6 1035 // architecture is specified but -m3dnow is explicitly provided. The 1036 // exact semantics need to be determined and emulated here. 1037 Builder.defineMacro("__k6_3__"); 1038 Builder.defineMacro("__tune_k6_3__"); 1039 } 1040 LLVM_FALLTHROUGH; 1041 case CK_K6: 1042 defineCPUMacros(Builder, "k6"); 1043 break; 1044 case CK_Athlon: 1045 case CK_AthlonXP: 1046 defineCPUMacros(Builder, "athlon"); 1047 if (SSELevel != NoSSE) { 1048 Builder.defineMacro("__athlon_sse__"); 1049 Builder.defineMacro("__tune_athlon_sse__"); 1050 } 1051 break; 1052 case CK_K8: 1053 case CK_K8SSE3: 1054 case CK_x86_64: 1055 defineCPUMacros(Builder, "k8"); 1056 break; 1057 case CK_AMDFAM10: 1058 defineCPUMacros(Builder, "amdfam10"); 1059 break; 1060 case CK_BTVER1: 1061 defineCPUMacros(Builder, "btver1"); 1062 break; 1063 case CK_BTVER2: 1064 defineCPUMacros(Builder, "btver2"); 1065 break; 1066 case CK_BDVER1: 1067 defineCPUMacros(Builder, "bdver1"); 1068 break; 1069 case CK_BDVER2: 1070 defineCPUMacros(Builder, "bdver2"); 1071 break; 1072 case CK_BDVER3: 1073 defineCPUMacros(Builder, "bdver3"); 1074 break; 1075 case CK_BDVER4: 1076 defineCPUMacros(Builder, "bdver4"); 1077 break; 1078 case CK_ZNVER1: 1079 defineCPUMacros(Builder, "znver1"); 1080 break; 1081 case CK_ZNVER2: 1082 defineCPUMacros(Builder, "znver2"); 1083 break; 1084 case CK_Geode: 1085 defineCPUMacros(Builder, "geode"); 1086 break; 1087 } 1088 1089 // Target properties. 1090 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1091 1092 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1093 // functions in glibc header files that use FP Stack inline asm which the 1094 // backend can't deal with (PR879). 1095 Builder.defineMacro("__NO_MATH_INLINES"); 1096 1097 if (HasAES) 1098 Builder.defineMacro("__AES__"); 1099 1100 if (HasVAES) 1101 Builder.defineMacro("__VAES__"); 1102 1103 if (HasPCLMUL) 1104 Builder.defineMacro("__PCLMUL__"); 1105 1106 if (HasVPCLMULQDQ) 1107 Builder.defineMacro("__VPCLMULQDQ__"); 1108 1109 if (HasLZCNT) 1110 Builder.defineMacro("__LZCNT__"); 1111 1112 if (HasRDRND) 1113 Builder.defineMacro("__RDRND__"); 1114 1115 if (HasFSGSBASE) 1116 Builder.defineMacro("__FSGSBASE__"); 1117 1118 if (HasBMI) 1119 Builder.defineMacro("__BMI__"); 1120 1121 if (HasBMI2) 1122 Builder.defineMacro("__BMI2__"); 1123 1124 if (HasPOPCNT) 1125 Builder.defineMacro("__POPCNT__"); 1126 1127 if (HasRTM) 1128 Builder.defineMacro("__RTM__"); 1129 1130 if (HasPRFCHW) 1131 Builder.defineMacro("__PRFCHW__"); 1132 1133 if (HasRDSEED) 1134 Builder.defineMacro("__RDSEED__"); 1135 1136 if (HasADX) 1137 Builder.defineMacro("__ADX__"); 1138 1139 if (HasTBM) 1140 Builder.defineMacro("__TBM__"); 1141 1142 if (HasLWP) 1143 Builder.defineMacro("__LWP__"); 1144 1145 if (HasMWAITX) 1146 Builder.defineMacro("__MWAITX__"); 1147 1148 if (HasMOVBE) 1149 Builder.defineMacro("__MOVBE__"); 1150 1151 switch (XOPLevel) { 1152 case XOP: 1153 Builder.defineMacro("__XOP__"); 1154 LLVM_FALLTHROUGH; 1155 case FMA4: 1156 Builder.defineMacro("__FMA4__"); 1157 LLVM_FALLTHROUGH; 1158 case SSE4A: 1159 Builder.defineMacro("__SSE4A__"); 1160 LLVM_FALLTHROUGH; 1161 case NoXOP: 1162 break; 1163 } 1164 1165 if (HasFMA) 1166 Builder.defineMacro("__FMA__"); 1167 1168 if (HasF16C) 1169 Builder.defineMacro("__F16C__"); 1170 1171 if (HasGFNI) 1172 Builder.defineMacro("__GFNI__"); 1173 1174 if (HasAVX512CD) 1175 Builder.defineMacro("__AVX512CD__"); 1176 if (HasAVX512VPOPCNTDQ) 1177 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1178 if (HasAVX512VNNI) 1179 Builder.defineMacro("__AVX512VNNI__"); 1180 if (HasAVX512BF16) 1181 Builder.defineMacro("__AVX512BF16__"); 1182 if (HasAVX512ER) 1183 Builder.defineMacro("__AVX512ER__"); 1184 if (HasAVX512PF) 1185 Builder.defineMacro("__AVX512PF__"); 1186 if (HasAVX512DQ) 1187 Builder.defineMacro("__AVX512DQ__"); 1188 if (HasAVX512BITALG) 1189 Builder.defineMacro("__AVX512BITALG__"); 1190 if (HasAVX512BW) 1191 Builder.defineMacro("__AVX512BW__"); 1192 if (HasAVX512VL) 1193 Builder.defineMacro("__AVX512VL__"); 1194 if (HasAVX512VBMI) 1195 Builder.defineMacro("__AVX512VBMI__"); 1196 if (HasAVX512VBMI2) 1197 Builder.defineMacro("__AVX512VBMI2__"); 1198 if (HasAVX512IFMA) 1199 Builder.defineMacro("__AVX512IFMA__"); 1200 if (HasAVX512VP2INTERSECT) 1201 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1202 if (HasSHA) 1203 Builder.defineMacro("__SHA__"); 1204 1205 if (HasFXSR) 1206 Builder.defineMacro("__FXSR__"); 1207 if (HasXSAVE) 1208 Builder.defineMacro("__XSAVE__"); 1209 if (HasXSAVEOPT) 1210 Builder.defineMacro("__XSAVEOPT__"); 1211 if (HasXSAVEC) 1212 Builder.defineMacro("__XSAVEC__"); 1213 if (HasXSAVES) 1214 Builder.defineMacro("__XSAVES__"); 1215 if (HasPKU) 1216 Builder.defineMacro("__PKU__"); 1217 if (HasCLFLUSHOPT) 1218 Builder.defineMacro("__CLFLUSHOPT__"); 1219 if (HasCLWB) 1220 Builder.defineMacro("__CLWB__"); 1221 if (HasWBNOINVD) 1222 Builder.defineMacro("__WBNOINVD__"); 1223 if (HasMPX) 1224 Builder.defineMacro("__MPX__"); 1225 if (HasSHSTK) 1226 Builder.defineMacro("__SHSTK__"); 1227 if (HasSGX) 1228 Builder.defineMacro("__SGX__"); 1229 if (HasPREFETCHWT1) 1230 Builder.defineMacro("__PREFETCHWT1__"); 1231 if (HasCLZERO) 1232 Builder.defineMacro("__CLZERO__"); 1233 if (HasRDPID) 1234 Builder.defineMacro("__RDPID__"); 1235 if (HasCLDEMOTE) 1236 Builder.defineMacro("__CLDEMOTE__"); 1237 if (HasWAITPKG) 1238 Builder.defineMacro("__WAITPKG__"); 1239 if (HasMOVDIRI) 1240 Builder.defineMacro("__MOVDIRI__"); 1241 if (HasMOVDIR64B) 1242 Builder.defineMacro("__MOVDIR64B__"); 1243 if (HasPCONFIG) 1244 Builder.defineMacro("__PCONFIG__"); 1245 if (HasPTWRITE) 1246 Builder.defineMacro("__PTWRITE__"); 1247 if (HasINVPCID) 1248 Builder.defineMacro("__INVPCID__"); 1249 if (HasENQCMD) 1250 Builder.defineMacro("__ENQCMD__"); 1251 1252 // Each case falls through to the previous one here. 1253 switch (SSELevel) { 1254 case AVX512F: 1255 Builder.defineMacro("__AVX512F__"); 1256 LLVM_FALLTHROUGH; 1257 case AVX2: 1258 Builder.defineMacro("__AVX2__"); 1259 LLVM_FALLTHROUGH; 1260 case AVX: 1261 Builder.defineMacro("__AVX__"); 1262 LLVM_FALLTHROUGH; 1263 case SSE42: 1264 Builder.defineMacro("__SSE4_2__"); 1265 LLVM_FALLTHROUGH; 1266 case SSE41: 1267 Builder.defineMacro("__SSE4_1__"); 1268 LLVM_FALLTHROUGH; 1269 case SSSE3: 1270 Builder.defineMacro("__SSSE3__"); 1271 LLVM_FALLTHROUGH; 1272 case SSE3: 1273 Builder.defineMacro("__SSE3__"); 1274 LLVM_FALLTHROUGH; 1275 case SSE2: 1276 Builder.defineMacro("__SSE2__"); 1277 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1278 LLVM_FALLTHROUGH; 1279 case SSE1: 1280 Builder.defineMacro("__SSE__"); 1281 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1282 LLVM_FALLTHROUGH; 1283 case NoSSE: 1284 break; 1285 } 1286 1287 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1288 switch (SSELevel) { 1289 case AVX512F: 1290 case AVX2: 1291 case AVX: 1292 case SSE42: 1293 case SSE41: 1294 case SSSE3: 1295 case SSE3: 1296 case SSE2: 1297 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1298 break; 1299 case SSE1: 1300 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1301 break; 1302 default: 1303 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1304 break; 1305 } 1306 } 1307 1308 // Each case falls through to the previous one here. 1309 switch (MMX3DNowLevel) { 1310 case AMD3DNowAthlon: 1311 Builder.defineMacro("__3dNOW_A__"); 1312 LLVM_FALLTHROUGH; 1313 case AMD3DNow: 1314 Builder.defineMacro("__3dNOW__"); 1315 LLVM_FALLTHROUGH; 1316 case MMX: 1317 Builder.defineMacro("__MMX__"); 1318 LLVM_FALLTHROUGH; 1319 case NoMMX3DNow: 1320 break; 1321 } 1322 1323 if (CPU >= CK_i486 || CPU == CK_Generic) { 1324 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1325 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1326 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1327 } 1328 if (HasCX8) 1329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1330 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1332 1333 if (HasFloat128) 1334 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1335 } 1336 1337 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1338 return llvm::StringSwitch<bool>(Name) 1339 .Case("3dnow", true) 1340 .Case("3dnowa", true) 1341 .Case("adx", true) 1342 .Case("aes", true) 1343 .Case("avx", true) 1344 .Case("avx2", true) 1345 .Case("avx512f", true) 1346 .Case("avx512cd", true) 1347 .Case("avx512vpopcntdq", true) 1348 .Case("avx512vnni", true) 1349 .Case("avx512bf16", true) 1350 .Case("avx512er", true) 1351 .Case("avx512pf", true) 1352 .Case("avx512dq", true) 1353 .Case("avx512bitalg", true) 1354 .Case("avx512bw", true) 1355 .Case("avx512vl", true) 1356 .Case("avx512vbmi", true) 1357 .Case("avx512vbmi2", true) 1358 .Case("avx512ifma", true) 1359 .Case("avx512vp2intersect", true) 1360 .Case("bmi", true) 1361 .Case("bmi2", true) 1362 .Case("cldemote", true) 1363 .Case("clflushopt", true) 1364 .Case("clwb", true) 1365 .Case("clzero", true) 1366 .Case("cx16", true) 1367 .Case("enqcmd", true) 1368 .Case("f16c", true) 1369 .Case("fma", true) 1370 .Case("fma4", true) 1371 .Case("fsgsbase", true) 1372 .Case("fxsr", true) 1373 .Case("gfni", true) 1374 .Case("invpcid", true) 1375 .Case("lwp", true) 1376 .Case("lzcnt", true) 1377 .Case("mmx", true) 1378 .Case("movbe", true) 1379 .Case("movdiri", true) 1380 .Case("movdir64b", true) 1381 .Case("mpx", true) 1382 .Case("mwaitx", true) 1383 .Case("pclmul", true) 1384 .Case("pconfig", true) 1385 .Case("pku", true) 1386 .Case("popcnt", true) 1387 .Case("prefetchwt1", true) 1388 .Case("prfchw", true) 1389 .Case("ptwrite", true) 1390 .Case("rdpid", true) 1391 .Case("rdrnd", true) 1392 .Case("rdseed", true) 1393 .Case("rtm", true) 1394 .Case("sahf", true) 1395 .Case("sgx", true) 1396 .Case("sha", true) 1397 .Case("shstk", true) 1398 .Case("sse", true) 1399 .Case("sse2", true) 1400 .Case("sse3", true) 1401 .Case("ssse3", true) 1402 .Case("sse4", true) 1403 .Case("sse4.1", true) 1404 .Case("sse4.2", true) 1405 .Case("sse4a", true) 1406 .Case("tbm", true) 1407 .Case("vaes", true) 1408 .Case("vpclmulqdq", true) 1409 .Case("wbnoinvd", true) 1410 .Case("waitpkg", true) 1411 .Case("x87", true) 1412 .Case("xop", true) 1413 .Case("xsave", true) 1414 .Case("xsavec", true) 1415 .Case("xsaves", true) 1416 .Case("xsaveopt", true) 1417 .Default(false); 1418 } 1419 1420 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1421 return llvm::StringSwitch<bool>(Feature) 1422 .Case("adx", HasADX) 1423 .Case("aes", HasAES) 1424 .Case("avx", SSELevel >= AVX) 1425 .Case("avx2", SSELevel >= AVX2) 1426 .Case("avx512f", SSELevel >= AVX512F) 1427 .Case("avx512cd", HasAVX512CD) 1428 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1429 .Case("avx512vnni", HasAVX512VNNI) 1430 .Case("avx512bf16", HasAVX512BF16) 1431 .Case("avx512er", HasAVX512ER) 1432 .Case("avx512pf", HasAVX512PF) 1433 .Case("avx512dq", HasAVX512DQ) 1434 .Case("avx512bitalg", HasAVX512BITALG) 1435 .Case("avx512bw", HasAVX512BW) 1436 .Case("avx512vl", HasAVX512VL) 1437 .Case("avx512vbmi", HasAVX512VBMI) 1438 .Case("avx512vbmi2", HasAVX512VBMI2) 1439 .Case("avx512ifma", HasAVX512IFMA) 1440 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1441 .Case("bmi", HasBMI) 1442 .Case("bmi2", HasBMI2) 1443 .Case("cldemote", HasCLDEMOTE) 1444 .Case("clflushopt", HasCLFLUSHOPT) 1445 .Case("clwb", HasCLWB) 1446 .Case("clzero", HasCLZERO) 1447 .Case("cx8", HasCX8) 1448 .Case("cx16", HasCX16) 1449 .Case("enqcmd", HasENQCMD) 1450 .Case("f16c", HasF16C) 1451 .Case("fma", HasFMA) 1452 .Case("fma4", XOPLevel >= FMA4) 1453 .Case("fsgsbase", HasFSGSBASE) 1454 .Case("fxsr", HasFXSR) 1455 .Case("gfni", HasGFNI) 1456 .Case("invpcid", HasINVPCID) 1457 .Case("lwp", HasLWP) 1458 .Case("lzcnt", HasLZCNT) 1459 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1460 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1461 .Case("mmx", MMX3DNowLevel >= MMX) 1462 .Case("movbe", HasMOVBE) 1463 .Case("movdiri", HasMOVDIRI) 1464 .Case("movdir64b", HasMOVDIR64B) 1465 .Case("mpx", HasMPX) 1466 .Case("mwaitx", HasMWAITX) 1467 .Case("pclmul", HasPCLMUL) 1468 .Case("pconfig", HasPCONFIG) 1469 .Case("pku", HasPKU) 1470 .Case("popcnt", HasPOPCNT) 1471 .Case("prefetchwt1", HasPREFETCHWT1) 1472 .Case("prfchw", HasPRFCHW) 1473 .Case("ptwrite", HasPTWRITE) 1474 .Case("rdpid", HasRDPID) 1475 .Case("rdrnd", HasRDRND) 1476 .Case("rdseed", HasRDSEED) 1477 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1478 .Case("rtm", HasRTM) 1479 .Case("sahf", HasLAHFSAHF) 1480 .Case("sgx", HasSGX) 1481 .Case("sha", HasSHA) 1482 .Case("shstk", HasSHSTK) 1483 .Case("sse", SSELevel >= SSE1) 1484 .Case("sse2", SSELevel >= SSE2) 1485 .Case("sse3", SSELevel >= SSE3) 1486 .Case("ssse3", SSELevel >= SSSE3) 1487 .Case("sse4.1", SSELevel >= SSE41) 1488 .Case("sse4.2", SSELevel >= SSE42) 1489 .Case("sse4a", XOPLevel >= SSE4A) 1490 .Case("tbm", HasTBM) 1491 .Case("vaes", HasVAES) 1492 .Case("vpclmulqdq", HasVPCLMULQDQ) 1493 .Case("wbnoinvd", HasWBNOINVD) 1494 .Case("waitpkg", HasWAITPKG) 1495 .Case("x86", true) 1496 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1497 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1498 .Case("xop", XOPLevel >= XOP) 1499 .Case("xsave", HasXSAVE) 1500 .Case("xsavec", HasXSAVEC) 1501 .Case("xsaves", HasXSAVES) 1502 .Case("xsaveopt", HasXSAVEOPT) 1503 .Default(false); 1504 } 1505 1506 // We can't use a generic validation scheme for the features accepted here 1507 // versus subtarget features accepted in the target attribute because the 1508 // bitfield structure that's initialized in the runtime only supports the 1509 // below currently rather than the full range of subtarget features. (See 1510 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1511 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1512 return llvm::StringSwitch<bool>(FeatureStr) 1513 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1514 #include "llvm/Support/X86TargetParser.def" 1515 .Default(false); 1516 } 1517 1518 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1519 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1520 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1521 #include "llvm/Support/X86TargetParser.def" 1522 ; 1523 // Note, this function should only be used after ensuring the value is 1524 // correct, so it asserts if the value is out of range. 1525 } 1526 1527 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1528 enum class FeatPriority { 1529 #define FEATURE(FEAT) FEAT, 1530 #include "clang/Basic/X86Target.def" 1531 }; 1532 switch (Feat) { 1533 #define FEATURE(FEAT) \ 1534 case llvm::X86::FEAT: \ 1535 return static_cast<unsigned>(FeatPriority::FEAT); 1536 #include "clang/Basic/X86Target.def" 1537 default: 1538 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1539 } 1540 } 1541 1542 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1543 // Valid CPUs have a 'key feature' that compares just better than its key 1544 // feature. 1545 CPUKind Kind = getCPUKind(Name); 1546 if (Kind != CK_Generic) { 1547 switch (Kind) { 1548 default: 1549 llvm_unreachable( 1550 "CPU Type without a key feature used in 'target' attribute"); 1551 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1552 case CK_##ENUM: \ 1553 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1554 #include "clang/Basic/X86Target.def" 1555 } 1556 } 1557 1558 // Now we know we have a feature, so get its priority and shift it a few so 1559 // that we have sufficient room for the CPUs (above). 1560 return getFeaturePriority(getFeature(Name)) << 1; 1561 } 1562 1563 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1564 return llvm::StringSwitch<bool>(Name) 1565 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1566 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1567 #include "clang/Basic/X86Target.def" 1568 .Default(false); 1569 } 1570 1571 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1572 return llvm::StringSwitch<StringRef>(Name) 1573 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1574 #include "clang/Basic/X86Target.def" 1575 .Default(Name); 1576 } 1577 1578 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1579 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1580 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1581 #include "clang/Basic/X86Target.def" 1582 .Default(0); 1583 } 1584 1585 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1586 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1587 StringRef WholeList = 1588 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1589 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1590 #include "clang/Basic/X86Target.def" 1591 .Default(""); 1592 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1593 } 1594 1595 // We can't use a generic validation scheme for the cpus accepted here 1596 // versus subtarget cpus accepted in the target attribute because the 1597 // variables intitialized by the runtime only support the below currently 1598 // rather than the full range of cpus. 1599 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1600 return llvm::StringSwitch<bool>(FeatureStr) 1601 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1602 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1603 .Cases(STR, ALIAS, true) 1604 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1605 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1606 #include "llvm/Support/X86TargetParser.def" 1607 .Default(false); 1608 } 1609 1610 static unsigned matchAsmCCConstraint(const char *&Name) { 1611 auto RV = llvm::StringSwitch<unsigned>(Name) 1612 .Case("@cca", 4) 1613 .Case("@ccae", 5) 1614 .Case("@ccb", 4) 1615 .Case("@ccbe", 5) 1616 .Case("@ccc", 4) 1617 .Case("@cce", 4) 1618 .Case("@ccz", 4) 1619 .Case("@ccg", 4) 1620 .Case("@ccge", 5) 1621 .Case("@ccl", 4) 1622 .Case("@ccle", 5) 1623 .Case("@ccna", 5) 1624 .Case("@ccnae", 6) 1625 .Case("@ccnb", 5) 1626 .Case("@ccnbe", 6) 1627 .Case("@ccnc", 5) 1628 .Case("@ccne", 5) 1629 .Case("@ccnz", 5) 1630 .Case("@ccng", 5) 1631 .Case("@ccnge", 6) 1632 .Case("@ccnl", 5) 1633 .Case("@ccnle", 6) 1634 .Case("@ccno", 5) 1635 .Case("@ccnp", 5) 1636 .Case("@ccns", 5) 1637 .Case("@cco", 4) 1638 .Case("@ccp", 4) 1639 .Case("@ccs", 4) 1640 .Default(0); 1641 return RV; 1642 } 1643 1644 bool X86TargetInfo::validateAsmConstraint( 1645 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1646 switch (*Name) { 1647 default: 1648 return false; 1649 // Constant constraints. 1650 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1651 // instructions. 1652 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1653 // x86_64 instructions. 1654 case 's': 1655 Info.setRequiresImmediate(); 1656 return true; 1657 case 'I': 1658 Info.setRequiresImmediate(0, 31); 1659 return true; 1660 case 'J': 1661 Info.setRequiresImmediate(0, 63); 1662 return true; 1663 case 'K': 1664 Info.setRequiresImmediate(-128, 127); 1665 return true; 1666 case 'L': 1667 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1668 return true; 1669 case 'M': 1670 Info.setRequiresImmediate(0, 3); 1671 return true; 1672 case 'N': 1673 Info.setRequiresImmediate(0, 255); 1674 return true; 1675 case 'O': 1676 Info.setRequiresImmediate(0, 127); 1677 return true; 1678 // Register constraints. 1679 case 'Y': // 'Y' is the first character for several 2-character constraints. 1680 // Shift the pointer to the second character of the constraint. 1681 Name++; 1682 switch (*Name) { 1683 default: 1684 return false; 1685 case 'z': 1686 case '0': // First SSE register. 1687 case '2': 1688 case 't': // Any SSE register, when SSE2 is enabled. 1689 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1690 case 'm': // Any MMX register, when inter-unit moves enabled. 1691 case 'k': // AVX512 arch mask registers: k1-k7. 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 case 'f': // Any x87 floating point stack register. 1696 // Constraint 'f' cannot be used for output operands. 1697 if (Info.ConstraintStr[0] == '=') 1698 return false; 1699 Info.setAllowsRegister(); 1700 return true; 1701 case 'a': // eax. 1702 case 'b': // ebx. 1703 case 'c': // ecx. 1704 case 'd': // edx. 1705 case 'S': // esi. 1706 case 'D': // edi. 1707 case 'A': // edx:eax. 1708 case 't': // Top of floating point stack. 1709 case 'u': // Second from top of floating point stack. 1710 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1711 case 'y': // Any MMX register. 1712 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1713 case 'x': // Any SSE register. 1714 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1715 // for intermideate k reg operations). 1716 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1717 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1718 case 'l': // "Index" registers: any general register that can be used as an 1719 // index in a base+index memory access. 1720 Info.setAllowsRegister(); 1721 return true; 1722 // Floating point constant constraints. 1723 case 'C': // SSE floating point constant. 1724 case 'G': // x87 floating point constant. 1725 return true; 1726 case '@': 1727 // CC condition changes. 1728 if (auto Len = matchAsmCCConstraint(Name)) { 1729 Name += Len - 1; 1730 Info.setAllowsRegister(); 1731 return true; 1732 } 1733 return false; 1734 } 1735 } 1736 1737 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1738 unsigned Size) const { 1739 // Strip off constraint modifiers. 1740 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1741 Constraint = Constraint.substr(1); 1742 1743 return validateOperandSize(Constraint, Size); 1744 } 1745 1746 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1747 unsigned Size) const { 1748 return validateOperandSize(Constraint, Size); 1749 } 1750 1751 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1752 unsigned Size) const { 1753 switch (Constraint[0]) { 1754 default: 1755 break; 1756 case 'k': 1757 // Registers k0-k7 (AVX512) size limit is 64 bit. 1758 case 'y': 1759 return Size <= 64; 1760 case 'f': 1761 case 't': 1762 case 'u': 1763 return Size <= 128; 1764 case 'Y': 1765 // 'Y' is the first character for several 2-character constraints. 1766 switch (Constraint[1]) { 1767 default: 1768 return false; 1769 case 'm': 1770 // 'Ym' is synonymous with 'y'. 1771 case 'k': 1772 return Size <= 64; 1773 case 'z': 1774 case '0': 1775 // XMM0 1776 if (SSELevel >= SSE1) 1777 return Size <= 128U; 1778 return false; 1779 case 'i': 1780 case 't': 1781 case '2': 1782 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1783 if (SSELevel < SSE2) 1784 return false; 1785 break; 1786 } 1787 LLVM_FALLTHROUGH; 1788 case 'v': 1789 case 'x': 1790 if (SSELevel >= AVX512F) 1791 // 512-bit zmm registers can be used if target supports AVX512F. 1792 return Size <= 512U; 1793 else if (SSELevel >= AVX) 1794 // 256-bit ymm registers can be used if target supports AVX. 1795 return Size <= 256U; 1796 return Size <= 128U; 1797 1798 } 1799 1800 return true; 1801 } 1802 1803 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1804 switch (*Constraint) { 1805 case '@': 1806 if (auto Len = matchAsmCCConstraint(Constraint)) { 1807 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1808 Constraint += Len - 1; 1809 return Converted; 1810 } 1811 return std::string(1, *Constraint); 1812 case 'a': 1813 return std::string("{ax}"); 1814 case 'b': 1815 return std::string("{bx}"); 1816 case 'c': 1817 return std::string("{cx}"); 1818 case 'd': 1819 return std::string("{dx}"); 1820 case 'S': 1821 return std::string("{si}"); 1822 case 'D': 1823 return std::string("{di}"); 1824 case 'p': // address 1825 return std::string("im"); 1826 case 't': // top of floating point stack. 1827 return std::string("{st}"); 1828 case 'u': // second from top of floating point stack. 1829 return std::string("{st(1)}"); // second from top of floating point stack. 1830 case 'Y': 1831 switch (Constraint[1]) { 1832 default: 1833 // Break from inner switch and fall through (copy single char), 1834 // continue parsing after copying the current constraint into 1835 // the return string. 1836 break; 1837 case 'k': 1838 case 'm': 1839 case 'i': 1840 case 't': 1841 case 'z': 1842 case '0': 1843 case '2': 1844 // "^" hints llvm that this is a 2 letter constraint. 1845 // "Constraint++" is used to promote the string iterator 1846 // to the next constraint. 1847 return std::string("^") + std::string(Constraint++, 2); 1848 } 1849 LLVM_FALLTHROUGH; 1850 default: 1851 return std::string(1, *Constraint); 1852 } 1853 } 1854 1855 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1856 // Perform any per-CPU checks necessary to determine if this CPU is 1857 // acceptable. 1858 switch (Kind) { 1859 case CK_Generic: 1860 // No processor selected! 1861 return false; 1862 #define PROC(ENUM, STRING, IS64BIT) \ 1863 case CK_##ENUM: \ 1864 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1865 #include "clang/Basic/X86Target.def" 1866 } 1867 llvm_unreachable("Unhandled CPU kind"); 1868 } 1869 1870 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1871 #define PROC(ENUM, STRING, IS64BIT) \ 1872 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1873 Values.emplace_back(STRING); 1874 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1875 #define PROC_ALIAS(ENUM, ALIAS) \ 1876 if (checkCPUKind(CK_##ENUM)) \ 1877 Values.emplace_back(ALIAS); 1878 #include "clang/Basic/X86Target.def" 1879 } 1880 1881 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1882 return llvm::StringSwitch<CPUKind>(CPU) 1883 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1884 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1885 #include "clang/Basic/X86Target.def" 1886 .Default(CK_Generic); 1887 } 1888 1889 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1890 return llvm::makeArrayRef(GCCRegNames); 1891 } 1892 1893 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1894 return llvm::makeArrayRef(AddlRegNames); 1895 } 1896 1897 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1898 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1899 Builtin::FirstTSBuiltin + 1); 1900 } 1901 1902 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1903 return llvm::makeArrayRef(BuiltinInfoX86, 1904 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1905 } 1906