1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 switch (Kind) { 119 case CK_Generic: 120 case CK_i386: 121 case CK_i486: 122 case CK_i586: 123 case CK_Pentium: 124 case CK_PentiumPro: 125 case CK_i686: 126 case CK_Lakemont: 127 break; 128 129 case CK_PentiumMMX: 130 case CK_Pentium2: 131 case CK_K6: 132 case CK_WinChipC6: 133 setFeatureEnabledImpl(Features, "mmx", true); 134 break; 135 136 case CK_IcelakeServer: 137 setFeatureEnabledImpl(Features, "pconfig", true); 138 setFeatureEnabledImpl(Features, "wbnoinvd", true); 139 LLVM_FALLTHROUGH; 140 case CK_IcelakeClient: 141 setFeatureEnabledImpl(Features, "vaes", true); 142 setFeatureEnabledImpl(Features, "gfni", true); 143 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 144 setFeatureEnabledImpl(Features, "avx512bitalg", true); 145 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 146 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 147 setFeatureEnabledImpl(Features, "rdpid", true); 148 LLVM_FALLTHROUGH; 149 case CK_Cannonlake: 150 setFeatureEnabledImpl(Features, "avx512ifma", true); 151 setFeatureEnabledImpl(Features, "avx512vbmi", true); 152 setFeatureEnabledImpl(Features, "sha", true); 153 LLVM_FALLTHROUGH; 154 case CK_Cascadelake: 155 //Cannonlake has no VNNI feature inside while Icelake has 156 if (Kind != CK_Cannonlake) 157 // CLK inherits all SKX features plus AVX512_VNNI 158 setFeatureEnabledImpl(Features, "avx512vnni", true); 159 LLVM_FALLTHROUGH; 160 case CK_SkylakeServer: 161 setFeatureEnabledImpl(Features, "avx512f", true); 162 setFeatureEnabledImpl(Features, "avx512cd", true); 163 setFeatureEnabledImpl(Features, "avx512dq", true); 164 setFeatureEnabledImpl(Features, "avx512bw", true); 165 setFeatureEnabledImpl(Features, "avx512vl", true); 166 setFeatureEnabledImpl(Features, "pku", true); 167 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 168 setFeatureEnabledImpl(Features, "clwb", true); 169 LLVM_FALLTHROUGH; 170 case CK_SkylakeClient: 171 setFeatureEnabledImpl(Features, "xsavec", true); 172 setFeatureEnabledImpl(Features, "xsaves", true); 173 setFeatureEnabledImpl(Features, "mpx", true); 174 if (Kind != CK_SkylakeServer 175 && Kind != CK_Cascadelake) 176 // SKX/CLX inherits all SKL features, except SGX 177 setFeatureEnabledImpl(Features, "sgx", true); 178 setFeatureEnabledImpl(Features, "clflushopt", true); 179 setFeatureEnabledImpl(Features, "aes", true); 180 LLVM_FALLTHROUGH; 181 case CK_Broadwell: 182 setFeatureEnabledImpl(Features, "rdseed", true); 183 setFeatureEnabledImpl(Features, "adx", true); 184 setFeatureEnabledImpl(Features, "prfchw", true); 185 LLVM_FALLTHROUGH; 186 case CK_Haswell: 187 setFeatureEnabledImpl(Features, "avx2", true); 188 setFeatureEnabledImpl(Features, "lzcnt", true); 189 setFeatureEnabledImpl(Features, "bmi", true); 190 setFeatureEnabledImpl(Features, "bmi2", true); 191 setFeatureEnabledImpl(Features, "fma", true); 192 setFeatureEnabledImpl(Features, "invpcid", true); 193 setFeatureEnabledImpl(Features, "movbe", true); 194 LLVM_FALLTHROUGH; 195 case CK_IvyBridge: 196 setFeatureEnabledImpl(Features, "rdrnd", true); 197 setFeatureEnabledImpl(Features, "f16c", true); 198 setFeatureEnabledImpl(Features, "fsgsbase", true); 199 LLVM_FALLTHROUGH; 200 case CK_SandyBridge: 201 setFeatureEnabledImpl(Features, "avx", true); 202 setFeatureEnabledImpl(Features, "xsave", true); 203 setFeatureEnabledImpl(Features, "xsaveopt", true); 204 LLVM_FALLTHROUGH; 205 case CK_Westmere: 206 setFeatureEnabledImpl(Features, "pclmul", true); 207 LLVM_FALLTHROUGH; 208 case CK_Nehalem: 209 setFeatureEnabledImpl(Features, "sse4.2", true); 210 LLVM_FALLTHROUGH; 211 case CK_Penryn: 212 setFeatureEnabledImpl(Features, "sse4.1", true); 213 LLVM_FALLTHROUGH; 214 case CK_Core2: 215 setFeatureEnabledImpl(Features, "ssse3", true); 216 setFeatureEnabledImpl(Features, "sahf", true); 217 LLVM_FALLTHROUGH; 218 case CK_Nocona: 219 setFeatureEnabledImpl(Features, "cx16", true); 220 LLVM_FALLTHROUGH; 221 case CK_Yonah: 222 case CK_Prescott: 223 setFeatureEnabledImpl(Features, "sse3", true); 224 LLVM_FALLTHROUGH; 225 case CK_PentiumM: 226 case CK_Pentium4: 227 case CK_x86_64: 228 setFeatureEnabledImpl(Features, "sse2", true); 229 LLVM_FALLTHROUGH; 230 case CK_Pentium3: 231 case CK_C3_2: 232 setFeatureEnabledImpl(Features, "sse", true); 233 setFeatureEnabledImpl(Features, "fxsr", true); 234 break; 235 236 case CK_Tremont: 237 setFeatureEnabledImpl(Features, "cldemote", true); 238 setFeatureEnabledImpl(Features, "movdiri", true); 239 setFeatureEnabledImpl(Features, "movdir64b", true); 240 setFeatureEnabledImpl(Features, "gfni", true); 241 setFeatureEnabledImpl(Features, "waitpkg", true); 242 LLVM_FALLTHROUGH; 243 case CK_GoldmontPlus: 244 setFeatureEnabledImpl(Features, "ptwrite", true); 245 setFeatureEnabledImpl(Features, "rdpid", true); 246 setFeatureEnabledImpl(Features, "sgx", true); 247 LLVM_FALLTHROUGH; 248 case CK_Goldmont: 249 setFeatureEnabledImpl(Features, "sha", true); 250 setFeatureEnabledImpl(Features, "rdseed", true); 251 setFeatureEnabledImpl(Features, "xsave", true); 252 setFeatureEnabledImpl(Features, "xsaveopt", true); 253 setFeatureEnabledImpl(Features, "xsavec", true); 254 setFeatureEnabledImpl(Features, "xsaves", true); 255 setFeatureEnabledImpl(Features, "clflushopt", true); 256 setFeatureEnabledImpl(Features, "mpx", true); 257 setFeatureEnabledImpl(Features, "fsgsbase", true); 258 setFeatureEnabledImpl(Features, "aes", true); 259 LLVM_FALLTHROUGH; 260 case CK_Silvermont: 261 setFeatureEnabledImpl(Features, "rdrnd", true); 262 setFeatureEnabledImpl(Features, "pclmul", true); 263 setFeatureEnabledImpl(Features, "sse4.2", true); 264 setFeatureEnabledImpl(Features, "prfchw", true); 265 LLVM_FALLTHROUGH; 266 case CK_Bonnell: 267 setFeatureEnabledImpl(Features, "movbe", true); 268 setFeatureEnabledImpl(Features, "ssse3", true); 269 setFeatureEnabledImpl(Features, "fxsr", true); 270 setFeatureEnabledImpl(Features, "cx16", true); 271 setFeatureEnabledImpl(Features, "sahf", true); 272 break; 273 274 case CK_KNM: 275 // TODO: Add avx5124fmaps/avx5124vnniw. 276 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 277 LLVM_FALLTHROUGH; 278 case CK_KNL: 279 setFeatureEnabledImpl(Features, "avx512f", true); 280 setFeatureEnabledImpl(Features, "avx512cd", true); 281 setFeatureEnabledImpl(Features, "avx512er", true); 282 setFeatureEnabledImpl(Features, "avx512pf", true); 283 setFeatureEnabledImpl(Features, "prfchw", true); 284 setFeatureEnabledImpl(Features, "prefetchwt1", true); 285 setFeatureEnabledImpl(Features, "fxsr", true); 286 setFeatureEnabledImpl(Features, "rdseed", true); 287 setFeatureEnabledImpl(Features, "adx", true); 288 setFeatureEnabledImpl(Features, "lzcnt", true); 289 setFeatureEnabledImpl(Features, "bmi", true); 290 setFeatureEnabledImpl(Features, "bmi2", true); 291 setFeatureEnabledImpl(Features, "fma", true); 292 setFeatureEnabledImpl(Features, "rdrnd", true); 293 setFeatureEnabledImpl(Features, "f16c", true); 294 setFeatureEnabledImpl(Features, "fsgsbase", true); 295 setFeatureEnabledImpl(Features, "aes", true); 296 setFeatureEnabledImpl(Features, "pclmul", true); 297 setFeatureEnabledImpl(Features, "cx16", true); 298 setFeatureEnabledImpl(Features, "xsaveopt", true); 299 setFeatureEnabledImpl(Features, "xsave", true); 300 setFeatureEnabledImpl(Features, "movbe", true); 301 setFeatureEnabledImpl(Features, "sahf", true); 302 break; 303 304 case CK_K6_2: 305 case CK_K6_3: 306 case CK_WinChip2: 307 case CK_C3: 308 setFeatureEnabledImpl(Features, "3dnow", true); 309 break; 310 311 case CK_AMDFAM10: 312 setFeatureEnabledImpl(Features, "sse4a", true); 313 setFeatureEnabledImpl(Features, "lzcnt", true); 314 setFeatureEnabledImpl(Features, "popcnt", true); 315 setFeatureEnabledImpl(Features, "sahf", true); 316 LLVM_FALLTHROUGH; 317 case CK_K8SSE3: 318 setFeatureEnabledImpl(Features, "sse3", true); 319 LLVM_FALLTHROUGH; 320 case CK_K8: 321 setFeatureEnabledImpl(Features, "sse2", true); 322 LLVM_FALLTHROUGH; 323 case CK_AthlonXP: 324 setFeatureEnabledImpl(Features, "sse", true); 325 setFeatureEnabledImpl(Features, "fxsr", true); 326 LLVM_FALLTHROUGH; 327 case CK_Athlon: 328 case CK_Geode: 329 setFeatureEnabledImpl(Features, "3dnowa", true); 330 break; 331 332 case CK_BTVER2: 333 setFeatureEnabledImpl(Features, "avx", true); 334 setFeatureEnabledImpl(Features, "aes", true); 335 setFeatureEnabledImpl(Features, "pclmul", true); 336 setFeatureEnabledImpl(Features, "bmi", true); 337 setFeatureEnabledImpl(Features, "f16c", true); 338 setFeatureEnabledImpl(Features, "xsaveopt", true); 339 setFeatureEnabledImpl(Features, "movbe", true); 340 LLVM_FALLTHROUGH; 341 case CK_BTVER1: 342 setFeatureEnabledImpl(Features, "ssse3", true); 343 setFeatureEnabledImpl(Features, "sse4a", true); 344 setFeatureEnabledImpl(Features, "lzcnt", true); 345 setFeatureEnabledImpl(Features, "popcnt", true); 346 setFeatureEnabledImpl(Features, "prfchw", true); 347 setFeatureEnabledImpl(Features, "cx16", true); 348 setFeatureEnabledImpl(Features, "fxsr", true); 349 setFeatureEnabledImpl(Features, "sahf", true); 350 break; 351 352 case CK_ZNVER2: 353 setFeatureEnabledImpl(Features, "clwb", true); 354 setFeatureEnabledImpl(Features, "rdpid", true); 355 setFeatureEnabledImpl(Features, "wbnoinvd", true); 356 LLVM_FALLTHROUGH; 357 case CK_ZNVER1: 358 setFeatureEnabledImpl(Features, "adx", true); 359 setFeatureEnabledImpl(Features, "aes", true); 360 setFeatureEnabledImpl(Features, "avx2", true); 361 setFeatureEnabledImpl(Features, "bmi", true); 362 setFeatureEnabledImpl(Features, "bmi2", true); 363 setFeatureEnabledImpl(Features, "clflushopt", true); 364 setFeatureEnabledImpl(Features, "clzero", true); 365 setFeatureEnabledImpl(Features, "cx16", true); 366 setFeatureEnabledImpl(Features, "f16c", true); 367 setFeatureEnabledImpl(Features, "fma", true); 368 setFeatureEnabledImpl(Features, "fsgsbase", true); 369 setFeatureEnabledImpl(Features, "fxsr", true); 370 setFeatureEnabledImpl(Features, "lzcnt", true); 371 setFeatureEnabledImpl(Features, "mwaitx", true); 372 setFeatureEnabledImpl(Features, "movbe", true); 373 setFeatureEnabledImpl(Features, "pclmul", true); 374 setFeatureEnabledImpl(Features, "popcnt", true); 375 setFeatureEnabledImpl(Features, "prfchw", true); 376 setFeatureEnabledImpl(Features, "rdrnd", true); 377 setFeatureEnabledImpl(Features, "rdseed", true); 378 setFeatureEnabledImpl(Features, "sahf", true); 379 setFeatureEnabledImpl(Features, "sha", true); 380 setFeatureEnabledImpl(Features, "sse4a", true); 381 setFeatureEnabledImpl(Features, "xsave", true); 382 setFeatureEnabledImpl(Features, "xsavec", true); 383 setFeatureEnabledImpl(Features, "xsaveopt", true); 384 setFeatureEnabledImpl(Features, "xsaves", true); 385 break; 386 387 case CK_BDVER4: 388 setFeatureEnabledImpl(Features, "avx2", true); 389 setFeatureEnabledImpl(Features, "bmi2", true); 390 setFeatureEnabledImpl(Features, "mwaitx", true); 391 LLVM_FALLTHROUGH; 392 case CK_BDVER3: 393 setFeatureEnabledImpl(Features, "fsgsbase", true); 394 setFeatureEnabledImpl(Features, "xsaveopt", true); 395 LLVM_FALLTHROUGH; 396 case CK_BDVER2: 397 setFeatureEnabledImpl(Features, "bmi", true); 398 setFeatureEnabledImpl(Features, "fma", true); 399 setFeatureEnabledImpl(Features, "f16c", true); 400 setFeatureEnabledImpl(Features, "tbm", true); 401 LLVM_FALLTHROUGH; 402 case CK_BDVER1: 403 // xop implies avx, sse4a and fma4. 404 setFeatureEnabledImpl(Features, "xop", true); 405 setFeatureEnabledImpl(Features, "lwp", true); 406 setFeatureEnabledImpl(Features, "lzcnt", true); 407 setFeatureEnabledImpl(Features, "aes", true); 408 setFeatureEnabledImpl(Features, "pclmul", true); 409 setFeatureEnabledImpl(Features, "prfchw", true); 410 setFeatureEnabledImpl(Features, "cx16", true); 411 setFeatureEnabledImpl(Features, "fxsr", true); 412 setFeatureEnabledImpl(Features, "xsave", true); 413 setFeatureEnabledImpl(Features, "sahf", true); 414 break; 415 } 416 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 417 return false; 418 419 // Can't do this earlier because we need to be able to explicitly enable 420 // or disable these features and the things that they depend upon. 421 422 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 423 auto I = Features.find("sse4.2"); 424 if (I != Features.end() && I->getValue() && 425 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 426 FeaturesVec.end()) 427 Features["popcnt"] = true; 428 429 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 430 I = Features.find("3dnow"); 431 if (I != Features.end() && I->getValue() && 432 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 433 FeaturesVec.end()) 434 Features["prfchw"] = true; 435 436 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 437 // then enable MMX. 438 I = Features.find("sse"); 439 if (I != Features.end() && I->getValue() && 440 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 441 FeaturesVec.end()) 442 Features["mmx"] = true; 443 444 return true; 445 } 446 447 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 448 X86SSEEnum Level, bool Enabled) { 449 if (Enabled) { 450 switch (Level) { 451 case AVX512F: 452 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 453 LLVM_FALLTHROUGH; 454 case AVX2: 455 Features["avx2"] = true; 456 LLVM_FALLTHROUGH; 457 case AVX: 458 Features["avx"] = true; 459 Features["xsave"] = true; 460 LLVM_FALLTHROUGH; 461 case SSE42: 462 Features["sse4.2"] = true; 463 LLVM_FALLTHROUGH; 464 case SSE41: 465 Features["sse4.1"] = true; 466 LLVM_FALLTHROUGH; 467 case SSSE3: 468 Features["ssse3"] = true; 469 LLVM_FALLTHROUGH; 470 case SSE3: 471 Features["sse3"] = true; 472 LLVM_FALLTHROUGH; 473 case SSE2: 474 Features["sse2"] = true; 475 LLVM_FALLTHROUGH; 476 case SSE1: 477 Features["sse"] = true; 478 LLVM_FALLTHROUGH; 479 case NoSSE: 480 break; 481 } 482 return; 483 } 484 485 switch (Level) { 486 case NoSSE: 487 case SSE1: 488 Features["sse"] = false; 489 LLVM_FALLTHROUGH; 490 case SSE2: 491 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 492 Features["gfni"] = false; 493 LLVM_FALLTHROUGH; 494 case SSE3: 495 Features["sse3"] = false; 496 setXOPLevel(Features, NoXOP, false); 497 LLVM_FALLTHROUGH; 498 case SSSE3: 499 Features["ssse3"] = false; 500 LLVM_FALLTHROUGH; 501 case SSE41: 502 Features["sse4.1"] = false; 503 LLVM_FALLTHROUGH; 504 case SSE42: 505 Features["sse4.2"] = false; 506 LLVM_FALLTHROUGH; 507 case AVX: 508 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 509 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 510 setXOPLevel(Features, FMA4, false); 511 LLVM_FALLTHROUGH; 512 case AVX2: 513 Features["avx2"] = false; 514 LLVM_FALLTHROUGH; 515 case AVX512F: 516 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 517 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 518 Features["avx512vl"] = Features["avx512vbmi"] = 519 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 520 Features["avx512bitalg"] = Features["avx512vnni"] = 521 Features["avx512vbmi2"] = false; 522 break; 523 } 524 } 525 526 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 527 MMX3DNowEnum Level, bool Enabled) { 528 if (Enabled) { 529 switch (Level) { 530 case AMD3DNowAthlon: 531 Features["3dnowa"] = true; 532 LLVM_FALLTHROUGH; 533 case AMD3DNow: 534 Features["3dnow"] = true; 535 LLVM_FALLTHROUGH; 536 case MMX: 537 Features["mmx"] = true; 538 LLVM_FALLTHROUGH; 539 case NoMMX3DNow: 540 break; 541 } 542 return; 543 } 544 545 switch (Level) { 546 case NoMMX3DNow: 547 case MMX: 548 Features["mmx"] = false; 549 LLVM_FALLTHROUGH; 550 case AMD3DNow: 551 Features["3dnow"] = false; 552 LLVM_FALLTHROUGH; 553 case AMD3DNowAthlon: 554 Features["3dnowa"] = false; 555 break; 556 } 557 } 558 559 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 560 bool Enabled) { 561 if (Enabled) { 562 switch (Level) { 563 case XOP: 564 Features["xop"] = true; 565 LLVM_FALLTHROUGH; 566 case FMA4: 567 Features["fma4"] = true; 568 setSSELevel(Features, AVX, true); 569 LLVM_FALLTHROUGH; 570 case SSE4A: 571 Features["sse4a"] = true; 572 setSSELevel(Features, SSE3, true); 573 LLVM_FALLTHROUGH; 574 case NoXOP: 575 break; 576 } 577 return; 578 } 579 580 switch (Level) { 581 case NoXOP: 582 case SSE4A: 583 Features["sse4a"] = false; 584 LLVM_FALLTHROUGH; 585 case FMA4: 586 Features["fma4"] = false; 587 LLVM_FALLTHROUGH; 588 case XOP: 589 Features["xop"] = false; 590 break; 591 } 592 } 593 594 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 595 StringRef Name, bool Enabled) { 596 // This is a bit of a hack to deal with the sse4 target feature when used 597 // as part of the target attribute. We handle sse4 correctly everywhere 598 // else. See below for more information on how we handle the sse4 options. 599 if (Name != "sse4") 600 Features[Name] = Enabled; 601 602 if (Name == "mmx") { 603 setMMXLevel(Features, MMX, Enabled); 604 } else if (Name == "sse") { 605 setSSELevel(Features, SSE1, Enabled); 606 } else if (Name == "sse2") { 607 setSSELevel(Features, SSE2, Enabled); 608 } else if (Name == "sse3") { 609 setSSELevel(Features, SSE3, Enabled); 610 } else if (Name == "ssse3") { 611 setSSELevel(Features, SSSE3, Enabled); 612 } else if (Name == "sse4.2") { 613 setSSELevel(Features, SSE42, Enabled); 614 } else if (Name == "sse4.1") { 615 setSSELevel(Features, SSE41, Enabled); 616 } else if (Name == "3dnow") { 617 setMMXLevel(Features, AMD3DNow, Enabled); 618 } else if (Name == "3dnowa") { 619 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 620 } else if (Name == "aes") { 621 if (Enabled) 622 setSSELevel(Features, SSE2, Enabled); 623 else 624 Features["vaes"] = false; 625 } else if (Name == "vaes") { 626 if (Enabled) { 627 setSSELevel(Features, AVX, Enabled); 628 Features["aes"] = true; 629 } 630 } else if (Name == "pclmul") { 631 if (Enabled) 632 setSSELevel(Features, SSE2, Enabled); 633 else 634 Features["vpclmulqdq"] = false; 635 } else if (Name == "vpclmulqdq") { 636 if (Enabled) { 637 setSSELevel(Features, AVX, Enabled); 638 Features["pclmul"] = true; 639 } 640 } else if (Name == "gfni") { 641 if (Enabled) 642 setSSELevel(Features, SSE2, Enabled); 643 } else if (Name == "avx") { 644 setSSELevel(Features, AVX, Enabled); 645 } else if (Name == "avx2") { 646 setSSELevel(Features, AVX2, Enabled); 647 } else if (Name == "avx512f") { 648 setSSELevel(Features, AVX512F, Enabled); 649 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 650 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 651 Name == "avx512vbmi" || Name == "avx512ifma" || 652 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 653 Name == "avx512vnni" || Name == "avx512vbmi2") { 654 if (Enabled) 655 setSSELevel(Features, AVX512F, Enabled); 656 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 657 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 658 Features["avx512bw"] = true; 659 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 660 if (Name == "avx512bw" && !Enabled) 661 Features["avx512vbmi"] = Features["avx512vbmi2"] = 662 Features["avx512bitalg"] = false; 663 } else if (Name == "fma") { 664 if (Enabled) 665 setSSELevel(Features, AVX, Enabled); 666 else 667 setSSELevel(Features, AVX512F, Enabled); 668 } else if (Name == "fma4") { 669 setXOPLevel(Features, FMA4, Enabled); 670 } else if (Name == "xop") { 671 setXOPLevel(Features, XOP, Enabled); 672 } else if (Name == "sse4a") { 673 setXOPLevel(Features, SSE4A, Enabled); 674 } else if (Name == "f16c") { 675 if (Enabled) 676 setSSELevel(Features, AVX, Enabled); 677 else 678 setSSELevel(Features, AVX512F, Enabled); 679 } else if (Name == "sha") { 680 if (Enabled) 681 setSSELevel(Features, SSE2, Enabled); 682 } else if (Name == "sse4") { 683 // We can get here via the __target__ attribute since that's not controlled 684 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 685 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 686 // disabled. 687 if (Enabled) 688 setSSELevel(Features, SSE42, Enabled); 689 else 690 setSSELevel(Features, SSE41, Enabled); 691 } else if (Name == "xsave") { 692 if (!Enabled) 693 Features["xsaveopt"] = false; 694 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 695 if (Enabled) 696 Features["xsave"] = true; 697 } 698 } 699 700 /// handleTargetFeatures - Perform initialization based on the user 701 /// configured set of features. 702 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 703 DiagnosticsEngine &Diags) { 704 for (const auto &Feature : Features) { 705 if (Feature[0] != '+') 706 continue; 707 708 if (Feature == "+aes") { 709 HasAES = true; 710 } else if (Feature == "+vaes") { 711 HasVAES = true; 712 } else if (Feature == "+pclmul") { 713 HasPCLMUL = true; 714 } else if (Feature == "+vpclmulqdq") { 715 HasVPCLMULQDQ = true; 716 } else if (Feature == "+lzcnt") { 717 HasLZCNT = true; 718 } else if (Feature == "+rdrnd") { 719 HasRDRND = true; 720 } else if (Feature == "+fsgsbase") { 721 HasFSGSBASE = true; 722 } else if (Feature == "+bmi") { 723 HasBMI = true; 724 } else if (Feature == "+bmi2") { 725 HasBMI2 = true; 726 } else if (Feature == "+popcnt") { 727 HasPOPCNT = true; 728 } else if (Feature == "+rtm") { 729 HasRTM = true; 730 } else if (Feature == "+prfchw") { 731 HasPRFCHW = true; 732 } else if (Feature == "+rdseed") { 733 HasRDSEED = true; 734 } else if (Feature == "+adx") { 735 HasADX = true; 736 } else if (Feature == "+tbm") { 737 HasTBM = true; 738 } else if (Feature == "+lwp") { 739 HasLWP = true; 740 } else if (Feature == "+fma") { 741 HasFMA = true; 742 } else if (Feature == "+f16c") { 743 HasF16C = true; 744 } else if (Feature == "+gfni") { 745 HasGFNI = true; 746 } else if (Feature == "+avx512cd") { 747 HasAVX512CD = true; 748 } else if (Feature == "+avx512vpopcntdq") { 749 HasAVX512VPOPCNTDQ = true; 750 } else if (Feature == "+avx512vnni") { 751 HasAVX512VNNI = true; 752 } else if (Feature == "+avx512er") { 753 HasAVX512ER = true; 754 } else if (Feature == "+avx512pf") { 755 HasAVX512PF = true; 756 } else if (Feature == "+avx512dq") { 757 HasAVX512DQ = true; 758 } else if (Feature == "+avx512bitalg") { 759 HasAVX512BITALG = true; 760 } else if (Feature == "+avx512bw") { 761 HasAVX512BW = true; 762 } else if (Feature == "+avx512vl") { 763 HasAVX512VL = true; 764 } else if (Feature == "+avx512vbmi") { 765 HasAVX512VBMI = true; 766 } else if (Feature == "+avx512vbmi2") { 767 HasAVX512VBMI2 = true; 768 } else if (Feature == "+avx512ifma") { 769 HasAVX512IFMA = true; 770 } else if (Feature == "+sha") { 771 HasSHA = true; 772 } else if (Feature == "+mpx") { 773 HasMPX = true; 774 } else if (Feature == "+shstk") { 775 HasSHSTK = true; 776 } else if (Feature == "+movbe") { 777 HasMOVBE = true; 778 } else if (Feature == "+sgx") { 779 HasSGX = true; 780 } else if (Feature == "+cx16") { 781 HasCX16 = true; 782 } else if (Feature == "+fxsr") { 783 HasFXSR = true; 784 } else if (Feature == "+xsave") { 785 HasXSAVE = true; 786 } else if (Feature == "+xsaveopt") { 787 HasXSAVEOPT = true; 788 } else if (Feature == "+xsavec") { 789 HasXSAVEC = true; 790 } else if (Feature == "+xsaves") { 791 HasXSAVES = true; 792 } else if (Feature == "+mwaitx") { 793 HasMWAITX = true; 794 } else if (Feature == "+pku") { 795 HasPKU = true; 796 } else if (Feature == "+clflushopt") { 797 HasCLFLUSHOPT = true; 798 } else if (Feature == "+clwb") { 799 HasCLWB = true; 800 } else if (Feature == "+wbnoinvd") { 801 HasWBNOINVD = true; 802 } else if (Feature == "+prefetchwt1") { 803 HasPREFETCHWT1 = true; 804 } else if (Feature == "+clzero") { 805 HasCLZERO = true; 806 } else if (Feature == "+cldemote") { 807 HasCLDEMOTE = true; 808 } else if (Feature == "+rdpid") { 809 HasRDPID = true; 810 } else if (Feature == "+retpoline-external-thunk") { 811 HasRetpolineExternalThunk = true; 812 } else if (Feature == "+sahf") { 813 HasLAHFSAHF = true; 814 } else if (Feature == "+waitpkg") { 815 HasWAITPKG = true; 816 } else if (Feature == "+movdiri") { 817 HasMOVDIRI = true; 818 } else if (Feature == "+movdir64b") { 819 HasMOVDIR64B = true; 820 } else if (Feature == "+pconfig") { 821 HasPCONFIG = true; 822 } else if (Feature == "+ptwrite") { 823 HasPTWRITE = true; 824 } else if (Feature == "+invpcid") { 825 HasINVPCID = true; 826 } 827 828 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 829 .Case("+avx512f", AVX512F) 830 .Case("+avx2", AVX2) 831 .Case("+avx", AVX) 832 .Case("+sse4.2", SSE42) 833 .Case("+sse4.1", SSE41) 834 .Case("+ssse3", SSSE3) 835 .Case("+sse3", SSE3) 836 .Case("+sse2", SSE2) 837 .Case("+sse", SSE1) 838 .Default(NoSSE); 839 SSELevel = std::max(SSELevel, Level); 840 841 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 842 .Case("+3dnowa", AMD3DNowAthlon) 843 .Case("+3dnow", AMD3DNow) 844 .Case("+mmx", MMX) 845 .Default(NoMMX3DNow); 846 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 847 848 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 849 .Case("+xop", XOP) 850 .Case("+fma4", FMA4) 851 .Case("+sse4a", SSE4A) 852 .Default(NoXOP); 853 XOPLevel = std::max(XOPLevel, XLevel); 854 } 855 856 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 857 // matches the selected sse level. 858 if ((FPMath == FP_SSE && SSELevel < SSE1) || 859 (FPMath == FP_387 && SSELevel >= SSE1)) { 860 Diags.Report(diag::err_target_unsupported_fpmath) 861 << (FPMath == FP_SSE ? "sse" : "387"); 862 return false; 863 } 864 865 SimdDefaultAlign = 866 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 867 return true; 868 } 869 870 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 871 /// definitions for this particular subtarget. 872 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 873 MacroBuilder &Builder) const { 874 // Inline assembly supports X86 flag outputs. 875 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 876 877 std::string CodeModel = getTargetOpts().CodeModel; 878 if (CodeModel == "default") 879 CodeModel = "small"; 880 Builder.defineMacro("__code_model_" + CodeModel + "_"); 881 882 // Target identification. 883 if (getTriple().getArch() == llvm::Triple::x86_64) { 884 Builder.defineMacro("__amd64__"); 885 Builder.defineMacro("__amd64"); 886 Builder.defineMacro("__x86_64"); 887 Builder.defineMacro("__x86_64__"); 888 if (getTriple().getArchName() == "x86_64h") { 889 Builder.defineMacro("__x86_64h"); 890 Builder.defineMacro("__x86_64h__"); 891 } 892 } else { 893 DefineStd(Builder, "i386", Opts); 894 } 895 896 // Subtarget options. 897 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 898 // truly should be based on -mtune options. 899 switch (CPU) { 900 case CK_Generic: 901 break; 902 case CK_i386: 903 // The rest are coming from the i386 define above. 904 Builder.defineMacro("__tune_i386__"); 905 break; 906 case CK_i486: 907 case CK_WinChipC6: 908 case CK_WinChip2: 909 case CK_C3: 910 defineCPUMacros(Builder, "i486"); 911 break; 912 case CK_PentiumMMX: 913 Builder.defineMacro("__pentium_mmx__"); 914 Builder.defineMacro("__tune_pentium_mmx__"); 915 LLVM_FALLTHROUGH; 916 case CK_i586: 917 case CK_Pentium: 918 defineCPUMacros(Builder, "i586"); 919 defineCPUMacros(Builder, "pentium"); 920 break; 921 case CK_Pentium3: 922 case CK_PentiumM: 923 Builder.defineMacro("__tune_pentium3__"); 924 LLVM_FALLTHROUGH; 925 case CK_Pentium2: 926 case CK_C3_2: 927 Builder.defineMacro("__tune_pentium2__"); 928 LLVM_FALLTHROUGH; 929 case CK_PentiumPro: 930 case CK_i686: 931 defineCPUMacros(Builder, "i686"); 932 defineCPUMacros(Builder, "pentiumpro"); 933 break; 934 case CK_Pentium4: 935 defineCPUMacros(Builder, "pentium4"); 936 break; 937 case CK_Yonah: 938 case CK_Prescott: 939 case CK_Nocona: 940 defineCPUMacros(Builder, "nocona"); 941 break; 942 case CK_Core2: 943 case CK_Penryn: 944 defineCPUMacros(Builder, "core2"); 945 break; 946 case CK_Bonnell: 947 defineCPUMacros(Builder, "atom"); 948 break; 949 case CK_Silvermont: 950 defineCPUMacros(Builder, "slm"); 951 break; 952 case CK_Goldmont: 953 defineCPUMacros(Builder, "goldmont"); 954 break; 955 case CK_GoldmontPlus: 956 defineCPUMacros(Builder, "goldmont_plus"); 957 break; 958 case CK_Tremont: 959 defineCPUMacros(Builder, "tremont"); 960 break; 961 case CK_Nehalem: 962 case CK_Westmere: 963 case CK_SandyBridge: 964 case CK_IvyBridge: 965 case CK_Haswell: 966 case CK_Broadwell: 967 case CK_SkylakeClient: 968 case CK_SkylakeServer: 969 case CK_Cascadelake: 970 case CK_Cannonlake: 971 case CK_IcelakeClient: 972 case CK_IcelakeServer: 973 // FIXME: Historically, we defined this legacy name, it would be nice to 974 // remove it at some point. We've never exposed fine-grained names for 975 // recent primary x86 CPUs, and we should keep it that way. 976 defineCPUMacros(Builder, "corei7"); 977 break; 978 case CK_KNL: 979 defineCPUMacros(Builder, "knl"); 980 break; 981 case CK_KNM: 982 break; 983 case CK_Lakemont: 984 defineCPUMacros(Builder, "i586", /*Tuning*/false); 985 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 986 Builder.defineMacro("__tune_lakemont__"); 987 break; 988 case CK_K6_2: 989 Builder.defineMacro("__k6_2__"); 990 Builder.defineMacro("__tune_k6_2__"); 991 LLVM_FALLTHROUGH; 992 case CK_K6_3: 993 if (CPU != CK_K6_2) { // In case of fallthrough 994 // FIXME: GCC may be enabling these in cases where some other k6 995 // architecture is specified but -m3dnow is explicitly provided. The 996 // exact semantics need to be determined and emulated here. 997 Builder.defineMacro("__k6_3__"); 998 Builder.defineMacro("__tune_k6_3__"); 999 } 1000 LLVM_FALLTHROUGH; 1001 case CK_K6: 1002 defineCPUMacros(Builder, "k6"); 1003 break; 1004 case CK_Athlon: 1005 case CK_AthlonXP: 1006 defineCPUMacros(Builder, "athlon"); 1007 if (SSELevel != NoSSE) { 1008 Builder.defineMacro("__athlon_sse__"); 1009 Builder.defineMacro("__tune_athlon_sse__"); 1010 } 1011 break; 1012 case CK_K8: 1013 case CK_K8SSE3: 1014 case CK_x86_64: 1015 defineCPUMacros(Builder, "k8"); 1016 break; 1017 case CK_AMDFAM10: 1018 defineCPUMacros(Builder, "amdfam10"); 1019 break; 1020 case CK_BTVER1: 1021 defineCPUMacros(Builder, "btver1"); 1022 break; 1023 case CK_BTVER2: 1024 defineCPUMacros(Builder, "btver2"); 1025 break; 1026 case CK_BDVER1: 1027 defineCPUMacros(Builder, "bdver1"); 1028 break; 1029 case CK_BDVER2: 1030 defineCPUMacros(Builder, "bdver2"); 1031 break; 1032 case CK_BDVER3: 1033 defineCPUMacros(Builder, "bdver3"); 1034 break; 1035 case CK_BDVER4: 1036 defineCPUMacros(Builder, "bdver4"); 1037 break; 1038 case CK_ZNVER1: 1039 defineCPUMacros(Builder, "znver1"); 1040 break; 1041 case CK_ZNVER2: 1042 defineCPUMacros(Builder, "znver2"); 1043 break; 1044 case CK_Geode: 1045 defineCPUMacros(Builder, "geode"); 1046 break; 1047 } 1048 1049 // Target properties. 1050 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1051 1052 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1053 // functions in glibc header files that use FP Stack inline asm which the 1054 // backend can't deal with (PR879). 1055 Builder.defineMacro("__NO_MATH_INLINES"); 1056 1057 if (HasAES) 1058 Builder.defineMacro("__AES__"); 1059 1060 if (HasVAES) 1061 Builder.defineMacro("__VAES__"); 1062 1063 if (HasPCLMUL) 1064 Builder.defineMacro("__PCLMUL__"); 1065 1066 if (HasVPCLMULQDQ) 1067 Builder.defineMacro("__VPCLMULQDQ__"); 1068 1069 if (HasLZCNT) 1070 Builder.defineMacro("__LZCNT__"); 1071 1072 if (HasRDRND) 1073 Builder.defineMacro("__RDRND__"); 1074 1075 if (HasFSGSBASE) 1076 Builder.defineMacro("__FSGSBASE__"); 1077 1078 if (HasBMI) 1079 Builder.defineMacro("__BMI__"); 1080 1081 if (HasBMI2) 1082 Builder.defineMacro("__BMI2__"); 1083 1084 if (HasPOPCNT) 1085 Builder.defineMacro("__POPCNT__"); 1086 1087 if (HasRTM) 1088 Builder.defineMacro("__RTM__"); 1089 1090 if (HasPRFCHW) 1091 Builder.defineMacro("__PRFCHW__"); 1092 1093 if (HasRDSEED) 1094 Builder.defineMacro("__RDSEED__"); 1095 1096 if (HasADX) 1097 Builder.defineMacro("__ADX__"); 1098 1099 if (HasTBM) 1100 Builder.defineMacro("__TBM__"); 1101 1102 if (HasLWP) 1103 Builder.defineMacro("__LWP__"); 1104 1105 if (HasMWAITX) 1106 Builder.defineMacro("__MWAITX__"); 1107 1108 if (HasMOVBE) 1109 Builder.defineMacro("__MOVBE__"); 1110 1111 switch (XOPLevel) { 1112 case XOP: 1113 Builder.defineMacro("__XOP__"); 1114 LLVM_FALLTHROUGH; 1115 case FMA4: 1116 Builder.defineMacro("__FMA4__"); 1117 LLVM_FALLTHROUGH; 1118 case SSE4A: 1119 Builder.defineMacro("__SSE4A__"); 1120 LLVM_FALLTHROUGH; 1121 case NoXOP: 1122 break; 1123 } 1124 1125 if (HasFMA) 1126 Builder.defineMacro("__FMA__"); 1127 1128 if (HasF16C) 1129 Builder.defineMacro("__F16C__"); 1130 1131 if (HasGFNI) 1132 Builder.defineMacro("__GFNI__"); 1133 1134 if (HasAVX512CD) 1135 Builder.defineMacro("__AVX512CD__"); 1136 if (HasAVX512VPOPCNTDQ) 1137 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1138 if (HasAVX512VNNI) 1139 Builder.defineMacro("__AVX512VNNI__"); 1140 if (HasAVX512ER) 1141 Builder.defineMacro("__AVX512ER__"); 1142 if (HasAVX512PF) 1143 Builder.defineMacro("__AVX512PF__"); 1144 if (HasAVX512DQ) 1145 Builder.defineMacro("__AVX512DQ__"); 1146 if (HasAVX512BITALG) 1147 Builder.defineMacro("__AVX512BITALG__"); 1148 if (HasAVX512BW) 1149 Builder.defineMacro("__AVX512BW__"); 1150 if (HasAVX512VL) 1151 Builder.defineMacro("__AVX512VL__"); 1152 if (HasAVX512VBMI) 1153 Builder.defineMacro("__AVX512VBMI__"); 1154 if (HasAVX512VBMI2) 1155 Builder.defineMacro("__AVX512VBMI2__"); 1156 if (HasAVX512IFMA) 1157 Builder.defineMacro("__AVX512IFMA__"); 1158 1159 if (HasSHA) 1160 Builder.defineMacro("__SHA__"); 1161 1162 if (HasFXSR) 1163 Builder.defineMacro("__FXSR__"); 1164 if (HasXSAVE) 1165 Builder.defineMacro("__XSAVE__"); 1166 if (HasXSAVEOPT) 1167 Builder.defineMacro("__XSAVEOPT__"); 1168 if (HasXSAVEC) 1169 Builder.defineMacro("__XSAVEC__"); 1170 if (HasXSAVES) 1171 Builder.defineMacro("__XSAVES__"); 1172 if (HasPKU) 1173 Builder.defineMacro("__PKU__"); 1174 if (HasCLFLUSHOPT) 1175 Builder.defineMacro("__CLFLUSHOPT__"); 1176 if (HasCLWB) 1177 Builder.defineMacro("__CLWB__"); 1178 if (HasWBNOINVD) 1179 Builder.defineMacro("__WBNOINVD__"); 1180 if (HasMPX) 1181 Builder.defineMacro("__MPX__"); 1182 if (HasSHSTK) 1183 Builder.defineMacro("__SHSTK__"); 1184 if (HasSGX) 1185 Builder.defineMacro("__SGX__"); 1186 if (HasPREFETCHWT1) 1187 Builder.defineMacro("__PREFETCHWT1__"); 1188 if (HasCLZERO) 1189 Builder.defineMacro("__CLZERO__"); 1190 if (HasRDPID) 1191 Builder.defineMacro("__RDPID__"); 1192 if (HasCLDEMOTE) 1193 Builder.defineMacro("__CLDEMOTE__"); 1194 if (HasWAITPKG) 1195 Builder.defineMacro("__WAITPKG__"); 1196 if (HasMOVDIRI) 1197 Builder.defineMacro("__MOVDIRI__"); 1198 if (HasMOVDIR64B) 1199 Builder.defineMacro("__MOVDIR64B__"); 1200 if (HasPCONFIG) 1201 Builder.defineMacro("__PCONFIG__"); 1202 if (HasPTWRITE) 1203 Builder.defineMacro("__PTWRITE__"); 1204 if (HasINVPCID) 1205 Builder.defineMacro("__INVPCID__"); 1206 1207 // Each case falls through to the previous one here. 1208 switch (SSELevel) { 1209 case AVX512F: 1210 Builder.defineMacro("__AVX512F__"); 1211 LLVM_FALLTHROUGH; 1212 case AVX2: 1213 Builder.defineMacro("__AVX2__"); 1214 LLVM_FALLTHROUGH; 1215 case AVX: 1216 Builder.defineMacro("__AVX__"); 1217 LLVM_FALLTHROUGH; 1218 case SSE42: 1219 Builder.defineMacro("__SSE4_2__"); 1220 LLVM_FALLTHROUGH; 1221 case SSE41: 1222 Builder.defineMacro("__SSE4_1__"); 1223 LLVM_FALLTHROUGH; 1224 case SSSE3: 1225 Builder.defineMacro("__SSSE3__"); 1226 LLVM_FALLTHROUGH; 1227 case SSE3: 1228 Builder.defineMacro("__SSE3__"); 1229 LLVM_FALLTHROUGH; 1230 case SSE2: 1231 Builder.defineMacro("__SSE2__"); 1232 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1233 LLVM_FALLTHROUGH; 1234 case SSE1: 1235 Builder.defineMacro("__SSE__"); 1236 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1237 LLVM_FALLTHROUGH; 1238 case NoSSE: 1239 break; 1240 } 1241 1242 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1243 switch (SSELevel) { 1244 case AVX512F: 1245 case AVX2: 1246 case AVX: 1247 case SSE42: 1248 case SSE41: 1249 case SSSE3: 1250 case SSE3: 1251 case SSE2: 1252 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1253 break; 1254 case SSE1: 1255 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1256 break; 1257 default: 1258 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1259 break; 1260 } 1261 } 1262 1263 // Each case falls through to the previous one here. 1264 switch (MMX3DNowLevel) { 1265 case AMD3DNowAthlon: 1266 Builder.defineMacro("__3dNOW_A__"); 1267 LLVM_FALLTHROUGH; 1268 case AMD3DNow: 1269 Builder.defineMacro("__3dNOW__"); 1270 LLVM_FALLTHROUGH; 1271 case MMX: 1272 Builder.defineMacro("__MMX__"); 1273 LLVM_FALLTHROUGH; 1274 case NoMMX3DNow: 1275 break; 1276 } 1277 1278 if (CPU >= CK_i486) { 1279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1281 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1282 } 1283 if (CPU >= CK_i586) 1284 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1285 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1286 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1287 1288 if (HasFloat128) 1289 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1290 } 1291 1292 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1293 return llvm::StringSwitch<bool>(Name) 1294 .Case("3dnow", true) 1295 .Case("3dnowa", true) 1296 .Case("adx", true) 1297 .Case("aes", true) 1298 .Case("avx", true) 1299 .Case("avx2", true) 1300 .Case("avx512f", true) 1301 .Case("avx512cd", true) 1302 .Case("avx512vpopcntdq", true) 1303 .Case("avx512vnni", true) 1304 .Case("avx512er", true) 1305 .Case("avx512pf", true) 1306 .Case("avx512dq", true) 1307 .Case("avx512bitalg", true) 1308 .Case("avx512bw", true) 1309 .Case("avx512vl", true) 1310 .Case("avx512vbmi", true) 1311 .Case("avx512vbmi2", true) 1312 .Case("avx512ifma", true) 1313 .Case("bmi", true) 1314 .Case("bmi2", true) 1315 .Case("cldemote", true) 1316 .Case("clflushopt", true) 1317 .Case("clwb", true) 1318 .Case("clzero", true) 1319 .Case("cx16", true) 1320 .Case("f16c", true) 1321 .Case("fma", true) 1322 .Case("fma4", true) 1323 .Case("fsgsbase", true) 1324 .Case("fxsr", true) 1325 .Case("gfni", true) 1326 .Case("invpcid", true) 1327 .Case("lwp", true) 1328 .Case("lzcnt", true) 1329 .Case("mmx", true) 1330 .Case("movbe", true) 1331 .Case("movdiri", true) 1332 .Case("movdir64b", true) 1333 .Case("mpx", true) 1334 .Case("mwaitx", true) 1335 .Case("pclmul", true) 1336 .Case("pconfig", true) 1337 .Case("pku", true) 1338 .Case("popcnt", true) 1339 .Case("prefetchwt1", true) 1340 .Case("prfchw", true) 1341 .Case("ptwrite", true) 1342 .Case("rdpid", true) 1343 .Case("rdrnd", true) 1344 .Case("rdseed", true) 1345 .Case("rtm", true) 1346 .Case("sahf", true) 1347 .Case("sgx", true) 1348 .Case("sha", true) 1349 .Case("shstk", true) 1350 .Case("sse", true) 1351 .Case("sse2", true) 1352 .Case("sse3", true) 1353 .Case("ssse3", true) 1354 .Case("sse4", true) 1355 .Case("sse4.1", true) 1356 .Case("sse4.2", true) 1357 .Case("sse4a", true) 1358 .Case("tbm", true) 1359 .Case("vaes", true) 1360 .Case("vpclmulqdq", true) 1361 .Case("wbnoinvd", true) 1362 .Case("waitpkg", true) 1363 .Case("x87", true) 1364 .Case("xop", true) 1365 .Case("xsave", true) 1366 .Case("xsavec", true) 1367 .Case("xsaves", true) 1368 .Case("xsaveopt", true) 1369 .Default(false); 1370 } 1371 1372 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1373 return llvm::StringSwitch<bool>(Feature) 1374 .Case("adx", HasADX) 1375 .Case("aes", HasAES) 1376 .Case("avx", SSELevel >= AVX) 1377 .Case("avx2", SSELevel >= AVX2) 1378 .Case("avx512f", SSELevel >= AVX512F) 1379 .Case("avx512cd", HasAVX512CD) 1380 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1381 .Case("avx512vnni", HasAVX512VNNI) 1382 .Case("avx512er", HasAVX512ER) 1383 .Case("avx512pf", HasAVX512PF) 1384 .Case("avx512dq", HasAVX512DQ) 1385 .Case("avx512bitalg", HasAVX512BITALG) 1386 .Case("avx512bw", HasAVX512BW) 1387 .Case("avx512vl", HasAVX512VL) 1388 .Case("avx512vbmi", HasAVX512VBMI) 1389 .Case("avx512vbmi2", HasAVX512VBMI2) 1390 .Case("avx512ifma", HasAVX512IFMA) 1391 .Case("bmi", HasBMI) 1392 .Case("bmi2", HasBMI2) 1393 .Case("cldemote", HasCLDEMOTE) 1394 .Case("clflushopt", HasCLFLUSHOPT) 1395 .Case("clwb", HasCLWB) 1396 .Case("clzero", HasCLZERO) 1397 .Case("cx16", HasCX16) 1398 .Case("f16c", HasF16C) 1399 .Case("fma", HasFMA) 1400 .Case("fma4", XOPLevel >= FMA4) 1401 .Case("fsgsbase", HasFSGSBASE) 1402 .Case("fxsr", HasFXSR) 1403 .Case("gfni", HasGFNI) 1404 .Case("invpcid", HasINVPCID) 1405 .Case("lwp", HasLWP) 1406 .Case("lzcnt", HasLZCNT) 1407 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1408 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1409 .Case("mmx", MMX3DNowLevel >= MMX) 1410 .Case("movbe", HasMOVBE) 1411 .Case("movdiri", HasMOVDIRI) 1412 .Case("movdir64b", HasMOVDIR64B) 1413 .Case("mpx", HasMPX) 1414 .Case("mwaitx", HasMWAITX) 1415 .Case("pclmul", HasPCLMUL) 1416 .Case("pconfig", HasPCONFIG) 1417 .Case("pku", HasPKU) 1418 .Case("popcnt", HasPOPCNT) 1419 .Case("prefetchwt1", HasPREFETCHWT1) 1420 .Case("prfchw", HasPRFCHW) 1421 .Case("ptwrite", HasPTWRITE) 1422 .Case("rdpid", HasRDPID) 1423 .Case("rdrnd", HasRDRND) 1424 .Case("rdseed", HasRDSEED) 1425 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1426 .Case("rtm", HasRTM) 1427 .Case("sahf", HasLAHFSAHF) 1428 .Case("sgx", HasSGX) 1429 .Case("sha", HasSHA) 1430 .Case("shstk", HasSHSTK) 1431 .Case("sse", SSELevel >= SSE1) 1432 .Case("sse2", SSELevel >= SSE2) 1433 .Case("sse3", SSELevel >= SSE3) 1434 .Case("ssse3", SSELevel >= SSSE3) 1435 .Case("sse4.1", SSELevel >= SSE41) 1436 .Case("sse4.2", SSELevel >= SSE42) 1437 .Case("sse4a", XOPLevel >= SSE4A) 1438 .Case("tbm", HasTBM) 1439 .Case("vaes", HasVAES) 1440 .Case("vpclmulqdq", HasVPCLMULQDQ) 1441 .Case("wbnoinvd", HasWBNOINVD) 1442 .Case("waitpkg", HasWAITPKG) 1443 .Case("x86", true) 1444 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1445 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1446 .Case("xop", XOPLevel >= XOP) 1447 .Case("xsave", HasXSAVE) 1448 .Case("xsavec", HasXSAVEC) 1449 .Case("xsaves", HasXSAVES) 1450 .Case("xsaveopt", HasXSAVEOPT) 1451 .Default(false); 1452 } 1453 1454 // We can't use a generic validation scheme for the features accepted here 1455 // versus subtarget features accepted in the target attribute because the 1456 // bitfield structure that's initialized in the runtime only supports the 1457 // below currently rather than the full range of subtarget features. (See 1458 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1459 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1460 return llvm::StringSwitch<bool>(FeatureStr) 1461 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1462 #include "llvm/Support/X86TargetParser.def" 1463 .Default(false); 1464 } 1465 1466 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1467 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1468 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1469 #include "llvm/Support/X86TargetParser.def" 1470 ; 1471 // Note, this function should only be used after ensuring the value is 1472 // correct, so it asserts if the value is out of range. 1473 } 1474 1475 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1476 enum class FeatPriority { 1477 #define FEATURE(FEAT) FEAT, 1478 #include "clang/Basic/X86Target.def" 1479 }; 1480 switch (Feat) { 1481 #define FEATURE(FEAT) \ 1482 case llvm::X86::FEAT: \ 1483 return static_cast<unsigned>(FeatPriority::FEAT); 1484 #include "clang/Basic/X86Target.def" 1485 default: 1486 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1487 } 1488 } 1489 1490 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1491 // Valid CPUs have a 'key feature' that compares just better than its key 1492 // feature. 1493 CPUKind Kind = getCPUKind(Name); 1494 if (Kind != CK_Generic) { 1495 switch (Kind) { 1496 default: 1497 llvm_unreachable( 1498 "CPU Type without a key feature used in 'target' attribute"); 1499 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1500 case CK_##ENUM: \ 1501 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1502 #include "clang/Basic/X86Target.def" 1503 } 1504 } 1505 1506 // Now we know we have a feature, so get its priority and shift it a few so 1507 // that we have sufficient room for the CPUs (above). 1508 return getFeaturePriority(getFeature(Name)) << 1; 1509 } 1510 1511 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1512 return llvm::StringSwitch<bool>(Name) 1513 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1514 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1515 #include "clang/Basic/X86Target.def" 1516 .Default(false); 1517 } 1518 1519 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1520 return llvm::StringSwitch<StringRef>(Name) 1521 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1522 #include "clang/Basic/X86Target.def" 1523 .Default(Name); 1524 } 1525 1526 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1527 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1528 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1529 #include "clang/Basic/X86Target.def" 1530 .Default(0); 1531 } 1532 1533 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1534 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1535 StringRef WholeList = 1536 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1537 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1538 #include "clang/Basic/X86Target.def" 1539 .Default(""); 1540 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1541 } 1542 1543 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1544 switch (Kind) { 1545 case CK_Generic: 1546 return ""; 1547 #define PROC(ENUM, STRING, IS64BIT) \ 1548 case CK_##ENUM: \ 1549 return STRING; 1550 #include "clang/Basic/X86Target.def" 1551 } 1552 llvm_unreachable("Invalid CPUKind"); 1553 } 1554 1555 // We can't use a generic validation scheme for the cpus accepted here 1556 // versus subtarget cpus accepted in the target attribute because the 1557 // variables intitialized by the runtime only support the below currently 1558 // rather than the full range of cpus. 1559 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1560 return llvm::StringSwitch<bool>(FeatureStr) 1561 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1562 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1563 .Cases(STR, ALIAS, true) 1564 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1565 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1566 #include "llvm/Support/X86TargetParser.def" 1567 .Default(false); 1568 } 1569 1570 static unsigned matchAsmCCConstraint(const char *&Name) { 1571 auto RV = llvm::StringSwitch<unsigned>(Name) 1572 .Case("@cca", 4) 1573 .Case("@ccae", 5) 1574 .Case("@ccb", 4) 1575 .Case("@ccbe", 5) 1576 .Case("@ccc", 4) 1577 .Case("@cce", 4) 1578 .Case("@ccz", 4) 1579 .Case("@ccg", 4) 1580 .Case("@ccge", 5) 1581 .Case("@ccl", 4) 1582 .Case("@ccle", 5) 1583 .Case("@ccna", 5) 1584 .Case("@ccnae", 6) 1585 .Case("@ccnb", 5) 1586 .Case("@ccnbe", 6) 1587 .Case("@ccnc", 5) 1588 .Case("@ccne", 5) 1589 .Case("@ccnz", 5) 1590 .Case("@ccng", 5) 1591 .Case("@ccnge", 6) 1592 .Case("@ccnl", 5) 1593 .Case("@ccnle", 6) 1594 .Case("@ccno", 5) 1595 .Case("@ccnp", 5) 1596 .Case("@ccns", 5) 1597 .Case("@cco", 4) 1598 .Case("@ccp", 4) 1599 .Case("@ccs", 4) 1600 .Default(0); 1601 return RV; 1602 } 1603 1604 bool X86TargetInfo::validateAsmConstraint( 1605 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1606 switch (*Name) { 1607 default: 1608 return false; 1609 // Constant constraints. 1610 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1611 // instructions. 1612 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1613 // x86_64 instructions. 1614 case 's': 1615 Info.setRequiresImmediate(); 1616 return true; 1617 case 'I': 1618 Info.setRequiresImmediate(0, 31); 1619 return true; 1620 case 'J': 1621 Info.setRequiresImmediate(0, 63); 1622 return true; 1623 case 'K': 1624 Info.setRequiresImmediate(-128, 127); 1625 return true; 1626 case 'L': 1627 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1628 return true; 1629 case 'M': 1630 Info.setRequiresImmediate(0, 3); 1631 return true; 1632 case 'N': 1633 Info.setRequiresImmediate(0, 255); 1634 return true; 1635 case 'O': 1636 Info.setRequiresImmediate(0, 127); 1637 return true; 1638 // Register constraints. 1639 case 'Y': // 'Y' is the first character for several 2-character constraints. 1640 // Shift the pointer to the second character of the constraint. 1641 Name++; 1642 switch (*Name) { 1643 default: 1644 return false; 1645 case 'z': 1646 case '0': // First SSE register. 1647 case '2': 1648 case 't': // Any SSE register, when SSE2 is enabled. 1649 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1650 case 'm': // Any MMX register, when inter-unit moves enabled. 1651 case 'k': // AVX512 arch mask registers: k1-k7. 1652 Info.setAllowsRegister(); 1653 return true; 1654 } 1655 case 'f': // Any x87 floating point stack register. 1656 // Constraint 'f' cannot be used for output operands. 1657 if (Info.ConstraintStr[0] == '=') 1658 return false; 1659 Info.setAllowsRegister(); 1660 return true; 1661 case 'a': // eax. 1662 case 'b': // ebx. 1663 case 'c': // ecx. 1664 case 'd': // edx. 1665 case 'S': // esi. 1666 case 'D': // edi. 1667 case 'A': // edx:eax. 1668 case 't': // Top of floating point stack. 1669 case 'u': // Second from top of floating point stack. 1670 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1671 case 'y': // Any MMX register. 1672 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1673 case 'x': // Any SSE register. 1674 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1675 // for intermideate k reg operations). 1676 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1677 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1678 case 'l': // "Index" registers: any general register that can be used as an 1679 // index in a base+index memory access. 1680 Info.setAllowsRegister(); 1681 return true; 1682 // Floating point constant constraints. 1683 case 'C': // SSE floating point constant. 1684 case 'G': // x87 floating point constant. 1685 return true; 1686 case '@': 1687 // CC condition changes. 1688 if (auto Len = matchAsmCCConstraint(Name)) { 1689 Name += Len - 1; 1690 Info.setAllowsRegister(); 1691 return true; 1692 } 1693 return false; 1694 } 1695 } 1696 1697 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1698 unsigned Size) const { 1699 // Strip off constraint modifiers. 1700 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1701 Constraint = Constraint.substr(1); 1702 1703 return validateOperandSize(Constraint, Size); 1704 } 1705 1706 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1707 unsigned Size) const { 1708 return validateOperandSize(Constraint, Size); 1709 } 1710 1711 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1712 unsigned Size) const { 1713 switch (Constraint[0]) { 1714 default: 1715 break; 1716 case 'k': 1717 // Registers k0-k7 (AVX512) size limit is 64 bit. 1718 case 'y': 1719 return Size <= 64; 1720 case 'f': 1721 case 't': 1722 case 'u': 1723 return Size <= 128; 1724 case 'Y': 1725 // 'Y' is the first character for several 2-character constraints. 1726 switch (Constraint[1]) { 1727 default: 1728 return false; 1729 case 'm': 1730 // 'Ym' is synonymous with 'y'. 1731 case 'k': 1732 return Size <= 64; 1733 case 'z': 1734 case '0': 1735 // XMM0 1736 if (SSELevel >= SSE1) 1737 return Size <= 128U; 1738 return false; 1739 case 'i': 1740 case 't': 1741 case '2': 1742 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1743 if (SSELevel < SSE2) 1744 return false; 1745 break; 1746 } 1747 LLVM_FALLTHROUGH; 1748 case 'v': 1749 case 'x': 1750 if (SSELevel >= AVX512F) 1751 // 512-bit zmm registers can be used if target supports AVX512F. 1752 return Size <= 512U; 1753 else if (SSELevel >= AVX) 1754 // 256-bit ymm registers can be used if target supports AVX. 1755 return Size <= 256U; 1756 return Size <= 128U; 1757 1758 } 1759 1760 return true; 1761 } 1762 1763 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1764 switch (*Constraint) { 1765 case '@': 1766 if (auto Len = matchAsmCCConstraint(Constraint)) { 1767 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1768 Constraint += Len - 1; 1769 return Converted; 1770 } 1771 return std::string(1, *Constraint); 1772 case 'a': 1773 return std::string("{ax}"); 1774 case 'b': 1775 return std::string("{bx}"); 1776 case 'c': 1777 return std::string("{cx}"); 1778 case 'd': 1779 return std::string("{dx}"); 1780 case 'S': 1781 return std::string("{si}"); 1782 case 'D': 1783 return std::string("{di}"); 1784 case 'p': // address 1785 return std::string("im"); 1786 case 't': // top of floating point stack. 1787 return std::string("{st}"); 1788 case 'u': // second from top of floating point stack. 1789 return std::string("{st(1)}"); // second from top of floating point stack. 1790 case 'Y': 1791 switch (Constraint[1]) { 1792 default: 1793 // Break from inner switch and fall through (copy single char), 1794 // continue parsing after copying the current constraint into 1795 // the return string. 1796 break; 1797 case 'k': 1798 case 'm': 1799 case 'i': 1800 case 't': 1801 case 'z': 1802 case '0': 1803 case '2': 1804 // "^" hints llvm that this is a 2 letter constraint. 1805 // "Constraint++" is used to promote the string iterator 1806 // to the next constraint. 1807 return std::string("^") + std::string(Constraint++, 2); 1808 } 1809 LLVM_FALLTHROUGH; 1810 default: 1811 return std::string(1, *Constraint); 1812 } 1813 } 1814 1815 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1816 // Perform any per-CPU checks necessary to determine if this CPU is 1817 // acceptable. 1818 switch (Kind) { 1819 case CK_Generic: 1820 // No processor selected! 1821 return false; 1822 #define PROC(ENUM, STRING, IS64BIT) \ 1823 case CK_##ENUM: \ 1824 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1825 #include "clang/Basic/X86Target.def" 1826 } 1827 llvm_unreachable("Unhandled CPU kind"); 1828 } 1829 1830 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1831 #define PROC(ENUM, STRING, IS64BIT) \ 1832 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1833 Values.emplace_back(STRING); 1834 // Go through CPUKind checking to ensure that the alias is de-aliased and 1835 // 64 bit-ness is checked. 1836 #define PROC_ALIAS(ENUM, ALIAS) \ 1837 if (checkCPUKind(getCPUKind(ALIAS))) \ 1838 Values.emplace_back(ALIAS); 1839 #include "clang/Basic/X86Target.def" 1840 } 1841 1842 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1843 return llvm::StringSwitch<CPUKind>(CPU) 1844 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1845 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1846 #include "clang/Basic/X86Target.def" 1847 .Default(CK_Generic); 1848 } 1849 1850 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1851 return llvm::makeArrayRef(GCCRegNames); 1852 } 1853 1854 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1855 return llvm::makeArrayRef(AddlRegNames); 1856 } 1857 1858 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1859 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1860 Builtin::FirstTSBuiltin + 1); 1861 } 1862 1863 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1864 return llvm::makeArrayRef(BuiltinInfoX86, 1865 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1866 } 1867