1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 switch (Kind) { 119 case CK_Generic: 120 case CK_i386: 121 case CK_i486: 122 case CK_i586: 123 case CK_Pentium: 124 case CK_PentiumPro: 125 case CK_Lakemont: 126 break; 127 128 case CK_PentiumMMX: 129 case CK_Pentium2: 130 case CK_K6: 131 case CK_WinChipC6: 132 setFeatureEnabledImpl(Features, "mmx", true); 133 break; 134 135 case CK_IcelakeServer: 136 setFeatureEnabledImpl(Features, "pconfig", true); 137 setFeatureEnabledImpl(Features, "wbnoinvd", true); 138 LLVM_FALLTHROUGH; 139 case CK_IcelakeClient: 140 setFeatureEnabledImpl(Features, "vaes", true); 141 setFeatureEnabledImpl(Features, "gfni", true); 142 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 143 setFeatureEnabledImpl(Features, "avx512bitalg", true); 144 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 145 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 146 setFeatureEnabledImpl(Features, "rdpid", true); 147 LLVM_FALLTHROUGH; 148 case CK_Cannonlake: 149 setFeatureEnabledImpl(Features, "avx512ifma", true); 150 setFeatureEnabledImpl(Features, "avx512vbmi", true); 151 setFeatureEnabledImpl(Features, "sha", true); 152 LLVM_FALLTHROUGH; 153 case CK_Cascadelake: 154 //Cannonlake has no VNNI feature inside while Icelake has 155 if (Kind != CK_Cannonlake) 156 // CLK inherits all SKX features plus AVX512_VNNI 157 setFeatureEnabledImpl(Features, "avx512vnni", true); 158 LLVM_FALLTHROUGH; 159 case CK_SkylakeServer: 160 setFeatureEnabledImpl(Features, "avx512f", true); 161 setFeatureEnabledImpl(Features, "avx512cd", true); 162 setFeatureEnabledImpl(Features, "avx512dq", true); 163 setFeatureEnabledImpl(Features, "avx512bw", true); 164 setFeatureEnabledImpl(Features, "avx512vl", true); 165 setFeatureEnabledImpl(Features, "pku", true); 166 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 167 setFeatureEnabledImpl(Features, "clwb", true); 168 LLVM_FALLTHROUGH; 169 case CK_SkylakeClient: 170 setFeatureEnabledImpl(Features, "xsavec", true); 171 setFeatureEnabledImpl(Features, "xsaves", true); 172 setFeatureEnabledImpl(Features, "mpx", true); 173 if (Kind != CK_SkylakeServer 174 && Kind != CK_Cascadelake) 175 // SKX/CLX inherits all SKL features, except SGX 176 setFeatureEnabledImpl(Features, "sgx", true); 177 setFeatureEnabledImpl(Features, "clflushopt", true); 178 setFeatureEnabledImpl(Features, "aes", true); 179 LLVM_FALLTHROUGH; 180 case CK_Broadwell: 181 setFeatureEnabledImpl(Features, "rdseed", true); 182 setFeatureEnabledImpl(Features, "adx", true); 183 setFeatureEnabledImpl(Features, "prfchw", true); 184 LLVM_FALLTHROUGH; 185 case CK_Haswell: 186 setFeatureEnabledImpl(Features, "avx2", true); 187 setFeatureEnabledImpl(Features, "lzcnt", true); 188 setFeatureEnabledImpl(Features, "bmi", true); 189 setFeatureEnabledImpl(Features, "bmi2", true); 190 setFeatureEnabledImpl(Features, "fma", true); 191 setFeatureEnabledImpl(Features, "invpcid", true); 192 setFeatureEnabledImpl(Features, "movbe", true); 193 LLVM_FALLTHROUGH; 194 case CK_IvyBridge: 195 setFeatureEnabledImpl(Features, "rdrnd", true); 196 setFeatureEnabledImpl(Features, "f16c", true); 197 setFeatureEnabledImpl(Features, "fsgsbase", true); 198 LLVM_FALLTHROUGH; 199 case CK_SandyBridge: 200 setFeatureEnabledImpl(Features, "avx", true); 201 setFeatureEnabledImpl(Features, "xsave", true); 202 setFeatureEnabledImpl(Features, "xsaveopt", true); 203 LLVM_FALLTHROUGH; 204 case CK_Westmere: 205 setFeatureEnabledImpl(Features, "pclmul", true); 206 LLVM_FALLTHROUGH; 207 case CK_Nehalem: 208 setFeatureEnabledImpl(Features, "sse4.2", true); 209 LLVM_FALLTHROUGH; 210 case CK_Penryn: 211 setFeatureEnabledImpl(Features, "sse4.1", true); 212 LLVM_FALLTHROUGH; 213 case CK_Core2: 214 setFeatureEnabledImpl(Features, "ssse3", true); 215 setFeatureEnabledImpl(Features, "sahf", true); 216 LLVM_FALLTHROUGH; 217 case CK_Yonah: 218 case CK_Prescott: 219 case CK_Nocona: 220 setFeatureEnabledImpl(Features, "sse3", true); 221 setFeatureEnabledImpl(Features, "cx16", true); 222 LLVM_FALLTHROUGH; 223 case CK_PentiumM: 224 case CK_Pentium4: 225 case CK_x86_64: 226 setFeatureEnabledImpl(Features, "sse2", true); 227 LLVM_FALLTHROUGH; 228 case CK_Pentium3: 229 case CK_C3_2: 230 setFeatureEnabledImpl(Features, "sse", true); 231 setFeatureEnabledImpl(Features, "fxsr", true); 232 break; 233 234 case CK_Tremont: 235 setFeatureEnabledImpl(Features, "cldemote", true); 236 setFeatureEnabledImpl(Features, "movdiri", true); 237 setFeatureEnabledImpl(Features, "movdir64b", true); 238 setFeatureEnabledImpl(Features, "gfni", true); 239 setFeatureEnabledImpl(Features, "waitpkg", true); 240 LLVM_FALLTHROUGH; 241 case CK_GoldmontPlus: 242 setFeatureEnabledImpl(Features, "ptwrite", true); 243 setFeatureEnabledImpl(Features, "rdpid", true); 244 setFeatureEnabledImpl(Features, "sgx", true); 245 LLVM_FALLTHROUGH; 246 case CK_Goldmont: 247 setFeatureEnabledImpl(Features, "sha", true); 248 setFeatureEnabledImpl(Features, "rdseed", true); 249 setFeatureEnabledImpl(Features, "xsave", true); 250 setFeatureEnabledImpl(Features, "xsaveopt", true); 251 setFeatureEnabledImpl(Features, "xsavec", true); 252 setFeatureEnabledImpl(Features, "xsaves", true); 253 setFeatureEnabledImpl(Features, "clflushopt", true); 254 setFeatureEnabledImpl(Features, "mpx", true); 255 setFeatureEnabledImpl(Features, "fsgsbase", true); 256 setFeatureEnabledImpl(Features, "aes", true); 257 LLVM_FALLTHROUGH; 258 case CK_Silvermont: 259 setFeatureEnabledImpl(Features, "rdrnd", true); 260 setFeatureEnabledImpl(Features, "pclmul", true); 261 setFeatureEnabledImpl(Features, "sse4.2", true); 262 setFeatureEnabledImpl(Features, "prfchw", true); 263 LLVM_FALLTHROUGH; 264 case CK_Bonnell: 265 setFeatureEnabledImpl(Features, "movbe", true); 266 setFeatureEnabledImpl(Features, "ssse3", true); 267 setFeatureEnabledImpl(Features, "fxsr", true); 268 setFeatureEnabledImpl(Features, "cx16", true); 269 setFeatureEnabledImpl(Features, "sahf", true); 270 break; 271 272 case CK_KNM: 273 // TODO: Add avx5124fmaps/avx5124vnniw. 274 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 275 LLVM_FALLTHROUGH; 276 case CK_KNL: 277 setFeatureEnabledImpl(Features, "avx512f", true); 278 setFeatureEnabledImpl(Features, "avx512cd", true); 279 setFeatureEnabledImpl(Features, "avx512er", true); 280 setFeatureEnabledImpl(Features, "avx512pf", true); 281 setFeatureEnabledImpl(Features, "prfchw", true); 282 setFeatureEnabledImpl(Features, "prefetchwt1", true); 283 setFeatureEnabledImpl(Features, "fxsr", true); 284 setFeatureEnabledImpl(Features, "rdseed", true); 285 setFeatureEnabledImpl(Features, "adx", true); 286 setFeatureEnabledImpl(Features, "lzcnt", true); 287 setFeatureEnabledImpl(Features, "bmi", true); 288 setFeatureEnabledImpl(Features, "bmi2", true); 289 setFeatureEnabledImpl(Features, "fma", true); 290 setFeatureEnabledImpl(Features, "rdrnd", true); 291 setFeatureEnabledImpl(Features, "f16c", true); 292 setFeatureEnabledImpl(Features, "fsgsbase", true); 293 setFeatureEnabledImpl(Features, "aes", true); 294 setFeatureEnabledImpl(Features, "pclmul", true); 295 setFeatureEnabledImpl(Features, "cx16", true); 296 setFeatureEnabledImpl(Features, "xsaveopt", true); 297 setFeatureEnabledImpl(Features, "xsave", true); 298 setFeatureEnabledImpl(Features, "movbe", true); 299 setFeatureEnabledImpl(Features, "sahf", true); 300 break; 301 302 case CK_K6_2: 303 case CK_K6_3: 304 case CK_WinChip2: 305 case CK_C3: 306 setFeatureEnabledImpl(Features, "3dnow", true); 307 break; 308 309 case CK_AMDFAM10: 310 setFeatureEnabledImpl(Features, "sse4a", true); 311 setFeatureEnabledImpl(Features, "lzcnt", true); 312 setFeatureEnabledImpl(Features, "popcnt", true); 313 setFeatureEnabledImpl(Features, "sahf", true); 314 LLVM_FALLTHROUGH; 315 case CK_K8SSE3: 316 setFeatureEnabledImpl(Features, "sse3", true); 317 LLVM_FALLTHROUGH; 318 case CK_K8: 319 setFeatureEnabledImpl(Features, "sse2", true); 320 LLVM_FALLTHROUGH; 321 case CK_AthlonXP: 322 setFeatureEnabledImpl(Features, "sse", true); 323 setFeatureEnabledImpl(Features, "fxsr", true); 324 LLVM_FALLTHROUGH; 325 case CK_Athlon: 326 case CK_Geode: 327 setFeatureEnabledImpl(Features, "3dnowa", true); 328 break; 329 330 case CK_BTVER2: 331 setFeatureEnabledImpl(Features, "avx", true); 332 setFeatureEnabledImpl(Features, "aes", true); 333 setFeatureEnabledImpl(Features, "pclmul", true); 334 setFeatureEnabledImpl(Features, "bmi", true); 335 setFeatureEnabledImpl(Features, "f16c", true); 336 setFeatureEnabledImpl(Features, "xsaveopt", true); 337 setFeatureEnabledImpl(Features, "movbe", true); 338 LLVM_FALLTHROUGH; 339 case CK_BTVER1: 340 setFeatureEnabledImpl(Features, "ssse3", true); 341 setFeatureEnabledImpl(Features, "sse4a", true); 342 setFeatureEnabledImpl(Features, "lzcnt", true); 343 setFeatureEnabledImpl(Features, "popcnt", true); 344 setFeatureEnabledImpl(Features, "prfchw", true); 345 setFeatureEnabledImpl(Features, "cx16", true); 346 setFeatureEnabledImpl(Features, "fxsr", true); 347 setFeatureEnabledImpl(Features, "sahf", true); 348 break; 349 350 case CK_ZNVER2: 351 setFeatureEnabledImpl(Features, "clwb", true); 352 setFeatureEnabledImpl(Features, "rdpid", true); 353 setFeatureEnabledImpl(Features, "wbnoinvd", true); 354 LLVM_FALLTHROUGH; 355 case CK_ZNVER1: 356 setFeatureEnabledImpl(Features, "adx", true); 357 setFeatureEnabledImpl(Features, "aes", true); 358 setFeatureEnabledImpl(Features, "avx2", true); 359 setFeatureEnabledImpl(Features, "bmi", true); 360 setFeatureEnabledImpl(Features, "bmi2", true); 361 setFeatureEnabledImpl(Features, "clflushopt", true); 362 setFeatureEnabledImpl(Features, "clzero", true); 363 setFeatureEnabledImpl(Features, "cx16", true); 364 setFeatureEnabledImpl(Features, "f16c", true); 365 setFeatureEnabledImpl(Features, "fma", true); 366 setFeatureEnabledImpl(Features, "fsgsbase", true); 367 setFeatureEnabledImpl(Features, "fxsr", true); 368 setFeatureEnabledImpl(Features, "lzcnt", true); 369 setFeatureEnabledImpl(Features, "mwaitx", true); 370 setFeatureEnabledImpl(Features, "movbe", true); 371 setFeatureEnabledImpl(Features, "pclmul", true); 372 setFeatureEnabledImpl(Features, "popcnt", true); 373 setFeatureEnabledImpl(Features, "prfchw", true); 374 setFeatureEnabledImpl(Features, "rdrnd", true); 375 setFeatureEnabledImpl(Features, "rdseed", true); 376 setFeatureEnabledImpl(Features, "sahf", true); 377 setFeatureEnabledImpl(Features, "sha", true); 378 setFeatureEnabledImpl(Features, "sse4a", true); 379 setFeatureEnabledImpl(Features, "xsave", true); 380 setFeatureEnabledImpl(Features, "xsavec", true); 381 setFeatureEnabledImpl(Features, "xsaveopt", true); 382 setFeatureEnabledImpl(Features, "xsaves", true); 383 break; 384 385 case CK_BDVER4: 386 setFeatureEnabledImpl(Features, "avx2", true); 387 setFeatureEnabledImpl(Features, "bmi2", true); 388 setFeatureEnabledImpl(Features, "mwaitx", true); 389 LLVM_FALLTHROUGH; 390 case CK_BDVER3: 391 setFeatureEnabledImpl(Features, "fsgsbase", true); 392 setFeatureEnabledImpl(Features, "xsaveopt", true); 393 LLVM_FALLTHROUGH; 394 case CK_BDVER2: 395 setFeatureEnabledImpl(Features, "bmi", true); 396 setFeatureEnabledImpl(Features, "fma", true); 397 setFeatureEnabledImpl(Features, "f16c", true); 398 setFeatureEnabledImpl(Features, "tbm", true); 399 LLVM_FALLTHROUGH; 400 case CK_BDVER1: 401 // xop implies avx, sse4a and fma4. 402 setFeatureEnabledImpl(Features, "xop", true); 403 setFeatureEnabledImpl(Features, "lwp", true); 404 setFeatureEnabledImpl(Features, "lzcnt", true); 405 setFeatureEnabledImpl(Features, "aes", true); 406 setFeatureEnabledImpl(Features, "pclmul", true); 407 setFeatureEnabledImpl(Features, "prfchw", true); 408 setFeatureEnabledImpl(Features, "cx16", true); 409 setFeatureEnabledImpl(Features, "fxsr", true); 410 setFeatureEnabledImpl(Features, "xsave", true); 411 setFeatureEnabledImpl(Features, "sahf", true); 412 break; 413 } 414 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 415 return false; 416 417 // Can't do this earlier because we need to be able to explicitly enable 418 // or disable these features and the things that they depend upon. 419 420 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 421 auto I = Features.find("sse4.2"); 422 if (I != Features.end() && I->getValue() && 423 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 424 FeaturesVec.end()) 425 Features["popcnt"] = true; 426 427 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 428 I = Features.find("3dnow"); 429 if (I != Features.end() && I->getValue() && 430 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 431 FeaturesVec.end()) 432 Features["prfchw"] = true; 433 434 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 435 // then enable MMX. 436 I = Features.find("sse"); 437 if (I != Features.end() && I->getValue() && 438 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 439 FeaturesVec.end()) 440 Features["mmx"] = true; 441 442 return true; 443 } 444 445 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 446 X86SSEEnum Level, bool Enabled) { 447 if (Enabled) { 448 switch (Level) { 449 case AVX512F: 450 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 451 LLVM_FALLTHROUGH; 452 case AVX2: 453 Features["avx2"] = true; 454 LLVM_FALLTHROUGH; 455 case AVX: 456 Features["avx"] = true; 457 Features["xsave"] = true; 458 LLVM_FALLTHROUGH; 459 case SSE42: 460 Features["sse4.2"] = true; 461 LLVM_FALLTHROUGH; 462 case SSE41: 463 Features["sse4.1"] = true; 464 LLVM_FALLTHROUGH; 465 case SSSE3: 466 Features["ssse3"] = true; 467 LLVM_FALLTHROUGH; 468 case SSE3: 469 Features["sse3"] = true; 470 LLVM_FALLTHROUGH; 471 case SSE2: 472 Features["sse2"] = true; 473 LLVM_FALLTHROUGH; 474 case SSE1: 475 Features["sse"] = true; 476 LLVM_FALLTHROUGH; 477 case NoSSE: 478 break; 479 } 480 return; 481 } 482 483 switch (Level) { 484 case NoSSE: 485 case SSE1: 486 Features["sse"] = false; 487 LLVM_FALLTHROUGH; 488 case SSE2: 489 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 490 Features["gfni"] = false; 491 LLVM_FALLTHROUGH; 492 case SSE3: 493 Features["sse3"] = false; 494 setXOPLevel(Features, NoXOP, false); 495 LLVM_FALLTHROUGH; 496 case SSSE3: 497 Features["ssse3"] = false; 498 LLVM_FALLTHROUGH; 499 case SSE41: 500 Features["sse4.1"] = false; 501 LLVM_FALLTHROUGH; 502 case SSE42: 503 Features["sse4.2"] = false; 504 LLVM_FALLTHROUGH; 505 case AVX: 506 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 507 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 508 setXOPLevel(Features, FMA4, false); 509 LLVM_FALLTHROUGH; 510 case AVX2: 511 Features["avx2"] = false; 512 LLVM_FALLTHROUGH; 513 case AVX512F: 514 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 515 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 516 Features["avx512vl"] = Features["avx512vbmi"] = 517 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 518 Features["avx512bitalg"] = Features["avx512vnni"] = 519 Features["avx512vbmi2"] = false; 520 break; 521 } 522 } 523 524 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 525 MMX3DNowEnum Level, bool Enabled) { 526 if (Enabled) { 527 switch (Level) { 528 case AMD3DNowAthlon: 529 Features["3dnowa"] = true; 530 LLVM_FALLTHROUGH; 531 case AMD3DNow: 532 Features["3dnow"] = true; 533 LLVM_FALLTHROUGH; 534 case MMX: 535 Features["mmx"] = true; 536 LLVM_FALLTHROUGH; 537 case NoMMX3DNow: 538 break; 539 } 540 return; 541 } 542 543 switch (Level) { 544 case NoMMX3DNow: 545 case MMX: 546 Features["mmx"] = false; 547 LLVM_FALLTHROUGH; 548 case AMD3DNow: 549 Features["3dnow"] = false; 550 LLVM_FALLTHROUGH; 551 case AMD3DNowAthlon: 552 Features["3dnowa"] = false; 553 break; 554 } 555 } 556 557 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 558 bool Enabled) { 559 if (Enabled) { 560 switch (Level) { 561 case XOP: 562 Features["xop"] = true; 563 LLVM_FALLTHROUGH; 564 case FMA4: 565 Features["fma4"] = true; 566 setSSELevel(Features, AVX, true); 567 LLVM_FALLTHROUGH; 568 case SSE4A: 569 Features["sse4a"] = true; 570 setSSELevel(Features, SSE3, true); 571 LLVM_FALLTHROUGH; 572 case NoXOP: 573 break; 574 } 575 return; 576 } 577 578 switch (Level) { 579 case NoXOP: 580 case SSE4A: 581 Features["sse4a"] = false; 582 LLVM_FALLTHROUGH; 583 case FMA4: 584 Features["fma4"] = false; 585 LLVM_FALLTHROUGH; 586 case XOP: 587 Features["xop"] = false; 588 break; 589 } 590 } 591 592 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 593 StringRef Name, bool Enabled) { 594 // This is a bit of a hack to deal with the sse4 target feature when used 595 // as part of the target attribute. We handle sse4 correctly everywhere 596 // else. See below for more information on how we handle the sse4 options. 597 if (Name != "sse4") 598 Features[Name] = Enabled; 599 600 if (Name == "mmx") { 601 setMMXLevel(Features, MMX, Enabled); 602 } else if (Name == "sse") { 603 setSSELevel(Features, SSE1, Enabled); 604 } else if (Name == "sse2") { 605 setSSELevel(Features, SSE2, Enabled); 606 } else if (Name == "sse3") { 607 setSSELevel(Features, SSE3, Enabled); 608 } else if (Name == "ssse3") { 609 setSSELevel(Features, SSSE3, Enabled); 610 } else if (Name == "sse4.2") { 611 setSSELevel(Features, SSE42, Enabled); 612 } else if (Name == "sse4.1") { 613 setSSELevel(Features, SSE41, Enabled); 614 } else if (Name == "3dnow") { 615 setMMXLevel(Features, AMD3DNow, Enabled); 616 } else if (Name == "3dnowa") { 617 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 618 } else if (Name == "aes") { 619 if (Enabled) 620 setSSELevel(Features, SSE2, Enabled); 621 else 622 Features["vaes"] = false; 623 } else if (Name == "vaes") { 624 if (Enabled) { 625 setSSELevel(Features, AVX, Enabled); 626 Features["aes"] = true; 627 } 628 } else if (Name == "pclmul") { 629 if (Enabled) 630 setSSELevel(Features, SSE2, Enabled); 631 else 632 Features["vpclmulqdq"] = false; 633 } else if (Name == "vpclmulqdq") { 634 if (Enabled) { 635 setSSELevel(Features, AVX, Enabled); 636 Features["pclmul"] = true; 637 } 638 } else if (Name == "gfni") { 639 if (Enabled) 640 setSSELevel(Features, SSE2, Enabled); 641 } else if (Name == "avx") { 642 setSSELevel(Features, AVX, Enabled); 643 } else if (Name == "avx2") { 644 setSSELevel(Features, AVX2, Enabled); 645 } else if (Name == "avx512f") { 646 setSSELevel(Features, AVX512F, Enabled); 647 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 648 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 649 Name == "avx512vbmi" || Name == "avx512ifma" || 650 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 651 Name == "avx512vnni" || Name == "avx512vbmi2") { 652 if (Enabled) 653 setSSELevel(Features, AVX512F, Enabled); 654 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 655 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 656 Features["avx512bw"] = true; 657 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 658 if (Name == "avx512bw" && !Enabled) 659 Features["avx512vbmi"] = Features["avx512vbmi2"] = 660 Features["avx512bitalg"] = false; 661 } else if (Name == "fma") { 662 if (Enabled) 663 setSSELevel(Features, AVX, Enabled); 664 else 665 setSSELevel(Features, AVX512F, Enabled); 666 } else if (Name == "fma4") { 667 setXOPLevel(Features, FMA4, Enabled); 668 } else if (Name == "xop") { 669 setXOPLevel(Features, XOP, Enabled); 670 } else if (Name == "sse4a") { 671 setXOPLevel(Features, SSE4A, Enabled); 672 } else if (Name == "f16c") { 673 if (Enabled) 674 setSSELevel(Features, AVX, Enabled); 675 else 676 setSSELevel(Features, AVX512F, Enabled); 677 } else if (Name == "sha") { 678 if (Enabled) 679 setSSELevel(Features, SSE2, Enabled); 680 } else if (Name == "sse4") { 681 // We can get here via the __target__ attribute since that's not controlled 682 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 683 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 684 // disabled. 685 if (Enabled) 686 setSSELevel(Features, SSE42, Enabled); 687 else 688 setSSELevel(Features, SSE41, Enabled); 689 } else if (Name == "xsave") { 690 if (!Enabled) 691 Features["xsaveopt"] = false; 692 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 693 if (Enabled) 694 Features["xsave"] = true; 695 } 696 } 697 698 /// handleTargetFeatures - Perform initialization based on the user 699 /// configured set of features. 700 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 701 DiagnosticsEngine &Diags) { 702 for (const auto &Feature : Features) { 703 if (Feature[0] != '+') 704 continue; 705 706 if (Feature == "+aes") { 707 HasAES = true; 708 } else if (Feature == "+vaes") { 709 HasVAES = true; 710 } else if (Feature == "+pclmul") { 711 HasPCLMUL = true; 712 } else if (Feature == "+vpclmulqdq") { 713 HasVPCLMULQDQ = true; 714 } else if (Feature == "+lzcnt") { 715 HasLZCNT = true; 716 } else if (Feature == "+rdrnd") { 717 HasRDRND = true; 718 } else if (Feature == "+fsgsbase") { 719 HasFSGSBASE = true; 720 } else if (Feature == "+bmi") { 721 HasBMI = true; 722 } else if (Feature == "+bmi2") { 723 HasBMI2 = true; 724 } else if (Feature == "+popcnt") { 725 HasPOPCNT = true; 726 } else if (Feature == "+rtm") { 727 HasRTM = true; 728 } else if (Feature == "+prfchw") { 729 HasPRFCHW = true; 730 } else if (Feature == "+rdseed") { 731 HasRDSEED = true; 732 } else if (Feature == "+adx") { 733 HasADX = true; 734 } else if (Feature == "+tbm") { 735 HasTBM = true; 736 } else if (Feature == "+lwp") { 737 HasLWP = true; 738 } else if (Feature == "+fma") { 739 HasFMA = true; 740 } else if (Feature == "+f16c") { 741 HasF16C = true; 742 } else if (Feature == "+gfni") { 743 HasGFNI = true; 744 } else if (Feature == "+avx512cd") { 745 HasAVX512CD = true; 746 } else if (Feature == "+avx512vpopcntdq") { 747 HasAVX512VPOPCNTDQ = true; 748 } else if (Feature == "+avx512vnni") { 749 HasAVX512VNNI = true; 750 } else if (Feature == "+avx512er") { 751 HasAVX512ER = true; 752 } else if (Feature == "+avx512pf") { 753 HasAVX512PF = true; 754 } else if (Feature == "+avx512dq") { 755 HasAVX512DQ = true; 756 } else if (Feature == "+avx512bitalg") { 757 HasAVX512BITALG = true; 758 } else if (Feature == "+avx512bw") { 759 HasAVX512BW = true; 760 } else if (Feature == "+avx512vl") { 761 HasAVX512VL = true; 762 } else if (Feature == "+avx512vbmi") { 763 HasAVX512VBMI = true; 764 } else if (Feature == "+avx512vbmi2") { 765 HasAVX512VBMI2 = true; 766 } else if (Feature == "+avx512ifma") { 767 HasAVX512IFMA = true; 768 } else if (Feature == "+sha") { 769 HasSHA = true; 770 } else if (Feature == "+mpx") { 771 HasMPX = true; 772 } else if (Feature == "+shstk") { 773 HasSHSTK = true; 774 } else if (Feature == "+movbe") { 775 HasMOVBE = true; 776 } else if (Feature == "+sgx") { 777 HasSGX = true; 778 } else if (Feature == "+cx16") { 779 HasCX16 = true; 780 } else if (Feature == "+fxsr") { 781 HasFXSR = true; 782 } else if (Feature == "+xsave") { 783 HasXSAVE = true; 784 } else if (Feature == "+xsaveopt") { 785 HasXSAVEOPT = true; 786 } else if (Feature == "+xsavec") { 787 HasXSAVEC = true; 788 } else if (Feature == "+xsaves") { 789 HasXSAVES = true; 790 } else if (Feature == "+mwaitx") { 791 HasMWAITX = true; 792 } else if (Feature == "+pku") { 793 HasPKU = true; 794 } else if (Feature == "+clflushopt") { 795 HasCLFLUSHOPT = true; 796 } else if (Feature == "+clwb") { 797 HasCLWB = true; 798 } else if (Feature == "+wbnoinvd") { 799 HasWBNOINVD = true; 800 } else if (Feature == "+prefetchwt1") { 801 HasPREFETCHWT1 = true; 802 } else if (Feature == "+clzero") { 803 HasCLZERO = true; 804 } else if (Feature == "+cldemote") { 805 HasCLDEMOTE = true; 806 } else if (Feature == "+rdpid") { 807 HasRDPID = true; 808 } else if (Feature == "+retpoline-external-thunk") { 809 HasRetpolineExternalThunk = true; 810 } else if (Feature == "+sahf") { 811 HasLAHFSAHF = true; 812 } else if (Feature == "+waitpkg") { 813 HasWAITPKG = true; 814 } else if (Feature == "+movdiri") { 815 HasMOVDIRI = true; 816 } else if (Feature == "+movdir64b") { 817 HasMOVDIR64B = true; 818 } else if (Feature == "+pconfig") { 819 HasPCONFIG = true; 820 } else if (Feature == "+ptwrite") { 821 HasPTWRITE = true; 822 } else if (Feature == "+invpcid") { 823 HasINVPCID = true; 824 } 825 826 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 827 .Case("+avx512f", AVX512F) 828 .Case("+avx2", AVX2) 829 .Case("+avx", AVX) 830 .Case("+sse4.2", SSE42) 831 .Case("+sse4.1", SSE41) 832 .Case("+ssse3", SSSE3) 833 .Case("+sse3", SSE3) 834 .Case("+sse2", SSE2) 835 .Case("+sse", SSE1) 836 .Default(NoSSE); 837 SSELevel = std::max(SSELevel, Level); 838 839 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 840 .Case("+3dnowa", AMD3DNowAthlon) 841 .Case("+3dnow", AMD3DNow) 842 .Case("+mmx", MMX) 843 .Default(NoMMX3DNow); 844 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 845 846 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 847 .Case("+xop", XOP) 848 .Case("+fma4", FMA4) 849 .Case("+sse4a", SSE4A) 850 .Default(NoXOP); 851 XOPLevel = std::max(XOPLevel, XLevel); 852 } 853 854 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 855 // matches the selected sse level. 856 if ((FPMath == FP_SSE && SSELevel < SSE1) || 857 (FPMath == FP_387 && SSELevel >= SSE1)) { 858 Diags.Report(diag::err_target_unsupported_fpmath) 859 << (FPMath == FP_SSE ? "sse" : "387"); 860 return false; 861 } 862 863 SimdDefaultAlign = 864 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 865 return true; 866 } 867 868 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 869 /// definitions for this particular subtarget. 870 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 871 MacroBuilder &Builder) const { 872 // Inline assembly supports X86 flag outputs. 873 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 874 875 std::string CodeModel = getTargetOpts().CodeModel; 876 if (CodeModel == "default") 877 CodeModel = "small"; 878 Builder.defineMacro("__code_model_" + CodeModel + "_"); 879 880 // Target identification. 881 if (getTriple().getArch() == llvm::Triple::x86_64) { 882 Builder.defineMacro("__amd64__"); 883 Builder.defineMacro("__amd64"); 884 Builder.defineMacro("__x86_64"); 885 Builder.defineMacro("__x86_64__"); 886 if (getTriple().getArchName() == "x86_64h") { 887 Builder.defineMacro("__x86_64h"); 888 Builder.defineMacro("__x86_64h__"); 889 } 890 } else { 891 DefineStd(Builder, "i386", Opts); 892 } 893 894 // Subtarget options. 895 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 896 // truly should be based on -mtune options. 897 switch (CPU) { 898 case CK_Generic: 899 break; 900 case CK_i386: 901 // The rest are coming from the i386 define above. 902 Builder.defineMacro("__tune_i386__"); 903 break; 904 case CK_i486: 905 case CK_WinChipC6: 906 case CK_WinChip2: 907 case CK_C3: 908 defineCPUMacros(Builder, "i486"); 909 break; 910 case CK_PentiumMMX: 911 Builder.defineMacro("__pentium_mmx__"); 912 Builder.defineMacro("__tune_pentium_mmx__"); 913 LLVM_FALLTHROUGH; 914 case CK_i586: 915 case CK_Pentium: 916 defineCPUMacros(Builder, "i586"); 917 defineCPUMacros(Builder, "pentium"); 918 break; 919 case CK_Pentium3: 920 case CK_PentiumM: 921 Builder.defineMacro("__tune_pentium3__"); 922 LLVM_FALLTHROUGH; 923 case CK_Pentium2: 924 case CK_C3_2: 925 Builder.defineMacro("__tune_pentium2__"); 926 LLVM_FALLTHROUGH; 927 case CK_PentiumPro: 928 defineCPUMacros(Builder, "i686"); 929 defineCPUMacros(Builder, "pentiumpro"); 930 break; 931 case CK_Pentium4: 932 defineCPUMacros(Builder, "pentium4"); 933 break; 934 case CK_Yonah: 935 case CK_Prescott: 936 case CK_Nocona: 937 defineCPUMacros(Builder, "nocona"); 938 break; 939 case CK_Core2: 940 case CK_Penryn: 941 defineCPUMacros(Builder, "core2"); 942 break; 943 case CK_Bonnell: 944 defineCPUMacros(Builder, "atom"); 945 break; 946 case CK_Silvermont: 947 defineCPUMacros(Builder, "slm"); 948 break; 949 case CK_Goldmont: 950 defineCPUMacros(Builder, "goldmont"); 951 break; 952 case CK_GoldmontPlus: 953 defineCPUMacros(Builder, "goldmont_plus"); 954 break; 955 case CK_Tremont: 956 defineCPUMacros(Builder, "tremont"); 957 break; 958 case CK_Nehalem: 959 case CK_Westmere: 960 case CK_SandyBridge: 961 case CK_IvyBridge: 962 case CK_Haswell: 963 case CK_Broadwell: 964 case CK_SkylakeClient: 965 case CK_SkylakeServer: 966 case CK_Cascadelake: 967 case CK_Cannonlake: 968 case CK_IcelakeClient: 969 case CK_IcelakeServer: 970 // FIXME: Historically, we defined this legacy name, it would be nice to 971 // remove it at some point. We've never exposed fine-grained names for 972 // recent primary x86 CPUs, and we should keep it that way. 973 defineCPUMacros(Builder, "corei7"); 974 break; 975 case CK_KNL: 976 defineCPUMacros(Builder, "knl"); 977 break; 978 case CK_KNM: 979 break; 980 case CK_Lakemont: 981 defineCPUMacros(Builder, "i586", /*Tuning*/false); 982 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 983 Builder.defineMacro("__tune_lakemont__"); 984 break; 985 case CK_K6_2: 986 Builder.defineMacro("__k6_2__"); 987 Builder.defineMacro("__tune_k6_2__"); 988 LLVM_FALLTHROUGH; 989 case CK_K6_3: 990 if (CPU != CK_K6_2) { // In case of fallthrough 991 // FIXME: GCC may be enabling these in cases where some other k6 992 // architecture is specified but -m3dnow is explicitly provided. The 993 // exact semantics need to be determined and emulated here. 994 Builder.defineMacro("__k6_3__"); 995 Builder.defineMacro("__tune_k6_3__"); 996 } 997 LLVM_FALLTHROUGH; 998 case CK_K6: 999 defineCPUMacros(Builder, "k6"); 1000 break; 1001 case CK_Athlon: 1002 case CK_AthlonXP: 1003 defineCPUMacros(Builder, "athlon"); 1004 if (SSELevel != NoSSE) { 1005 Builder.defineMacro("__athlon_sse__"); 1006 Builder.defineMacro("__tune_athlon_sse__"); 1007 } 1008 break; 1009 case CK_K8: 1010 case CK_K8SSE3: 1011 case CK_x86_64: 1012 defineCPUMacros(Builder, "k8"); 1013 break; 1014 case CK_AMDFAM10: 1015 defineCPUMacros(Builder, "amdfam10"); 1016 break; 1017 case CK_BTVER1: 1018 defineCPUMacros(Builder, "btver1"); 1019 break; 1020 case CK_BTVER2: 1021 defineCPUMacros(Builder, "btver2"); 1022 break; 1023 case CK_BDVER1: 1024 defineCPUMacros(Builder, "bdver1"); 1025 break; 1026 case CK_BDVER2: 1027 defineCPUMacros(Builder, "bdver2"); 1028 break; 1029 case CK_BDVER3: 1030 defineCPUMacros(Builder, "bdver3"); 1031 break; 1032 case CK_BDVER4: 1033 defineCPUMacros(Builder, "bdver4"); 1034 break; 1035 case CK_ZNVER1: 1036 defineCPUMacros(Builder, "znver1"); 1037 break; 1038 case CK_ZNVER2: 1039 defineCPUMacros(Builder, "znver2"); 1040 break; 1041 case CK_Geode: 1042 defineCPUMacros(Builder, "geode"); 1043 break; 1044 } 1045 1046 // Target properties. 1047 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1048 1049 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1050 // functions in glibc header files that use FP Stack inline asm which the 1051 // backend can't deal with (PR879). 1052 Builder.defineMacro("__NO_MATH_INLINES"); 1053 1054 if (HasAES) 1055 Builder.defineMacro("__AES__"); 1056 1057 if (HasVAES) 1058 Builder.defineMacro("__VAES__"); 1059 1060 if (HasPCLMUL) 1061 Builder.defineMacro("__PCLMUL__"); 1062 1063 if (HasVPCLMULQDQ) 1064 Builder.defineMacro("__VPCLMULQDQ__"); 1065 1066 if (HasLZCNT) 1067 Builder.defineMacro("__LZCNT__"); 1068 1069 if (HasRDRND) 1070 Builder.defineMacro("__RDRND__"); 1071 1072 if (HasFSGSBASE) 1073 Builder.defineMacro("__FSGSBASE__"); 1074 1075 if (HasBMI) 1076 Builder.defineMacro("__BMI__"); 1077 1078 if (HasBMI2) 1079 Builder.defineMacro("__BMI2__"); 1080 1081 if (HasPOPCNT) 1082 Builder.defineMacro("__POPCNT__"); 1083 1084 if (HasRTM) 1085 Builder.defineMacro("__RTM__"); 1086 1087 if (HasPRFCHW) 1088 Builder.defineMacro("__PRFCHW__"); 1089 1090 if (HasRDSEED) 1091 Builder.defineMacro("__RDSEED__"); 1092 1093 if (HasADX) 1094 Builder.defineMacro("__ADX__"); 1095 1096 if (HasTBM) 1097 Builder.defineMacro("__TBM__"); 1098 1099 if (HasLWP) 1100 Builder.defineMacro("__LWP__"); 1101 1102 if (HasMWAITX) 1103 Builder.defineMacro("__MWAITX__"); 1104 1105 if (HasMOVBE) 1106 Builder.defineMacro("__MOVBE__"); 1107 1108 switch (XOPLevel) { 1109 case XOP: 1110 Builder.defineMacro("__XOP__"); 1111 LLVM_FALLTHROUGH; 1112 case FMA4: 1113 Builder.defineMacro("__FMA4__"); 1114 LLVM_FALLTHROUGH; 1115 case SSE4A: 1116 Builder.defineMacro("__SSE4A__"); 1117 LLVM_FALLTHROUGH; 1118 case NoXOP: 1119 break; 1120 } 1121 1122 if (HasFMA) 1123 Builder.defineMacro("__FMA__"); 1124 1125 if (HasF16C) 1126 Builder.defineMacro("__F16C__"); 1127 1128 if (HasGFNI) 1129 Builder.defineMacro("__GFNI__"); 1130 1131 if (HasAVX512CD) 1132 Builder.defineMacro("__AVX512CD__"); 1133 if (HasAVX512VPOPCNTDQ) 1134 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1135 if (HasAVX512VNNI) 1136 Builder.defineMacro("__AVX512VNNI__"); 1137 if (HasAVX512ER) 1138 Builder.defineMacro("__AVX512ER__"); 1139 if (HasAVX512PF) 1140 Builder.defineMacro("__AVX512PF__"); 1141 if (HasAVX512DQ) 1142 Builder.defineMacro("__AVX512DQ__"); 1143 if (HasAVX512BITALG) 1144 Builder.defineMacro("__AVX512BITALG__"); 1145 if (HasAVX512BW) 1146 Builder.defineMacro("__AVX512BW__"); 1147 if (HasAVX512VL) 1148 Builder.defineMacro("__AVX512VL__"); 1149 if (HasAVX512VBMI) 1150 Builder.defineMacro("__AVX512VBMI__"); 1151 if (HasAVX512VBMI2) 1152 Builder.defineMacro("__AVX512VBMI2__"); 1153 if (HasAVX512IFMA) 1154 Builder.defineMacro("__AVX512IFMA__"); 1155 1156 if (HasSHA) 1157 Builder.defineMacro("__SHA__"); 1158 1159 if (HasFXSR) 1160 Builder.defineMacro("__FXSR__"); 1161 if (HasXSAVE) 1162 Builder.defineMacro("__XSAVE__"); 1163 if (HasXSAVEOPT) 1164 Builder.defineMacro("__XSAVEOPT__"); 1165 if (HasXSAVEC) 1166 Builder.defineMacro("__XSAVEC__"); 1167 if (HasXSAVES) 1168 Builder.defineMacro("__XSAVES__"); 1169 if (HasPKU) 1170 Builder.defineMacro("__PKU__"); 1171 if (HasCLFLUSHOPT) 1172 Builder.defineMacro("__CLFLUSHOPT__"); 1173 if (HasCLWB) 1174 Builder.defineMacro("__CLWB__"); 1175 if (HasWBNOINVD) 1176 Builder.defineMacro("__WBNOINVD__"); 1177 if (HasMPX) 1178 Builder.defineMacro("__MPX__"); 1179 if (HasSHSTK) 1180 Builder.defineMacro("__SHSTK__"); 1181 if (HasSGX) 1182 Builder.defineMacro("__SGX__"); 1183 if (HasPREFETCHWT1) 1184 Builder.defineMacro("__PREFETCHWT1__"); 1185 if (HasCLZERO) 1186 Builder.defineMacro("__CLZERO__"); 1187 if (HasRDPID) 1188 Builder.defineMacro("__RDPID__"); 1189 if (HasCLDEMOTE) 1190 Builder.defineMacro("__CLDEMOTE__"); 1191 if (HasWAITPKG) 1192 Builder.defineMacro("__WAITPKG__"); 1193 if (HasMOVDIRI) 1194 Builder.defineMacro("__MOVDIRI__"); 1195 if (HasMOVDIR64B) 1196 Builder.defineMacro("__MOVDIR64B__"); 1197 if (HasPCONFIG) 1198 Builder.defineMacro("__PCONFIG__"); 1199 if (HasPTWRITE) 1200 Builder.defineMacro("__PTWRITE__"); 1201 if (HasINVPCID) 1202 Builder.defineMacro("__INVPCID__"); 1203 1204 // Each case falls through to the previous one here. 1205 switch (SSELevel) { 1206 case AVX512F: 1207 Builder.defineMacro("__AVX512F__"); 1208 LLVM_FALLTHROUGH; 1209 case AVX2: 1210 Builder.defineMacro("__AVX2__"); 1211 LLVM_FALLTHROUGH; 1212 case AVX: 1213 Builder.defineMacro("__AVX__"); 1214 LLVM_FALLTHROUGH; 1215 case SSE42: 1216 Builder.defineMacro("__SSE4_2__"); 1217 LLVM_FALLTHROUGH; 1218 case SSE41: 1219 Builder.defineMacro("__SSE4_1__"); 1220 LLVM_FALLTHROUGH; 1221 case SSSE3: 1222 Builder.defineMacro("__SSSE3__"); 1223 LLVM_FALLTHROUGH; 1224 case SSE3: 1225 Builder.defineMacro("__SSE3__"); 1226 LLVM_FALLTHROUGH; 1227 case SSE2: 1228 Builder.defineMacro("__SSE2__"); 1229 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1230 LLVM_FALLTHROUGH; 1231 case SSE1: 1232 Builder.defineMacro("__SSE__"); 1233 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1234 LLVM_FALLTHROUGH; 1235 case NoSSE: 1236 break; 1237 } 1238 1239 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1240 switch (SSELevel) { 1241 case AVX512F: 1242 case AVX2: 1243 case AVX: 1244 case SSE42: 1245 case SSE41: 1246 case SSSE3: 1247 case SSE3: 1248 case SSE2: 1249 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1250 break; 1251 case SSE1: 1252 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1253 break; 1254 default: 1255 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1256 break; 1257 } 1258 } 1259 1260 // Each case falls through to the previous one here. 1261 switch (MMX3DNowLevel) { 1262 case AMD3DNowAthlon: 1263 Builder.defineMacro("__3dNOW_A__"); 1264 LLVM_FALLTHROUGH; 1265 case AMD3DNow: 1266 Builder.defineMacro("__3dNOW__"); 1267 LLVM_FALLTHROUGH; 1268 case MMX: 1269 Builder.defineMacro("__MMX__"); 1270 LLVM_FALLTHROUGH; 1271 case NoMMX3DNow: 1272 break; 1273 } 1274 1275 if (CPU >= CK_i486) { 1276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1279 } 1280 if (CPU >= CK_i586) 1281 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1282 if (HasCX16) 1283 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1284 1285 if (HasFloat128) 1286 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1287 } 1288 1289 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1290 return llvm::StringSwitch<bool>(Name) 1291 .Case("3dnow", true) 1292 .Case("3dnowa", true) 1293 .Case("adx", true) 1294 .Case("aes", true) 1295 .Case("avx", true) 1296 .Case("avx2", true) 1297 .Case("avx512f", true) 1298 .Case("avx512cd", true) 1299 .Case("avx512vpopcntdq", true) 1300 .Case("avx512vnni", true) 1301 .Case("avx512er", true) 1302 .Case("avx512pf", true) 1303 .Case("avx512dq", true) 1304 .Case("avx512bitalg", true) 1305 .Case("avx512bw", true) 1306 .Case("avx512vl", true) 1307 .Case("avx512vbmi", true) 1308 .Case("avx512vbmi2", true) 1309 .Case("avx512ifma", true) 1310 .Case("bmi", true) 1311 .Case("bmi2", true) 1312 .Case("cldemote", true) 1313 .Case("clflushopt", true) 1314 .Case("clwb", true) 1315 .Case("clzero", true) 1316 .Case("cx16", true) 1317 .Case("f16c", true) 1318 .Case("fma", true) 1319 .Case("fma4", true) 1320 .Case("fsgsbase", true) 1321 .Case("fxsr", true) 1322 .Case("gfni", true) 1323 .Case("invpcid", true) 1324 .Case("lwp", true) 1325 .Case("lzcnt", true) 1326 .Case("mmx", true) 1327 .Case("movbe", true) 1328 .Case("movdiri", true) 1329 .Case("movdir64b", true) 1330 .Case("mpx", true) 1331 .Case("mwaitx", true) 1332 .Case("pclmul", true) 1333 .Case("pconfig", true) 1334 .Case("pku", true) 1335 .Case("popcnt", true) 1336 .Case("prefetchwt1", true) 1337 .Case("prfchw", true) 1338 .Case("ptwrite", true) 1339 .Case("rdpid", true) 1340 .Case("rdrnd", true) 1341 .Case("rdseed", true) 1342 .Case("rtm", true) 1343 .Case("sahf", true) 1344 .Case("sgx", true) 1345 .Case("sha", true) 1346 .Case("shstk", true) 1347 .Case("sse", true) 1348 .Case("sse2", true) 1349 .Case("sse3", true) 1350 .Case("ssse3", true) 1351 .Case("sse4", true) 1352 .Case("sse4.1", true) 1353 .Case("sse4.2", true) 1354 .Case("sse4a", true) 1355 .Case("tbm", true) 1356 .Case("vaes", true) 1357 .Case("vpclmulqdq", true) 1358 .Case("wbnoinvd", true) 1359 .Case("waitpkg", true) 1360 .Case("x87", true) 1361 .Case("xop", true) 1362 .Case("xsave", true) 1363 .Case("xsavec", true) 1364 .Case("xsaves", true) 1365 .Case("xsaveopt", true) 1366 .Default(false); 1367 } 1368 1369 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1370 return llvm::StringSwitch<bool>(Feature) 1371 .Case("adx", HasADX) 1372 .Case("aes", HasAES) 1373 .Case("avx", SSELevel >= AVX) 1374 .Case("avx2", SSELevel >= AVX2) 1375 .Case("avx512f", SSELevel >= AVX512F) 1376 .Case("avx512cd", HasAVX512CD) 1377 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1378 .Case("avx512vnni", HasAVX512VNNI) 1379 .Case("avx512er", HasAVX512ER) 1380 .Case("avx512pf", HasAVX512PF) 1381 .Case("avx512dq", HasAVX512DQ) 1382 .Case("avx512bitalg", HasAVX512BITALG) 1383 .Case("avx512bw", HasAVX512BW) 1384 .Case("avx512vl", HasAVX512VL) 1385 .Case("avx512vbmi", HasAVX512VBMI) 1386 .Case("avx512vbmi2", HasAVX512VBMI2) 1387 .Case("avx512ifma", HasAVX512IFMA) 1388 .Case("bmi", HasBMI) 1389 .Case("bmi2", HasBMI2) 1390 .Case("cldemote", HasCLDEMOTE) 1391 .Case("clflushopt", HasCLFLUSHOPT) 1392 .Case("clwb", HasCLWB) 1393 .Case("clzero", HasCLZERO) 1394 .Case("cx16", HasCX16) 1395 .Case("f16c", HasF16C) 1396 .Case("fma", HasFMA) 1397 .Case("fma4", XOPLevel >= FMA4) 1398 .Case("fsgsbase", HasFSGSBASE) 1399 .Case("fxsr", HasFXSR) 1400 .Case("gfni", HasGFNI) 1401 .Case("invpcid", HasINVPCID) 1402 .Case("lwp", HasLWP) 1403 .Case("lzcnt", HasLZCNT) 1404 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1405 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1406 .Case("mmx", MMX3DNowLevel >= MMX) 1407 .Case("movbe", HasMOVBE) 1408 .Case("movdiri", HasMOVDIRI) 1409 .Case("movdir64b", HasMOVDIR64B) 1410 .Case("mpx", HasMPX) 1411 .Case("mwaitx", HasMWAITX) 1412 .Case("pclmul", HasPCLMUL) 1413 .Case("pconfig", HasPCONFIG) 1414 .Case("pku", HasPKU) 1415 .Case("popcnt", HasPOPCNT) 1416 .Case("prefetchwt1", HasPREFETCHWT1) 1417 .Case("prfchw", HasPRFCHW) 1418 .Case("ptwrite", HasPTWRITE) 1419 .Case("rdpid", HasRDPID) 1420 .Case("rdrnd", HasRDRND) 1421 .Case("rdseed", HasRDSEED) 1422 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1423 .Case("rtm", HasRTM) 1424 .Case("sahf", HasLAHFSAHF) 1425 .Case("sgx", HasSGX) 1426 .Case("sha", HasSHA) 1427 .Case("shstk", HasSHSTK) 1428 .Case("sse", SSELevel >= SSE1) 1429 .Case("sse2", SSELevel >= SSE2) 1430 .Case("sse3", SSELevel >= SSE3) 1431 .Case("ssse3", SSELevel >= SSSE3) 1432 .Case("sse4.1", SSELevel >= SSE41) 1433 .Case("sse4.2", SSELevel >= SSE42) 1434 .Case("sse4a", XOPLevel >= SSE4A) 1435 .Case("tbm", HasTBM) 1436 .Case("vaes", HasVAES) 1437 .Case("vpclmulqdq", HasVPCLMULQDQ) 1438 .Case("wbnoinvd", HasWBNOINVD) 1439 .Case("waitpkg", HasWAITPKG) 1440 .Case("x86", true) 1441 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1442 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1443 .Case("xop", XOPLevel >= XOP) 1444 .Case("xsave", HasXSAVE) 1445 .Case("xsavec", HasXSAVEC) 1446 .Case("xsaves", HasXSAVES) 1447 .Case("xsaveopt", HasXSAVEOPT) 1448 .Default(false); 1449 } 1450 1451 // We can't use a generic validation scheme for the features accepted here 1452 // versus subtarget features accepted in the target attribute because the 1453 // bitfield structure that's initialized in the runtime only supports the 1454 // below currently rather than the full range of subtarget features. (See 1455 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1456 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1457 return llvm::StringSwitch<bool>(FeatureStr) 1458 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1459 #include "llvm/Support/X86TargetParser.def" 1460 .Default(false); 1461 } 1462 1463 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1464 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1465 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1466 #include "llvm/Support/X86TargetParser.def" 1467 ; 1468 // Note, this function should only be used after ensuring the value is 1469 // correct, so it asserts if the value is out of range. 1470 } 1471 1472 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1473 enum class FeatPriority { 1474 #define FEATURE(FEAT) FEAT, 1475 #include "clang/Basic/X86Target.def" 1476 }; 1477 switch (Feat) { 1478 #define FEATURE(FEAT) \ 1479 case llvm::X86::FEAT: \ 1480 return static_cast<unsigned>(FeatPriority::FEAT); 1481 #include "clang/Basic/X86Target.def" 1482 default: 1483 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1484 } 1485 } 1486 1487 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1488 // Valid CPUs have a 'key feature' that compares just better than its key 1489 // feature. 1490 CPUKind Kind = getCPUKind(Name); 1491 if (Kind != CK_Generic) { 1492 switch (Kind) { 1493 default: 1494 llvm_unreachable( 1495 "CPU Type without a key feature used in 'target' attribute"); 1496 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1497 case CK_##ENUM: \ 1498 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1499 #include "clang/Basic/X86Target.def" 1500 } 1501 } 1502 1503 // Now we know we have a feature, so get its priority and shift it a few so 1504 // that we have sufficient room for the CPUs (above). 1505 return getFeaturePriority(getFeature(Name)) << 1; 1506 } 1507 1508 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1509 return llvm::StringSwitch<bool>(Name) 1510 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1511 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1512 #include "clang/Basic/X86Target.def" 1513 .Default(false); 1514 } 1515 1516 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1517 return llvm::StringSwitch<StringRef>(Name) 1518 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1519 #include "clang/Basic/X86Target.def" 1520 .Default(Name); 1521 } 1522 1523 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1524 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1525 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1526 #include "clang/Basic/X86Target.def" 1527 .Default(0); 1528 } 1529 1530 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1531 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1532 StringRef WholeList = 1533 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1534 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1535 #include "clang/Basic/X86Target.def" 1536 .Default(""); 1537 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1538 } 1539 1540 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1541 switch (Kind) { 1542 case CK_Generic: 1543 return ""; 1544 #define PROC(ENUM, STRING, IS64BIT) \ 1545 case CK_##ENUM: \ 1546 return STRING; 1547 #include "clang/Basic/X86Target.def" 1548 } 1549 llvm_unreachable("Invalid CPUKind"); 1550 } 1551 1552 // We can't use a generic validation scheme for the cpus accepted here 1553 // versus subtarget cpus accepted in the target attribute because the 1554 // variables intitialized by the runtime only support the below currently 1555 // rather than the full range of cpus. 1556 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1557 return llvm::StringSwitch<bool>(FeatureStr) 1558 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1559 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1560 .Cases(STR, ALIAS, true) 1561 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1562 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1563 #include "llvm/Support/X86TargetParser.def" 1564 .Default(false); 1565 } 1566 1567 static unsigned matchAsmCCConstraint(const char *&Name) { 1568 auto RV = llvm::StringSwitch<unsigned>(Name) 1569 .Case("@cca", 4) 1570 .Case("@ccae", 5) 1571 .Case("@ccb", 4) 1572 .Case("@ccbe", 5) 1573 .Case("@ccc", 4) 1574 .Case("@cce", 4) 1575 .Case("@ccz", 4) 1576 .Case("@ccg", 4) 1577 .Case("@ccge", 5) 1578 .Case("@ccl", 4) 1579 .Case("@ccle", 5) 1580 .Case("@ccna", 5) 1581 .Case("@ccnae", 6) 1582 .Case("@ccnb", 5) 1583 .Case("@ccnbe", 6) 1584 .Case("@ccnc", 5) 1585 .Case("@ccne", 5) 1586 .Case("@ccnz", 5) 1587 .Case("@ccng", 5) 1588 .Case("@ccnge", 6) 1589 .Case("@ccnl", 5) 1590 .Case("@ccnle", 6) 1591 .Case("@ccno", 5) 1592 .Case("@ccnp", 5) 1593 .Case("@ccns", 5) 1594 .Case("@cco", 4) 1595 .Case("@ccp", 4) 1596 .Case("@ccs", 4) 1597 .Default(0); 1598 return RV; 1599 } 1600 1601 bool X86TargetInfo::validateAsmConstraint( 1602 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1603 switch (*Name) { 1604 default: 1605 return false; 1606 // Constant constraints. 1607 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1608 // instructions. 1609 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1610 // x86_64 instructions. 1611 case 's': 1612 Info.setRequiresImmediate(); 1613 return true; 1614 case 'I': 1615 Info.setRequiresImmediate(0, 31); 1616 return true; 1617 case 'J': 1618 Info.setRequiresImmediate(0, 63); 1619 return true; 1620 case 'K': 1621 Info.setRequiresImmediate(-128, 127); 1622 return true; 1623 case 'L': 1624 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1625 return true; 1626 case 'M': 1627 Info.setRequiresImmediate(0, 3); 1628 return true; 1629 case 'N': 1630 Info.setRequiresImmediate(0, 255); 1631 return true; 1632 case 'O': 1633 Info.setRequiresImmediate(0, 127); 1634 return true; 1635 // Register constraints. 1636 case 'Y': // 'Y' is the first character for several 2-character constraints. 1637 // Shift the pointer to the second character of the constraint. 1638 Name++; 1639 switch (*Name) { 1640 default: 1641 return false; 1642 case 'z': 1643 case '0': // First SSE register. 1644 case '2': 1645 case 't': // Any SSE register, when SSE2 is enabled. 1646 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1647 case 'm': // Any MMX register, when inter-unit moves enabled. 1648 case 'k': // AVX512 arch mask registers: k1-k7. 1649 Info.setAllowsRegister(); 1650 return true; 1651 } 1652 case 'f': // Any x87 floating point stack register. 1653 // Constraint 'f' cannot be used for output operands. 1654 if (Info.ConstraintStr[0] == '=') 1655 return false; 1656 Info.setAllowsRegister(); 1657 return true; 1658 case 'a': // eax. 1659 case 'b': // ebx. 1660 case 'c': // ecx. 1661 case 'd': // edx. 1662 case 'S': // esi. 1663 case 'D': // edi. 1664 case 'A': // edx:eax. 1665 case 't': // Top of floating point stack. 1666 case 'u': // Second from top of floating point stack. 1667 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1668 case 'y': // Any MMX register. 1669 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1670 case 'x': // Any SSE register. 1671 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1672 // for intermideate k reg operations). 1673 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1674 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1675 case 'l': // "Index" registers: any general register that can be used as an 1676 // index in a base+index memory access. 1677 Info.setAllowsRegister(); 1678 return true; 1679 // Floating point constant constraints. 1680 case 'C': // SSE floating point constant. 1681 case 'G': // x87 floating point constant. 1682 return true; 1683 case '@': 1684 // CC condition changes. 1685 if (auto Len = matchAsmCCConstraint(Name)) { 1686 Name += Len - 1; 1687 Info.setAllowsRegister(); 1688 return true; 1689 } 1690 return false; 1691 } 1692 } 1693 1694 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1695 unsigned Size) const { 1696 // Strip off constraint modifiers. 1697 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1698 Constraint = Constraint.substr(1); 1699 1700 return validateOperandSize(Constraint, Size); 1701 } 1702 1703 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1704 unsigned Size) const { 1705 return validateOperandSize(Constraint, Size); 1706 } 1707 1708 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1709 unsigned Size) const { 1710 switch (Constraint[0]) { 1711 default: 1712 break; 1713 case 'k': 1714 // Registers k0-k7 (AVX512) size limit is 64 bit. 1715 case 'y': 1716 return Size <= 64; 1717 case 'f': 1718 case 't': 1719 case 'u': 1720 return Size <= 128; 1721 case 'Y': 1722 // 'Y' is the first character for several 2-character constraints. 1723 switch (Constraint[1]) { 1724 default: 1725 return false; 1726 case 'm': 1727 // 'Ym' is synonymous with 'y'. 1728 case 'k': 1729 return Size <= 64; 1730 case 'z': 1731 case '0': 1732 // XMM0 1733 if (SSELevel >= SSE1) 1734 return Size <= 128U; 1735 return false; 1736 case 'i': 1737 case 't': 1738 case '2': 1739 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1740 if (SSELevel < SSE2) 1741 return false; 1742 break; 1743 } 1744 LLVM_FALLTHROUGH; 1745 case 'v': 1746 case 'x': 1747 if (SSELevel >= AVX512F) 1748 // 512-bit zmm registers can be used if target supports AVX512F. 1749 return Size <= 512U; 1750 else if (SSELevel >= AVX) 1751 // 256-bit ymm registers can be used if target supports AVX. 1752 return Size <= 256U; 1753 return Size <= 128U; 1754 1755 } 1756 1757 return true; 1758 } 1759 1760 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1761 switch (*Constraint) { 1762 case '@': 1763 if (auto Len = matchAsmCCConstraint(Constraint)) { 1764 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1765 Constraint += Len - 1; 1766 return Converted; 1767 } 1768 return std::string(1, *Constraint); 1769 case 'a': 1770 return std::string("{ax}"); 1771 case 'b': 1772 return std::string("{bx}"); 1773 case 'c': 1774 return std::string("{cx}"); 1775 case 'd': 1776 return std::string("{dx}"); 1777 case 'S': 1778 return std::string("{si}"); 1779 case 'D': 1780 return std::string("{di}"); 1781 case 'p': // address 1782 return std::string("im"); 1783 case 't': // top of floating point stack. 1784 return std::string("{st}"); 1785 case 'u': // second from top of floating point stack. 1786 return std::string("{st(1)}"); // second from top of floating point stack. 1787 case 'Y': 1788 switch (Constraint[1]) { 1789 default: 1790 // Break from inner switch and fall through (copy single char), 1791 // continue parsing after copying the current constraint into 1792 // the return string. 1793 break; 1794 case 'k': 1795 case 'm': 1796 case 'i': 1797 case 't': 1798 case 'z': 1799 case '0': 1800 case '2': 1801 // "^" hints llvm that this is a 2 letter constraint. 1802 // "Constraint++" is used to promote the string iterator 1803 // to the next constraint. 1804 return std::string("^") + std::string(Constraint++, 2); 1805 } 1806 LLVM_FALLTHROUGH; 1807 default: 1808 return std::string(1, *Constraint); 1809 } 1810 } 1811 1812 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1813 // Perform any per-CPU checks necessary to determine if this CPU is 1814 // acceptable. 1815 switch (Kind) { 1816 case CK_Generic: 1817 // No processor selected! 1818 return false; 1819 #define PROC(ENUM, STRING, IS64BIT) \ 1820 case CK_##ENUM: \ 1821 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1822 #include "clang/Basic/X86Target.def" 1823 } 1824 llvm_unreachable("Unhandled CPU kind"); 1825 } 1826 1827 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1828 #define PROC(ENUM, STRING, IS64BIT) \ 1829 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1830 Values.emplace_back(STRING); 1831 // Go through CPUKind checking to ensure that the alias is de-aliased and 1832 // 64 bit-ness is checked. 1833 #define PROC_ALIAS(ENUM, ALIAS) \ 1834 if (checkCPUKind(getCPUKind(ALIAS))) \ 1835 Values.emplace_back(ALIAS); 1836 #include "clang/Basic/X86Target.def" 1837 } 1838 1839 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1840 return llvm::StringSwitch<CPUKind>(CPU) 1841 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1842 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1843 #include "clang/Basic/X86Target.def" 1844 .Default(CK_Generic); 1845 } 1846 1847 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1848 return llvm::makeArrayRef(GCCRegNames); 1849 } 1850 1851 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1852 return llvm::makeArrayRef(AddlRegNames); 1853 } 1854 1855 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1856 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1857 Builtin::FirstTSBuiltin + 1); 1858 } 1859 1860 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1861 return llvm::makeArrayRef(BuiltinInfoX86, 1862 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1863 } 1864