1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end()) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end()) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end()) 156 Features["xsave"] = true; 157 158 return true; 159 } 160 161 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 162 StringRef Name, bool Enabled) const { 163 if (Name == "sse4") { 164 // We can get here via the __target__ attribute since that's not controlled 165 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 166 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 167 // disabled. 168 if (Enabled) 169 Name = "sse4.2"; 170 else 171 Name = "sse4.1"; 172 } 173 174 Features[Name] = Enabled; 175 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 176 } 177 178 /// handleTargetFeatures - Perform initialization based on the user 179 /// configured set of features. 180 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 181 DiagnosticsEngine &Diags) { 182 for (const auto &Feature : Features) { 183 if (Feature[0] != '+') 184 continue; 185 186 if (Feature == "+aes") { 187 HasAES = true; 188 } else if (Feature == "+vaes") { 189 HasVAES = true; 190 } else if (Feature == "+pclmul") { 191 HasPCLMUL = true; 192 } else if (Feature == "+vpclmulqdq") { 193 HasVPCLMULQDQ = true; 194 } else if (Feature == "+lzcnt") { 195 HasLZCNT = true; 196 } else if (Feature == "+rdrnd") { 197 HasRDRND = true; 198 } else if (Feature == "+fsgsbase") { 199 HasFSGSBASE = true; 200 } else if (Feature == "+bmi") { 201 HasBMI = true; 202 } else if (Feature == "+bmi2") { 203 HasBMI2 = true; 204 } else if (Feature == "+popcnt") { 205 HasPOPCNT = true; 206 } else if (Feature == "+rtm") { 207 HasRTM = true; 208 } else if (Feature == "+prfchw") { 209 HasPRFCHW = true; 210 } else if (Feature == "+rdseed") { 211 HasRDSEED = true; 212 } else if (Feature == "+adx") { 213 HasADX = true; 214 } else if (Feature == "+tbm") { 215 HasTBM = true; 216 } else if (Feature == "+lwp") { 217 HasLWP = true; 218 } else if (Feature == "+fma") { 219 HasFMA = true; 220 } else if (Feature == "+f16c") { 221 HasF16C = true; 222 } else if (Feature == "+gfni") { 223 HasGFNI = true; 224 } else if (Feature == "+avx512cd") { 225 HasAVX512CD = true; 226 } else if (Feature == "+avx512vpopcntdq") { 227 HasAVX512VPOPCNTDQ = true; 228 } else if (Feature == "+avx512vnni") { 229 HasAVX512VNNI = true; 230 } else if (Feature == "+avx512bf16") { 231 HasAVX512BF16 = true; 232 } else if (Feature == "+avx512er") { 233 HasAVX512ER = true; 234 } else if (Feature == "+avx512fp16") { 235 HasAVX512FP16 = true; 236 HasFloat16 = true; 237 } else if (Feature == "+avx512pf") { 238 HasAVX512PF = true; 239 } else if (Feature == "+avx512dq") { 240 HasAVX512DQ = true; 241 } else if (Feature == "+avx512bitalg") { 242 HasAVX512BITALG = true; 243 } else if (Feature == "+avx512bw") { 244 HasAVX512BW = true; 245 } else if (Feature == "+avx512vl") { 246 HasAVX512VL = true; 247 } else if (Feature == "+avx512vbmi") { 248 HasAVX512VBMI = true; 249 } else if (Feature == "+avx512vbmi2") { 250 HasAVX512VBMI2 = true; 251 } else if (Feature == "+avx512ifma") { 252 HasAVX512IFMA = true; 253 } else if (Feature == "+avx512vp2intersect") { 254 HasAVX512VP2INTERSECT = true; 255 } else if (Feature == "+sha") { 256 HasSHA = true; 257 } else if (Feature == "+shstk") { 258 HasSHSTK = true; 259 } else if (Feature == "+movbe") { 260 HasMOVBE = true; 261 } else if (Feature == "+sgx") { 262 HasSGX = true; 263 } else if (Feature == "+cx8") { 264 HasCX8 = true; 265 } else if (Feature == "+cx16") { 266 HasCX16 = true; 267 } else if (Feature == "+fxsr") { 268 HasFXSR = true; 269 } else if (Feature == "+xsave") { 270 HasXSAVE = true; 271 } else if (Feature == "+xsaveopt") { 272 HasXSAVEOPT = true; 273 } else if (Feature == "+xsavec") { 274 HasXSAVEC = true; 275 } else if (Feature == "+xsaves") { 276 HasXSAVES = true; 277 } else if (Feature == "+mwaitx") { 278 HasMWAITX = true; 279 } else if (Feature == "+pku") { 280 HasPKU = true; 281 } else if (Feature == "+clflushopt") { 282 HasCLFLUSHOPT = true; 283 } else if (Feature == "+clwb") { 284 HasCLWB = true; 285 } else if (Feature == "+wbnoinvd") { 286 HasWBNOINVD = true; 287 } else if (Feature == "+prefetchwt1") { 288 HasPREFETCHWT1 = true; 289 } else if (Feature == "+clzero") { 290 HasCLZERO = true; 291 } else if (Feature == "+cldemote") { 292 HasCLDEMOTE = true; 293 } else if (Feature == "+rdpid") { 294 HasRDPID = true; 295 } else if (Feature == "+kl") { 296 HasKL = true; 297 } else if (Feature == "+widekl") { 298 HasWIDEKL = true; 299 } else if (Feature == "+retpoline-external-thunk") { 300 HasRetpolineExternalThunk = true; 301 } else if (Feature == "+sahf") { 302 HasLAHFSAHF = true; 303 } else if (Feature == "+waitpkg") { 304 HasWAITPKG = true; 305 } else if (Feature == "+movdiri") { 306 HasMOVDIRI = true; 307 } else if (Feature == "+movdir64b") { 308 HasMOVDIR64B = true; 309 } else if (Feature == "+pconfig") { 310 HasPCONFIG = true; 311 } else if (Feature == "+ptwrite") { 312 HasPTWRITE = true; 313 } else if (Feature == "+invpcid") { 314 HasINVPCID = true; 315 } else if (Feature == "+enqcmd") { 316 HasENQCMD = true; 317 } else if (Feature == "+hreset") { 318 HasHRESET = true; 319 } else if (Feature == "+amx-bf16") { 320 HasAMXBF16 = true; 321 } else if (Feature == "+amx-int8") { 322 HasAMXINT8 = true; 323 } else if (Feature == "+amx-tile") { 324 HasAMXTILE = true; 325 } else if (Feature == "+avxvnni") { 326 HasAVXVNNI = true; 327 } else if (Feature == "+serialize") { 328 HasSERIALIZE = true; 329 } else if (Feature == "+tsxldtrk") { 330 HasTSXLDTRK = true; 331 } else if (Feature == "+uintr") { 332 HasUINTR = true; 333 } 334 335 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 336 .Case("+avx512f", AVX512F) 337 .Case("+avx2", AVX2) 338 .Case("+avx", AVX) 339 .Case("+sse4.2", SSE42) 340 .Case("+sse4.1", SSE41) 341 .Case("+ssse3", SSSE3) 342 .Case("+sse3", SSE3) 343 .Case("+sse2", SSE2) 344 .Case("+sse", SSE1) 345 .Default(NoSSE); 346 SSELevel = std::max(SSELevel, Level); 347 348 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 349 .Case("+3dnowa", AMD3DNowAthlon) 350 .Case("+3dnow", AMD3DNow) 351 .Case("+mmx", MMX) 352 .Default(NoMMX3DNow); 353 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 354 355 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 356 .Case("+xop", XOP) 357 .Case("+fma4", FMA4) 358 .Case("+sse4a", SSE4A) 359 .Default(NoXOP); 360 XOPLevel = std::max(XOPLevel, XLevel); 361 } 362 363 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 364 // matches the selected sse level. 365 if ((FPMath == FP_SSE && SSELevel < SSE1) || 366 (FPMath == FP_387 && SSELevel >= SSE1)) { 367 Diags.Report(diag::err_target_unsupported_fpmath) 368 << (FPMath == FP_SSE ? "sse" : "387"); 369 return false; 370 } 371 372 SimdDefaultAlign = 373 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 374 return true; 375 } 376 377 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 378 /// definitions for this particular subtarget. 379 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 380 MacroBuilder &Builder) const { 381 // Inline assembly supports X86 flag outputs. 382 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 383 384 std::string CodeModel = getTargetOpts().CodeModel; 385 if (CodeModel == "default") 386 CodeModel = "small"; 387 Builder.defineMacro("__code_model_" + CodeModel + "__"); 388 389 // Target identification. 390 if (getTriple().getArch() == llvm::Triple::x86_64) { 391 Builder.defineMacro("__amd64__"); 392 Builder.defineMacro("__amd64"); 393 Builder.defineMacro("__x86_64"); 394 Builder.defineMacro("__x86_64__"); 395 if (getTriple().getArchName() == "x86_64h") { 396 Builder.defineMacro("__x86_64h"); 397 Builder.defineMacro("__x86_64h__"); 398 } 399 } else { 400 DefineStd(Builder, "i386", Opts); 401 } 402 403 Builder.defineMacro("__SEG_GS"); 404 Builder.defineMacro("__SEG_FS"); 405 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 406 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 407 408 // Subtarget options. 409 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 410 // truly should be based on -mtune options. 411 using namespace llvm::X86; 412 switch (CPU) { 413 case CK_None: 414 break; 415 case CK_i386: 416 // The rest are coming from the i386 define above. 417 Builder.defineMacro("__tune_i386__"); 418 break; 419 case CK_i486: 420 case CK_WinChipC6: 421 case CK_WinChip2: 422 case CK_C3: 423 defineCPUMacros(Builder, "i486"); 424 break; 425 case CK_PentiumMMX: 426 Builder.defineMacro("__pentium_mmx__"); 427 Builder.defineMacro("__tune_pentium_mmx__"); 428 LLVM_FALLTHROUGH; 429 case CK_i586: 430 case CK_Pentium: 431 defineCPUMacros(Builder, "i586"); 432 defineCPUMacros(Builder, "pentium"); 433 break; 434 case CK_Pentium3: 435 case CK_PentiumM: 436 Builder.defineMacro("__tune_pentium3__"); 437 LLVM_FALLTHROUGH; 438 case CK_Pentium2: 439 case CK_C3_2: 440 Builder.defineMacro("__tune_pentium2__"); 441 LLVM_FALLTHROUGH; 442 case CK_PentiumPro: 443 case CK_i686: 444 defineCPUMacros(Builder, "i686"); 445 defineCPUMacros(Builder, "pentiumpro"); 446 break; 447 case CK_Pentium4: 448 defineCPUMacros(Builder, "pentium4"); 449 break; 450 case CK_Yonah: 451 case CK_Prescott: 452 case CK_Nocona: 453 defineCPUMacros(Builder, "nocona"); 454 break; 455 case CK_Core2: 456 case CK_Penryn: 457 defineCPUMacros(Builder, "core2"); 458 break; 459 case CK_Bonnell: 460 defineCPUMacros(Builder, "atom"); 461 break; 462 case CK_Silvermont: 463 defineCPUMacros(Builder, "slm"); 464 break; 465 case CK_Goldmont: 466 defineCPUMacros(Builder, "goldmont"); 467 break; 468 case CK_GoldmontPlus: 469 defineCPUMacros(Builder, "goldmont_plus"); 470 break; 471 case CK_Tremont: 472 defineCPUMacros(Builder, "tremont"); 473 break; 474 case CK_Nehalem: 475 case CK_Westmere: 476 case CK_SandyBridge: 477 case CK_IvyBridge: 478 case CK_Haswell: 479 case CK_Broadwell: 480 case CK_SkylakeClient: 481 case CK_SkylakeServer: 482 case CK_Cascadelake: 483 case CK_Cooperlake: 484 case CK_Cannonlake: 485 case CK_IcelakeClient: 486 case CK_Rocketlake: 487 case CK_IcelakeServer: 488 case CK_Tigerlake: 489 case CK_SapphireRapids: 490 case CK_Alderlake: 491 // FIXME: Historically, we defined this legacy name, it would be nice to 492 // remove it at some point. We've never exposed fine-grained names for 493 // recent primary x86 CPUs, and we should keep it that way. 494 defineCPUMacros(Builder, "corei7"); 495 break; 496 case CK_KNL: 497 defineCPUMacros(Builder, "knl"); 498 break; 499 case CK_KNM: 500 break; 501 case CK_Lakemont: 502 defineCPUMacros(Builder, "i586", /*Tuning*/false); 503 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 504 Builder.defineMacro("__tune_lakemont__"); 505 break; 506 case CK_K6_2: 507 Builder.defineMacro("__k6_2__"); 508 Builder.defineMacro("__tune_k6_2__"); 509 LLVM_FALLTHROUGH; 510 case CK_K6_3: 511 if (CPU != CK_K6_2) { // In case of fallthrough 512 // FIXME: GCC may be enabling these in cases where some other k6 513 // architecture is specified but -m3dnow is explicitly provided. The 514 // exact semantics need to be determined and emulated here. 515 Builder.defineMacro("__k6_3__"); 516 Builder.defineMacro("__tune_k6_3__"); 517 } 518 LLVM_FALLTHROUGH; 519 case CK_K6: 520 defineCPUMacros(Builder, "k6"); 521 break; 522 case CK_Athlon: 523 case CK_AthlonXP: 524 defineCPUMacros(Builder, "athlon"); 525 if (SSELevel != NoSSE) { 526 Builder.defineMacro("__athlon_sse__"); 527 Builder.defineMacro("__tune_athlon_sse__"); 528 } 529 break; 530 case CK_K8: 531 case CK_K8SSE3: 532 case CK_x86_64: 533 defineCPUMacros(Builder, "k8"); 534 break; 535 case CK_x86_64_v2: 536 case CK_x86_64_v3: 537 case CK_x86_64_v4: 538 break; 539 case CK_AMDFAM10: 540 defineCPUMacros(Builder, "amdfam10"); 541 break; 542 case CK_BTVER1: 543 defineCPUMacros(Builder, "btver1"); 544 break; 545 case CK_BTVER2: 546 defineCPUMacros(Builder, "btver2"); 547 break; 548 case CK_BDVER1: 549 defineCPUMacros(Builder, "bdver1"); 550 break; 551 case CK_BDVER2: 552 defineCPUMacros(Builder, "bdver2"); 553 break; 554 case CK_BDVER3: 555 defineCPUMacros(Builder, "bdver3"); 556 break; 557 case CK_BDVER4: 558 defineCPUMacros(Builder, "bdver4"); 559 break; 560 case CK_ZNVER1: 561 defineCPUMacros(Builder, "znver1"); 562 break; 563 case CK_ZNVER2: 564 defineCPUMacros(Builder, "znver2"); 565 break; 566 case CK_ZNVER3: 567 defineCPUMacros(Builder, "znver3"); 568 break; 569 case CK_Geode: 570 defineCPUMacros(Builder, "geode"); 571 break; 572 } 573 574 // Target properties. 575 Builder.defineMacro("__REGISTER_PREFIX__", ""); 576 577 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 578 // functions in glibc header files that use FP Stack inline asm which the 579 // backend can't deal with (PR879). 580 Builder.defineMacro("__NO_MATH_INLINES"); 581 582 if (HasAES) 583 Builder.defineMacro("__AES__"); 584 585 if (HasVAES) 586 Builder.defineMacro("__VAES__"); 587 588 if (HasPCLMUL) 589 Builder.defineMacro("__PCLMUL__"); 590 591 if (HasVPCLMULQDQ) 592 Builder.defineMacro("__VPCLMULQDQ__"); 593 594 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 595 // the feature flag only applies to 64-bit mode. 596 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 597 Builder.defineMacro("__LAHF_SAHF__"); 598 599 if (HasLZCNT) 600 Builder.defineMacro("__LZCNT__"); 601 602 if (HasRDRND) 603 Builder.defineMacro("__RDRND__"); 604 605 if (HasFSGSBASE) 606 Builder.defineMacro("__FSGSBASE__"); 607 608 if (HasBMI) 609 Builder.defineMacro("__BMI__"); 610 611 if (HasBMI2) 612 Builder.defineMacro("__BMI2__"); 613 614 if (HasPOPCNT) 615 Builder.defineMacro("__POPCNT__"); 616 617 if (HasRTM) 618 Builder.defineMacro("__RTM__"); 619 620 if (HasPRFCHW) 621 Builder.defineMacro("__PRFCHW__"); 622 623 if (HasRDSEED) 624 Builder.defineMacro("__RDSEED__"); 625 626 if (HasADX) 627 Builder.defineMacro("__ADX__"); 628 629 if (HasTBM) 630 Builder.defineMacro("__TBM__"); 631 632 if (HasLWP) 633 Builder.defineMacro("__LWP__"); 634 635 if (HasMWAITX) 636 Builder.defineMacro("__MWAITX__"); 637 638 if (HasMOVBE) 639 Builder.defineMacro("__MOVBE__"); 640 641 switch (XOPLevel) { 642 case XOP: 643 Builder.defineMacro("__XOP__"); 644 LLVM_FALLTHROUGH; 645 case FMA4: 646 Builder.defineMacro("__FMA4__"); 647 LLVM_FALLTHROUGH; 648 case SSE4A: 649 Builder.defineMacro("__SSE4A__"); 650 LLVM_FALLTHROUGH; 651 case NoXOP: 652 break; 653 } 654 655 if (HasFMA) 656 Builder.defineMacro("__FMA__"); 657 658 if (HasF16C) 659 Builder.defineMacro("__F16C__"); 660 661 if (HasGFNI) 662 Builder.defineMacro("__GFNI__"); 663 664 if (HasAVX512CD) 665 Builder.defineMacro("__AVX512CD__"); 666 if (HasAVX512VPOPCNTDQ) 667 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 668 if (HasAVX512VNNI) 669 Builder.defineMacro("__AVX512VNNI__"); 670 if (HasAVX512BF16) 671 Builder.defineMacro("__AVX512BF16__"); 672 if (HasAVX512ER) 673 Builder.defineMacro("__AVX512ER__"); 674 if (HasAVX512FP16) 675 Builder.defineMacro("__AVX512FP16__"); 676 if (HasAVX512PF) 677 Builder.defineMacro("__AVX512PF__"); 678 if (HasAVX512DQ) 679 Builder.defineMacro("__AVX512DQ__"); 680 if (HasAVX512BITALG) 681 Builder.defineMacro("__AVX512BITALG__"); 682 if (HasAVX512BW) 683 Builder.defineMacro("__AVX512BW__"); 684 if (HasAVX512VL) 685 Builder.defineMacro("__AVX512VL__"); 686 if (HasAVX512VBMI) 687 Builder.defineMacro("__AVX512VBMI__"); 688 if (HasAVX512VBMI2) 689 Builder.defineMacro("__AVX512VBMI2__"); 690 if (HasAVX512IFMA) 691 Builder.defineMacro("__AVX512IFMA__"); 692 if (HasAVX512VP2INTERSECT) 693 Builder.defineMacro("__AVX512VP2INTERSECT__"); 694 if (HasSHA) 695 Builder.defineMacro("__SHA__"); 696 697 if (HasFXSR) 698 Builder.defineMacro("__FXSR__"); 699 if (HasXSAVE) 700 Builder.defineMacro("__XSAVE__"); 701 if (HasXSAVEOPT) 702 Builder.defineMacro("__XSAVEOPT__"); 703 if (HasXSAVEC) 704 Builder.defineMacro("__XSAVEC__"); 705 if (HasXSAVES) 706 Builder.defineMacro("__XSAVES__"); 707 if (HasPKU) 708 Builder.defineMacro("__PKU__"); 709 if (HasCLFLUSHOPT) 710 Builder.defineMacro("__CLFLUSHOPT__"); 711 if (HasCLWB) 712 Builder.defineMacro("__CLWB__"); 713 if (HasWBNOINVD) 714 Builder.defineMacro("__WBNOINVD__"); 715 if (HasSHSTK) 716 Builder.defineMacro("__SHSTK__"); 717 if (HasSGX) 718 Builder.defineMacro("__SGX__"); 719 if (HasPREFETCHWT1) 720 Builder.defineMacro("__PREFETCHWT1__"); 721 if (HasCLZERO) 722 Builder.defineMacro("__CLZERO__"); 723 if (HasKL) 724 Builder.defineMacro("__KL__"); 725 if (HasWIDEKL) 726 Builder.defineMacro("__WIDEKL__"); 727 if (HasRDPID) 728 Builder.defineMacro("__RDPID__"); 729 if (HasCLDEMOTE) 730 Builder.defineMacro("__CLDEMOTE__"); 731 if (HasWAITPKG) 732 Builder.defineMacro("__WAITPKG__"); 733 if (HasMOVDIRI) 734 Builder.defineMacro("__MOVDIRI__"); 735 if (HasMOVDIR64B) 736 Builder.defineMacro("__MOVDIR64B__"); 737 if (HasPCONFIG) 738 Builder.defineMacro("__PCONFIG__"); 739 if (HasPTWRITE) 740 Builder.defineMacro("__PTWRITE__"); 741 if (HasINVPCID) 742 Builder.defineMacro("__INVPCID__"); 743 if (HasENQCMD) 744 Builder.defineMacro("__ENQCMD__"); 745 if (HasHRESET) 746 Builder.defineMacro("__HRESET__"); 747 if (HasAMXTILE) 748 Builder.defineMacro("__AMXTILE__"); 749 if (HasAMXINT8) 750 Builder.defineMacro("__AMXINT8__"); 751 if (HasAMXBF16) 752 Builder.defineMacro("__AMXBF16__"); 753 if (HasAVXVNNI) 754 Builder.defineMacro("__AVXVNNI__"); 755 if (HasSERIALIZE) 756 Builder.defineMacro("__SERIALIZE__"); 757 if (HasTSXLDTRK) 758 Builder.defineMacro("__TSXLDTRK__"); 759 if (HasUINTR) 760 Builder.defineMacro("__UINTR__"); 761 762 // Each case falls through to the previous one here. 763 switch (SSELevel) { 764 case AVX512F: 765 Builder.defineMacro("__AVX512F__"); 766 LLVM_FALLTHROUGH; 767 case AVX2: 768 Builder.defineMacro("__AVX2__"); 769 LLVM_FALLTHROUGH; 770 case AVX: 771 Builder.defineMacro("__AVX__"); 772 LLVM_FALLTHROUGH; 773 case SSE42: 774 Builder.defineMacro("__SSE4_2__"); 775 LLVM_FALLTHROUGH; 776 case SSE41: 777 Builder.defineMacro("__SSE4_1__"); 778 LLVM_FALLTHROUGH; 779 case SSSE3: 780 Builder.defineMacro("__SSSE3__"); 781 LLVM_FALLTHROUGH; 782 case SSE3: 783 Builder.defineMacro("__SSE3__"); 784 LLVM_FALLTHROUGH; 785 case SSE2: 786 Builder.defineMacro("__SSE2__"); 787 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 788 LLVM_FALLTHROUGH; 789 case SSE1: 790 Builder.defineMacro("__SSE__"); 791 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 792 LLVM_FALLTHROUGH; 793 case NoSSE: 794 break; 795 } 796 797 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 798 switch (SSELevel) { 799 case AVX512F: 800 case AVX2: 801 case AVX: 802 case SSE42: 803 case SSE41: 804 case SSSE3: 805 case SSE3: 806 case SSE2: 807 Builder.defineMacro("_M_IX86_FP", Twine(2)); 808 break; 809 case SSE1: 810 Builder.defineMacro("_M_IX86_FP", Twine(1)); 811 break; 812 default: 813 Builder.defineMacro("_M_IX86_FP", Twine(0)); 814 break; 815 } 816 } 817 818 // Each case falls through to the previous one here. 819 switch (MMX3DNowLevel) { 820 case AMD3DNowAthlon: 821 Builder.defineMacro("__3dNOW_A__"); 822 LLVM_FALLTHROUGH; 823 case AMD3DNow: 824 Builder.defineMacro("__3dNOW__"); 825 LLVM_FALLTHROUGH; 826 case MMX: 827 Builder.defineMacro("__MMX__"); 828 LLVM_FALLTHROUGH; 829 case NoMMX3DNow: 830 break; 831 } 832 833 if (CPU >= CK_i486 || CPU == CK_None) { 834 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 837 } 838 if (HasCX8) 839 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 840 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 841 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 842 843 if (HasFloat128) 844 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 845 } 846 847 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 848 return llvm::StringSwitch<bool>(Name) 849 .Case("3dnow", true) 850 .Case("3dnowa", true) 851 .Case("adx", true) 852 .Case("aes", true) 853 .Case("amx-bf16", true) 854 .Case("amx-int8", true) 855 .Case("amx-tile", true) 856 .Case("avx", true) 857 .Case("avx2", true) 858 .Case("avx512f", true) 859 .Case("avx512cd", true) 860 .Case("avx512vpopcntdq", true) 861 .Case("avx512vnni", true) 862 .Case("avx512bf16", true) 863 .Case("avx512er", true) 864 .Case("avx512fp16", true) 865 .Case("avx512pf", true) 866 .Case("avx512dq", true) 867 .Case("avx512bitalg", true) 868 .Case("avx512bw", true) 869 .Case("avx512vl", true) 870 .Case("avx512vbmi", true) 871 .Case("avx512vbmi2", true) 872 .Case("avx512ifma", true) 873 .Case("avx512vp2intersect", true) 874 .Case("avxvnni", true) 875 .Case("bmi", true) 876 .Case("bmi2", true) 877 .Case("cldemote", true) 878 .Case("clflushopt", true) 879 .Case("clwb", true) 880 .Case("clzero", true) 881 .Case("cx16", true) 882 .Case("enqcmd", true) 883 .Case("f16c", true) 884 .Case("fma", true) 885 .Case("fma4", true) 886 .Case("fsgsbase", true) 887 .Case("fxsr", true) 888 .Case("general-regs-only", true) 889 .Case("gfni", true) 890 .Case("hreset", true) 891 .Case("invpcid", true) 892 .Case("kl", true) 893 .Case("widekl", true) 894 .Case("lwp", true) 895 .Case("lzcnt", true) 896 .Case("mmx", true) 897 .Case("movbe", true) 898 .Case("movdiri", true) 899 .Case("movdir64b", true) 900 .Case("mwaitx", true) 901 .Case("pclmul", true) 902 .Case("pconfig", true) 903 .Case("pku", true) 904 .Case("popcnt", true) 905 .Case("prefetchwt1", true) 906 .Case("prfchw", true) 907 .Case("ptwrite", true) 908 .Case("rdpid", true) 909 .Case("rdrnd", true) 910 .Case("rdseed", true) 911 .Case("rtm", true) 912 .Case("sahf", true) 913 .Case("serialize", true) 914 .Case("sgx", true) 915 .Case("sha", true) 916 .Case("shstk", true) 917 .Case("sse", true) 918 .Case("sse2", true) 919 .Case("sse3", true) 920 .Case("ssse3", true) 921 .Case("sse4", true) 922 .Case("sse4.1", true) 923 .Case("sse4.2", true) 924 .Case("sse4a", true) 925 .Case("tbm", true) 926 .Case("tsxldtrk", true) 927 .Case("uintr", true) 928 .Case("vaes", true) 929 .Case("vpclmulqdq", true) 930 .Case("wbnoinvd", true) 931 .Case("waitpkg", true) 932 .Case("x87", true) 933 .Case("xop", true) 934 .Case("xsave", true) 935 .Case("xsavec", true) 936 .Case("xsaves", true) 937 .Case("xsaveopt", true) 938 .Default(false); 939 } 940 941 bool X86TargetInfo::hasFeature(StringRef Feature) const { 942 return llvm::StringSwitch<bool>(Feature) 943 .Case("adx", HasADX) 944 .Case("aes", HasAES) 945 .Case("amx-bf16", HasAMXBF16) 946 .Case("amx-int8", HasAMXINT8) 947 .Case("amx-tile", HasAMXTILE) 948 .Case("avxvnni", HasAVXVNNI) 949 .Case("avx", SSELevel >= AVX) 950 .Case("avx2", SSELevel >= AVX2) 951 .Case("avx512f", SSELevel >= AVX512F) 952 .Case("avx512cd", HasAVX512CD) 953 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 954 .Case("avx512vnni", HasAVX512VNNI) 955 .Case("avx512bf16", HasAVX512BF16) 956 .Case("avx512er", HasAVX512ER) 957 .Case("avx512fp16", HasAVX512FP16) 958 .Case("avx512pf", HasAVX512PF) 959 .Case("avx512dq", HasAVX512DQ) 960 .Case("avx512bitalg", HasAVX512BITALG) 961 .Case("avx512bw", HasAVX512BW) 962 .Case("avx512vl", HasAVX512VL) 963 .Case("avx512vbmi", HasAVX512VBMI) 964 .Case("avx512vbmi2", HasAVX512VBMI2) 965 .Case("avx512ifma", HasAVX512IFMA) 966 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 967 .Case("bmi", HasBMI) 968 .Case("bmi2", HasBMI2) 969 .Case("cldemote", HasCLDEMOTE) 970 .Case("clflushopt", HasCLFLUSHOPT) 971 .Case("clwb", HasCLWB) 972 .Case("clzero", HasCLZERO) 973 .Case("cx8", HasCX8) 974 .Case("cx16", HasCX16) 975 .Case("enqcmd", HasENQCMD) 976 .Case("f16c", HasF16C) 977 .Case("fma", HasFMA) 978 .Case("fma4", XOPLevel >= FMA4) 979 .Case("fsgsbase", HasFSGSBASE) 980 .Case("fxsr", HasFXSR) 981 .Case("gfni", HasGFNI) 982 .Case("hreset", HasHRESET) 983 .Case("invpcid", HasINVPCID) 984 .Case("kl", HasKL) 985 .Case("widekl", HasWIDEKL) 986 .Case("lwp", HasLWP) 987 .Case("lzcnt", HasLZCNT) 988 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 989 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 990 .Case("mmx", MMX3DNowLevel >= MMX) 991 .Case("movbe", HasMOVBE) 992 .Case("movdiri", HasMOVDIRI) 993 .Case("movdir64b", HasMOVDIR64B) 994 .Case("mwaitx", HasMWAITX) 995 .Case("pclmul", HasPCLMUL) 996 .Case("pconfig", HasPCONFIG) 997 .Case("pku", HasPKU) 998 .Case("popcnt", HasPOPCNT) 999 .Case("prefetchwt1", HasPREFETCHWT1) 1000 .Case("prfchw", HasPRFCHW) 1001 .Case("ptwrite", HasPTWRITE) 1002 .Case("rdpid", HasRDPID) 1003 .Case("rdrnd", HasRDRND) 1004 .Case("rdseed", HasRDSEED) 1005 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1006 .Case("rtm", HasRTM) 1007 .Case("sahf", HasLAHFSAHF) 1008 .Case("serialize", HasSERIALIZE) 1009 .Case("sgx", HasSGX) 1010 .Case("sha", HasSHA) 1011 .Case("shstk", HasSHSTK) 1012 .Case("sse", SSELevel >= SSE1) 1013 .Case("sse2", SSELevel >= SSE2) 1014 .Case("sse3", SSELevel >= SSE3) 1015 .Case("ssse3", SSELevel >= SSSE3) 1016 .Case("sse4.1", SSELevel >= SSE41) 1017 .Case("sse4.2", SSELevel >= SSE42) 1018 .Case("sse4a", XOPLevel >= SSE4A) 1019 .Case("tbm", HasTBM) 1020 .Case("tsxldtrk", HasTSXLDTRK) 1021 .Case("uintr", HasUINTR) 1022 .Case("vaes", HasVAES) 1023 .Case("vpclmulqdq", HasVPCLMULQDQ) 1024 .Case("wbnoinvd", HasWBNOINVD) 1025 .Case("waitpkg", HasWAITPKG) 1026 .Case("x86", true) 1027 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1028 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1029 .Case("xop", XOPLevel >= XOP) 1030 .Case("xsave", HasXSAVE) 1031 .Case("xsavec", HasXSAVEC) 1032 .Case("xsaves", HasXSAVES) 1033 .Case("xsaveopt", HasXSAVEOPT) 1034 .Default(false); 1035 } 1036 1037 // We can't use a generic validation scheme for the features accepted here 1038 // versus subtarget features accepted in the target attribute because the 1039 // bitfield structure that's initialized in the runtime only supports the 1040 // below currently rather than the full range of subtarget features. (See 1041 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1042 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1043 return llvm::StringSwitch<bool>(FeatureStr) 1044 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1045 #include "llvm/Support/X86TargetParser.def" 1046 .Default(false); 1047 } 1048 1049 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1050 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1051 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1052 .Case(STR, llvm::X86::FEATURE_##ENUM) 1053 1054 #include "llvm/Support/X86TargetParser.def" 1055 ; 1056 // Note, this function should only be used after ensuring the value is 1057 // correct, so it asserts if the value is out of range. 1058 } 1059 1060 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1061 // Valid CPUs have a 'key feature' that compares just better than its key 1062 // feature. 1063 using namespace llvm::X86; 1064 CPUKind Kind = parseArchX86(Name); 1065 if (Kind != CK_None) { 1066 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1067 return (getFeaturePriority(KeyFeature) << 1) + 1; 1068 } 1069 1070 // Now we know we have a feature, so get its priority and shift it a few so 1071 // that we have sufficient room for the CPUs (above). 1072 return getFeaturePriority(getFeature(Name)) << 1; 1073 } 1074 1075 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1076 return llvm::StringSwitch<bool>(Name) 1077 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1078 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1079 #include "llvm/Support/X86TargetParser.def" 1080 .Default(false); 1081 } 1082 1083 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1084 return llvm::StringSwitch<StringRef>(Name) 1085 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1086 #include "llvm/Support/X86TargetParser.def" 1087 .Default(Name); 1088 } 1089 1090 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1091 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1092 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1093 #include "llvm/Support/X86TargetParser.def" 1094 .Default(0); 1095 } 1096 1097 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1098 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1099 StringRef WholeList = 1100 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1101 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1102 #include "llvm/Support/X86TargetParser.def" 1103 .Default(""); 1104 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1105 } 1106 1107 // We can't use a generic validation scheme for the cpus accepted here 1108 // versus subtarget cpus accepted in the target attribute because the 1109 // variables intitialized by the runtime only support the below currently 1110 // rather than the full range of cpus. 1111 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1112 return llvm::StringSwitch<bool>(FeatureStr) 1113 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1114 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1115 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1116 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1117 #include "llvm/Support/X86TargetParser.def" 1118 .Default(false); 1119 } 1120 1121 static unsigned matchAsmCCConstraint(const char *&Name) { 1122 auto RV = llvm::StringSwitch<unsigned>(Name) 1123 .Case("@cca", 4) 1124 .Case("@ccae", 5) 1125 .Case("@ccb", 4) 1126 .Case("@ccbe", 5) 1127 .Case("@ccc", 4) 1128 .Case("@cce", 4) 1129 .Case("@ccz", 4) 1130 .Case("@ccg", 4) 1131 .Case("@ccge", 5) 1132 .Case("@ccl", 4) 1133 .Case("@ccle", 5) 1134 .Case("@ccna", 5) 1135 .Case("@ccnae", 6) 1136 .Case("@ccnb", 5) 1137 .Case("@ccnbe", 6) 1138 .Case("@ccnc", 5) 1139 .Case("@ccne", 5) 1140 .Case("@ccnz", 5) 1141 .Case("@ccng", 5) 1142 .Case("@ccnge", 6) 1143 .Case("@ccnl", 5) 1144 .Case("@ccnle", 6) 1145 .Case("@ccno", 5) 1146 .Case("@ccnp", 5) 1147 .Case("@ccns", 5) 1148 .Case("@cco", 4) 1149 .Case("@ccp", 4) 1150 .Case("@ccs", 4) 1151 .Default(0); 1152 return RV; 1153 } 1154 1155 bool X86TargetInfo::validateAsmConstraint( 1156 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1157 switch (*Name) { 1158 default: 1159 return false; 1160 // Constant constraints. 1161 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1162 // instructions. 1163 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1164 // x86_64 instructions. 1165 case 's': 1166 Info.setRequiresImmediate(); 1167 return true; 1168 case 'I': 1169 Info.setRequiresImmediate(0, 31); 1170 return true; 1171 case 'J': 1172 Info.setRequiresImmediate(0, 63); 1173 return true; 1174 case 'K': 1175 Info.setRequiresImmediate(-128, 127); 1176 return true; 1177 case 'L': 1178 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1179 return true; 1180 case 'M': 1181 Info.setRequiresImmediate(0, 3); 1182 return true; 1183 case 'N': 1184 Info.setRequiresImmediate(0, 255); 1185 return true; 1186 case 'O': 1187 Info.setRequiresImmediate(0, 127); 1188 return true; 1189 // Register constraints. 1190 case 'Y': // 'Y' is the first character for several 2-character constraints. 1191 // Shift the pointer to the second character of the constraint. 1192 Name++; 1193 switch (*Name) { 1194 default: 1195 return false; 1196 case 'z': // First SSE register. 1197 case '2': 1198 case 't': // Any SSE register, when SSE2 is enabled. 1199 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1200 case 'm': // Any MMX register, when inter-unit moves enabled. 1201 case 'k': // AVX512 arch mask registers: k1-k7. 1202 Info.setAllowsRegister(); 1203 return true; 1204 } 1205 case 'f': // Any x87 floating point stack register. 1206 // Constraint 'f' cannot be used for output operands. 1207 if (Info.ConstraintStr[0] == '=') 1208 return false; 1209 Info.setAllowsRegister(); 1210 return true; 1211 case 'a': // eax. 1212 case 'b': // ebx. 1213 case 'c': // ecx. 1214 case 'd': // edx. 1215 case 'S': // esi. 1216 case 'D': // edi. 1217 case 'A': // edx:eax. 1218 case 't': // Top of floating point stack. 1219 case 'u': // Second from top of floating point stack. 1220 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1221 case 'y': // Any MMX register. 1222 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1223 case 'x': // Any SSE register. 1224 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1225 // for intermideate k reg operations). 1226 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1227 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1228 case 'l': // "Index" registers: any general register that can be used as an 1229 // index in a base+index memory access. 1230 Info.setAllowsRegister(); 1231 return true; 1232 // Floating point constant constraints. 1233 case 'C': // SSE floating point constant. 1234 case 'G': // x87 floating point constant. 1235 return true; 1236 case '@': 1237 // CC condition changes. 1238 if (auto Len = matchAsmCCConstraint(Name)) { 1239 Name += Len - 1; 1240 Info.setAllowsRegister(); 1241 return true; 1242 } 1243 return false; 1244 } 1245 } 1246 1247 // Below is based on the following information: 1248 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1249 // | Processor Name | Cache Line Size (Bytes) | Source | 1250 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1251 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1252 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1253 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1254 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1255 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1256 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1257 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1258 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1259 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1260 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1261 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1262 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1263 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1264 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1265 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1266 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1267 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1268 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1269 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1270 using namespace llvm::X86; 1271 switch (CPU) { 1272 // i386 1273 case CK_i386: 1274 // i486 1275 case CK_i486: 1276 case CK_WinChipC6: 1277 case CK_WinChip2: 1278 case CK_C3: 1279 // Lakemont 1280 case CK_Lakemont: 1281 return 16; 1282 1283 // i586 1284 case CK_i586: 1285 case CK_Pentium: 1286 case CK_PentiumMMX: 1287 // i686 1288 case CK_PentiumPro: 1289 case CK_i686: 1290 case CK_Pentium2: 1291 case CK_Pentium3: 1292 case CK_PentiumM: 1293 case CK_C3_2: 1294 // K6 1295 case CK_K6: 1296 case CK_K6_2: 1297 case CK_K6_3: 1298 // Geode 1299 case CK_Geode: 1300 return 32; 1301 1302 // Netburst 1303 case CK_Pentium4: 1304 case CK_Prescott: 1305 case CK_Nocona: 1306 // Atom 1307 case CK_Bonnell: 1308 case CK_Silvermont: 1309 case CK_Goldmont: 1310 case CK_GoldmontPlus: 1311 case CK_Tremont: 1312 1313 case CK_Westmere: 1314 case CK_SandyBridge: 1315 case CK_IvyBridge: 1316 case CK_Haswell: 1317 case CK_Broadwell: 1318 case CK_SkylakeClient: 1319 case CK_SkylakeServer: 1320 case CK_Cascadelake: 1321 case CK_Nehalem: 1322 case CK_Cooperlake: 1323 case CK_Cannonlake: 1324 case CK_Tigerlake: 1325 case CK_SapphireRapids: 1326 case CK_IcelakeClient: 1327 case CK_Rocketlake: 1328 case CK_IcelakeServer: 1329 case CK_Alderlake: 1330 case CK_KNL: 1331 case CK_KNM: 1332 // K7 1333 case CK_Athlon: 1334 case CK_AthlonXP: 1335 // K8 1336 case CK_K8: 1337 case CK_K8SSE3: 1338 case CK_AMDFAM10: 1339 // Bobcat 1340 case CK_BTVER1: 1341 case CK_BTVER2: 1342 // Bulldozer 1343 case CK_BDVER1: 1344 case CK_BDVER2: 1345 case CK_BDVER3: 1346 case CK_BDVER4: 1347 // Zen 1348 case CK_ZNVER1: 1349 case CK_ZNVER2: 1350 case CK_ZNVER3: 1351 // Deprecated 1352 case CK_x86_64: 1353 case CK_x86_64_v2: 1354 case CK_x86_64_v3: 1355 case CK_x86_64_v4: 1356 case CK_Yonah: 1357 case CK_Penryn: 1358 case CK_Core2: 1359 return 64; 1360 1361 // The following currently have unknown cache line sizes (but they are probably all 64): 1362 // Core 1363 case CK_None: 1364 return None; 1365 } 1366 llvm_unreachable("Unknown CPU kind"); 1367 } 1368 1369 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1370 StringRef Constraint, 1371 unsigned Size) const { 1372 // Strip off constraint modifiers. 1373 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1374 Constraint = Constraint.substr(1); 1375 1376 return validateOperandSize(FeatureMap, Constraint, Size); 1377 } 1378 1379 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1380 StringRef Constraint, 1381 unsigned Size) const { 1382 return validateOperandSize(FeatureMap, Constraint, Size); 1383 } 1384 1385 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1386 StringRef Constraint, 1387 unsigned Size) const { 1388 switch (Constraint[0]) { 1389 default: 1390 break; 1391 case 'k': 1392 // Registers k0-k7 (AVX512) size limit is 64 bit. 1393 case 'y': 1394 return Size <= 64; 1395 case 'f': 1396 case 't': 1397 case 'u': 1398 return Size <= 128; 1399 case 'Y': 1400 // 'Y' is the first character for several 2-character constraints. 1401 switch (Constraint[1]) { 1402 default: 1403 return false; 1404 case 'm': 1405 // 'Ym' is synonymous with 'y'. 1406 case 'k': 1407 return Size <= 64; 1408 case 'z': 1409 // XMM0/YMM/ZMM0 1410 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1411 // ZMM0 can be used if target supports AVX512F. 1412 return Size <= 512U; 1413 else if (hasFeatureEnabled(FeatureMap, "avx")) 1414 // YMM0 can be used if target supports AVX. 1415 return Size <= 256U; 1416 else if (hasFeatureEnabled(FeatureMap, "sse")) 1417 return Size <= 128U; 1418 return false; 1419 case 'i': 1420 case 't': 1421 case '2': 1422 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1423 if (SSELevel < SSE2) 1424 return false; 1425 break; 1426 } 1427 break; 1428 case 'v': 1429 case 'x': 1430 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1431 // 512-bit zmm registers can be used if target supports AVX512F. 1432 return Size <= 512U; 1433 else if (hasFeatureEnabled(FeatureMap, "avx")) 1434 // 256-bit ymm registers can be used if target supports AVX. 1435 return Size <= 256U; 1436 return Size <= 128U; 1437 1438 } 1439 1440 return true; 1441 } 1442 1443 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1444 switch (*Constraint) { 1445 case '@': 1446 if (auto Len = matchAsmCCConstraint(Constraint)) { 1447 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1448 Constraint += Len - 1; 1449 return Converted; 1450 } 1451 return std::string(1, *Constraint); 1452 case 'a': 1453 return std::string("{ax}"); 1454 case 'b': 1455 return std::string("{bx}"); 1456 case 'c': 1457 return std::string("{cx}"); 1458 case 'd': 1459 return std::string("{dx}"); 1460 case 'S': 1461 return std::string("{si}"); 1462 case 'D': 1463 return std::string("{di}"); 1464 case 'p': // address 1465 return std::string("im"); 1466 case 't': // top of floating point stack. 1467 return std::string("{st}"); 1468 case 'u': // second from top of floating point stack. 1469 return std::string("{st(1)}"); // second from top of floating point stack. 1470 case 'Y': 1471 switch (Constraint[1]) { 1472 default: 1473 // Break from inner switch and fall through (copy single char), 1474 // continue parsing after copying the current constraint into 1475 // the return string. 1476 break; 1477 case 'k': 1478 case 'm': 1479 case 'i': 1480 case 't': 1481 case 'z': 1482 case '2': 1483 // "^" hints llvm that this is a 2 letter constraint. 1484 // "Constraint++" is used to promote the string iterator 1485 // to the next constraint. 1486 return std::string("^") + std::string(Constraint++, 2); 1487 } 1488 LLVM_FALLTHROUGH; 1489 default: 1490 return std::string(1, *Constraint); 1491 } 1492 } 1493 1494 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1495 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1496 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1497 } 1498 1499 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1500 llvm::X86::fillValidTuneCPUList(Values); 1501 } 1502 1503 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1504 return llvm::makeArrayRef(GCCRegNames); 1505 } 1506 1507 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1508 return llvm::makeArrayRef(AddlRegNames); 1509 } 1510 1511 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1512 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1513 Builtin::FirstTSBuiltin + 1); 1514 } 1515 1516 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1517 return llvm::makeArrayRef(BuiltinInfoX86, 1518 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1519 } 1520