1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::checkCFProtectionReturnSupported( 106 DiagnosticsEngine &Diags) const { 107 if (HasSHSTK) 108 return true; 109 110 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 111 << "-mshstk"; 112 return false; 113 } 114 115 bool X86TargetInfo::checkCFProtectionBranchSupported( 116 DiagnosticsEngine &Diags) const { 117 if (HasIBT) 118 return true; 119 120 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 121 << "-mibt"; 122 return false; 123 } 124 125 bool X86TargetInfo::initFeatureMap( 126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 127 const std::vector<std::string> &FeaturesVec) const { 128 // FIXME: This *really* should not be here. 129 // X86_64 always has SSE2. 130 if (getTriple().getArch() == llvm::Triple::x86_64) 131 setFeatureEnabledImpl(Features, "sse2", true); 132 133 const CPUKind Kind = getCPUKind(CPU); 134 135 // Enable X87 for all X86 processors but Lakemont. 136 if (Kind != CK_Lakemont) 137 setFeatureEnabledImpl(Features, "x87", true); 138 139 switch (Kind) { 140 case CK_Generic: 141 case CK_i386: 142 case CK_i486: 143 case CK_i586: 144 case CK_Pentium: 145 case CK_PentiumPro: 146 case CK_Lakemont: 147 break; 148 149 case CK_PentiumMMX: 150 case CK_Pentium2: 151 case CK_K6: 152 case CK_WinChipC6: 153 setFeatureEnabledImpl(Features, "mmx", true); 154 break; 155 156 case CK_Icelake: 157 setFeatureEnabledImpl(Features, "vaes", true); 158 setFeatureEnabledImpl(Features, "gfni", true); 159 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 160 setFeatureEnabledImpl(Features, "avx512bitalg", true); 161 setFeatureEnabledImpl(Features, "avx512vnni", true); 162 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 163 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 164 setFeatureEnabledImpl(Features, "rdpid", true); 165 LLVM_FALLTHROUGH; 166 case CK_Cannonlake: 167 setFeatureEnabledImpl(Features, "avx512ifma", true); 168 setFeatureEnabledImpl(Features, "avx512vbmi", true); 169 setFeatureEnabledImpl(Features, "sha", true); 170 LLVM_FALLTHROUGH; 171 case CK_SkylakeServer: 172 setFeatureEnabledImpl(Features, "avx512f", true); 173 setFeatureEnabledImpl(Features, "avx512cd", true); 174 setFeatureEnabledImpl(Features, "avx512dq", true); 175 setFeatureEnabledImpl(Features, "avx512bw", true); 176 setFeatureEnabledImpl(Features, "avx512vl", true); 177 setFeatureEnabledImpl(Features, "pku", true); 178 setFeatureEnabledImpl(Features, "clwb", true); 179 LLVM_FALLTHROUGH; 180 case CK_SkylakeClient: 181 setFeatureEnabledImpl(Features, "xsavec", true); 182 setFeatureEnabledImpl(Features, "xsaves", true); 183 setFeatureEnabledImpl(Features, "mpx", true); 184 setFeatureEnabledImpl(Features, "sgx", true); 185 setFeatureEnabledImpl(Features, "clflushopt", true); 186 setFeatureEnabledImpl(Features, "rtm", true); 187 LLVM_FALLTHROUGH; 188 case CK_Broadwell: 189 setFeatureEnabledImpl(Features, "rdseed", true); 190 setFeatureEnabledImpl(Features, "adx", true); 191 setFeatureEnabledImpl(Features, "prfchw", true); 192 LLVM_FALLTHROUGH; 193 case CK_Haswell: 194 setFeatureEnabledImpl(Features, "avx2", true); 195 setFeatureEnabledImpl(Features, "lzcnt", true); 196 setFeatureEnabledImpl(Features, "bmi", true); 197 setFeatureEnabledImpl(Features, "bmi2", true); 198 setFeatureEnabledImpl(Features, "fma", true); 199 setFeatureEnabledImpl(Features, "movbe", true); 200 LLVM_FALLTHROUGH; 201 case CK_IvyBridge: 202 setFeatureEnabledImpl(Features, "rdrnd", true); 203 setFeatureEnabledImpl(Features, "f16c", true); 204 setFeatureEnabledImpl(Features, "fsgsbase", true); 205 LLVM_FALLTHROUGH; 206 case CK_SandyBridge: 207 setFeatureEnabledImpl(Features, "avx", true); 208 setFeatureEnabledImpl(Features, "xsave", true); 209 setFeatureEnabledImpl(Features, "xsaveopt", true); 210 LLVM_FALLTHROUGH; 211 case CK_Westmere: 212 setFeatureEnabledImpl(Features, "aes", true); 213 setFeatureEnabledImpl(Features, "pclmul", true); 214 LLVM_FALLTHROUGH; 215 case CK_Nehalem: 216 setFeatureEnabledImpl(Features, "sse4.2", true); 217 LLVM_FALLTHROUGH; 218 case CK_Penryn: 219 setFeatureEnabledImpl(Features, "sse4.1", true); 220 LLVM_FALLTHROUGH; 221 case CK_Core2: 222 setFeatureEnabledImpl(Features, "ssse3", true); 223 LLVM_FALLTHROUGH; 224 case CK_Yonah: 225 case CK_Prescott: 226 case CK_Nocona: 227 setFeatureEnabledImpl(Features, "sse3", true); 228 setFeatureEnabledImpl(Features, "cx16", true); 229 LLVM_FALLTHROUGH; 230 case CK_PentiumM: 231 case CK_Pentium4: 232 case CK_x86_64: 233 setFeatureEnabledImpl(Features, "sse2", true); 234 LLVM_FALLTHROUGH; 235 case CK_Pentium3: 236 case CK_C3_2: 237 setFeatureEnabledImpl(Features, "sse", true); 238 setFeatureEnabledImpl(Features, "fxsr", true); 239 break; 240 241 case CK_Goldmont: 242 setFeatureEnabledImpl(Features, "sha", true); 243 setFeatureEnabledImpl(Features, "rdseed", true); 244 setFeatureEnabledImpl(Features, "xsave", true); 245 setFeatureEnabledImpl(Features, "xsaveopt", true); 246 setFeatureEnabledImpl(Features, "xsavec", true); 247 setFeatureEnabledImpl(Features, "xsaves", true); 248 setFeatureEnabledImpl(Features, "clflushopt", true); 249 setFeatureEnabledImpl(Features, "mpx", true); 250 setFeatureEnabledImpl(Features, "fsgsbase", true); 251 LLVM_FALLTHROUGH; 252 case CK_Silvermont: 253 setFeatureEnabledImpl(Features, "rdrnd", true); 254 setFeatureEnabledImpl(Features, "aes", true); 255 setFeatureEnabledImpl(Features, "pclmul", true); 256 setFeatureEnabledImpl(Features, "sse4.2", true); 257 setFeatureEnabledImpl(Features, "prfchw", true); 258 LLVM_FALLTHROUGH; 259 case CK_Bonnell: 260 setFeatureEnabledImpl(Features, "movbe", true); 261 setFeatureEnabledImpl(Features, "ssse3", true); 262 setFeatureEnabledImpl(Features, "fxsr", true); 263 setFeatureEnabledImpl(Features, "cx16", true); 264 break; 265 266 case CK_KNM: 267 // TODO: Add avx5124fmaps/avx5124vnniw. 268 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 269 LLVM_FALLTHROUGH; 270 case CK_KNL: 271 setFeatureEnabledImpl(Features, "avx512f", true); 272 setFeatureEnabledImpl(Features, "avx512cd", true); 273 setFeatureEnabledImpl(Features, "avx512er", true); 274 setFeatureEnabledImpl(Features, "avx512pf", true); 275 setFeatureEnabledImpl(Features, "prfchw", true); 276 setFeatureEnabledImpl(Features, "prefetchwt1", true); 277 setFeatureEnabledImpl(Features, "fxsr", true); 278 setFeatureEnabledImpl(Features, "rdseed", true); 279 setFeatureEnabledImpl(Features, "adx", true); 280 setFeatureEnabledImpl(Features, "lzcnt", true); 281 setFeatureEnabledImpl(Features, "bmi", true); 282 setFeatureEnabledImpl(Features, "bmi2", true); 283 setFeatureEnabledImpl(Features, "rtm", true); 284 setFeatureEnabledImpl(Features, "fma", true); 285 setFeatureEnabledImpl(Features, "rdrnd", true); 286 setFeatureEnabledImpl(Features, "f16c", true); 287 setFeatureEnabledImpl(Features, "fsgsbase", true); 288 setFeatureEnabledImpl(Features, "aes", true); 289 setFeatureEnabledImpl(Features, "pclmul", true); 290 setFeatureEnabledImpl(Features, "cx16", true); 291 setFeatureEnabledImpl(Features, "xsaveopt", true); 292 setFeatureEnabledImpl(Features, "xsave", true); 293 setFeatureEnabledImpl(Features, "movbe", true); 294 break; 295 296 case CK_K6_2: 297 case CK_K6_3: 298 case CK_WinChip2: 299 case CK_C3: 300 setFeatureEnabledImpl(Features, "3dnow", true); 301 break; 302 303 case CK_AMDFAM10: 304 setFeatureEnabledImpl(Features, "sse4a", true); 305 setFeatureEnabledImpl(Features, "lzcnt", true); 306 setFeatureEnabledImpl(Features, "popcnt", true); 307 LLVM_FALLTHROUGH; 308 case CK_K8SSE3: 309 setFeatureEnabledImpl(Features, "sse3", true); 310 LLVM_FALLTHROUGH; 311 case CK_K8: 312 setFeatureEnabledImpl(Features, "sse2", true); 313 LLVM_FALLTHROUGH; 314 case CK_AthlonXP: 315 setFeatureEnabledImpl(Features, "sse", true); 316 setFeatureEnabledImpl(Features, "fxsr", true); 317 LLVM_FALLTHROUGH; 318 case CK_Athlon: 319 case CK_Geode: 320 setFeatureEnabledImpl(Features, "3dnowa", true); 321 break; 322 323 case CK_BTVER2: 324 setFeatureEnabledImpl(Features, "avx", true); 325 setFeatureEnabledImpl(Features, "aes", true); 326 setFeatureEnabledImpl(Features, "pclmul", true); 327 setFeatureEnabledImpl(Features, "bmi", true); 328 setFeatureEnabledImpl(Features, "f16c", true); 329 setFeatureEnabledImpl(Features, "xsaveopt", true); 330 setFeatureEnabledImpl(Features, "movbe", true); 331 LLVM_FALLTHROUGH; 332 case CK_BTVER1: 333 setFeatureEnabledImpl(Features, "ssse3", true); 334 setFeatureEnabledImpl(Features, "sse4a", true); 335 setFeatureEnabledImpl(Features, "lzcnt", true); 336 setFeatureEnabledImpl(Features, "popcnt", true); 337 setFeatureEnabledImpl(Features, "prfchw", true); 338 setFeatureEnabledImpl(Features, "cx16", true); 339 setFeatureEnabledImpl(Features, "fxsr", true); 340 break; 341 342 case CK_ZNVER1: 343 setFeatureEnabledImpl(Features, "adx", true); 344 setFeatureEnabledImpl(Features, "aes", true); 345 setFeatureEnabledImpl(Features, "avx2", true); 346 setFeatureEnabledImpl(Features, "bmi", true); 347 setFeatureEnabledImpl(Features, "bmi2", true); 348 setFeatureEnabledImpl(Features, "clflushopt", true); 349 setFeatureEnabledImpl(Features, "clzero", true); 350 setFeatureEnabledImpl(Features, "cx16", true); 351 setFeatureEnabledImpl(Features, "f16c", true); 352 setFeatureEnabledImpl(Features, "fma", true); 353 setFeatureEnabledImpl(Features, "fsgsbase", true); 354 setFeatureEnabledImpl(Features, "fxsr", true); 355 setFeatureEnabledImpl(Features, "lzcnt", true); 356 setFeatureEnabledImpl(Features, "mwaitx", true); 357 setFeatureEnabledImpl(Features, "movbe", true); 358 setFeatureEnabledImpl(Features, "pclmul", true); 359 setFeatureEnabledImpl(Features, "popcnt", true); 360 setFeatureEnabledImpl(Features, "prfchw", true); 361 setFeatureEnabledImpl(Features, "rdrnd", true); 362 setFeatureEnabledImpl(Features, "rdseed", true); 363 setFeatureEnabledImpl(Features, "sha", true); 364 setFeatureEnabledImpl(Features, "sse4a", true); 365 setFeatureEnabledImpl(Features, "xsave", true); 366 setFeatureEnabledImpl(Features, "xsavec", true); 367 setFeatureEnabledImpl(Features, "xsaveopt", true); 368 setFeatureEnabledImpl(Features, "xsaves", true); 369 break; 370 371 case CK_BDVER4: 372 setFeatureEnabledImpl(Features, "avx2", true); 373 setFeatureEnabledImpl(Features, "bmi2", true); 374 setFeatureEnabledImpl(Features, "mwaitx", true); 375 LLVM_FALLTHROUGH; 376 case CK_BDVER3: 377 setFeatureEnabledImpl(Features, "fsgsbase", true); 378 setFeatureEnabledImpl(Features, "xsaveopt", true); 379 LLVM_FALLTHROUGH; 380 case CK_BDVER2: 381 setFeatureEnabledImpl(Features, "bmi", true); 382 setFeatureEnabledImpl(Features, "fma", true); 383 setFeatureEnabledImpl(Features, "f16c", true); 384 setFeatureEnabledImpl(Features, "tbm", true); 385 LLVM_FALLTHROUGH; 386 case CK_BDVER1: 387 // xop implies avx, sse4a and fma4. 388 setFeatureEnabledImpl(Features, "xop", true); 389 setFeatureEnabledImpl(Features, "lwp", true); 390 setFeatureEnabledImpl(Features, "lzcnt", true); 391 setFeatureEnabledImpl(Features, "aes", true); 392 setFeatureEnabledImpl(Features, "pclmul", true); 393 setFeatureEnabledImpl(Features, "prfchw", true); 394 setFeatureEnabledImpl(Features, "cx16", true); 395 setFeatureEnabledImpl(Features, "fxsr", true); 396 setFeatureEnabledImpl(Features, "xsave", true); 397 break; 398 } 399 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 400 return false; 401 402 // Can't do this earlier because we need to be able to explicitly enable 403 // or disable these features and the things that they depend upon. 404 405 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 406 auto I = Features.find("sse4.2"); 407 if (I != Features.end() && I->getValue() && 408 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 409 FeaturesVec.end()) 410 Features["popcnt"] = true; 411 412 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 413 I = Features.find("3dnow"); 414 if (I != Features.end() && I->getValue() && 415 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 416 FeaturesVec.end()) 417 Features["prfchw"] = true; 418 419 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 420 // then enable MMX. 421 I = Features.find("sse"); 422 if (I != Features.end() && I->getValue() && 423 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 424 FeaturesVec.end()) 425 Features["mmx"] = true; 426 427 return true; 428 } 429 430 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 431 X86SSEEnum Level, bool Enabled) { 432 if (Enabled) { 433 switch (Level) { 434 case AVX512F: 435 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 436 LLVM_FALLTHROUGH; 437 case AVX2: 438 Features["avx2"] = true; 439 LLVM_FALLTHROUGH; 440 case AVX: 441 Features["avx"] = true; 442 Features["xsave"] = true; 443 LLVM_FALLTHROUGH; 444 case SSE42: 445 Features["sse4.2"] = true; 446 LLVM_FALLTHROUGH; 447 case SSE41: 448 Features["sse4.1"] = true; 449 LLVM_FALLTHROUGH; 450 case SSSE3: 451 Features["ssse3"] = true; 452 LLVM_FALLTHROUGH; 453 case SSE3: 454 Features["sse3"] = true; 455 LLVM_FALLTHROUGH; 456 case SSE2: 457 Features["sse2"] = true; 458 LLVM_FALLTHROUGH; 459 case SSE1: 460 Features["sse"] = true; 461 LLVM_FALLTHROUGH; 462 case NoSSE: 463 break; 464 } 465 return; 466 } 467 468 switch (Level) { 469 case NoSSE: 470 case SSE1: 471 Features["sse"] = false; 472 LLVM_FALLTHROUGH; 473 case SSE2: 474 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 475 Features["gfni"] = false; 476 LLVM_FALLTHROUGH; 477 case SSE3: 478 Features["sse3"] = false; 479 setXOPLevel(Features, NoXOP, false); 480 LLVM_FALLTHROUGH; 481 case SSSE3: 482 Features["ssse3"] = false; 483 LLVM_FALLTHROUGH; 484 case SSE41: 485 Features["sse4.1"] = false; 486 LLVM_FALLTHROUGH; 487 case SSE42: 488 Features["sse4.2"] = false; 489 LLVM_FALLTHROUGH; 490 case AVX: 491 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 492 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 493 setXOPLevel(Features, FMA4, false); 494 LLVM_FALLTHROUGH; 495 case AVX2: 496 Features["avx2"] = false; 497 LLVM_FALLTHROUGH; 498 case AVX512F: 499 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 500 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 501 Features["avx512vl"] = Features["avx512vbmi"] = 502 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 503 Features["avx512bitalg"] = Features["avx512vnni"] = 504 Features["avx512vbmi2"] = false; 505 break; 506 } 507 } 508 509 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 510 MMX3DNowEnum Level, bool Enabled) { 511 if (Enabled) { 512 switch (Level) { 513 case AMD3DNowAthlon: 514 Features["3dnowa"] = true; 515 LLVM_FALLTHROUGH; 516 case AMD3DNow: 517 Features["3dnow"] = true; 518 LLVM_FALLTHROUGH; 519 case MMX: 520 Features["mmx"] = true; 521 LLVM_FALLTHROUGH; 522 case NoMMX3DNow: 523 break; 524 } 525 return; 526 } 527 528 switch (Level) { 529 case NoMMX3DNow: 530 case MMX: 531 Features["mmx"] = false; 532 LLVM_FALLTHROUGH; 533 case AMD3DNow: 534 Features["3dnow"] = false; 535 LLVM_FALLTHROUGH; 536 case AMD3DNowAthlon: 537 Features["3dnowa"] = false; 538 break; 539 } 540 } 541 542 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 543 bool Enabled) { 544 if (Enabled) { 545 switch (Level) { 546 case XOP: 547 Features["xop"] = true; 548 LLVM_FALLTHROUGH; 549 case FMA4: 550 Features["fma4"] = true; 551 setSSELevel(Features, AVX, true); 552 LLVM_FALLTHROUGH; 553 case SSE4A: 554 Features["sse4a"] = true; 555 setSSELevel(Features, SSE3, true); 556 LLVM_FALLTHROUGH; 557 case NoXOP: 558 break; 559 } 560 return; 561 } 562 563 switch (Level) { 564 case NoXOP: 565 case SSE4A: 566 Features["sse4a"] = false; 567 LLVM_FALLTHROUGH; 568 case FMA4: 569 Features["fma4"] = false; 570 LLVM_FALLTHROUGH; 571 case XOP: 572 Features["xop"] = false; 573 break; 574 } 575 } 576 577 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 578 StringRef Name, bool Enabled) { 579 // This is a bit of a hack to deal with the sse4 target feature when used 580 // as part of the target attribute. We handle sse4 correctly everywhere 581 // else. See below for more information on how we handle the sse4 options. 582 if (Name != "sse4") 583 Features[Name] = Enabled; 584 585 if (Name == "mmx") { 586 setMMXLevel(Features, MMX, Enabled); 587 } else if (Name == "sse") { 588 setSSELevel(Features, SSE1, Enabled); 589 } else if (Name == "sse2") { 590 setSSELevel(Features, SSE2, Enabled); 591 } else if (Name == "sse3") { 592 setSSELevel(Features, SSE3, Enabled); 593 } else if (Name == "ssse3") { 594 setSSELevel(Features, SSSE3, Enabled); 595 } else if (Name == "sse4.2") { 596 setSSELevel(Features, SSE42, Enabled); 597 } else if (Name == "sse4.1") { 598 setSSELevel(Features, SSE41, Enabled); 599 } else if (Name == "3dnow") { 600 setMMXLevel(Features, AMD3DNow, Enabled); 601 } else if (Name == "3dnowa") { 602 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 603 } else if (Name == "aes") { 604 if (Enabled) 605 setSSELevel(Features, SSE2, Enabled); 606 else 607 Features["vaes"] = false; 608 } else if (Name == "vaes") { 609 if (Enabled) { 610 setSSELevel(Features, AVX, Enabled); 611 Features["aes"] = true; 612 } 613 } else if (Name == "pclmul") { 614 if (Enabled) 615 setSSELevel(Features, SSE2, Enabled); 616 else 617 Features["vpclmulqdq"] = false; 618 } else if (Name == "vpclmulqdq") { 619 if (Enabled) { 620 setSSELevel(Features, AVX, Enabled); 621 Features["pclmul"] = true; 622 } 623 } else if (Name == "gfni") { 624 if (Enabled) 625 setSSELevel(Features, SSE2, Enabled); 626 } else if (Name == "avx") { 627 setSSELevel(Features, AVX, Enabled); 628 } else if (Name == "avx2") { 629 setSSELevel(Features, AVX2, Enabled); 630 } else if (Name == "avx512f") { 631 setSSELevel(Features, AVX512F, Enabled); 632 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 633 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 634 Name == "avx512vbmi" || Name == "avx512ifma" || 635 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 636 Name == "avx512vnni" || Name == "avx512vbmi2") { 637 if (Enabled) 638 setSSELevel(Features, AVX512F, Enabled); 639 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 640 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 641 Features["avx512bw"] = true; 642 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 643 if (Name == "avx512bw" && !Enabled) 644 Features["avx512vbmi"] = Features["avx512vbmi2"] = 645 Features["avx512bitalg"] = false; 646 } else if (Name == "fma") { 647 if (Enabled) 648 setSSELevel(Features, AVX, Enabled); 649 else 650 setSSELevel(Features, AVX512F, Enabled); 651 } else if (Name == "fma4") { 652 setXOPLevel(Features, FMA4, Enabled); 653 } else if (Name == "xop") { 654 setXOPLevel(Features, XOP, Enabled); 655 } else if (Name == "sse4a") { 656 setXOPLevel(Features, SSE4A, Enabled); 657 } else if (Name == "f16c") { 658 if (Enabled) 659 setSSELevel(Features, AVX, Enabled); 660 else 661 setSSELevel(Features, AVX512F, Enabled); 662 } else if (Name == "sha") { 663 if (Enabled) 664 setSSELevel(Features, SSE2, Enabled); 665 } else if (Name == "sse4") { 666 // We can get here via the __target__ attribute since that's not controlled 667 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 668 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 669 // disabled. 670 if (Enabled) 671 setSSELevel(Features, SSE42, Enabled); 672 else 673 setSSELevel(Features, SSE41, Enabled); 674 } else if (Name == "xsave") { 675 if (!Enabled) 676 Features["xsaveopt"] = false; 677 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 678 if (Enabled) 679 Features["xsave"] = true; 680 } 681 } 682 683 /// handleTargetFeatures - Perform initialization based on the user 684 /// configured set of features. 685 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 686 DiagnosticsEngine &Diags) { 687 for (const auto &Feature : Features) { 688 if (Feature[0] != '+') 689 continue; 690 691 if (Feature == "+aes") { 692 HasAES = true; 693 } else if (Feature == "+vaes") { 694 HasVAES = true; 695 } else if (Feature == "+pclmul") { 696 HasPCLMUL = true; 697 } else if (Feature == "+vpclmulqdq") { 698 HasVPCLMULQDQ = true; 699 } else if (Feature == "+lzcnt") { 700 HasLZCNT = true; 701 } else if (Feature == "+rdrnd") { 702 HasRDRND = true; 703 } else if (Feature == "+fsgsbase") { 704 HasFSGSBASE = true; 705 } else if (Feature == "+bmi") { 706 HasBMI = true; 707 } else if (Feature == "+bmi2") { 708 HasBMI2 = true; 709 } else if (Feature == "+popcnt") { 710 HasPOPCNT = true; 711 } else if (Feature == "+rtm") { 712 HasRTM = true; 713 } else if (Feature == "+prfchw") { 714 HasPRFCHW = true; 715 } else if (Feature == "+rdseed") { 716 HasRDSEED = true; 717 } else if (Feature == "+adx") { 718 HasADX = true; 719 } else if (Feature == "+tbm") { 720 HasTBM = true; 721 } else if (Feature == "+lwp") { 722 HasLWP = true; 723 } else if (Feature == "+fma") { 724 HasFMA = true; 725 } else if (Feature == "+f16c") { 726 HasF16C = true; 727 } else if (Feature == "+gfni") { 728 HasGFNI = true; 729 } else if (Feature == "+avx512cd") { 730 HasAVX512CD = true; 731 } else if (Feature == "+avx512vpopcntdq") { 732 HasAVX512VPOPCNTDQ = true; 733 } else if (Feature == "+avx512vnni") { 734 HasAVX512VNNI = true; 735 } else if (Feature == "+avx512er") { 736 HasAVX512ER = true; 737 } else if (Feature == "+avx512pf") { 738 HasAVX512PF = true; 739 } else if (Feature == "+avx512dq") { 740 HasAVX512DQ = true; 741 } else if (Feature == "+avx512bitalg") { 742 HasAVX512BITALG = true; 743 } else if (Feature == "+avx512bw") { 744 HasAVX512BW = true; 745 } else if (Feature == "+avx512vl") { 746 HasAVX512VL = true; 747 } else if (Feature == "+avx512vbmi") { 748 HasAVX512VBMI = true; 749 } else if (Feature == "+avx512vbmi2") { 750 HasAVX512VBMI2 = true; 751 } else if (Feature == "+avx512ifma") { 752 HasAVX512IFMA = true; 753 } else if (Feature == "+sha") { 754 HasSHA = true; 755 } else if (Feature == "+mpx") { 756 HasMPX = true; 757 } else if (Feature == "+shstk") { 758 HasSHSTK = true; 759 } else if (Feature == "+ibt") { 760 HasIBT = true; 761 } else if (Feature == "+movbe") { 762 HasMOVBE = true; 763 } else if (Feature == "+sgx") { 764 HasSGX = true; 765 } else if (Feature == "+cx16") { 766 HasCX16 = true; 767 } else if (Feature == "+fxsr") { 768 HasFXSR = true; 769 } else if (Feature == "+xsave") { 770 HasXSAVE = true; 771 } else if (Feature == "+xsaveopt") { 772 HasXSAVEOPT = true; 773 } else if (Feature == "+xsavec") { 774 HasXSAVEC = true; 775 } else if (Feature == "+xsaves") { 776 HasXSAVES = true; 777 } else if (Feature == "+mwaitx") { 778 HasMWAITX = true; 779 } else if (Feature == "+pku") { 780 HasPKU = true; 781 } else if (Feature == "+clflushopt") { 782 HasCLFLUSHOPT = true; 783 } else if (Feature == "+clwb") { 784 HasCLWB = true; 785 } else if (Feature == "+prefetchwt1") { 786 HasPREFETCHWT1 = true; 787 } else if (Feature == "+clzero") { 788 HasCLZERO = true; 789 } else if (Feature == "+rdpid") { 790 HasRDPID = true; 791 } else if (Feature == "+retpoline") { 792 HasRetpoline = true; 793 } else if (Feature == "+retpoline-external-thunk") { 794 HasRetpolineExternalThunk = true; 795 } 796 797 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 798 .Case("+avx512f", AVX512F) 799 .Case("+avx2", AVX2) 800 .Case("+avx", AVX) 801 .Case("+sse4.2", SSE42) 802 .Case("+sse4.1", SSE41) 803 .Case("+ssse3", SSSE3) 804 .Case("+sse3", SSE3) 805 .Case("+sse2", SSE2) 806 .Case("+sse", SSE1) 807 .Default(NoSSE); 808 SSELevel = std::max(SSELevel, Level); 809 810 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 811 .Case("+3dnowa", AMD3DNowAthlon) 812 .Case("+3dnow", AMD3DNow) 813 .Case("+mmx", MMX) 814 .Default(NoMMX3DNow); 815 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 816 817 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 818 .Case("+xop", XOP) 819 .Case("+fma4", FMA4) 820 .Case("+sse4a", SSE4A) 821 .Default(NoXOP); 822 XOPLevel = std::max(XOPLevel, XLevel); 823 } 824 825 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 826 // matches the selected sse level. 827 if ((FPMath == FP_SSE && SSELevel < SSE1) || 828 (FPMath == FP_387 && SSELevel >= SSE1)) { 829 Diags.Report(diag::err_target_unsupported_fpmath) 830 << (FPMath == FP_SSE ? "sse" : "387"); 831 return false; 832 } 833 834 SimdDefaultAlign = 835 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 836 return true; 837 } 838 839 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 840 /// definitions for this particular subtarget. 841 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 842 MacroBuilder &Builder) const { 843 // Target identification. 844 if (getTriple().getArch() == llvm::Triple::x86_64) { 845 Builder.defineMacro("__amd64__"); 846 Builder.defineMacro("__amd64"); 847 Builder.defineMacro("__x86_64"); 848 Builder.defineMacro("__x86_64__"); 849 if (getTriple().getArchName() == "x86_64h") { 850 Builder.defineMacro("__x86_64h"); 851 Builder.defineMacro("__x86_64h__"); 852 } 853 } else { 854 DefineStd(Builder, "i386", Opts); 855 } 856 857 // Subtarget options. 858 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 859 // truly should be based on -mtune options. 860 switch (CPU) { 861 case CK_Generic: 862 break; 863 case CK_i386: 864 // The rest are coming from the i386 define above. 865 Builder.defineMacro("__tune_i386__"); 866 break; 867 case CK_i486: 868 case CK_WinChipC6: 869 case CK_WinChip2: 870 case CK_C3: 871 defineCPUMacros(Builder, "i486"); 872 break; 873 case CK_PentiumMMX: 874 Builder.defineMacro("__pentium_mmx__"); 875 Builder.defineMacro("__tune_pentium_mmx__"); 876 LLVM_FALLTHROUGH; 877 case CK_i586: 878 case CK_Pentium: 879 defineCPUMacros(Builder, "i586"); 880 defineCPUMacros(Builder, "pentium"); 881 break; 882 case CK_Pentium3: 883 case CK_PentiumM: 884 Builder.defineMacro("__tune_pentium3__"); 885 LLVM_FALLTHROUGH; 886 case CK_Pentium2: 887 case CK_C3_2: 888 Builder.defineMacro("__tune_pentium2__"); 889 LLVM_FALLTHROUGH; 890 case CK_PentiumPro: 891 defineCPUMacros(Builder, "i686"); 892 defineCPUMacros(Builder, "pentiumpro"); 893 break; 894 case CK_Pentium4: 895 defineCPUMacros(Builder, "pentium4"); 896 break; 897 case CK_Yonah: 898 case CK_Prescott: 899 case CK_Nocona: 900 defineCPUMacros(Builder, "nocona"); 901 break; 902 case CK_Core2: 903 case CK_Penryn: 904 defineCPUMacros(Builder, "core2"); 905 break; 906 case CK_Bonnell: 907 defineCPUMacros(Builder, "atom"); 908 break; 909 case CK_Silvermont: 910 defineCPUMacros(Builder, "slm"); 911 break; 912 case CK_Goldmont: 913 defineCPUMacros(Builder, "goldmont"); 914 break; 915 case CK_Nehalem: 916 case CK_Westmere: 917 case CK_SandyBridge: 918 case CK_IvyBridge: 919 case CK_Haswell: 920 case CK_Broadwell: 921 case CK_SkylakeClient: 922 case CK_SkylakeServer: 923 case CK_Cannonlake: 924 case CK_Icelake: 925 // FIXME: Historically, we defined this legacy name, it would be nice to 926 // remove it at some point. We've never exposed fine-grained names for 927 // recent primary x86 CPUs, and we should keep it that way. 928 defineCPUMacros(Builder, "corei7"); 929 break; 930 case CK_KNL: 931 defineCPUMacros(Builder, "knl"); 932 break; 933 case CK_KNM: 934 break; 935 case CK_Lakemont: 936 defineCPUMacros(Builder, "i586", /*Tuning*/false); 937 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 938 Builder.defineMacro("__tune_lakemont__"); 939 break; 940 case CK_K6_2: 941 Builder.defineMacro("__k6_2__"); 942 Builder.defineMacro("__tune_k6_2__"); 943 LLVM_FALLTHROUGH; 944 case CK_K6_3: 945 if (CPU != CK_K6_2) { // In case of fallthrough 946 // FIXME: GCC may be enabling these in cases where some other k6 947 // architecture is specified but -m3dnow is explicitly provided. The 948 // exact semantics need to be determined and emulated here. 949 Builder.defineMacro("__k6_3__"); 950 Builder.defineMacro("__tune_k6_3__"); 951 } 952 LLVM_FALLTHROUGH; 953 case CK_K6: 954 defineCPUMacros(Builder, "k6"); 955 break; 956 case CK_Athlon: 957 case CK_AthlonXP: 958 defineCPUMacros(Builder, "athlon"); 959 if (SSELevel != NoSSE) { 960 Builder.defineMacro("__athlon_sse__"); 961 Builder.defineMacro("__tune_athlon_sse__"); 962 } 963 break; 964 case CK_K8: 965 case CK_K8SSE3: 966 case CK_x86_64: 967 defineCPUMacros(Builder, "k8"); 968 break; 969 case CK_AMDFAM10: 970 defineCPUMacros(Builder, "amdfam10"); 971 break; 972 case CK_BTVER1: 973 defineCPUMacros(Builder, "btver1"); 974 break; 975 case CK_BTVER2: 976 defineCPUMacros(Builder, "btver2"); 977 break; 978 case CK_BDVER1: 979 defineCPUMacros(Builder, "bdver1"); 980 break; 981 case CK_BDVER2: 982 defineCPUMacros(Builder, "bdver2"); 983 break; 984 case CK_BDVER3: 985 defineCPUMacros(Builder, "bdver3"); 986 break; 987 case CK_BDVER4: 988 defineCPUMacros(Builder, "bdver4"); 989 break; 990 case CK_ZNVER1: 991 defineCPUMacros(Builder, "znver1"); 992 break; 993 case CK_Geode: 994 defineCPUMacros(Builder, "geode"); 995 break; 996 } 997 998 // Target properties. 999 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1000 1001 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1002 // functions in glibc header files that use FP Stack inline asm which the 1003 // backend can't deal with (PR879). 1004 Builder.defineMacro("__NO_MATH_INLINES"); 1005 1006 if (HasAES) 1007 Builder.defineMacro("__AES__"); 1008 1009 if (HasVAES) 1010 Builder.defineMacro("__VAES__"); 1011 1012 if (HasPCLMUL) 1013 Builder.defineMacro("__PCLMUL__"); 1014 1015 if (HasVPCLMULQDQ) 1016 Builder.defineMacro("__VPCLMULQDQ__"); 1017 1018 if (HasLZCNT) 1019 Builder.defineMacro("__LZCNT__"); 1020 1021 if (HasRDRND) 1022 Builder.defineMacro("__RDRND__"); 1023 1024 if (HasFSGSBASE) 1025 Builder.defineMacro("__FSGSBASE__"); 1026 1027 if (HasBMI) 1028 Builder.defineMacro("__BMI__"); 1029 1030 if (HasBMI2) 1031 Builder.defineMacro("__BMI2__"); 1032 1033 if (HasPOPCNT) 1034 Builder.defineMacro("__POPCNT__"); 1035 1036 if (HasRTM) 1037 Builder.defineMacro("__RTM__"); 1038 1039 if (HasPRFCHW) 1040 Builder.defineMacro("__PRFCHW__"); 1041 1042 if (HasRDSEED) 1043 Builder.defineMacro("__RDSEED__"); 1044 1045 if (HasADX) 1046 Builder.defineMacro("__ADX__"); 1047 1048 if (HasTBM) 1049 Builder.defineMacro("__TBM__"); 1050 1051 if (HasLWP) 1052 Builder.defineMacro("__LWP__"); 1053 1054 if (HasMWAITX) 1055 Builder.defineMacro("__MWAITX__"); 1056 1057 switch (XOPLevel) { 1058 case XOP: 1059 Builder.defineMacro("__XOP__"); 1060 LLVM_FALLTHROUGH; 1061 case FMA4: 1062 Builder.defineMacro("__FMA4__"); 1063 LLVM_FALLTHROUGH; 1064 case SSE4A: 1065 Builder.defineMacro("__SSE4A__"); 1066 LLVM_FALLTHROUGH; 1067 case NoXOP: 1068 break; 1069 } 1070 1071 if (HasFMA) 1072 Builder.defineMacro("__FMA__"); 1073 1074 if (HasF16C) 1075 Builder.defineMacro("__F16C__"); 1076 1077 if (HasGFNI) 1078 Builder.defineMacro("__GFNI__"); 1079 1080 if (HasAVX512CD) 1081 Builder.defineMacro("__AVX512CD__"); 1082 if (HasAVX512VPOPCNTDQ) 1083 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1084 if (HasAVX512VNNI) 1085 Builder.defineMacro("__AVX512VNNI__"); 1086 if (HasAVX512ER) 1087 Builder.defineMacro("__AVX512ER__"); 1088 if (HasAVX512PF) 1089 Builder.defineMacro("__AVX512PF__"); 1090 if (HasAVX512DQ) 1091 Builder.defineMacro("__AVX512DQ__"); 1092 if (HasAVX512BITALG) 1093 Builder.defineMacro("__AVX512BITALG__"); 1094 if (HasAVX512BW) 1095 Builder.defineMacro("__AVX512BW__"); 1096 if (HasAVX512VL) 1097 Builder.defineMacro("__AVX512VL__"); 1098 if (HasAVX512VBMI) 1099 Builder.defineMacro("__AVX512VBMI__"); 1100 if (HasAVX512VBMI2) 1101 Builder.defineMacro("__AVX512VBMI2__"); 1102 if (HasAVX512IFMA) 1103 Builder.defineMacro("__AVX512IFMA__"); 1104 1105 if (HasSHA) 1106 Builder.defineMacro("__SHA__"); 1107 1108 if (HasFXSR) 1109 Builder.defineMacro("__FXSR__"); 1110 if (HasXSAVE) 1111 Builder.defineMacro("__XSAVE__"); 1112 if (HasXSAVEOPT) 1113 Builder.defineMacro("__XSAVEOPT__"); 1114 if (HasXSAVEC) 1115 Builder.defineMacro("__XSAVEC__"); 1116 if (HasXSAVES) 1117 Builder.defineMacro("__XSAVES__"); 1118 if (HasPKU) 1119 Builder.defineMacro("__PKU__"); 1120 if (HasCLFLUSHOPT) 1121 Builder.defineMacro("__CLFLUSHOPT__"); 1122 if (HasCLWB) 1123 Builder.defineMacro("__CLWB__"); 1124 if (HasMPX) 1125 Builder.defineMacro("__MPX__"); 1126 if (HasSHSTK) 1127 Builder.defineMacro("__SHSTK__"); 1128 if (HasIBT) 1129 Builder.defineMacro("__IBT__"); 1130 if (HasSGX) 1131 Builder.defineMacro("__SGX__"); 1132 if (HasPREFETCHWT1) 1133 Builder.defineMacro("__PREFETCHWT1__"); 1134 if (HasCLZERO) 1135 Builder.defineMacro("__CLZERO__"); 1136 if (HasRDPID) 1137 Builder.defineMacro("__RDPID__"); 1138 1139 // Each case falls through to the previous one here. 1140 switch (SSELevel) { 1141 case AVX512F: 1142 Builder.defineMacro("__AVX512F__"); 1143 LLVM_FALLTHROUGH; 1144 case AVX2: 1145 Builder.defineMacro("__AVX2__"); 1146 LLVM_FALLTHROUGH; 1147 case AVX: 1148 Builder.defineMacro("__AVX__"); 1149 LLVM_FALLTHROUGH; 1150 case SSE42: 1151 Builder.defineMacro("__SSE4_2__"); 1152 LLVM_FALLTHROUGH; 1153 case SSE41: 1154 Builder.defineMacro("__SSE4_1__"); 1155 LLVM_FALLTHROUGH; 1156 case SSSE3: 1157 Builder.defineMacro("__SSSE3__"); 1158 LLVM_FALLTHROUGH; 1159 case SSE3: 1160 Builder.defineMacro("__SSE3__"); 1161 LLVM_FALLTHROUGH; 1162 case SSE2: 1163 Builder.defineMacro("__SSE2__"); 1164 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1165 LLVM_FALLTHROUGH; 1166 case SSE1: 1167 Builder.defineMacro("__SSE__"); 1168 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1169 LLVM_FALLTHROUGH; 1170 case NoSSE: 1171 break; 1172 } 1173 1174 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1175 switch (SSELevel) { 1176 case AVX512F: 1177 case AVX2: 1178 case AVX: 1179 case SSE42: 1180 case SSE41: 1181 case SSSE3: 1182 case SSE3: 1183 case SSE2: 1184 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1185 break; 1186 case SSE1: 1187 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1188 break; 1189 default: 1190 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1191 break; 1192 } 1193 } 1194 1195 // Each case falls through to the previous one here. 1196 switch (MMX3DNowLevel) { 1197 case AMD3DNowAthlon: 1198 Builder.defineMacro("__3dNOW_A__"); 1199 LLVM_FALLTHROUGH; 1200 case AMD3DNow: 1201 Builder.defineMacro("__3dNOW__"); 1202 LLVM_FALLTHROUGH; 1203 case MMX: 1204 Builder.defineMacro("__MMX__"); 1205 LLVM_FALLTHROUGH; 1206 case NoMMX3DNow: 1207 break; 1208 } 1209 1210 if (CPU >= CK_i486) { 1211 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1212 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1213 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1214 } 1215 if (CPU >= CK_i586) 1216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1217 if (HasCX16) 1218 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1219 1220 if (HasFloat128) 1221 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1222 } 1223 1224 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1225 return llvm::StringSwitch<bool>(Name) 1226 .Case("3dnow", true) 1227 .Case("3dnowa", true) 1228 .Case("adx", true) 1229 .Case("aes", true) 1230 .Case("avx", true) 1231 .Case("avx2", true) 1232 .Case("avx512f", true) 1233 .Case("avx512cd", true) 1234 .Case("avx512vpopcntdq", true) 1235 .Case("avx512vnni", true) 1236 .Case("avx512er", true) 1237 .Case("avx512pf", true) 1238 .Case("avx512dq", true) 1239 .Case("avx512bitalg", true) 1240 .Case("avx512bw", true) 1241 .Case("avx512vl", true) 1242 .Case("avx512vbmi", true) 1243 .Case("avx512vbmi2", true) 1244 .Case("avx512ifma", true) 1245 .Case("bmi", true) 1246 .Case("bmi2", true) 1247 .Case("clflushopt", true) 1248 .Case("clwb", true) 1249 .Case("clzero", true) 1250 .Case("cx16", true) 1251 .Case("f16c", true) 1252 .Case("fma", true) 1253 .Case("fma4", true) 1254 .Case("fsgsbase", true) 1255 .Case("fxsr", true) 1256 .Case("gfni", true) 1257 .Case("lwp", true) 1258 .Case("lzcnt", true) 1259 .Case("mmx", true) 1260 .Case("movbe", true) 1261 .Case("mpx", true) 1262 .Case("mwaitx", true) 1263 .Case("pclmul", true) 1264 .Case("pku", true) 1265 .Case("popcnt", true) 1266 .Case("prefetchwt1", true) 1267 .Case("prfchw", true) 1268 .Case("rdpid", true) 1269 .Case("rdrnd", true) 1270 .Case("rdseed", true) 1271 .Case("rtm", true) 1272 .Case("sgx", true) 1273 .Case("sha", true) 1274 .Case("shstk", true) 1275 .Case("sse", true) 1276 .Case("sse2", true) 1277 .Case("sse3", true) 1278 .Case("ssse3", true) 1279 .Case("sse4", true) 1280 .Case("sse4.1", true) 1281 .Case("sse4.2", true) 1282 .Case("sse4a", true) 1283 .Case("tbm", true) 1284 .Case("vaes", true) 1285 .Case("vpclmulqdq", true) 1286 .Case("x87", true) 1287 .Case("xop", true) 1288 .Case("xsave", true) 1289 .Case("xsavec", true) 1290 .Case("xsaves", true) 1291 .Case("xsaveopt", true) 1292 .Default(false); 1293 } 1294 1295 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1296 return llvm::StringSwitch<bool>(Feature) 1297 .Case("adx", HasADX) 1298 .Case("aes", HasAES) 1299 .Case("avx", SSELevel >= AVX) 1300 .Case("avx2", SSELevel >= AVX2) 1301 .Case("avx512f", SSELevel >= AVX512F) 1302 .Case("avx512cd", HasAVX512CD) 1303 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1304 .Case("avx512vnni", HasAVX512VNNI) 1305 .Case("avx512er", HasAVX512ER) 1306 .Case("avx512pf", HasAVX512PF) 1307 .Case("avx512dq", HasAVX512DQ) 1308 .Case("avx512bitalg", HasAVX512BITALG) 1309 .Case("avx512bw", HasAVX512BW) 1310 .Case("avx512vl", HasAVX512VL) 1311 .Case("avx512vbmi", HasAVX512VBMI) 1312 .Case("avx512vbmi2", HasAVX512VBMI2) 1313 .Case("avx512ifma", HasAVX512IFMA) 1314 .Case("bmi", HasBMI) 1315 .Case("bmi2", HasBMI2) 1316 .Case("clflushopt", HasCLFLUSHOPT) 1317 .Case("clwb", HasCLWB) 1318 .Case("clzero", HasCLZERO) 1319 .Case("cx16", HasCX16) 1320 .Case("f16c", HasF16C) 1321 .Case("fma", HasFMA) 1322 .Case("fma4", XOPLevel >= FMA4) 1323 .Case("fsgsbase", HasFSGSBASE) 1324 .Case("fxsr", HasFXSR) 1325 .Case("gfni", HasGFNI) 1326 .Case("ibt", HasIBT) 1327 .Case("lwp", HasLWP) 1328 .Case("lzcnt", HasLZCNT) 1329 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1330 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1331 .Case("mmx", MMX3DNowLevel >= MMX) 1332 .Case("movbe", HasMOVBE) 1333 .Case("mpx", HasMPX) 1334 .Case("mwaitx", HasMWAITX) 1335 .Case("pclmul", HasPCLMUL) 1336 .Case("pku", HasPKU) 1337 .Case("popcnt", HasPOPCNT) 1338 .Case("prefetchwt1", HasPREFETCHWT1) 1339 .Case("prfchw", HasPRFCHW) 1340 .Case("rdpid", HasRDPID) 1341 .Case("rdrnd", HasRDRND) 1342 .Case("rdseed", HasRDSEED) 1343 .Case("retpoline", HasRetpoline) 1344 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1345 .Case("rtm", HasRTM) 1346 .Case("sgx", HasSGX) 1347 .Case("sha", HasSHA) 1348 .Case("shstk", HasSHSTK) 1349 .Case("sse", SSELevel >= SSE1) 1350 .Case("sse2", SSELevel >= SSE2) 1351 .Case("sse3", SSELevel >= SSE3) 1352 .Case("ssse3", SSELevel >= SSSE3) 1353 .Case("sse4.1", SSELevel >= SSE41) 1354 .Case("sse4.2", SSELevel >= SSE42) 1355 .Case("sse4a", XOPLevel >= SSE4A) 1356 .Case("tbm", HasTBM) 1357 .Case("vaes", HasVAES) 1358 .Case("vpclmulqdq", HasVPCLMULQDQ) 1359 .Case("x86", true) 1360 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1361 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1362 .Case("xop", XOPLevel >= XOP) 1363 .Case("xsave", HasXSAVE) 1364 .Case("xsavec", HasXSAVEC) 1365 .Case("xsaves", HasXSAVES) 1366 .Case("xsaveopt", HasXSAVEOPT) 1367 .Default(false); 1368 } 1369 1370 // We can't use a generic validation scheme for the features accepted here 1371 // versus subtarget features accepted in the target attribute because the 1372 // bitfield structure that's initialized in the runtime only supports the 1373 // below currently rather than the full range of subtarget features. (See 1374 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1375 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1376 return llvm::StringSwitch<bool>(FeatureStr) 1377 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1378 #include "llvm/Support/X86TargetParser.def" 1379 .Default(false); 1380 } 1381 1382 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1383 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1384 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1385 #include "llvm/Support/X86TargetParser.def" 1386 ; 1387 // Note, this function should only be used after ensuring the value is 1388 // correct, so it asserts if the value is out of range. 1389 } 1390 1391 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1392 enum class FeatPriority { 1393 #define FEATURE(FEAT) FEAT, 1394 #include "clang/Basic/X86Target.def" 1395 }; 1396 switch (Feat) { 1397 #define FEATURE(FEAT) \ 1398 case llvm::X86::FEAT: \ 1399 return static_cast<unsigned>(FeatPriority::FEAT); 1400 #include "clang/Basic/X86Target.def" 1401 default: 1402 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1403 } 1404 } 1405 1406 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1407 // Valid CPUs have a 'key feature' that compares just better than its key 1408 // feature. 1409 CPUKind Kind = getCPUKind(Name); 1410 if (Kind != CK_Generic) { 1411 switch (Kind) { 1412 default: 1413 llvm_unreachable( 1414 "CPU Type without a key feature used in 'target' attribute"); 1415 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1416 case CK_##ENUM: \ 1417 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1418 #include "clang/Basic/X86Target.def" 1419 } 1420 } 1421 1422 // Now we know we have a feature, so get its priority and shift it a few so 1423 // that we have sufficient room for the CPUs (above). 1424 return getFeaturePriority(getFeature(Name)) << 1; 1425 } 1426 1427 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1428 switch (Kind) { 1429 case CK_Generic: 1430 return ""; 1431 #define PROC(ENUM, STRING, IS64BIT) \ 1432 case CK_##ENUM: \ 1433 return STRING; 1434 #include "clang/Basic/X86Target.def" 1435 } 1436 llvm_unreachable("Invalid CPUKind"); 1437 } 1438 1439 // We can't use a generic validation scheme for the cpus accepted here 1440 // versus subtarget cpus accepted in the target attribute because the 1441 // variables intitialized by the runtime only support the below currently 1442 // rather than the full range of cpus. 1443 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1444 return llvm::StringSwitch<bool>(FeatureStr) 1445 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1446 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1447 .Cases(STR, ALIAS, true) 1448 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1449 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1450 #include "llvm/Support/X86TargetParser.def" 1451 .Default(false); 1452 } 1453 1454 bool X86TargetInfo::validateAsmConstraint( 1455 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1456 switch (*Name) { 1457 default: 1458 return false; 1459 // Constant constraints. 1460 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1461 // instructions. 1462 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1463 // x86_64 instructions. 1464 case 's': 1465 Info.setRequiresImmediate(); 1466 return true; 1467 case 'I': 1468 Info.setRequiresImmediate(0, 31); 1469 return true; 1470 case 'J': 1471 Info.setRequiresImmediate(0, 63); 1472 return true; 1473 case 'K': 1474 Info.setRequiresImmediate(-128, 127); 1475 return true; 1476 case 'L': 1477 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1478 return true; 1479 case 'M': 1480 Info.setRequiresImmediate(0, 3); 1481 return true; 1482 case 'N': 1483 Info.setRequiresImmediate(0, 255); 1484 return true; 1485 case 'O': 1486 Info.setRequiresImmediate(0, 127); 1487 return true; 1488 // Register constraints. 1489 case 'Y': // 'Y' is the first character for several 2-character constraints. 1490 // Shift the pointer to the second character of the constraint. 1491 Name++; 1492 switch (*Name) { 1493 default: 1494 return false; 1495 case 'z': 1496 case '0': // First SSE register. 1497 case '2': 1498 case 't': // Any SSE register, when SSE2 is enabled. 1499 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1500 case 'm': // Any MMX register, when inter-unit moves enabled. 1501 case 'k': // AVX512 arch mask registers: k1-k7. 1502 Info.setAllowsRegister(); 1503 return true; 1504 } 1505 case 'f': // Any x87 floating point stack register. 1506 // Constraint 'f' cannot be used for output operands. 1507 if (Info.ConstraintStr[0] == '=') 1508 return false; 1509 Info.setAllowsRegister(); 1510 return true; 1511 case 'a': // eax. 1512 case 'b': // ebx. 1513 case 'c': // ecx. 1514 case 'd': // edx. 1515 case 'S': // esi. 1516 case 'D': // edi. 1517 case 'A': // edx:eax. 1518 case 't': // Top of floating point stack. 1519 case 'u': // Second from top of floating point stack. 1520 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1521 case 'y': // Any MMX register. 1522 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1523 case 'x': // Any SSE register. 1524 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1525 // for intermideate k reg operations). 1526 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1527 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1528 case 'l': // "Index" registers: any general register that can be used as an 1529 // index in a base+index memory access. 1530 Info.setAllowsRegister(); 1531 return true; 1532 // Floating point constant constraints. 1533 case 'C': // SSE floating point constant. 1534 case 'G': // x87 floating point constant. 1535 return true; 1536 } 1537 } 1538 1539 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1540 unsigned Size) const { 1541 // Strip off constraint modifiers. 1542 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1543 Constraint = Constraint.substr(1); 1544 1545 return validateOperandSize(Constraint, Size); 1546 } 1547 1548 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1549 unsigned Size) const { 1550 return validateOperandSize(Constraint, Size); 1551 } 1552 1553 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1554 unsigned Size) const { 1555 switch (Constraint[0]) { 1556 default: 1557 break; 1558 case 'k': 1559 // Registers k0-k7 (AVX512) size limit is 64 bit. 1560 case 'y': 1561 return Size <= 64; 1562 case 'f': 1563 case 't': 1564 case 'u': 1565 return Size <= 128; 1566 case 'Y': 1567 // 'Y' is the first character for several 2-character constraints. 1568 switch (Constraint[1]) { 1569 default: 1570 return false; 1571 case 'm': 1572 // 'Ym' is synonymous with 'y'. 1573 case 'k': 1574 return Size <= 64; 1575 case 'z': 1576 case '0': 1577 // XMM0 1578 if (SSELevel >= SSE1) 1579 return Size <= 128U; 1580 return false; 1581 case 'i': 1582 case 't': 1583 case '2': 1584 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1585 if (SSELevel < SSE2) 1586 return false; 1587 break; 1588 } 1589 case 'v': 1590 case 'x': 1591 if (SSELevel >= AVX512F) 1592 // 512-bit zmm registers can be used if target supports AVX512F. 1593 return Size <= 512U; 1594 else if (SSELevel >= AVX) 1595 // 256-bit ymm registers can be used if target supports AVX. 1596 return Size <= 256U; 1597 return Size <= 128U; 1598 1599 } 1600 1601 return true; 1602 } 1603 1604 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1605 switch (*Constraint) { 1606 case 'a': 1607 return std::string("{ax}"); 1608 case 'b': 1609 return std::string("{bx}"); 1610 case 'c': 1611 return std::string("{cx}"); 1612 case 'd': 1613 return std::string("{dx}"); 1614 case 'S': 1615 return std::string("{si}"); 1616 case 'D': 1617 return std::string("{di}"); 1618 case 'p': // address 1619 return std::string("im"); 1620 case 't': // top of floating point stack. 1621 return std::string("{st}"); 1622 case 'u': // second from top of floating point stack. 1623 return std::string("{st(1)}"); // second from top of floating point stack. 1624 case 'Y': 1625 switch (Constraint[1]) { 1626 default: 1627 // Break from inner switch and fall through (copy single char), 1628 // continue parsing after copying the current constraint into 1629 // the return string. 1630 break; 1631 case 'k': 1632 case 'm': 1633 case 'i': 1634 case 't': 1635 case 'z': 1636 case '0': 1637 case '2': 1638 // "^" hints llvm that this is a 2 letter constraint. 1639 // "Constraint++" is used to promote the string iterator 1640 // to the next constraint. 1641 return std::string("^") + std::string(Constraint++, 2); 1642 } 1643 LLVM_FALLTHROUGH; 1644 default: 1645 return std::string(1, *Constraint); 1646 } 1647 } 1648 1649 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1650 // Perform any per-CPU checks necessary to determine if this CPU is 1651 // acceptable. 1652 switch (Kind) { 1653 case CK_Generic: 1654 // No processor selected! 1655 return false; 1656 #define PROC(ENUM, STRING, IS64BIT) \ 1657 case CK_##ENUM: \ 1658 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1659 #include "clang/Basic/X86Target.def" 1660 } 1661 llvm_unreachable("Unhandled CPU kind"); 1662 } 1663 1664 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1665 #define PROC(ENUM, STRING, IS64BIT) \ 1666 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1667 Values.emplace_back(STRING); 1668 // Go through CPUKind checking to ensure that the alias is de-aliased and 1669 // 64 bit-ness is checked. 1670 #define PROC_ALIAS(ENUM, ALIAS) \ 1671 if (checkCPUKind(getCPUKind(ALIAS))) \ 1672 Values.emplace_back(ALIAS); 1673 #include "clang/Basic/X86Target.def" 1674 } 1675 1676 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1677 return llvm::StringSwitch<CPUKind>(CPU) 1678 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1679 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1680 #include "clang/Basic/X86Target.def" 1681 .Default(CK_Generic); 1682 } 1683 1684 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1685 return llvm::makeArrayRef(GCCRegNames); 1686 } 1687 1688 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1689 return llvm::makeArrayRef(AddlRegNames); 1690 } 1691 1692 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1693 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1694 Builtin::FirstTSBuiltin + 1); 1695 } 1696 1697 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1698 return llvm::makeArrayRef(BuiltinInfoX86, 1699 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1700 } 1701