1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::checkCFProtectionReturnSupported( 106 DiagnosticsEngine &Diags) const { 107 if (HasSHSTK) 108 return true; 109 110 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 111 << "-mshstk"; 112 return false; 113 } 114 115 bool X86TargetInfo::checkCFProtectionBranchSupported( 116 DiagnosticsEngine &Diags) const { 117 if (HasIBT) 118 return true; 119 120 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 121 << "-mibt"; 122 return false; 123 } 124 125 bool X86TargetInfo::initFeatureMap( 126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 127 const std::vector<std::string> &FeaturesVec) const { 128 // FIXME: This *really* should not be here. 129 // X86_64 always has SSE2. 130 if (getTriple().getArch() == llvm::Triple::x86_64) 131 setFeatureEnabledImpl(Features, "sse2", true); 132 133 const CPUKind Kind = getCPUKind(CPU); 134 135 // Enable X87 for all X86 processors but Lakemont. 136 if (Kind != CK_Lakemont) 137 setFeatureEnabledImpl(Features, "x87", true); 138 139 switch (Kind) { 140 case CK_Generic: 141 case CK_i386: 142 case CK_i486: 143 case CK_i586: 144 case CK_Pentium: 145 case CK_PentiumPro: 146 case CK_Lakemont: 147 break; 148 149 case CK_PentiumMMX: 150 case CK_Pentium2: 151 case CK_K6: 152 case CK_WinChipC6: 153 setFeatureEnabledImpl(Features, "mmx", true); 154 break; 155 156 case CK_IcelakeServer: 157 setFeatureEnabledImpl(Features, "wbnoinvd", true); 158 LLVM_FALLTHROUGH; 159 case CK_IcelakeClient: 160 setFeatureEnabledImpl(Features, "vaes", true); 161 setFeatureEnabledImpl(Features, "gfni", true); 162 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 163 setFeatureEnabledImpl(Features, "avx512bitalg", true); 164 setFeatureEnabledImpl(Features, "avx512vnni", true); 165 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 166 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 167 setFeatureEnabledImpl(Features, "rdpid", true); 168 LLVM_FALLTHROUGH; 169 case CK_Cannonlake: 170 setFeatureEnabledImpl(Features, "avx512ifma", true); 171 setFeatureEnabledImpl(Features, "avx512vbmi", true); 172 setFeatureEnabledImpl(Features, "sha", true); 173 LLVM_FALLTHROUGH; 174 case CK_SkylakeServer: 175 setFeatureEnabledImpl(Features, "avx512f", true); 176 setFeatureEnabledImpl(Features, "avx512cd", true); 177 setFeatureEnabledImpl(Features, "avx512dq", true); 178 setFeatureEnabledImpl(Features, "avx512bw", true); 179 setFeatureEnabledImpl(Features, "avx512vl", true); 180 setFeatureEnabledImpl(Features, "pku", true); 181 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 182 setFeatureEnabledImpl(Features, "clwb", true); 183 LLVM_FALLTHROUGH; 184 case CK_SkylakeClient: 185 setFeatureEnabledImpl(Features, "xsavec", true); 186 setFeatureEnabledImpl(Features, "xsaves", true); 187 setFeatureEnabledImpl(Features, "mpx", true); 188 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 189 setFeatureEnabledImpl(Features, "sgx", true); 190 setFeatureEnabledImpl(Features, "clflushopt", true); 191 setFeatureEnabledImpl(Features, "rtm", true); 192 LLVM_FALLTHROUGH; 193 case CK_Broadwell: 194 setFeatureEnabledImpl(Features, "rdseed", true); 195 setFeatureEnabledImpl(Features, "adx", true); 196 setFeatureEnabledImpl(Features, "prfchw", true); 197 LLVM_FALLTHROUGH; 198 case CK_Haswell: 199 setFeatureEnabledImpl(Features, "avx2", true); 200 setFeatureEnabledImpl(Features, "lzcnt", true); 201 setFeatureEnabledImpl(Features, "bmi", true); 202 setFeatureEnabledImpl(Features, "bmi2", true); 203 setFeatureEnabledImpl(Features, "fma", true); 204 setFeatureEnabledImpl(Features, "movbe", true); 205 LLVM_FALLTHROUGH; 206 case CK_IvyBridge: 207 setFeatureEnabledImpl(Features, "rdrnd", true); 208 setFeatureEnabledImpl(Features, "f16c", true); 209 setFeatureEnabledImpl(Features, "fsgsbase", true); 210 LLVM_FALLTHROUGH; 211 case CK_SandyBridge: 212 setFeatureEnabledImpl(Features, "avx", true); 213 setFeatureEnabledImpl(Features, "xsave", true); 214 setFeatureEnabledImpl(Features, "xsaveopt", true); 215 LLVM_FALLTHROUGH; 216 case CK_Westmere: 217 setFeatureEnabledImpl(Features, "aes", true); 218 setFeatureEnabledImpl(Features, "pclmul", true); 219 LLVM_FALLTHROUGH; 220 case CK_Nehalem: 221 setFeatureEnabledImpl(Features, "sse4.2", true); 222 LLVM_FALLTHROUGH; 223 case CK_Penryn: 224 setFeatureEnabledImpl(Features, "sse4.1", true); 225 LLVM_FALLTHROUGH; 226 case CK_Core2: 227 setFeatureEnabledImpl(Features, "ssse3", true); 228 setFeatureEnabledImpl(Features, "sahf", true); 229 LLVM_FALLTHROUGH; 230 case CK_Yonah: 231 case CK_Prescott: 232 case CK_Nocona: 233 setFeatureEnabledImpl(Features, "sse3", true); 234 setFeatureEnabledImpl(Features, "cx16", true); 235 LLVM_FALLTHROUGH; 236 case CK_PentiumM: 237 case CK_Pentium4: 238 case CK_x86_64: 239 setFeatureEnabledImpl(Features, "sse2", true); 240 LLVM_FALLTHROUGH; 241 case CK_Pentium3: 242 case CK_C3_2: 243 setFeatureEnabledImpl(Features, "sse", true); 244 setFeatureEnabledImpl(Features, "fxsr", true); 245 break; 246 247 case CK_Tremont: 248 setFeatureEnabledImpl(Features, "cldemote", true); 249 setFeatureEnabledImpl(Features, "movdiri", true); 250 setFeatureEnabledImpl(Features, "movdir64b", true); 251 setFeatureEnabledImpl(Features, "gfni", true); 252 setFeatureEnabledImpl(Features, "waitpkg", true); 253 LLVM_FALLTHROUGH; 254 case CK_GoldmontPlus: 255 setFeatureEnabledImpl(Features, "rdpid", true); 256 setFeatureEnabledImpl(Features, "sgx", true); 257 LLVM_FALLTHROUGH; 258 case CK_Goldmont: 259 setFeatureEnabledImpl(Features, "sha", true); 260 setFeatureEnabledImpl(Features, "rdseed", true); 261 setFeatureEnabledImpl(Features, "xsave", true); 262 setFeatureEnabledImpl(Features, "xsaveopt", true); 263 setFeatureEnabledImpl(Features, "xsavec", true); 264 setFeatureEnabledImpl(Features, "xsaves", true); 265 setFeatureEnabledImpl(Features, "clflushopt", true); 266 setFeatureEnabledImpl(Features, "mpx", true); 267 setFeatureEnabledImpl(Features, "fsgsbase", true); 268 LLVM_FALLTHROUGH; 269 case CK_Silvermont: 270 setFeatureEnabledImpl(Features, "rdrnd", true); 271 setFeatureEnabledImpl(Features, "aes", true); 272 setFeatureEnabledImpl(Features, "pclmul", true); 273 setFeatureEnabledImpl(Features, "sse4.2", true); 274 setFeatureEnabledImpl(Features, "prfchw", true); 275 LLVM_FALLTHROUGH; 276 case CK_Bonnell: 277 setFeatureEnabledImpl(Features, "movbe", true); 278 setFeatureEnabledImpl(Features, "ssse3", true); 279 setFeatureEnabledImpl(Features, "fxsr", true); 280 setFeatureEnabledImpl(Features, "cx16", true); 281 setFeatureEnabledImpl(Features, "sahf", true); 282 break; 283 284 case CK_KNM: 285 // TODO: Add avx5124fmaps/avx5124vnniw. 286 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 287 LLVM_FALLTHROUGH; 288 case CK_KNL: 289 setFeatureEnabledImpl(Features, "avx512f", true); 290 setFeatureEnabledImpl(Features, "avx512cd", true); 291 setFeatureEnabledImpl(Features, "avx512er", true); 292 setFeatureEnabledImpl(Features, "avx512pf", true); 293 setFeatureEnabledImpl(Features, "prfchw", true); 294 setFeatureEnabledImpl(Features, "prefetchwt1", true); 295 setFeatureEnabledImpl(Features, "fxsr", true); 296 setFeatureEnabledImpl(Features, "rdseed", true); 297 setFeatureEnabledImpl(Features, "adx", true); 298 setFeatureEnabledImpl(Features, "lzcnt", true); 299 setFeatureEnabledImpl(Features, "bmi", true); 300 setFeatureEnabledImpl(Features, "bmi2", true); 301 setFeatureEnabledImpl(Features, "rtm", true); 302 setFeatureEnabledImpl(Features, "fma", true); 303 setFeatureEnabledImpl(Features, "rdrnd", true); 304 setFeatureEnabledImpl(Features, "f16c", true); 305 setFeatureEnabledImpl(Features, "fsgsbase", true); 306 setFeatureEnabledImpl(Features, "aes", true); 307 setFeatureEnabledImpl(Features, "pclmul", true); 308 setFeatureEnabledImpl(Features, "cx16", true); 309 setFeatureEnabledImpl(Features, "xsaveopt", true); 310 setFeatureEnabledImpl(Features, "xsave", true); 311 setFeatureEnabledImpl(Features, "movbe", true); 312 setFeatureEnabledImpl(Features, "sahf", true); 313 break; 314 315 case CK_K6_2: 316 case CK_K6_3: 317 case CK_WinChip2: 318 case CK_C3: 319 setFeatureEnabledImpl(Features, "3dnow", true); 320 break; 321 322 case CK_AMDFAM10: 323 setFeatureEnabledImpl(Features, "sse4a", true); 324 setFeatureEnabledImpl(Features, "lzcnt", true); 325 setFeatureEnabledImpl(Features, "popcnt", true); 326 setFeatureEnabledImpl(Features, "sahf", true); 327 LLVM_FALLTHROUGH; 328 case CK_K8SSE3: 329 setFeatureEnabledImpl(Features, "sse3", true); 330 LLVM_FALLTHROUGH; 331 case CK_K8: 332 setFeatureEnabledImpl(Features, "sse2", true); 333 LLVM_FALLTHROUGH; 334 case CK_AthlonXP: 335 setFeatureEnabledImpl(Features, "sse", true); 336 setFeatureEnabledImpl(Features, "fxsr", true); 337 LLVM_FALLTHROUGH; 338 case CK_Athlon: 339 case CK_Geode: 340 setFeatureEnabledImpl(Features, "3dnowa", true); 341 break; 342 343 case CK_BTVER2: 344 setFeatureEnabledImpl(Features, "avx", true); 345 setFeatureEnabledImpl(Features, "aes", true); 346 setFeatureEnabledImpl(Features, "pclmul", true); 347 setFeatureEnabledImpl(Features, "bmi", true); 348 setFeatureEnabledImpl(Features, "f16c", true); 349 setFeatureEnabledImpl(Features, "xsaveopt", true); 350 setFeatureEnabledImpl(Features, "movbe", true); 351 LLVM_FALLTHROUGH; 352 case CK_BTVER1: 353 setFeatureEnabledImpl(Features, "ssse3", true); 354 setFeatureEnabledImpl(Features, "sse4a", true); 355 setFeatureEnabledImpl(Features, "lzcnt", true); 356 setFeatureEnabledImpl(Features, "popcnt", true); 357 setFeatureEnabledImpl(Features, "prfchw", true); 358 setFeatureEnabledImpl(Features, "cx16", true); 359 setFeatureEnabledImpl(Features, "fxsr", true); 360 setFeatureEnabledImpl(Features, "sahf", true); 361 break; 362 363 case CK_ZNVER1: 364 setFeatureEnabledImpl(Features, "adx", true); 365 setFeatureEnabledImpl(Features, "aes", true); 366 setFeatureEnabledImpl(Features, "avx2", true); 367 setFeatureEnabledImpl(Features, "bmi", true); 368 setFeatureEnabledImpl(Features, "bmi2", true); 369 setFeatureEnabledImpl(Features, "clflushopt", true); 370 setFeatureEnabledImpl(Features, "clzero", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "f16c", true); 373 setFeatureEnabledImpl(Features, "fma", true); 374 setFeatureEnabledImpl(Features, "fsgsbase", true); 375 setFeatureEnabledImpl(Features, "fxsr", true); 376 setFeatureEnabledImpl(Features, "lzcnt", true); 377 setFeatureEnabledImpl(Features, "mwaitx", true); 378 setFeatureEnabledImpl(Features, "movbe", true); 379 setFeatureEnabledImpl(Features, "pclmul", true); 380 setFeatureEnabledImpl(Features, "popcnt", true); 381 setFeatureEnabledImpl(Features, "prfchw", true); 382 setFeatureEnabledImpl(Features, "rdrnd", true); 383 setFeatureEnabledImpl(Features, "rdseed", true); 384 setFeatureEnabledImpl(Features, "sahf", true); 385 setFeatureEnabledImpl(Features, "sha", true); 386 setFeatureEnabledImpl(Features, "sse4a", true); 387 setFeatureEnabledImpl(Features, "xsave", true); 388 setFeatureEnabledImpl(Features, "xsavec", true); 389 setFeatureEnabledImpl(Features, "xsaveopt", true); 390 setFeatureEnabledImpl(Features, "xsaves", true); 391 break; 392 393 case CK_BDVER4: 394 setFeatureEnabledImpl(Features, "avx2", true); 395 setFeatureEnabledImpl(Features, "bmi2", true); 396 setFeatureEnabledImpl(Features, "mwaitx", true); 397 LLVM_FALLTHROUGH; 398 case CK_BDVER3: 399 setFeatureEnabledImpl(Features, "fsgsbase", true); 400 setFeatureEnabledImpl(Features, "xsaveopt", true); 401 LLVM_FALLTHROUGH; 402 case CK_BDVER2: 403 setFeatureEnabledImpl(Features, "bmi", true); 404 setFeatureEnabledImpl(Features, "fma", true); 405 setFeatureEnabledImpl(Features, "f16c", true); 406 setFeatureEnabledImpl(Features, "tbm", true); 407 LLVM_FALLTHROUGH; 408 case CK_BDVER1: 409 // xop implies avx, sse4a and fma4. 410 setFeatureEnabledImpl(Features, "xop", true); 411 setFeatureEnabledImpl(Features, "lwp", true); 412 setFeatureEnabledImpl(Features, "lzcnt", true); 413 setFeatureEnabledImpl(Features, "aes", true); 414 setFeatureEnabledImpl(Features, "pclmul", true); 415 setFeatureEnabledImpl(Features, "prfchw", true); 416 setFeatureEnabledImpl(Features, "cx16", true); 417 setFeatureEnabledImpl(Features, "fxsr", true); 418 setFeatureEnabledImpl(Features, "xsave", true); 419 setFeatureEnabledImpl(Features, "sahf", true); 420 break; 421 } 422 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 423 return false; 424 425 // Can't do this earlier because we need to be able to explicitly enable 426 // or disable these features and the things that they depend upon. 427 428 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 429 auto I = Features.find("sse4.2"); 430 if (I != Features.end() && I->getValue() && 431 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 432 FeaturesVec.end()) 433 Features["popcnt"] = true; 434 435 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 436 I = Features.find("3dnow"); 437 if (I != Features.end() && I->getValue() && 438 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 439 FeaturesVec.end()) 440 Features["prfchw"] = true; 441 442 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 443 // then enable MMX. 444 I = Features.find("sse"); 445 if (I != Features.end() && I->getValue() && 446 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 447 FeaturesVec.end()) 448 Features["mmx"] = true; 449 450 return true; 451 } 452 453 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 454 X86SSEEnum Level, bool Enabled) { 455 if (Enabled) { 456 switch (Level) { 457 case AVX512F: 458 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 459 LLVM_FALLTHROUGH; 460 case AVX2: 461 Features["avx2"] = true; 462 LLVM_FALLTHROUGH; 463 case AVX: 464 Features["avx"] = true; 465 Features["xsave"] = true; 466 LLVM_FALLTHROUGH; 467 case SSE42: 468 Features["sse4.2"] = true; 469 LLVM_FALLTHROUGH; 470 case SSE41: 471 Features["sse4.1"] = true; 472 LLVM_FALLTHROUGH; 473 case SSSE3: 474 Features["ssse3"] = true; 475 LLVM_FALLTHROUGH; 476 case SSE3: 477 Features["sse3"] = true; 478 LLVM_FALLTHROUGH; 479 case SSE2: 480 Features["sse2"] = true; 481 LLVM_FALLTHROUGH; 482 case SSE1: 483 Features["sse"] = true; 484 LLVM_FALLTHROUGH; 485 case NoSSE: 486 break; 487 } 488 return; 489 } 490 491 switch (Level) { 492 case NoSSE: 493 case SSE1: 494 Features["sse"] = false; 495 LLVM_FALLTHROUGH; 496 case SSE2: 497 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 498 Features["gfni"] = false; 499 LLVM_FALLTHROUGH; 500 case SSE3: 501 Features["sse3"] = false; 502 setXOPLevel(Features, NoXOP, false); 503 LLVM_FALLTHROUGH; 504 case SSSE3: 505 Features["ssse3"] = false; 506 LLVM_FALLTHROUGH; 507 case SSE41: 508 Features["sse4.1"] = false; 509 LLVM_FALLTHROUGH; 510 case SSE42: 511 Features["sse4.2"] = false; 512 LLVM_FALLTHROUGH; 513 case AVX: 514 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 515 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 516 setXOPLevel(Features, FMA4, false); 517 LLVM_FALLTHROUGH; 518 case AVX2: 519 Features["avx2"] = false; 520 LLVM_FALLTHROUGH; 521 case AVX512F: 522 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 523 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 524 Features["avx512vl"] = Features["avx512vbmi"] = 525 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 526 Features["avx512bitalg"] = Features["avx512vnni"] = 527 Features["avx512vbmi2"] = false; 528 break; 529 } 530 } 531 532 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 533 MMX3DNowEnum Level, bool Enabled) { 534 if (Enabled) { 535 switch (Level) { 536 case AMD3DNowAthlon: 537 Features["3dnowa"] = true; 538 LLVM_FALLTHROUGH; 539 case AMD3DNow: 540 Features["3dnow"] = true; 541 LLVM_FALLTHROUGH; 542 case MMX: 543 Features["mmx"] = true; 544 LLVM_FALLTHROUGH; 545 case NoMMX3DNow: 546 break; 547 } 548 return; 549 } 550 551 switch (Level) { 552 case NoMMX3DNow: 553 case MMX: 554 Features["mmx"] = false; 555 LLVM_FALLTHROUGH; 556 case AMD3DNow: 557 Features["3dnow"] = false; 558 LLVM_FALLTHROUGH; 559 case AMD3DNowAthlon: 560 Features["3dnowa"] = false; 561 break; 562 } 563 } 564 565 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 566 bool Enabled) { 567 if (Enabled) { 568 switch (Level) { 569 case XOP: 570 Features["xop"] = true; 571 LLVM_FALLTHROUGH; 572 case FMA4: 573 Features["fma4"] = true; 574 setSSELevel(Features, AVX, true); 575 LLVM_FALLTHROUGH; 576 case SSE4A: 577 Features["sse4a"] = true; 578 setSSELevel(Features, SSE3, true); 579 LLVM_FALLTHROUGH; 580 case NoXOP: 581 break; 582 } 583 return; 584 } 585 586 switch (Level) { 587 case NoXOP: 588 case SSE4A: 589 Features["sse4a"] = false; 590 LLVM_FALLTHROUGH; 591 case FMA4: 592 Features["fma4"] = false; 593 LLVM_FALLTHROUGH; 594 case XOP: 595 Features["xop"] = false; 596 break; 597 } 598 } 599 600 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 601 StringRef Name, bool Enabled) { 602 // This is a bit of a hack to deal with the sse4 target feature when used 603 // as part of the target attribute. We handle sse4 correctly everywhere 604 // else. See below for more information on how we handle the sse4 options. 605 if (Name != "sse4") 606 Features[Name] = Enabled; 607 608 if (Name == "mmx") { 609 setMMXLevel(Features, MMX, Enabled); 610 } else if (Name == "sse") { 611 setSSELevel(Features, SSE1, Enabled); 612 } else if (Name == "sse2") { 613 setSSELevel(Features, SSE2, Enabled); 614 } else if (Name == "sse3") { 615 setSSELevel(Features, SSE3, Enabled); 616 } else if (Name == "ssse3") { 617 setSSELevel(Features, SSSE3, Enabled); 618 } else if (Name == "sse4.2") { 619 setSSELevel(Features, SSE42, Enabled); 620 } else if (Name == "sse4.1") { 621 setSSELevel(Features, SSE41, Enabled); 622 } else if (Name == "3dnow") { 623 setMMXLevel(Features, AMD3DNow, Enabled); 624 } else if (Name == "3dnowa") { 625 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 626 } else if (Name == "aes") { 627 if (Enabled) 628 setSSELevel(Features, SSE2, Enabled); 629 else 630 Features["vaes"] = false; 631 } else if (Name == "vaes") { 632 if (Enabled) { 633 setSSELevel(Features, AVX, Enabled); 634 Features["aes"] = true; 635 } 636 } else if (Name == "pclmul") { 637 if (Enabled) 638 setSSELevel(Features, SSE2, Enabled); 639 else 640 Features["vpclmulqdq"] = false; 641 } else if (Name == "vpclmulqdq") { 642 if (Enabled) { 643 setSSELevel(Features, AVX, Enabled); 644 Features["pclmul"] = true; 645 } 646 } else if (Name == "gfni") { 647 if (Enabled) 648 setSSELevel(Features, SSE2, Enabled); 649 } else if (Name == "avx") { 650 setSSELevel(Features, AVX, Enabled); 651 } else if (Name == "avx2") { 652 setSSELevel(Features, AVX2, Enabled); 653 } else if (Name == "avx512f") { 654 setSSELevel(Features, AVX512F, Enabled); 655 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 656 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 657 Name == "avx512vbmi" || Name == "avx512ifma" || 658 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 659 Name == "avx512vnni" || Name == "avx512vbmi2") { 660 if (Enabled) 661 setSSELevel(Features, AVX512F, Enabled); 662 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 663 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 664 Features["avx512bw"] = true; 665 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 666 if (Name == "avx512bw" && !Enabled) 667 Features["avx512vbmi"] = Features["avx512vbmi2"] = 668 Features["avx512bitalg"] = false; 669 } else if (Name == "fma") { 670 if (Enabled) 671 setSSELevel(Features, AVX, Enabled); 672 else 673 setSSELevel(Features, AVX512F, Enabled); 674 } else if (Name == "fma4") { 675 setXOPLevel(Features, FMA4, Enabled); 676 } else if (Name == "xop") { 677 setXOPLevel(Features, XOP, Enabled); 678 } else if (Name == "sse4a") { 679 setXOPLevel(Features, SSE4A, Enabled); 680 } else if (Name == "f16c") { 681 if (Enabled) 682 setSSELevel(Features, AVX, Enabled); 683 else 684 setSSELevel(Features, AVX512F, Enabled); 685 } else if (Name == "sha") { 686 if (Enabled) 687 setSSELevel(Features, SSE2, Enabled); 688 } else if (Name == "sse4") { 689 // We can get here via the __target__ attribute since that's not controlled 690 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 691 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 692 // disabled. 693 if (Enabled) 694 setSSELevel(Features, SSE42, Enabled); 695 else 696 setSSELevel(Features, SSE41, Enabled); 697 } else if (Name == "xsave") { 698 if (!Enabled) 699 Features["xsaveopt"] = false; 700 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 701 if (Enabled) 702 Features["xsave"] = true; 703 } 704 } 705 706 /// handleTargetFeatures - Perform initialization based on the user 707 /// configured set of features. 708 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 709 DiagnosticsEngine &Diags) { 710 for (const auto &Feature : Features) { 711 if (Feature[0] != '+') 712 continue; 713 714 if (Feature == "+aes") { 715 HasAES = true; 716 } else if (Feature == "+vaes") { 717 HasVAES = true; 718 } else if (Feature == "+pclmul") { 719 HasPCLMUL = true; 720 } else if (Feature == "+vpclmulqdq") { 721 HasVPCLMULQDQ = true; 722 } else if (Feature == "+lzcnt") { 723 HasLZCNT = true; 724 } else if (Feature == "+rdrnd") { 725 HasRDRND = true; 726 } else if (Feature == "+fsgsbase") { 727 HasFSGSBASE = true; 728 } else if (Feature == "+bmi") { 729 HasBMI = true; 730 } else if (Feature == "+bmi2") { 731 HasBMI2 = true; 732 } else if (Feature == "+popcnt") { 733 HasPOPCNT = true; 734 } else if (Feature == "+rtm") { 735 HasRTM = true; 736 } else if (Feature == "+prfchw") { 737 HasPRFCHW = true; 738 } else if (Feature == "+rdseed") { 739 HasRDSEED = true; 740 } else if (Feature == "+adx") { 741 HasADX = true; 742 } else if (Feature == "+tbm") { 743 HasTBM = true; 744 } else if (Feature == "+lwp") { 745 HasLWP = true; 746 } else if (Feature == "+fma") { 747 HasFMA = true; 748 } else if (Feature == "+f16c") { 749 HasF16C = true; 750 } else if (Feature == "+gfni") { 751 HasGFNI = true; 752 } else if (Feature == "+avx512cd") { 753 HasAVX512CD = true; 754 } else if (Feature == "+avx512vpopcntdq") { 755 HasAVX512VPOPCNTDQ = true; 756 } else if (Feature == "+avx512vnni") { 757 HasAVX512VNNI = true; 758 } else if (Feature == "+avx512er") { 759 HasAVX512ER = true; 760 } else if (Feature == "+avx512pf") { 761 HasAVX512PF = true; 762 } else if (Feature == "+avx512dq") { 763 HasAVX512DQ = true; 764 } else if (Feature == "+avx512bitalg") { 765 HasAVX512BITALG = true; 766 } else if (Feature == "+avx512bw") { 767 HasAVX512BW = true; 768 } else if (Feature == "+avx512vl") { 769 HasAVX512VL = true; 770 } else if (Feature == "+avx512vbmi") { 771 HasAVX512VBMI = true; 772 } else if (Feature == "+avx512vbmi2") { 773 HasAVX512VBMI2 = true; 774 } else if (Feature == "+avx512ifma") { 775 HasAVX512IFMA = true; 776 } else if (Feature == "+sha") { 777 HasSHA = true; 778 } else if (Feature == "+mpx") { 779 HasMPX = true; 780 } else if (Feature == "+shstk") { 781 HasSHSTK = true; 782 } else if (Feature == "+ibt") { 783 HasIBT = true; 784 } else if (Feature == "+movbe") { 785 HasMOVBE = true; 786 } else if (Feature == "+sgx") { 787 HasSGX = true; 788 } else if (Feature == "+cx16") { 789 HasCX16 = true; 790 } else if (Feature == "+fxsr") { 791 HasFXSR = true; 792 } else if (Feature == "+xsave") { 793 HasXSAVE = true; 794 } else if (Feature == "+xsaveopt") { 795 HasXSAVEOPT = true; 796 } else if (Feature == "+xsavec") { 797 HasXSAVEC = true; 798 } else if (Feature == "+xsaves") { 799 HasXSAVES = true; 800 } else if (Feature == "+mwaitx") { 801 HasMWAITX = true; 802 } else if (Feature == "+pku") { 803 HasPKU = true; 804 } else if (Feature == "+clflushopt") { 805 HasCLFLUSHOPT = true; 806 } else if (Feature == "+clwb") { 807 HasCLWB = true; 808 } else if (Feature == "+wbnoinvd") { 809 HasWBNOINVD = true; 810 } else if (Feature == "+prefetchwt1") { 811 HasPREFETCHWT1 = true; 812 } else if (Feature == "+clzero") { 813 HasCLZERO = true; 814 } else if (Feature == "+cldemote") { 815 HasCLDEMOTE = true; 816 } else if (Feature == "+rdpid") { 817 HasRDPID = true; 818 } else if (Feature == "+retpoline") { 819 HasRetpoline = true; 820 } else if (Feature == "+retpoline-external-thunk") { 821 HasRetpolineExternalThunk = true; 822 } else if (Feature == "+sahf") { 823 HasLAHFSAHF = true; 824 } else if (Feature == "+waitpkg") { 825 HasWAITPKG = true; 826 } else if (Feature == "+movdiri") { 827 HasMOVDIRI = true; 828 } else if (Feature == "+movdir64b") { 829 HasMOVDIR64B = true; 830 } 831 832 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 833 .Case("+avx512f", AVX512F) 834 .Case("+avx2", AVX2) 835 .Case("+avx", AVX) 836 .Case("+sse4.2", SSE42) 837 .Case("+sse4.1", SSE41) 838 .Case("+ssse3", SSSE3) 839 .Case("+sse3", SSE3) 840 .Case("+sse2", SSE2) 841 .Case("+sse", SSE1) 842 .Default(NoSSE); 843 SSELevel = std::max(SSELevel, Level); 844 845 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 846 .Case("+3dnowa", AMD3DNowAthlon) 847 .Case("+3dnow", AMD3DNow) 848 .Case("+mmx", MMX) 849 .Default(NoMMX3DNow); 850 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 851 852 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 853 .Case("+xop", XOP) 854 .Case("+fma4", FMA4) 855 .Case("+sse4a", SSE4A) 856 .Default(NoXOP); 857 XOPLevel = std::max(XOPLevel, XLevel); 858 } 859 860 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 861 // matches the selected sse level. 862 if ((FPMath == FP_SSE && SSELevel < SSE1) || 863 (FPMath == FP_387 && SSELevel >= SSE1)) { 864 Diags.Report(diag::err_target_unsupported_fpmath) 865 << (FPMath == FP_SSE ? "sse" : "387"); 866 return false; 867 } 868 869 SimdDefaultAlign = 870 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 871 return true; 872 } 873 874 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 875 /// definitions for this particular subtarget. 876 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 877 MacroBuilder &Builder) const { 878 // Target identification. 879 if (getTriple().getArch() == llvm::Triple::x86_64) { 880 Builder.defineMacro("__amd64__"); 881 Builder.defineMacro("__amd64"); 882 Builder.defineMacro("__x86_64"); 883 Builder.defineMacro("__x86_64__"); 884 if (getTriple().getArchName() == "x86_64h") { 885 Builder.defineMacro("__x86_64h"); 886 Builder.defineMacro("__x86_64h__"); 887 } 888 } else { 889 DefineStd(Builder, "i386", Opts); 890 } 891 892 // Subtarget options. 893 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 894 // truly should be based on -mtune options. 895 switch (CPU) { 896 case CK_Generic: 897 break; 898 case CK_i386: 899 // The rest are coming from the i386 define above. 900 Builder.defineMacro("__tune_i386__"); 901 break; 902 case CK_i486: 903 case CK_WinChipC6: 904 case CK_WinChip2: 905 case CK_C3: 906 defineCPUMacros(Builder, "i486"); 907 break; 908 case CK_PentiumMMX: 909 Builder.defineMacro("__pentium_mmx__"); 910 Builder.defineMacro("__tune_pentium_mmx__"); 911 LLVM_FALLTHROUGH; 912 case CK_i586: 913 case CK_Pentium: 914 defineCPUMacros(Builder, "i586"); 915 defineCPUMacros(Builder, "pentium"); 916 break; 917 case CK_Pentium3: 918 case CK_PentiumM: 919 Builder.defineMacro("__tune_pentium3__"); 920 LLVM_FALLTHROUGH; 921 case CK_Pentium2: 922 case CK_C3_2: 923 Builder.defineMacro("__tune_pentium2__"); 924 LLVM_FALLTHROUGH; 925 case CK_PentiumPro: 926 defineCPUMacros(Builder, "i686"); 927 defineCPUMacros(Builder, "pentiumpro"); 928 break; 929 case CK_Pentium4: 930 defineCPUMacros(Builder, "pentium4"); 931 break; 932 case CK_Yonah: 933 case CK_Prescott: 934 case CK_Nocona: 935 defineCPUMacros(Builder, "nocona"); 936 break; 937 case CK_Core2: 938 case CK_Penryn: 939 defineCPUMacros(Builder, "core2"); 940 break; 941 case CK_Bonnell: 942 defineCPUMacros(Builder, "atom"); 943 break; 944 case CK_Silvermont: 945 defineCPUMacros(Builder, "slm"); 946 break; 947 case CK_Goldmont: 948 defineCPUMacros(Builder, "goldmont"); 949 break; 950 case CK_GoldmontPlus: 951 defineCPUMacros(Builder, "goldmont_plus"); 952 break; 953 case CK_Tremont: 954 defineCPUMacros(Builder, "tremont"); 955 break; 956 case CK_Nehalem: 957 case CK_Westmere: 958 case CK_SandyBridge: 959 case CK_IvyBridge: 960 case CK_Haswell: 961 case CK_Broadwell: 962 case CK_SkylakeClient: 963 case CK_SkylakeServer: 964 case CK_Cannonlake: 965 case CK_IcelakeClient: 966 case CK_IcelakeServer: 967 // FIXME: Historically, we defined this legacy name, it would be nice to 968 // remove it at some point. We've never exposed fine-grained names for 969 // recent primary x86 CPUs, and we should keep it that way. 970 defineCPUMacros(Builder, "corei7"); 971 break; 972 case CK_KNL: 973 defineCPUMacros(Builder, "knl"); 974 break; 975 case CK_KNM: 976 break; 977 case CK_Lakemont: 978 defineCPUMacros(Builder, "i586", /*Tuning*/false); 979 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 980 Builder.defineMacro("__tune_lakemont__"); 981 break; 982 case CK_K6_2: 983 Builder.defineMacro("__k6_2__"); 984 Builder.defineMacro("__tune_k6_2__"); 985 LLVM_FALLTHROUGH; 986 case CK_K6_3: 987 if (CPU != CK_K6_2) { // In case of fallthrough 988 // FIXME: GCC may be enabling these in cases where some other k6 989 // architecture is specified but -m3dnow is explicitly provided. The 990 // exact semantics need to be determined and emulated here. 991 Builder.defineMacro("__k6_3__"); 992 Builder.defineMacro("__tune_k6_3__"); 993 } 994 LLVM_FALLTHROUGH; 995 case CK_K6: 996 defineCPUMacros(Builder, "k6"); 997 break; 998 case CK_Athlon: 999 case CK_AthlonXP: 1000 defineCPUMacros(Builder, "athlon"); 1001 if (SSELevel != NoSSE) { 1002 Builder.defineMacro("__athlon_sse__"); 1003 Builder.defineMacro("__tune_athlon_sse__"); 1004 } 1005 break; 1006 case CK_K8: 1007 case CK_K8SSE3: 1008 case CK_x86_64: 1009 defineCPUMacros(Builder, "k8"); 1010 break; 1011 case CK_AMDFAM10: 1012 defineCPUMacros(Builder, "amdfam10"); 1013 break; 1014 case CK_BTVER1: 1015 defineCPUMacros(Builder, "btver1"); 1016 break; 1017 case CK_BTVER2: 1018 defineCPUMacros(Builder, "btver2"); 1019 break; 1020 case CK_BDVER1: 1021 defineCPUMacros(Builder, "bdver1"); 1022 break; 1023 case CK_BDVER2: 1024 defineCPUMacros(Builder, "bdver2"); 1025 break; 1026 case CK_BDVER3: 1027 defineCPUMacros(Builder, "bdver3"); 1028 break; 1029 case CK_BDVER4: 1030 defineCPUMacros(Builder, "bdver4"); 1031 break; 1032 case CK_ZNVER1: 1033 defineCPUMacros(Builder, "znver1"); 1034 break; 1035 case CK_Geode: 1036 defineCPUMacros(Builder, "geode"); 1037 break; 1038 } 1039 1040 // Target properties. 1041 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1042 1043 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1044 // functions in glibc header files that use FP Stack inline asm which the 1045 // backend can't deal with (PR879). 1046 Builder.defineMacro("__NO_MATH_INLINES"); 1047 1048 if (HasAES) 1049 Builder.defineMacro("__AES__"); 1050 1051 if (HasVAES) 1052 Builder.defineMacro("__VAES__"); 1053 1054 if (HasPCLMUL) 1055 Builder.defineMacro("__PCLMUL__"); 1056 1057 if (HasVPCLMULQDQ) 1058 Builder.defineMacro("__VPCLMULQDQ__"); 1059 1060 if (HasLZCNT) 1061 Builder.defineMacro("__LZCNT__"); 1062 1063 if (HasRDRND) 1064 Builder.defineMacro("__RDRND__"); 1065 1066 if (HasFSGSBASE) 1067 Builder.defineMacro("__FSGSBASE__"); 1068 1069 if (HasBMI) 1070 Builder.defineMacro("__BMI__"); 1071 1072 if (HasBMI2) 1073 Builder.defineMacro("__BMI2__"); 1074 1075 if (HasPOPCNT) 1076 Builder.defineMacro("__POPCNT__"); 1077 1078 if (HasRTM) 1079 Builder.defineMacro("__RTM__"); 1080 1081 if (HasPRFCHW) 1082 Builder.defineMacro("__PRFCHW__"); 1083 1084 if (HasRDSEED) 1085 Builder.defineMacro("__RDSEED__"); 1086 1087 if (HasADX) 1088 Builder.defineMacro("__ADX__"); 1089 1090 if (HasTBM) 1091 Builder.defineMacro("__TBM__"); 1092 1093 if (HasLWP) 1094 Builder.defineMacro("__LWP__"); 1095 1096 if (HasMWAITX) 1097 Builder.defineMacro("__MWAITX__"); 1098 1099 switch (XOPLevel) { 1100 case XOP: 1101 Builder.defineMacro("__XOP__"); 1102 LLVM_FALLTHROUGH; 1103 case FMA4: 1104 Builder.defineMacro("__FMA4__"); 1105 LLVM_FALLTHROUGH; 1106 case SSE4A: 1107 Builder.defineMacro("__SSE4A__"); 1108 LLVM_FALLTHROUGH; 1109 case NoXOP: 1110 break; 1111 } 1112 1113 if (HasFMA) 1114 Builder.defineMacro("__FMA__"); 1115 1116 if (HasF16C) 1117 Builder.defineMacro("__F16C__"); 1118 1119 if (HasGFNI) 1120 Builder.defineMacro("__GFNI__"); 1121 1122 if (HasAVX512CD) 1123 Builder.defineMacro("__AVX512CD__"); 1124 if (HasAVX512VPOPCNTDQ) 1125 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1126 if (HasAVX512VNNI) 1127 Builder.defineMacro("__AVX512VNNI__"); 1128 if (HasAVX512ER) 1129 Builder.defineMacro("__AVX512ER__"); 1130 if (HasAVX512PF) 1131 Builder.defineMacro("__AVX512PF__"); 1132 if (HasAVX512DQ) 1133 Builder.defineMacro("__AVX512DQ__"); 1134 if (HasAVX512BITALG) 1135 Builder.defineMacro("__AVX512BITALG__"); 1136 if (HasAVX512BW) 1137 Builder.defineMacro("__AVX512BW__"); 1138 if (HasAVX512VL) 1139 Builder.defineMacro("__AVX512VL__"); 1140 if (HasAVX512VBMI) 1141 Builder.defineMacro("__AVX512VBMI__"); 1142 if (HasAVX512VBMI2) 1143 Builder.defineMacro("__AVX512VBMI2__"); 1144 if (HasAVX512IFMA) 1145 Builder.defineMacro("__AVX512IFMA__"); 1146 1147 if (HasSHA) 1148 Builder.defineMacro("__SHA__"); 1149 1150 if (HasFXSR) 1151 Builder.defineMacro("__FXSR__"); 1152 if (HasXSAVE) 1153 Builder.defineMacro("__XSAVE__"); 1154 if (HasXSAVEOPT) 1155 Builder.defineMacro("__XSAVEOPT__"); 1156 if (HasXSAVEC) 1157 Builder.defineMacro("__XSAVEC__"); 1158 if (HasXSAVES) 1159 Builder.defineMacro("__XSAVES__"); 1160 if (HasPKU) 1161 Builder.defineMacro("__PKU__"); 1162 if (HasCLFLUSHOPT) 1163 Builder.defineMacro("__CLFLUSHOPT__"); 1164 if (HasCLWB) 1165 Builder.defineMacro("__CLWB__"); 1166 if (HasWBNOINVD) 1167 Builder.defineMacro("__WBNOINVD__"); 1168 if (HasMPX) 1169 Builder.defineMacro("__MPX__"); 1170 if (HasSHSTK) 1171 Builder.defineMacro("__SHSTK__"); 1172 if (HasIBT) 1173 Builder.defineMacro("__IBT__"); 1174 if (HasSGX) 1175 Builder.defineMacro("__SGX__"); 1176 if (HasPREFETCHWT1) 1177 Builder.defineMacro("__PREFETCHWT1__"); 1178 if (HasCLZERO) 1179 Builder.defineMacro("__CLZERO__"); 1180 if (HasRDPID) 1181 Builder.defineMacro("__RDPID__"); 1182 if (HasCLDEMOTE) 1183 Builder.defineMacro("__CLDEMOTE__"); 1184 if (HasWAITPKG) 1185 Builder.defineMacro("__WAITPKG__"); 1186 if (HasMOVDIRI) 1187 Builder.defineMacro("__MOVDIRI__"); 1188 if (HasMOVDIR64B) 1189 Builder.defineMacro("__MOVDIR64B__"); 1190 1191 // Each case falls through to the previous one here. 1192 switch (SSELevel) { 1193 case AVX512F: 1194 Builder.defineMacro("__AVX512F__"); 1195 LLVM_FALLTHROUGH; 1196 case AVX2: 1197 Builder.defineMacro("__AVX2__"); 1198 LLVM_FALLTHROUGH; 1199 case AVX: 1200 Builder.defineMacro("__AVX__"); 1201 LLVM_FALLTHROUGH; 1202 case SSE42: 1203 Builder.defineMacro("__SSE4_2__"); 1204 LLVM_FALLTHROUGH; 1205 case SSE41: 1206 Builder.defineMacro("__SSE4_1__"); 1207 LLVM_FALLTHROUGH; 1208 case SSSE3: 1209 Builder.defineMacro("__SSSE3__"); 1210 LLVM_FALLTHROUGH; 1211 case SSE3: 1212 Builder.defineMacro("__SSE3__"); 1213 LLVM_FALLTHROUGH; 1214 case SSE2: 1215 Builder.defineMacro("__SSE2__"); 1216 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1217 LLVM_FALLTHROUGH; 1218 case SSE1: 1219 Builder.defineMacro("__SSE__"); 1220 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1221 LLVM_FALLTHROUGH; 1222 case NoSSE: 1223 break; 1224 } 1225 1226 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1227 switch (SSELevel) { 1228 case AVX512F: 1229 case AVX2: 1230 case AVX: 1231 case SSE42: 1232 case SSE41: 1233 case SSSE3: 1234 case SSE3: 1235 case SSE2: 1236 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1237 break; 1238 case SSE1: 1239 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1240 break; 1241 default: 1242 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1243 break; 1244 } 1245 } 1246 1247 // Each case falls through to the previous one here. 1248 switch (MMX3DNowLevel) { 1249 case AMD3DNowAthlon: 1250 Builder.defineMacro("__3dNOW_A__"); 1251 LLVM_FALLTHROUGH; 1252 case AMD3DNow: 1253 Builder.defineMacro("__3dNOW__"); 1254 LLVM_FALLTHROUGH; 1255 case MMX: 1256 Builder.defineMacro("__MMX__"); 1257 LLVM_FALLTHROUGH; 1258 case NoMMX3DNow: 1259 break; 1260 } 1261 1262 if (CPU >= CK_i486) { 1263 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1264 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1265 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1266 } 1267 if (CPU >= CK_i586) 1268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1269 if (HasCX16) 1270 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1271 1272 if (HasFloat128) 1273 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1274 } 1275 1276 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1277 return llvm::StringSwitch<bool>(Name) 1278 .Case("3dnow", true) 1279 .Case("3dnowa", true) 1280 .Case("adx", true) 1281 .Case("aes", true) 1282 .Case("avx", true) 1283 .Case("avx2", true) 1284 .Case("avx512f", true) 1285 .Case("avx512cd", true) 1286 .Case("avx512vpopcntdq", true) 1287 .Case("avx512vnni", true) 1288 .Case("avx512er", true) 1289 .Case("avx512pf", true) 1290 .Case("avx512dq", true) 1291 .Case("avx512bitalg", true) 1292 .Case("avx512bw", true) 1293 .Case("avx512vl", true) 1294 .Case("avx512vbmi", true) 1295 .Case("avx512vbmi2", true) 1296 .Case("avx512ifma", true) 1297 .Case("bmi", true) 1298 .Case("bmi2", true) 1299 .Case("cldemote", true) 1300 .Case("clflushopt", true) 1301 .Case("clwb", true) 1302 .Case("clzero", true) 1303 .Case("cx16", true) 1304 .Case("f16c", true) 1305 .Case("fma", true) 1306 .Case("fma4", true) 1307 .Case("fsgsbase", true) 1308 .Case("fxsr", true) 1309 .Case("gfni", true) 1310 .Case("lwp", true) 1311 .Case("lzcnt", true) 1312 .Case("mmx", true) 1313 .Case("movbe", true) 1314 .Case("movdiri", true) 1315 .Case("movdir64b", true) 1316 .Case("mpx", true) 1317 .Case("mwaitx", true) 1318 .Case("pclmul", true) 1319 .Case("pku", true) 1320 .Case("popcnt", true) 1321 .Case("prefetchwt1", true) 1322 .Case("prfchw", true) 1323 .Case("rdpid", true) 1324 .Case("rdrnd", true) 1325 .Case("rdseed", true) 1326 .Case("rtm", true) 1327 .Case("sahf", true) 1328 .Case("sgx", true) 1329 .Case("sha", true) 1330 .Case("shstk", true) 1331 .Case("sse", true) 1332 .Case("sse2", true) 1333 .Case("sse3", true) 1334 .Case("ssse3", true) 1335 .Case("sse4", true) 1336 .Case("sse4.1", true) 1337 .Case("sse4.2", true) 1338 .Case("sse4a", true) 1339 .Case("tbm", true) 1340 .Case("vaes", true) 1341 .Case("vpclmulqdq", true) 1342 .Case("wbnoinvd", true) 1343 .Case("waitpkg", true) 1344 .Case("x87", true) 1345 .Case("xop", true) 1346 .Case("xsave", true) 1347 .Case("xsavec", true) 1348 .Case("xsaves", true) 1349 .Case("xsaveopt", true) 1350 .Default(false); 1351 } 1352 1353 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1354 return llvm::StringSwitch<bool>(Feature) 1355 .Case("adx", HasADX) 1356 .Case("aes", HasAES) 1357 .Case("avx", SSELevel >= AVX) 1358 .Case("avx2", SSELevel >= AVX2) 1359 .Case("avx512f", SSELevel >= AVX512F) 1360 .Case("avx512cd", HasAVX512CD) 1361 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1362 .Case("avx512vnni", HasAVX512VNNI) 1363 .Case("avx512er", HasAVX512ER) 1364 .Case("avx512pf", HasAVX512PF) 1365 .Case("avx512dq", HasAVX512DQ) 1366 .Case("avx512bitalg", HasAVX512BITALG) 1367 .Case("avx512bw", HasAVX512BW) 1368 .Case("avx512vl", HasAVX512VL) 1369 .Case("avx512vbmi", HasAVX512VBMI) 1370 .Case("avx512vbmi2", HasAVX512VBMI2) 1371 .Case("avx512ifma", HasAVX512IFMA) 1372 .Case("bmi", HasBMI) 1373 .Case("bmi2", HasBMI2) 1374 .Case("cldemote", HasCLDEMOTE) 1375 .Case("clflushopt", HasCLFLUSHOPT) 1376 .Case("clwb", HasCLWB) 1377 .Case("clzero", HasCLZERO) 1378 .Case("cx16", HasCX16) 1379 .Case("f16c", HasF16C) 1380 .Case("fma", HasFMA) 1381 .Case("fma4", XOPLevel >= FMA4) 1382 .Case("fsgsbase", HasFSGSBASE) 1383 .Case("fxsr", HasFXSR) 1384 .Case("gfni", HasGFNI) 1385 .Case("ibt", HasIBT) 1386 .Case("lwp", HasLWP) 1387 .Case("lzcnt", HasLZCNT) 1388 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1389 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1390 .Case("mmx", MMX3DNowLevel >= MMX) 1391 .Case("movbe", HasMOVBE) 1392 .Case("movdiri", HasMOVDIRI) 1393 .Case("movdir64b", HasMOVDIR64B) 1394 .Case("mpx", HasMPX) 1395 .Case("mwaitx", HasMWAITX) 1396 .Case("pclmul", HasPCLMUL) 1397 .Case("pku", HasPKU) 1398 .Case("popcnt", HasPOPCNT) 1399 .Case("prefetchwt1", HasPREFETCHWT1) 1400 .Case("prfchw", HasPRFCHW) 1401 .Case("rdpid", HasRDPID) 1402 .Case("rdrnd", HasRDRND) 1403 .Case("rdseed", HasRDSEED) 1404 .Case("retpoline", HasRetpoline) 1405 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1406 .Case("rtm", HasRTM) 1407 .Case("sahf", HasLAHFSAHF) 1408 .Case("sgx", HasSGX) 1409 .Case("sha", HasSHA) 1410 .Case("shstk", HasSHSTK) 1411 .Case("sse", SSELevel >= SSE1) 1412 .Case("sse2", SSELevel >= SSE2) 1413 .Case("sse3", SSELevel >= SSE3) 1414 .Case("ssse3", SSELevel >= SSSE3) 1415 .Case("sse4.1", SSELevel >= SSE41) 1416 .Case("sse4.2", SSELevel >= SSE42) 1417 .Case("sse4a", XOPLevel >= SSE4A) 1418 .Case("tbm", HasTBM) 1419 .Case("vaes", HasVAES) 1420 .Case("vpclmulqdq", HasVPCLMULQDQ) 1421 .Case("wbnoinvd", HasWBNOINVD) 1422 .Case("waitpkg", HasWAITPKG) 1423 .Case("x86", true) 1424 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1425 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1426 .Case("xop", XOPLevel >= XOP) 1427 .Case("xsave", HasXSAVE) 1428 .Case("xsavec", HasXSAVEC) 1429 .Case("xsaves", HasXSAVES) 1430 .Case("xsaveopt", HasXSAVEOPT) 1431 .Default(false); 1432 } 1433 1434 // We can't use a generic validation scheme for the features accepted here 1435 // versus subtarget features accepted in the target attribute because the 1436 // bitfield structure that's initialized in the runtime only supports the 1437 // below currently rather than the full range of subtarget features. (See 1438 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1439 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1440 return llvm::StringSwitch<bool>(FeatureStr) 1441 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1442 #include "llvm/Support/X86TargetParser.def" 1443 .Default(false); 1444 } 1445 1446 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1447 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1448 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1449 #include "llvm/Support/X86TargetParser.def" 1450 ; 1451 // Note, this function should only be used after ensuring the value is 1452 // correct, so it asserts if the value is out of range. 1453 } 1454 1455 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1456 enum class FeatPriority { 1457 #define FEATURE(FEAT) FEAT, 1458 #include "clang/Basic/X86Target.def" 1459 }; 1460 switch (Feat) { 1461 #define FEATURE(FEAT) \ 1462 case llvm::X86::FEAT: \ 1463 return static_cast<unsigned>(FeatPriority::FEAT); 1464 #include "clang/Basic/X86Target.def" 1465 default: 1466 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1467 } 1468 } 1469 1470 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1471 // Valid CPUs have a 'key feature' that compares just better than its key 1472 // feature. 1473 CPUKind Kind = getCPUKind(Name); 1474 if (Kind != CK_Generic) { 1475 switch (Kind) { 1476 default: 1477 llvm_unreachable( 1478 "CPU Type without a key feature used in 'target' attribute"); 1479 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1480 case CK_##ENUM: \ 1481 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1482 #include "clang/Basic/X86Target.def" 1483 } 1484 } 1485 1486 // Now we know we have a feature, so get its priority and shift it a few so 1487 // that we have sufficient room for the CPUs (above). 1488 return getFeaturePriority(getFeature(Name)) << 1; 1489 } 1490 1491 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1492 switch (Kind) { 1493 case CK_Generic: 1494 return ""; 1495 #define PROC(ENUM, STRING, IS64BIT) \ 1496 case CK_##ENUM: \ 1497 return STRING; 1498 #include "clang/Basic/X86Target.def" 1499 } 1500 llvm_unreachable("Invalid CPUKind"); 1501 } 1502 1503 // We can't use a generic validation scheme for the cpus accepted here 1504 // versus subtarget cpus accepted in the target attribute because the 1505 // variables intitialized by the runtime only support the below currently 1506 // rather than the full range of cpus. 1507 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1508 return llvm::StringSwitch<bool>(FeatureStr) 1509 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1510 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1511 .Cases(STR, ALIAS, true) 1512 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1513 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1514 #include "llvm/Support/X86TargetParser.def" 1515 .Default(false); 1516 } 1517 1518 bool X86TargetInfo::validateAsmConstraint( 1519 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1520 switch (*Name) { 1521 default: 1522 return false; 1523 // Constant constraints. 1524 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1525 // instructions. 1526 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1527 // x86_64 instructions. 1528 case 's': 1529 Info.setRequiresImmediate(); 1530 return true; 1531 case 'I': 1532 Info.setRequiresImmediate(0, 31); 1533 return true; 1534 case 'J': 1535 Info.setRequiresImmediate(0, 63); 1536 return true; 1537 case 'K': 1538 Info.setRequiresImmediate(-128, 127); 1539 return true; 1540 case 'L': 1541 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1542 return true; 1543 case 'M': 1544 Info.setRequiresImmediate(0, 3); 1545 return true; 1546 case 'N': 1547 Info.setRequiresImmediate(0, 255); 1548 return true; 1549 case 'O': 1550 Info.setRequiresImmediate(0, 127); 1551 return true; 1552 // Register constraints. 1553 case 'Y': // 'Y' is the first character for several 2-character constraints. 1554 // Shift the pointer to the second character of the constraint. 1555 Name++; 1556 switch (*Name) { 1557 default: 1558 return false; 1559 case 'z': 1560 case '0': // First SSE register. 1561 case '2': 1562 case 't': // Any SSE register, when SSE2 is enabled. 1563 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1564 case 'm': // Any MMX register, when inter-unit moves enabled. 1565 case 'k': // AVX512 arch mask registers: k1-k7. 1566 Info.setAllowsRegister(); 1567 return true; 1568 } 1569 case 'f': // Any x87 floating point stack register. 1570 // Constraint 'f' cannot be used for output operands. 1571 if (Info.ConstraintStr[0] == '=') 1572 return false; 1573 Info.setAllowsRegister(); 1574 return true; 1575 case 'a': // eax. 1576 case 'b': // ebx. 1577 case 'c': // ecx. 1578 case 'd': // edx. 1579 case 'S': // esi. 1580 case 'D': // edi. 1581 case 'A': // edx:eax. 1582 case 't': // Top of floating point stack. 1583 case 'u': // Second from top of floating point stack. 1584 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1585 case 'y': // Any MMX register. 1586 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1587 case 'x': // Any SSE register. 1588 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1589 // for intermideate k reg operations). 1590 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1591 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1592 case 'l': // "Index" registers: any general register that can be used as an 1593 // index in a base+index memory access. 1594 Info.setAllowsRegister(); 1595 return true; 1596 // Floating point constant constraints. 1597 case 'C': // SSE floating point constant. 1598 case 'G': // x87 floating point constant. 1599 return true; 1600 } 1601 } 1602 1603 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1604 unsigned Size) const { 1605 // Strip off constraint modifiers. 1606 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1607 Constraint = Constraint.substr(1); 1608 1609 return validateOperandSize(Constraint, Size); 1610 } 1611 1612 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1613 unsigned Size) const { 1614 return validateOperandSize(Constraint, Size); 1615 } 1616 1617 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1618 unsigned Size) const { 1619 switch (Constraint[0]) { 1620 default: 1621 break; 1622 case 'k': 1623 // Registers k0-k7 (AVX512) size limit is 64 bit. 1624 case 'y': 1625 return Size <= 64; 1626 case 'f': 1627 case 't': 1628 case 'u': 1629 return Size <= 128; 1630 case 'Y': 1631 // 'Y' is the first character for several 2-character constraints. 1632 switch (Constraint[1]) { 1633 default: 1634 return false; 1635 case 'm': 1636 // 'Ym' is synonymous with 'y'. 1637 case 'k': 1638 return Size <= 64; 1639 case 'z': 1640 case '0': 1641 // XMM0 1642 if (SSELevel >= SSE1) 1643 return Size <= 128U; 1644 return false; 1645 case 'i': 1646 case 't': 1647 case '2': 1648 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1649 if (SSELevel < SSE2) 1650 return false; 1651 break; 1652 } 1653 case 'v': 1654 case 'x': 1655 if (SSELevel >= AVX512F) 1656 // 512-bit zmm registers can be used if target supports AVX512F. 1657 return Size <= 512U; 1658 else if (SSELevel >= AVX) 1659 // 256-bit ymm registers can be used if target supports AVX. 1660 return Size <= 256U; 1661 return Size <= 128U; 1662 1663 } 1664 1665 return true; 1666 } 1667 1668 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1669 switch (*Constraint) { 1670 case 'a': 1671 return std::string("{ax}"); 1672 case 'b': 1673 return std::string("{bx}"); 1674 case 'c': 1675 return std::string("{cx}"); 1676 case 'd': 1677 return std::string("{dx}"); 1678 case 'S': 1679 return std::string("{si}"); 1680 case 'D': 1681 return std::string("{di}"); 1682 case 'p': // address 1683 return std::string("im"); 1684 case 't': // top of floating point stack. 1685 return std::string("{st}"); 1686 case 'u': // second from top of floating point stack. 1687 return std::string("{st(1)}"); // second from top of floating point stack. 1688 case 'Y': 1689 switch (Constraint[1]) { 1690 default: 1691 // Break from inner switch and fall through (copy single char), 1692 // continue parsing after copying the current constraint into 1693 // the return string. 1694 break; 1695 case 'k': 1696 case 'm': 1697 case 'i': 1698 case 't': 1699 case 'z': 1700 case '0': 1701 case '2': 1702 // "^" hints llvm that this is a 2 letter constraint. 1703 // "Constraint++" is used to promote the string iterator 1704 // to the next constraint. 1705 return std::string("^") + std::string(Constraint++, 2); 1706 } 1707 LLVM_FALLTHROUGH; 1708 default: 1709 return std::string(1, *Constraint); 1710 } 1711 } 1712 1713 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1714 // Perform any per-CPU checks necessary to determine if this CPU is 1715 // acceptable. 1716 switch (Kind) { 1717 case CK_Generic: 1718 // No processor selected! 1719 return false; 1720 #define PROC(ENUM, STRING, IS64BIT) \ 1721 case CK_##ENUM: \ 1722 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1723 #include "clang/Basic/X86Target.def" 1724 } 1725 llvm_unreachable("Unhandled CPU kind"); 1726 } 1727 1728 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1729 #define PROC(ENUM, STRING, IS64BIT) \ 1730 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1731 Values.emplace_back(STRING); 1732 // Go through CPUKind checking to ensure that the alias is de-aliased and 1733 // 64 bit-ness is checked. 1734 #define PROC_ALIAS(ENUM, ALIAS) \ 1735 if (checkCPUKind(getCPUKind(ALIAS))) \ 1736 Values.emplace_back(ALIAS); 1737 #include "clang/Basic/X86Target.def" 1738 } 1739 1740 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1741 return llvm::StringSwitch<CPUKind>(CPU) 1742 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1743 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1744 #include "clang/Basic/X86Target.def" 1745 .Default(CK_Generic); 1746 } 1747 1748 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1749 return llvm::makeArrayRef(GCCRegNames); 1750 } 1751 1752 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1753 return llvm::makeArrayRef(AddlRegNames); 1754 } 1755 1756 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1757 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1758 Builtin::FirstTSBuiltin + 1); 1759 } 1760 1761 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1762 return llvm::makeArrayRef(BuiltinInfoX86, 1763 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1764 } 1765