1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::checkCFProtectionReturnSupported( 106 DiagnosticsEngine &Diags) const { 107 if (HasSHSTK) 108 return true; 109 110 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 111 << "-mshstk"; 112 return false; 113 } 114 115 bool X86TargetInfo::checkCFProtectionBranchSupported( 116 DiagnosticsEngine &Diags) const { 117 if (HasIBT) 118 return true; 119 120 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 121 << "-mibt"; 122 return false; 123 } 124 125 bool X86TargetInfo::initFeatureMap( 126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 127 const std::vector<std::string> &FeaturesVec) const { 128 // FIXME: This *really* should not be here. 129 // X86_64 always has SSE2. 130 if (getTriple().getArch() == llvm::Triple::x86_64) 131 setFeatureEnabledImpl(Features, "sse2", true); 132 133 const CPUKind Kind = getCPUKind(CPU); 134 135 // Enable X87 for all X86 processors but Lakemont. 136 if (Kind != CK_Lakemont) 137 setFeatureEnabledImpl(Features, "x87", true); 138 139 switch (Kind) { 140 case CK_Generic: 141 case CK_i386: 142 case CK_i486: 143 case CK_i586: 144 case CK_Pentium: 145 case CK_PentiumPro: 146 case CK_Lakemont: 147 break; 148 149 case CK_PentiumMMX: 150 case CK_Pentium2: 151 case CK_K6: 152 case CK_WinChipC6: 153 setFeatureEnabledImpl(Features, "mmx", true); 154 break; 155 156 case CK_IcelakeServer: 157 setFeatureEnabledImpl(Features, "wbnoinvd", true); 158 LLVM_FALLTHROUGH; 159 case CK_IcelakeClient: 160 setFeatureEnabledImpl(Features, "vaes", true); 161 setFeatureEnabledImpl(Features, "gfni", true); 162 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 163 setFeatureEnabledImpl(Features, "avx512bitalg", true); 164 setFeatureEnabledImpl(Features, "avx512vnni", true); 165 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 166 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 167 setFeatureEnabledImpl(Features, "rdpid", true); 168 LLVM_FALLTHROUGH; 169 case CK_Cannonlake: 170 setFeatureEnabledImpl(Features, "avx512ifma", true); 171 setFeatureEnabledImpl(Features, "avx512vbmi", true); 172 setFeatureEnabledImpl(Features, "sha", true); 173 LLVM_FALLTHROUGH; 174 case CK_SkylakeServer: 175 setFeatureEnabledImpl(Features, "avx512f", true); 176 setFeatureEnabledImpl(Features, "avx512cd", true); 177 setFeatureEnabledImpl(Features, "avx512dq", true); 178 setFeatureEnabledImpl(Features, "avx512bw", true); 179 setFeatureEnabledImpl(Features, "avx512vl", true); 180 setFeatureEnabledImpl(Features, "pku", true); 181 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 182 setFeatureEnabledImpl(Features, "clwb", true); 183 LLVM_FALLTHROUGH; 184 case CK_SkylakeClient: 185 setFeatureEnabledImpl(Features, "xsavec", true); 186 setFeatureEnabledImpl(Features, "xsaves", true); 187 setFeatureEnabledImpl(Features, "mpx", true); 188 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 189 setFeatureEnabledImpl(Features, "sgx", true); 190 setFeatureEnabledImpl(Features, "clflushopt", true); 191 setFeatureEnabledImpl(Features, "rtm", true); 192 LLVM_FALLTHROUGH; 193 case CK_Broadwell: 194 setFeatureEnabledImpl(Features, "rdseed", true); 195 setFeatureEnabledImpl(Features, "adx", true); 196 setFeatureEnabledImpl(Features, "prfchw", true); 197 LLVM_FALLTHROUGH; 198 case CK_Haswell: 199 setFeatureEnabledImpl(Features, "avx2", true); 200 setFeatureEnabledImpl(Features, "lzcnt", true); 201 setFeatureEnabledImpl(Features, "bmi", true); 202 setFeatureEnabledImpl(Features, "bmi2", true); 203 setFeatureEnabledImpl(Features, "fma", true); 204 setFeatureEnabledImpl(Features, "movbe", true); 205 LLVM_FALLTHROUGH; 206 case CK_IvyBridge: 207 setFeatureEnabledImpl(Features, "rdrnd", true); 208 setFeatureEnabledImpl(Features, "f16c", true); 209 setFeatureEnabledImpl(Features, "fsgsbase", true); 210 LLVM_FALLTHROUGH; 211 case CK_SandyBridge: 212 setFeatureEnabledImpl(Features, "avx", true); 213 setFeatureEnabledImpl(Features, "xsave", true); 214 setFeatureEnabledImpl(Features, "xsaveopt", true); 215 LLVM_FALLTHROUGH; 216 case CK_Westmere: 217 setFeatureEnabledImpl(Features, "aes", true); 218 setFeatureEnabledImpl(Features, "pclmul", true); 219 LLVM_FALLTHROUGH; 220 case CK_Nehalem: 221 setFeatureEnabledImpl(Features, "sse4.2", true); 222 LLVM_FALLTHROUGH; 223 case CK_Penryn: 224 setFeatureEnabledImpl(Features, "sse4.1", true); 225 LLVM_FALLTHROUGH; 226 case CK_Core2: 227 setFeatureEnabledImpl(Features, "ssse3", true); 228 setFeatureEnabledImpl(Features, "sahf", true); 229 LLVM_FALLTHROUGH; 230 case CK_Yonah: 231 case CK_Prescott: 232 case CK_Nocona: 233 setFeatureEnabledImpl(Features, "sse3", true); 234 setFeatureEnabledImpl(Features, "cx16", true); 235 LLVM_FALLTHROUGH; 236 case CK_PentiumM: 237 case CK_Pentium4: 238 case CK_x86_64: 239 setFeatureEnabledImpl(Features, "sse2", true); 240 LLVM_FALLTHROUGH; 241 case CK_Pentium3: 242 case CK_C3_2: 243 setFeatureEnabledImpl(Features, "sse", true); 244 setFeatureEnabledImpl(Features, "fxsr", true); 245 break; 246 247 case CK_Tremont: 248 setFeatureEnabledImpl(Features, "cldemote", true); 249 setFeatureEnabledImpl(Features, "gfni", true); 250 setFeatureEnabledImpl(Features, "waitpkg", true); 251 LLVM_FALLTHROUGH; 252 case CK_GoldmontPlus: 253 setFeatureEnabledImpl(Features, "rdpid", true); 254 setFeatureEnabledImpl(Features, "sgx", true); 255 LLVM_FALLTHROUGH; 256 case CK_Goldmont: 257 setFeatureEnabledImpl(Features, "sha", true); 258 setFeatureEnabledImpl(Features, "rdseed", true); 259 setFeatureEnabledImpl(Features, "xsave", true); 260 setFeatureEnabledImpl(Features, "xsaveopt", true); 261 setFeatureEnabledImpl(Features, "xsavec", true); 262 setFeatureEnabledImpl(Features, "xsaves", true); 263 setFeatureEnabledImpl(Features, "clflushopt", true); 264 setFeatureEnabledImpl(Features, "mpx", true); 265 setFeatureEnabledImpl(Features, "fsgsbase", true); 266 LLVM_FALLTHROUGH; 267 case CK_Silvermont: 268 setFeatureEnabledImpl(Features, "rdrnd", true); 269 setFeatureEnabledImpl(Features, "aes", true); 270 setFeatureEnabledImpl(Features, "pclmul", true); 271 setFeatureEnabledImpl(Features, "sse4.2", true); 272 setFeatureEnabledImpl(Features, "prfchw", true); 273 LLVM_FALLTHROUGH; 274 case CK_Bonnell: 275 setFeatureEnabledImpl(Features, "movbe", true); 276 setFeatureEnabledImpl(Features, "ssse3", true); 277 setFeatureEnabledImpl(Features, "fxsr", true); 278 setFeatureEnabledImpl(Features, "cx16", true); 279 setFeatureEnabledImpl(Features, "sahf", true); 280 break; 281 282 case CK_KNM: 283 // TODO: Add avx5124fmaps/avx5124vnniw. 284 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 285 LLVM_FALLTHROUGH; 286 case CK_KNL: 287 setFeatureEnabledImpl(Features, "avx512f", true); 288 setFeatureEnabledImpl(Features, "avx512cd", true); 289 setFeatureEnabledImpl(Features, "avx512er", true); 290 setFeatureEnabledImpl(Features, "avx512pf", true); 291 setFeatureEnabledImpl(Features, "prfchw", true); 292 setFeatureEnabledImpl(Features, "prefetchwt1", true); 293 setFeatureEnabledImpl(Features, "fxsr", true); 294 setFeatureEnabledImpl(Features, "rdseed", true); 295 setFeatureEnabledImpl(Features, "adx", true); 296 setFeatureEnabledImpl(Features, "lzcnt", true); 297 setFeatureEnabledImpl(Features, "bmi", true); 298 setFeatureEnabledImpl(Features, "bmi2", true); 299 setFeatureEnabledImpl(Features, "rtm", true); 300 setFeatureEnabledImpl(Features, "fma", true); 301 setFeatureEnabledImpl(Features, "rdrnd", true); 302 setFeatureEnabledImpl(Features, "f16c", true); 303 setFeatureEnabledImpl(Features, "fsgsbase", true); 304 setFeatureEnabledImpl(Features, "aes", true); 305 setFeatureEnabledImpl(Features, "pclmul", true); 306 setFeatureEnabledImpl(Features, "cx16", true); 307 setFeatureEnabledImpl(Features, "xsaveopt", true); 308 setFeatureEnabledImpl(Features, "xsave", true); 309 setFeatureEnabledImpl(Features, "movbe", true); 310 setFeatureEnabledImpl(Features, "sahf", true); 311 break; 312 313 case CK_K6_2: 314 case CK_K6_3: 315 case CK_WinChip2: 316 case CK_C3: 317 setFeatureEnabledImpl(Features, "3dnow", true); 318 break; 319 320 case CK_AMDFAM10: 321 setFeatureEnabledImpl(Features, "sse4a", true); 322 setFeatureEnabledImpl(Features, "lzcnt", true); 323 setFeatureEnabledImpl(Features, "popcnt", true); 324 setFeatureEnabledImpl(Features, "sahf", true); 325 LLVM_FALLTHROUGH; 326 case CK_K8SSE3: 327 setFeatureEnabledImpl(Features, "sse3", true); 328 LLVM_FALLTHROUGH; 329 case CK_K8: 330 setFeatureEnabledImpl(Features, "sse2", true); 331 LLVM_FALLTHROUGH; 332 case CK_AthlonXP: 333 setFeatureEnabledImpl(Features, "sse", true); 334 setFeatureEnabledImpl(Features, "fxsr", true); 335 LLVM_FALLTHROUGH; 336 case CK_Athlon: 337 case CK_Geode: 338 setFeatureEnabledImpl(Features, "3dnowa", true); 339 break; 340 341 case CK_BTVER2: 342 setFeatureEnabledImpl(Features, "avx", true); 343 setFeatureEnabledImpl(Features, "aes", true); 344 setFeatureEnabledImpl(Features, "pclmul", true); 345 setFeatureEnabledImpl(Features, "bmi", true); 346 setFeatureEnabledImpl(Features, "f16c", true); 347 setFeatureEnabledImpl(Features, "xsaveopt", true); 348 setFeatureEnabledImpl(Features, "movbe", true); 349 LLVM_FALLTHROUGH; 350 case CK_BTVER1: 351 setFeatureEnabledImpl(Features, "ssse3", true); 352 setFeatureEnabledImpl(Features, "sse4a", true); 353 setFeatureEnabledImpl(Features, "lzcnt", true); 354 setFeatureEnabledImpl(Features, "popcnt", true); 355 setFeatureEnabledImpl(Features, "prfchw", true); 356 setFeatureEnabledImpl(Features, "cx16", true); 357 setFeatureEnabledImpl(Features, "fxsr", true); 358 setFeatureEnabledImpl(Features, "sahf", true); 359 break; 360 361 case CK_ZNVER1: 362 setFeatureEnabledImpl(Features, "adx", true); 363 setFeatureEnabledImpl(Features, "aes", true); 364 setFeatureEnabledImpl(Features, "avx2", true); 365 setFeatureEnabledImpl(Features, "bmi", true); 366 setFeatureEnabledImpl(Features, "bmi2", true); 367 setFeatureEnabledImpl(Features, "clflushopt", true); 368 setFeatureEnabledImpl(Features, "clzero", true); 369 setFeatureEnabledImpl(Features, "cx16", true); 370 setFeatureEnabledImpl(Features, "f16c", true); 371 setFeatureEnabledImpl(Features, "fma", true); 372 setFeatureEnabledImpl(Features, "fsgsbase", true); 373 setFeatureEnabledImpl(Features, "fxsr", true); 374 setFeatureEnabledImpl(Features, "lzcnt", true); 375 setFeatureEnabledImpl(Features, "mwaitx", true); 376 setFeatureEnabledImpl(Features, "movbe", true); 377 setFeatureEnabledImpl(Features, "pclmul", true); 378 setFeatureEnabledImpl(Features, "popcnt", true); 379 setFeatureEnabledImpl(Features, "prfchw", true); 380 setFeatureEnabledImpl(Features, "rdrnd", true); 381 setFeatureEnabledImpl(Features, "rdseed", true); 382 setFeatureEnabledImpl(Features, "sahf", true); 383 setFeatureEnabledImpl(Features, "sha", true); 384 setFeatureEnabledImpl(Features, "sse4a", true); 385 setFeatureEnabledImpl(Features, "xsave", true); 386 setFeatureEnabledImpl(Features, "xsavec", true); 387 setFeatureEnabledImpl(Features, "xsaveopt", true); 388 setFeatureEnabledImpl(Features, "xsaves", true); 389 break; 390 391 case CK_BDVER4: 392 setFeatureEnabledImpl(Features, "avx2", true); 393 setFeatureEnabledImpl(Features, "bmi2", true); 394 setFeatureEnabledImpl(Features, "mwaitx", true); 395 LLVM_FALLTHROUGH; 396 case CK_BDVER3: 397 setFeatureEnabledImpl(Features, "fsgsbase", true); 398 setFeatureEnabledImpl(Features, "xsaveopt", true); 399 LLVM_FALLTHROUGH; 400 case CK_BDVER2: 401 setFeatureEnabledImpl(Features, "bmi", true); 402 setFeatureEnabledImpl(Features, "fma", true); 403 setFeatureEnabledImpl(Features, "f16c", true); 404 setFeatureEnabledImpl(Features, "tbm", true); 405 LLVM_FALLTHROUGH; 406 case CK_BDVER1: 407 // xop implies avx, sse4a and fma4. 408 setFeatureEnabledImpl(Features, "xop", true); 409 setFeatureEnabledImpl(Features, "lwp", true); 410 setFeatureEnabledImpl(Features, "lzcnt", true); 411 setFeatureEnabledImpl(Features, "aes", true); 412 setFeatureEnabledImpl(Features, "pclmul", true); 413 setFeatureEnabledImpl(Features, "prfchw", true); 414 setFeatureEnabledImpl(Features, "cx16", true); 415 setFeatureEnabledImpl(Features, "fxsr", true); 416 setFeatureEnabledImpl(Features, "xsave", true); 417 setFeatureEnabledImpl(Features, "sahf", true); 418 break; 419 } 420 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 421 return false; 422 423 // Can't do this earlier because we need to be able to explicitly enable 424 // or disable these features and the things that they depend upon. 425 426 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 427 auto I = Features.find("sse4.2"); 428 if (I != Features.end() && I->getValue() && 429 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 430 FeaturesVec.end()) 431 Features["popcnt"] = true; 432 433 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 434 I = Features.find("3dnow"); 435 if (I != Features.end() && I->getValue() && 436 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 437 FeaturesVec.end()) 438 Features["prfchw"] = true; 439 440 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 441 // then enable MMX. 442 I = Features.find("sse"); 443 if (I != Features.end() && I->getValue() && 444 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 445 FeaturesVec.end()) 446 Features["mmx"] = true; 447 448 return true; 449 } 450 451 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 452 X86SSEEnum Level, bool Enabled) { 453 if (Enabled) { 454 switch (Level) { 455 case AVX512F: 456 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 457 LLVM_FALLTHROUGH; 458 case AVX2: 459 Features["avx2"] = true; 460 LLVM_FALLTHROUGH; 461 case AVX: 462 Features["avx"] = true; 463 Features["xsave"] = true; 464 LLVM_FALLTHROUGH; 465 case SSE42: 466 Features["sse4.2"] = true; 467 LLVM_FALLTHROUGH; 468 case SSE41: 469 Features["sse4.1"] = true; 470 LLVM_FALLTHROUGH; 471 case SSSE3: 472 Features["ssse3"] = true; 473 LLVM_FALLTHROUGH; 474 case SSE3: 475 Features["sse3"] = true; 476 LLVM_FALLTHROUGH; 477 case SSE2: 478 Features["sse2"] = true; 479 LLVM_FALLTHROUGH; 480 case SSE1: 481 Features["sse"] = true; 482 LLVM_FALLTHROUGH; 483 case NoSSE: 484 break; 485 } 486 return; 487 } 488 489 switch (Level) { 490 case NoSSE: 491 case SSE1: 492 Features["sse"] = false; 493 LLVM_FALLTHROUGH; 494 case SSE2: 495 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 496 Features["gfni"] = false; 497 LLVM_FALLTHROUGH; 498 case SSE3: 499 Features["sse3"] = false; 500 setXOPLevel(Features, NoXOP, false); 501 LLVM_FALLTHROUGH; 502 case SSSE3: 503 Features["ssse3"] = false; 504 LLVM_FALLTHROUGH; 505 case SSE41: 506 Features["sse4.1"] = false; 507 LLVM_FALLTHROUGH; 508 case SSE42: 509 Features["sse4.2"] = false; 510 LLVM_FALLTHROUGH; 511 case AVX: 512 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 513 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 514 setXOPLevel(Features, FMA4, false); 515 LLVM_FALLTHROUGH; 516 case AVX2: 517 Features["avx2"] = false; 518 LLVM_FALLTHROUGH; 519 case AVX512F: 520 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 521 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 522 Features["avx512vl"] = Features["avx512vbmi"] = 523 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 524 Features["avx512bitalg"] = Features["avx512vnni"] = 525 Features["avx512vbmi2"] = false; 526 break; 527 } 528 } 529 530 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 531 MMX3DNowEnum Level, bool Enabled) { 532 if (Enabled) { 533 switch (Level) { 534 case AMD3DNowAthlon: 535 Features["3dnowa"] = true; 536 LLVM_FALLTHROUGH; 537 case AMD3DNow: 538 Features["3dnow"] = true; 539 LLVM_FALLTHROUGH; 540 case MMX: 541 Features["mmx"] = true; 542 LLVM_FALLTHROUGH; 543 case NoMMX3DNow: 544 break; 545 } 546 return; 547 } 548 549 switch (Level) { 550 case NoMMX3DNow: 551 case MMX: 552 Features["mmx"] = false; 553 LLVM_FALLTHROUGH; 554 case AMD3DNow: 555 Features["3dnow"] = false; 556 LLVM_FALLTHROUGH; 557 case AMD3DNowAthlon: 558 Features["3dnowa"] = false; 559 break; 560 } 561 } 562 563 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 564 bool Enabled) { 565 if (Enabled) { 566 switch (Level) { 567 case XOP: 568 Features["xop"] = true; 569 LLVM_FALLTHROUGH; 570 case FMA4: 571 Features["fma4"] = true; 572 setSSELevel(Features, AVX, true); 573 LLVM_FALLTHROUGH; 574 case SSE4A: 575 Features["sse4a"] = true; 576 setSSELevel(Features, SSE3, true); 577 LLVM_FALLTHROUGH; 578 case NoXOP: 579 break; 580 } 581 return; 582 } 583 584 switch (Level) { 585 case NoXOP: 586 case SSE4A: 587 Features["sse4a"] = false; 588 LLVM_FALLTHROUGH; 589 case FMA4: 590 Features["fma4"] = false; 591 LLVM_FALLTHROUGH; 592 case XOP: 593 Features["xop"] = false; 594 break; 595 } 596 } 597 598 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 599 StringRef Name, bool Enabled) { 600 // This is a bit of a hack to deal with the sse4 target feature when used 601 // as part of the target attribute. We handle sse4 correctly everywhere 602 // else. See below for more information on how we handle the sse4 options. 603 if (Name != "sse4") 604 Features[Name] = Enabled; 605 606 if (Name == "mmx") { 607 setMMXLevel(Features, MMX, Enabled); 608 } else if (Name == "sse") { 609 setSSELevel(Features, SSE1, Enabled); 610 } else if (Name == "sse2") { 611 setSSELevel(Features, SSE2, Enabled); 612 } else if (Name == "sse3") { 613 setSSELevel(Features, SSE3, Enabled); 614 } else if (Name == "ssse3") { 615 setSSELevel(Features, SSSE3, Enabled); 616 } else if (Name == "sse4.2") { 617 setSSELevel(Features, SSE42, Enabled); 618 } else if (Name == "sse4.1") { 619 setSSELevel(Features, SSE41, Enabled); 620 } else if (Name == "3dnow") { 621 setMMXLevel(Features, AMD3DNow, Enabled); 622 } else if (Name == "3dnowa") { 623 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 624 } else if (Name == "aes") { 625 if (Enabled) 626 setSSELevel(Features, SSE2, Enabled); 627 else 628 Features["vaes"] = false; 629 } else if (Name == "vaes") { 630 if (Enabled) { 631 setSSELevel(Features, AVX, Enabled); 632 Features["aes"] = true; 633 } 634 } else if (Name == "pclmul") { 635 if (Enabled) 636 setSSELevel(Features, SSE2, Enabled); 637 else 638 Features["vpclmulqdq"] = false; 639 } else if (Name == "vpclmulqdq") { 640 if (Enabled) { 641 setSSELevel(Features, AVX, Enabled); 642 Features["pclmul"] = true; 643 } 644 } else if (Name == "gfni") { 645 if (Enabled) 646 setSSELevel(Features, SSE2, Enabled); 647 } else if (Name == "avx") { 648 setSSELevel(Features, AVX, Enabled); 649 } else if (Name == "avx2") { 650 setSSELevel(Features, AVX2, Enabled); 651 } else if (Name == "avx512f") { 652 setSSELevel(Features, AVX512F, Enabled); 653 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 654 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 655 Name == "avx512vbmi" || Name == "avx512ifma" || 656 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 657 Name == "avx512vnni" || Name == "avx512vbmi2") { 658 if (Enabled) 659 setSSELevel(Features, AVX512F, Enabled); 660 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 661 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 662 Features["avx512bw"] = true; 663 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 664 if (Name == "avx512bw" && !Enabled) 665 Features["avx512vbmi"] = Features["avx512vbmi2"] = 666 Features["avx512bitalg"] = false; 667 } else if (Name == "fma") { 668 if (Enabled) 669 setSSELevel(Features, AVX, Enabled); 670 else 671 setSSELevel(Features, AVX512F, Enabled); 672 } else if (Name == "fma4") { 673 setXOPLevel(Features, FMA4, Enabled); 674 } else if (Name == "xop") { 675 setXOPLevel(Features, XOP, Enabled); 676 } else if (Name == "sse4a") { 677 setXOPLevel(Features, SSE4A, Enabled); 678 } else if (Name == "f16c") { 679 if (Enabled) 680 setSSELevel(Features, AVX, Enabled); 681 else 682 setSSELevel(Features, AVX512F, Enabled); 683 } else if (Name == "sha") { 684 if (Enabled) 685 setSSELevel(Features, SSE2, Enabled); 686 } else if (Name == "sse4") { 687 // We can get here via the __target__ attribute since that's not controlled 688 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 689 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 690 // disabled. 691 if (Enabled) 692 setSSELevel(Features, SSE42, Enabled); 693 else 694 setSSELevel(Features, SSE41, Enabled); 695 } else if (Name == "xsave") { 696 if (!Enabled) 697 Features["xsaveopt"] = false; 698 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 699 if (Enabled) 700 Features["xsave"] = true; 701 } 702 } 703 704 /// handleTargetFeatures - Perform initialization based on the user 705 /// configured set of features. 706 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 707 DiagnosticsEngine &Diags) { 708 for (const auto &Feature : Features) { 709 if (Feature[0] != '+') 710 continue; 711 712 if (Feature == "+aes") { 713 HasAES = true; 714 } else if (Feature == "+vaes") { 715 HasVAES = true; 716 } else if (Feature == "+pclmul") { 717 HasPCLMUL = true; 718 } else if (Feature == "+vpclmulqdq") { 719 HasVPCLMULQDQ = true; 720 } else if (Feature == "+lzcnt") { 721 HasLZCNT = true; 722 } else if (Feature == "+rdrnd") { 723 HasRDRND = true; 724 } else if (Feature == "+fsgsbase") { 725 HasFSGSBASE = true; 726 } else if (Feature == "+bmi") { 727 HasBMI = true; 728 } else if (Feature == "+bmi2") { 729 HasBMI2 = true; 730 } else if (Feature == "+popcnt") { 731 HasPOPCNT = true; 732 } else if (Feature == "+rtm") { 733 HasRTM = true; 734 } else if (Feature == "+prfchw") { 735 HasPRFCHW = true; 736 } else if (Feature == "+rdseed") { 737 HasRDSEED = true; 738 } else if (Feature == "+adx") { 739 HasADX = true; 740 } else if (Feature == "+tbm") { 741 HasTBM = true; 742 } else if (Feature == "+lwp") { 743 HasLWP = true; 744 } else if (Feature == "+fma") { 745 HasFMA = true; 746 } else if (Feature == "+f16c") { 747 HasF16C = true; 748 } else if (Feature == "+gfni") { 749 HasGFNI = true; 750 } else if (Feature == "+avx512cd") { 751 HasAVX512CD = true; 752 } else if (Feature == "+avx512vpopcntdq") { 753 HasAVX512VPOPCNTDQ = true; 754 } else if (Feature == "+avx512vnni") { 755 HasAVX512VNNI = true; 756 } else if (Feature == "+avx512er") { 757 HasAVX512ER = true; 758 } else if (Feature == "+avx512pf") { 759 HasAVX512PF = true; 760 } else if (Feature == "+avx512dq") { 761 HasAVX512DQ = true; 762 } else if (Feature == "+avx512bitalg") { 763 HasAVX512BITALG = true; 764 } else if (Feature == "+avx512bw") { 765 HasAVX512BW = true; 766 } else if (Feature == "+avx512vl") { 767 HasAVX512VL = true; 768 } else if (Feature == "+avx512vbmi") { 769 HasAVX512VBMI = true; 770 } else if (Feature == "+avx512vbmi2") { 771 HasAVX512VBMI2 = true; 772 } else if (Feature == "+avx512ifma") { 773 HasAVX512IFMA = true; 774 } else if (Feature == "+sha") { 775 HasSHA = true; 776 } else if (Feature == "+mpx") { 777 HasMPX = true; 778 } else if (Feature == "+shstk") { 779 HasSHSTK = true; 780 } else if (Feature == "+ibt") { 781 HasIBT = true; 782 } else if (Feature == "+movbe") { 783 HasMOVBE = true; 784 } else if (Feature == "+sgx") { 785 HasSGX = true; 786 } else if (Feature == "+cx16") { 787 HasCX16 = true; 788 } else if (Feature == "+fxsr") { 789 HasFXSR = true; 790 } else if (Feature == "+xsave") { 791 HasXSAVE = true; 792 } else if (Feature == "+xsaveopt") { 793 HasXSAVEOPT = true; 794 } else if (Feature == "+xsavec") { 795 HasXSAVEC = true; 796 } else if (Feature == "+xsaves") { 797 HasXSAVES = true; 798 } else if (Feature == "+mwaitx") { 799 HasMWAITX = true; 800 } else if (Feature == "+pku") { 801 HasPKU = true; 802 } else if (Feature == "+clflushopt") { 803 HasCLFLUSHOPT = true; 804 } else if (Feature == "+clwb") { 805 HasCLWB = true; 806 } else if (Feature == "+wbnoinvd") { 807 HasWBNOINVD = true; 808 } else if (Feature == "+prefetchwt1") { 809 HasPREFETCHWT1 = true; 810 } else if (Feature == "+clzero") { 811 HasCLZERO = true; 812 } else if (Feature == "+cldemote") { 813 HasCLDEMOTE = true; 814 } else if (Feature == "+rdpid") { 815 HasRDPID = true; 816 } else if (Feature == "+retpoline") { 817 HasRetpoline = true; 818 } else if (Feature == "+retpoline-external-thunk") { 819 HasRetpolineExternalThunk = true; 820 } else if (Feature == "+sahf") { 821 HasLAHFSAHF = true; 822 } else if (Feature == "+waitpkg") { 823 HasWAITPKG = true; 824 } 825 826 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 827 .Case("+avx512f", AVX512F) 828 .Case("+avx2", AVX2) 829 .Case("+avx", AVX) 830 .Case("+sse4.2", SSE42) 831 .Case("+sse4.1", SSE41) 832 .Case("+ssse3", SSSE3) 833 .Case("+sse3", SSE3) 834 .Case("+sse2", SSE2) 835 .Case("+sse", SSE1) 836 .Default(NoSSE); 837 SSELevel = std::max(SSELevel, Level); 838 839 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 840 .Case("+3dnowa", AMD3DNowAthlon) 841 .Case("+3dnow", AMD3DNow) 842 .Case("+mmx", MMX) 843 .Default(NoMMX3DNow); 844 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 845 846 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 847 .Case("+xop", XOP) 848 .Case("+fma4", FMA4) 849 .Case("+sse4a", SSE4A) 850 .Default(NoXOP); 851 XOPLevel = std::max(XOPLevel, XLevel); 852 } 853 854 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 855 // matches the selected sse level. 856 if ((FPMath == FP_SSE && SSELevel < SSE1) || 857 (FPMath == FP_387 && SSELevel >= SSE1)) { 858 Diags.Report(diag::err_target_unsupported_fpmath) 859 << (FPMath == FP_SSE ? "sse" : "387"); 860 return false; 861 } 862 863 SimdDefaultAlign = 864 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 865 return true; 866 } 867 868 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 869 /// definitions for this particular subtarget. 870 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 871 MacroBuilder &Builder) const { 872 // Target identification. 873 if (getTriple().getArch() == llvm::Triple::x86_64) { 874 Builder.defineMacro("__amd64__"); 875 Builder.defineMacro("__amd64"); 876 Builder.defineMacro("__x86_64"); 877 Builder.defineMacro("__x86_64__"); 878 if (getTriple().getArchName() == "x86_64h") { 879 Builder.defineMacro("__x86_64h"); 880 Builder.defineMacro("__x86_64h__"); 881 } 882 } else { 883 DefineStd(Builder, "i386", Opts); 884 } 885 886 // Subtarget options. 887 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 888 // truly should be based on -mtune options. 889 switch (CPU) { 890 case CK_Generic: 891 break; 892 case CK_i386: 893 // The rest are coming from the i386 define above. 894 Builder.defineMacro("__tune_i386__"); 895 break; 896 case CK_i486: 897 case CK_WinChipC6: 898 case CK_WinChip2: 899 case CK_C3: 900 defineCPUMacros(Builder, "i486"); 901 break; 902 case CK_PentiumMMX: 903 Builder.defineMacro("__pentium_mmx__"); 904 Builder.defineMacro("__tune_pentium_mmx__"); 905 LLVM_FALLTHROUGH; 906 case CK_i586: 907 case CK_Pentium: 908 defineCPUMacros(Builder, "i586"); 909 defineCPUMacros(Builder, "pentium"); 910 break; 911 case CK_Pentium3: 912 case CK_PentiumM: 913 Builder.defineMacro("__tune_pentium3__"); 914 LLVM_FALLTHROUGH; 915 case CK_Pentium2: 916 case CK_C3_2: 917 Builder.defineMacro("__tune_pentium2__"); 918 LLVM_FALLTHROUGH; 919 case CK_PentiumPro: 920 defineCPUMacros(Builder, "i686"); 921 defineCPUMacros(Builder, "pentiumpro"); 922 break; 923 case CK_Pentium4: 924 defineCPUMacros(Builder, "pentium4"); 925 break; 926 case CK_Yonah: 927 case CK_Prescott: 928 case CK_Nocona: 929 defineCPUMacros(Builder, "nocona"); 930 break; 931 case CK_Core2: 932 case CK_Penryn: 933 defineCPUMacros(Builder, "core2"); 934 break; 935 case CK_Bonnell: 936 defineCPUMacros(Builder, "atom"); 937 break; 938 case CK_Silvermont: 939 defineCPUMacros(Builder, "slm"); 940 break; 941 case CK_Goldmont: 942 defineCPUMacros(Builder, "goldmont"); 943 break; 944 case CK_GoldmontPlus: 945 defineCPUMacros(Builder, "goldmont_plus"); 946 break; 947 case CK_Tremont: 948 defineCPUMacros(Builder, "tremont"); 949 break; 950 case CK_Nehalem: 951 case CK_Westmere: 952 case CK_SandyBridge: 953 case CK_IvyBridge: 954 case CK_Haswell: 955 case CK_Broadwell: 956 case CK_SkylakeClient: 957 case CK_SkylakeServer: 958 case CK_Cannonlake: 959 case CK_IcelakeClient: 960 case CK_IcelakeServer: 961 // FIXME: Historically, we defined this legacy name, it would be nice to 962 // remove it at some point. We've never exposed fine-grained names for 963 // recent primary x86 CPUs, and we should keep it that way. 964 defineCPUMacros(Builder, "corei7"); 965 break; 966 case CK_KNL: 967 defineCPUMacros(Builder, "knl"); 968 break; 969 case CK_KNM: 970 break; 971 case CK_Lakemont: 972 defineCPUMacros(Builder, "i586", /*Tuning*/false); 973 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 974 Builder.defineMacro("__tune_lakemont__"); 975 break; 976 case CK_K6_2: 977 Builder.defineMacro("__k6_2__"); 978 Builder.defineMacro("__tune_k6_2__"); 979 LLVM_FALLTHROUGH; 980 case CK_K6_3: 981 if (CPU != CK_K6_2) { // In case of fallthrough 982 // FIXME: GCC may be enabling these in cases where some other k6 983 // architecture is specified but -m3dnow is explicitly provided. The 984 // exact semantics need to be determined and emulated here. 985 Builder.defineMacro("__k6_3__"); 986 Builder.defineMacro("__tune_k6_3__"); 987 } 988 LLVM_FALLTHROUGH; 989 case CK_K6: 990 defineCPUMacros(Builder, "k6"); 991 break; 992 case CK_Athlon: 993 case CK_AthlonXP: 994 defineCPUMacros(Builder, "athlon"); 995 if (SSELevel != NoSSE) { 996 Builder.defineMacro("__athlon_sse__"); 997 Builder.defineMacro("__tune_athlon_sse__"); 998 } 999 break; 1000 case CK_K8: 1001 case CK_K8SSE3: 1002 case CK_x86_64: 1003 defineCPUMacros(Builder, "k8"); 1004 break; 1005 case CK_AMDFAM10: 1006 defineCPUMacros(Builder, "amdfam10"); 1007 break; 1008 case CK_BTVER1: 1009 defineCPUMacros(Builder, "btver1"); 1010 break; 1011 case CK_BTVER2: 1012 defineCPUMacros(Builder, "btver2"); 1013 break; 1014 case CK_BDVER1: 1015 defineCPUMacros(Builder, "bdver1"); 1016 break; 1017 case CK_BDVER2: 1018 defineCPUMacros(Builder, "bdver2"); 1019 break; 1020 case CK_BDVER3: 1021 defineCPUMacros(Builder, "bdver3"); 1022 break; 1023 case CK_BDVER4: 1024 defineCPUMacros(Builder, "bdver4"); 1025 break; 1026 case CK_ZNVER1: 1027 defineCPUMacros(Builder, "znver1"); 1028 break; 1029 case CK_Geode: 1030 defineCPUMacros(Builder, "geode"); 1031 break; 1032 } 1033 1034 // Target properties. 1035 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1036 1037 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1038 // functions in glibc header files that use FP Stack inline asm which the 1039 // backend can't deal with (PR879). 1040 Builder.defineMacro("__NO_MATH_INLINES"); 1041 1042 if (HasAES) 1043 Builder.defineMacro("__AES__"); 1044 1045 if (HasVAES) 1046 Builder.defineMacro("__VAES__"); 1047 1048 if (HasPCLMUL) 1049 Builder.defineMacro("__PCLMUL__"); 1050 1051 if (HasVPCLMULQDQ) 1052 Builder.defineMacro("__VPCLMULQDQ__"); 1053 1054 if (HasLZCNT) 1055 Builder.defineMacro("__LZCNT__"); 1056 1057 if (HasRDRND) 1058 Builder.defineMacro("__RDRND__"); 1059 1060 if (HasFSGSBASE) 1061 Builder.defineMacro("__FSGSBASE__"); 1062 1063 if (HasBMI) 1064 Builder.defineMacro("__BMI__"); 1065 1066 if (HasBMI2) 1067 Builder.defineMacro("__BMI2__"); 1068 1069 if (HasPOPCNT) 1070 Builder.defineMacro("__POPCNT__"); 1071 1072 if (HasRTM) 1073 Builder.defineMacro("__RTM__"); 1074 1075 if (HasPRFCHW) 1076 Builder.defineMacro("__PRFCHW__"); 1077 1078 if (HasRDSEED) 1079 Builder.defineMacro("__RDSEED__"); 1080 1081 if (HasADX) 1082 Builder.defineMacro("__ADX__"); 1083 1084 if (HasTBM) 1085 Builder.defineMacro("__TBM__"); 1086 1087 if (HasLWP) 1088 Builder.defineMacro("__LWP__"); 1089 1090 if (HasMWAITX) 1091 Builder.defineMacro("__MWAITX__"); 1092 1093 switch (XOPLevel) { 1094 case XOP: 1095 Builder.defineMacro("__XOP__"); 1096 LLVM_FALLTHROUGH; 1097 case FMA4: 1098 Builder.defineMacro("__FMA4__"); 1099 LLVM_FALLTHROUGH; 1100 case SSE4A: 1101 Builder.defineMacro("__SSE4A__"); 1102 LLVM_FALLTHROUGH; 1103 case NoXOP: 1104 break; 1105 } 1106 1107 if (HasFMA) 1108 Builder.defineMacro("__FMA__"); 1109 1110 if (HasF16C) 1111 Builder.defineMacro("__F16C__"); 1112 1113 if (HasGFNI) 1114 Builder.defineMacro("__GFNI__"); 1115 1116 if (HasAVX512CD) 1117 Builder.defineMacro("__AVX512CD__"); 1118 if (HasAVX512VPOPCNTDQ) 1119 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1120 if (HasAVX512VNNI) 1121 Builder.defineMacro("__AVX512VNNI__"); 1122 if (HasAVX512ER) 1123 Builder.defineMacro("__AVX512ER__"); 1124 if (HasAVX512PF) 1125 Builder.defineMacro("__AVX512PF__"); 1126 if (HasAVX512DQ) 1127 Builder.defineMacro("__AVX512DQ__"); 1128 if (HasAVX512BITALG) 1129 Builder.defineMacro("__AVX512BITALG__"); 1130 if (HasAVX512BW) 1131 Builder.defineMacro("__AVX512BW__"); 1132 if (HasAVX512VL) 1133 Builder.defineMacro("__AVX512VL__"); 1134 if (HasAVX512VBMI) 1135 Builder.defineMacro("__AVX512VBMI__"); 1136 if (HasAVX512VBMI2) 1137 Builder.defineMacro("__AVX512VBMI2__"); 1138 if (HasAVX512IFMA) 1139 Builder.defineMacro("__AVX512IFMA__"); 1140 1141 if (HasSHA) 1142 Builder.defineMacro("__SHA__"); 1143 1144 if (HasFXSR) 1145 Builder.defineMacro("__FXSR__"); 1146 if (HasXSAVE) 1147 Builder.defineMacro("__XSAVE__"); 1148 if (HasXSAVEOPT) 1149 Builder.defineMacro("__XSAVEOPT__"); 1150 if (HasXSAVEC) 1151 Builder.defineMacro("__XSAVEC__"); 1152 if (HasXSAVES) 1153 Builder.defineMacro("__XSAVES__"); 1154 if (HasPKU) 1155 Builder.defineMacro("__PKU__"); 1156 if (HasCLFLUSHOPT) 1157 Builder.defineMacro("__CLFLUSHOPT__"); 1158 if (HasCLWB) 1159 Builder.defineMacro("__CLWB__"); 1160 if (HasWBNOINVD) 1161 Builder.defineMacro("__WBNOINVD__"); 1162 if (HasMPX) 1163 Builder.defineMacro("__MPX__"); 1164 if (HasSHSTK) 1165 Builder.defineMacro("__SHSTK__"); 1166 if (HasIBT) 1167 Builder.defineMacro("__IBT__"); 1168 if (HasSGX) 1169 Builder.defineMacro("__SGX__"); 1170 if (HasPREFETCHWT1) 1171 Builder.defineMacro("__PREFETCHWT1__"); 1172 if (HasCLZERO) 1173 Builder.defineMacro("__CLZERO__"); 1174 if (HasRDPID) 1175 Builder.defineMacro("__RDPID__"); 1176 if (HasCLDEMOTE) 1177 Builder.defineMacro("__CLDEMOTE__"); 1178 if (HasWAITPKG) 1179 Builder.defineMacro("__WAITPKG__"); 1180 1181 // Each case falls through to the previous one here. 1182 switch (SSELevel) { 1183 case AVX512F: 1184 Builder.defineMacro("__AVX512F__"); 1185 LLVM_FALLTHROUGH; 1186 case AVX2: 1187 Builder.defineMacro("__AVX2__"); 1188 LLVM_FALLTHROUGH; 1189 case AVX: 1190 Builder.defineMacro("__AVX__"); 1191 LLVM_FALLTHROUGH; 1192 case SSE42: 1193 Builder.defineMacro("__SSE4_2__"); 1194 LLVM_FALLTHROUGH; 1195 case SSE41: 1196 Builder.defineMacro("__SSE4_1__"); 1197 LLVM_FALLTHROUGH; 1198 case SSSE3: 1199 Builder.defineMacro("__SSSE3__"); 1200 LLVM_FALLTHROUGH; 1201 case SSE3: 1202 Builder.defineMacro("__SSE3__"); 1203 LLVM_FALLTHROUGH; 1204 case SSE2: 1205 Builder.defineMacro("__SSE2__"); 1206 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1207 LLVM_FALLTHROUGH; 1208 case SSE1: 1209 Builder.defineMacro("__SSE__"); 1210 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1211 LLVM_FALLTHROUGH; 1212 case NoSSE: 1213 break; 1214 } 1215 1216 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1217 switch (SSELevel) { 1218 case AVX512F: 1219 case AVX2: 1220 case AVX: 1221 case SSE42: 1222 case SSE41: 1223 case SSSE3: 1224 case SSE3: 1225 case SSE2: 1226 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1227 break; 1228 case SSE1: 1229 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1230 break; 1231 default: 1232 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1233 break; 1234 } 1235 } 1236 1237 // Each case falls through to the previous one here. 1238 switch (MMX3DNowLevel) { 1239 case AMD3DNowAthlon: 1240 Builder.defineMacro("__3dNOW_A__"); 1241 LLVM_FALLTHROUGH; 1242 case AMD3DNow: 1243 Builder.defineMacro("__3dNOW__"); 1244 LLVM_FALLTHROUGH; 1245 case MMX: 1246 Builder.defineMacro("__MMX__"); 1247 LLVM_FALLTHROUGH; 1248 case NoMMX3DNow: 1249 break; 1250 } 1251 1252 if (CPU >= CK_i486) { 1253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1256 } 1257 if (CPU >= CK_i586) 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1259 if (HasCX16) 1260 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1261 1262 if (HasFloat128) 1263 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1264 } 1265 1266 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1267 return llvm::StringSwitch<bool>(Name) 1268 .Case("3dnow", true) 1269 .Case("3dnowa", true) 1270 .Case("adx", true) 1271 .Case("aes", true) 1272 .Case("avx", true) 1273 .Case("avx2", true) 1274 .Case("avx512f", true) 1275 .Case("avx512cd", true) 1276 .Case("avx512vpopcntdq", true) 1277 .Case("avx512vnni", true) 1278 .Case("avx512er", true) 1279 .Case("avx512pf", true) 1280 .Case("avx512dq", true) 1281 .Case("avx512bitalg", true) 1282 .Case("avx512bw", true) 1283 .Case("avx512vl", true) 1284 .Case("avx512vbmi", true) 1285 .Case("avx512vbmi2", true) 1286 .Case("avx512ifma", true) 1287 .Case("bmi", true) 1288 .Case("bmi2", true) 1289 .Case("cldemote", true) 1290 .Case("clflushopt", true) 1291 .Case("clwb", true) 1292 .Case("clzero", true) 1293 .Case("cx16", true) 1294 .Case("f16c", true) 1295 .Case("fma", true) 1296 .Case("fma4", true) 1297 .Case("fsgsbase", true) 1298 .Case("fxsr", true) 1299 .Case("gfni", true) 1300 .Case("lwp", true) 1301 .Case("lzcnt", true) 1302 .Case("mmx", true) 1303 .Case("movbe", true) 1304 .Case("mpx", true) 1305 .Case("mwaitx", true) 1306 .Case("pclmul", true) 1307 .Case("pku", true) 1308 .Case("popcnt", true) 1309 .Case("prefetchwt1", true) 1310 .Case("prfchw", true) 1311 .Case("rdpid", true) 1312 .Case("rdrnd", true) 1313 .Case("rdseed", true) 1314 .Case("rtm", true) 1315 .Case("sahf", true) 1316 .Case("sgx", true) 1317 .Case("sha", true) 1318 .Case("shstk", true) 1319 .Case("sse", true) 1320 .Case("sse2", true) 1321 .Case("sse3", true) 1322 .Case("ssse3", true) 1323 .Case("sse4", true) 1324 .Case("sse4.1", true) 1325 .Case("sse4.2", true) 1326 .Case("sse4a", true) 1327 .Case("tbm", true) 1328 .Case("vaes", true) 1329 .Case("vpclmulqdq", true) 1330 .Case("wbnoinvd", true) 1331 .Case("waitpkg", true) 1332 .Case("x87", true) 1333 .Case("xop", true) 1334 .Case("xsave", true) 1335 .Case("xsavec", true) 1336 .Case("xsaves", true) 1337 .Case("xsaveopt", true) 1338 .Default(false); 1339 } 1340 1341 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1342 return llvm::StringSwitch<bool>(Feature) 1343 .Case("adx", HasADX) 1344 .Case("aes", HasAES) 1345 .Case("avx", SSELevel >= AVX) 1346 .Case("avx2", SSELevel >= AVX2) 1347 .Case("avx512f", SSELevel >= AVX512F) 1348 .Case("avx512cd", HasAVX512CD) 1349 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1350 .Case("avx512vnni", HasAVX512VNNI) 1351 .Case("avx512er", HasAVX512ER) 1352 .Case("avx512pf", HasAVX512PF) 1353 .Case("avx512dq", HasAVX512DQ) 1354 .Case("avx512bitalg", HasAVX512BITALG) 1355 .Case("avx512bw", HasAVX512BW) 1356 .Case("avx512vl", HasAVX512VL) 1357 .Case("avx512vbmi", HasAVX512VBMI) 1358 .Case("avx512vbmi2", HasAVX512VBMI2) 1359 .Case("avx512ifma", HasAVX512IFMA) 1360 .Case("bmi", HasBMI) 1361 .Case("bmi2", HasBMI2) 1362 .Case("cldemote", HasCLDEMOTE) 1363 .Case("clflushopt", HasCLFLUSHOPT) 1364 .Case("clwb", HasCLWB) 1365 .Case("clzero", HasCLZERO) 1366 .Case("cx16", HasCX16) 1367 .Case("f16c", HasF16C) 1368 .Case("fma", HasFMA) 1369 .Case("fma4", XOPLevel >= FMA4) 1370 .Case("fsgsbase", HasFSGSBASE) 1371 .Case("fxsr", HasFXSR) 1372 .Case("gfni", HasGFNI) 1373 .Case("ibt", HasIBT) 1374 .Case("lwp", HasLWP) 1375 .Case("lzcnt", HasLZCNT) 1376 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1377 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1378 .Case("mmx", MMX3DNowLevel >= MMX) 1379 .Case("movbe", HasMOVBE) 1380 .Case("mpx", HasMPX) 1381 .Case("mwaitx", HasMWAITX) 1382 .Case("pclmul", HasPCLMUL) 1383 .Case("pku", HasPKU) 1384 .Case("popcnt", HasPOPCNT) 1385 .Case("prefetchwt1", HasPREFETCHWT1) 1386 .Case("prfchw", HasPRFCHW) 1387 .Case("rdpid", HasRDPID) 1388 .Case("rdrnd", HasRDRND) 1389 .Case("rdseed", HasRDSEED) 1390 .Case("retpoline", HasRetpoline) 1391 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1392 .Case("rtm", HasRTM) 1393 .Case("sahf", HasLAHFSAHF) 1394 .Case("sgx", HasSGX) 1395 .Case("sha", HasSHA) 1396 .Case("shstk", HasSHSTK) 1397 .Case("sse", SSELevel >= SSE1) 1398 .Case("sse2", SSELevel >= SSE2) 1399 .Case("sse3", SSELevel >= SSE3) 1400 .Case("ssse3", SSELevel >= SSSE3) 1401 .Case("sse4.1", SSELevel >= SSE41) 1402 .Case("sse4.2", SSELevel >= SSE42) 1403 .Case("sse4a", XOPLevel >= SSE4A) 1404 .Case("tbm", HasTBM) 1405 .Case("vaes", HasVAES) 1406 .Case("vpclmulqdq", HasVPCLMULQDQ) 1407 .Case("wbnoinvd", HasWBNOINVD) 1408 .Case("waitpkg", HasWAITPKG) 1409 .Case("x86", true) 1410 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1411 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1412 .Case("xop", XOPLevel >= XOP) 1413 .Case("xsave", HasXSAVE) 1414 .Case("xsavec", HasXSAVEC) 1415 .Case("xsaves", HasXSAVES) 1416 .Case("xsaveopt", HasXSAVEOPT) 1417 .Default(false); 1418 } 1419 1420 // We can't use a generic validation scheme for the features accepted here 1421 // versus subtarget features accepted in the target attribute because the 1422 // bitfield structure that's initialized in the runtime only supports the 1423 // below currently rather than the full range of subtarget features. (See 1424 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1425 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1426 return llvm::StringSwitch<bool>(FeatureStr) 1427 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1428 #include "llvm/Support/X86TargetParser.def" 1429 .Default(false); 1430 } 1431 1432 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1433 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1434 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1435 #include "llvm/Support/X86TargetParser.def" 1436 ; 1437 // Note, this function should only be used after ensuring the value is 1438 // correct, so it asserts if the value is out of range. 1439 } 1440 1441 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1442 enum class FeatPriority { 1443 #define FEATURE(FEAT) FEAT, 1444 #include "clang/Basic/X86Target.def" 1445 }; 1446 switch (Feat) { 1447 #define FEATURE(FEAT) \ 1448 case llvm::X86::FEAT: \ 1449 return static_cast<unsigned>(FeatPriority::FEAT); 1450 #include "clang/Basic/X86Target.def" 1451 default: 1452 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1453 } 1454 } 1455 1456 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1457 // Valid CPUs have a 'key feature' that compares just better than its key 1458 // feature. 1459 CPUKind Kind = getCPUKind(Name); 1460 if (Kind != CK_Generic) { 1461 switch (Kind) { 1462 default: 1463 llvm_unreachable( 1464 "CPU Type without a key feature used in 'target' attribute"); 1465 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1466 case CK_##ENUM: \ 1467 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1468 #include "clang/Basic/X86Target.def" 1469 } 1470 } 1471 1472 // Now we know we have a feature, so get its priority and shift it a few so 1473 // that we have sufficient room for the CPUs (above). 1474 return getFeaturePriority(getFeature(Name)) << 1; 1475 } 1476 1477 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1478 switch (Kind) { 1479 case CK_Generic: 1480 return ""; 1481 #define PROC(ENUM, STRING, IS64BIT) \ 1482 case CK_##ENUM: \ 1483 return STRING; 1484 #include "clang/Basic/X86Target.def" 1485 } 1486 llvm_unreachable("Invalid CPUKind"); 1487 } 1488 1489 // We can't use a generic validation scheme for the cpus accepted here 1490 // versus subtarget cpus accepted in the target attribute because the 1491 // variables intitialized by the runtime only support the below currently 1492 // rather than the full range of cpus. 1493 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1494 return llvm::StringSwitch<bool>(FeatureStr) 1495 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1496 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1497 .Cases(STR, ALIAS, true) 1498 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1499 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1500 #include "llvm/Support/X86TargetParser.def" 1501 .Default(false); 1502 } 1503 1504 bool X86TargetInfo::validateAsmConstraint( 1505 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1506 switch (*Name) { 1507 default: 1508 return false; 1509 // Constant constraints. 1510 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1511 // instructions. 1512 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1513 // x86_64 instructions. 1514 case 's': 1515 Info.setRequiresImmediate(); 1516 return true; 1517 case 'I': 1518 Info.setRequiresImmediate(0, 31); 1519 return true; 1520 case 'J': 1521 Info.setRequiresImmediate(0, 63); 1522 return true; 1523 case 'K': 1524 Info.setRequiresImmediate(-128, 127); 1525 return true; 1526 case 'L': 1527 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1528 return true; 1529 case 'M': 1530 Info.setRequiresImmediate(0, 3); 1531 return true; 1532 case 'N': 1533 Info.setRequiresImmediate(0, 255); 1534 return true; 1535 case 'O': 1536 Info.setRequiresImmediate(0, 127); 1537 return true; 1538 // Register constraints. 1539 case 'Y': // 'Y' is the first character for several 2-character constraints. 1540 // Shift the pointer to the second character of the constraint. 1541 Name++; 1542 switch (*Name) { 1543 default: 1544 return false; 1545 case 'z': 1546 case '0': // First SSE register. 1547 case '2': 1548 case 't': // Any SSE register, when SSE2 is enabled. 1549 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1550 case 'm': // Any MMX register, when inter-unit moves enabled. 1551 case 'k': // AVX512 arch mask registers: k1-k7. 1552 Info.setAllowsRegister(); 1553 return true; 1554 } 1555 case 'f': // Any x87 floating point stack register. 1556 // Constraint 'f' cannot be used for output operands. 1557 if (Info.ConstraintStr[0] == '=') 1558 return false; 1559 Info.setAllowsRegister(); 1560 return true; 1561 case 'a': // eax. 1562 case 'b': // ebx. 1563 case 'c': // ecx. 1564 case 'd': // edx. 1565 case 'S': // esi. 1566 case 'D': // edi. 1567 case 'A': // edx:eax. 1568 case 't': // Top of floating point stack. 1569 case 'u': // Second from top of floating point stack. 1570 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1571 case 'y': // Any MMX register. 1572 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1573 case 'x': // Any SSE register. 1574 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1575 // for intermideate k reg operations). 1576 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1577 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1578 case 'l': // "Index" registers: any general register that can be used as an 1579 // index in a base+index memory access. 1580 Info.setAllowsRegister(); 1581 return true; 1582 // Floating point constant constraints. 1583 case 'C': // SSE floating point constant. 1584 case 'G': // x87 floating point constant. 1585 return true; 1586 } 1587 } 1588 1589 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1590 unsigned Size) const { 1591 // Strip off constraint modifiers. 1592 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1593 Constraint = Constraint.substr(1); 1594 1595 return validateOperandSize(Constraint, Size); 1596 } 1597 1598 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1599 unsigned Size) const { 1600 return validateOperandSize(Constraint, Size); 1601 } 1602 1603 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1604 unsigned Size) const { 1605 switch (Constraint[0]) { 1606 default: 1607 break; 1608 case 'k': 1609 // Registers k0-k7 (AVX512) size limit is 64 bit. 1610 case 'y': 1611 return Size <= 64; 1612 case 'f': 1613 case 't': 1614 case 'u': 1615 return Size <= 128; 1616 case 'Y': 1617 // 'Y' is the first character for several 2-character constraints. 1618 switch (Constraint[1]) { 1619 default: 1620 return false; 1621 case 'm': 1622 // 'Ym' is synonymous with 'y'. 1623 case 'k': 1624 return Size <= 64; 1625 case 'z': 1626 case '0': 1627 // XMM0 1628 if (SSELevel >= SSE1) 1629 return Size <= 128U; 1630 return false; 1631 case 'i': 1632 case 't': 1633 case '2': 1634 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1635 if (SSELevel < SSE2) 1636 return false; 1637 break; 1638 } 1639 case 'v': 1640 case 'x': 1641 if (SSELevel >= AVX512F) 1642 // 512-bit zmm registers can be used if target supports AVX512F. 1643 return Size <= 512U; 1644 else if (SSELevel >= AVX) 1645 // 256-bit ymm registers can be used if target supports AVX. 1646 return Size <= 256U; 1647 return Size <= 128U; 1648 1649 } 1650 1651 return true; 1652 } 1653 1654 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1655 switch (*Constraint) { 1656 case 'a': 1657 return std::string("{ax}"); 1658 case 'b': 1659 return std::string("{bx}"); 1660 case 'c': 1661 return std::string("{cx}"); 1662 case 'd': 1663 return std::string("{dx}"); 1664 case 'S': 1665 return std::string("{si}"); 1666 case 'D': 1667 return std::string("{di}"); 1668 case 'p': // address 1669 return std::string("im"); 1670 case 't': // top of floating point stack. 1671 return std::string("{st}"); 1672 case 'u': // second from top of floating point stack. 1673 return std::string("{st(1)}"); // second from top of floating point stack. 1674 case 'Y': 1675 switch (Constraint[1]) { 1676 default: 1677 // Break from inner switch and fall through (copy single char), 1678 // continue parsing after copying the current constraint into 1679 // the return string. 1680 break; 1681 case 'k': 1682 case 'm': 1683 case 'i': 1684 case 't': 1685 case 'z': 1686 case '0': 1687 case '2': 1688 // "^" hints llvm that this is a 2 letter constraint. 1689 // "Constraint++" is used to promote the string iterator 1690 // to the next constraint. 1691 return std::string("^") + std::string(Constraint++, 2); 1692 } 1693 LLVM_FALLTHROUGH; 1694 default: 1695 return std::string(1, *Constraint); 1696 } 1697 } 1698 1699 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1700 // Perform any per-CPU checks necessary to determine if this CPU is 1701 // acceptable. 1702 switch (Kind) { 1703 case CK_Generic: 1704 // No processor selected! 1705 return false; 1706 #define PROC(ENUM, STRING, IS64BIT) \ 1707 case CK_##ENUM: \ 1708 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1709 #include "clang/Basic/X86Target.def" 1710 } 1711 llvm_unreachable("Unhandled CPU kind"); 1712 } 1713 1714 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1715 #define PROC(ENUM, STRING, IS64BIT) \ 1716 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1717 Values.emplace_back(STRING); 1718 // Go through CPUKind checking to ensure that the alias is de-aliased and 1719 // 64 bit-ness is checked. 1720 #define PROC_ALIAS(ENUM, ALIAS) \ 1721 if (checkCPUKind(getCPUKind(ALIAS))) \ 1722 Values.emplace_back(ALIAS); 1723 #include "clang/Basic/X86Target.def" 1724 } 1725 1726 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1727 return llvm::StringSwitch<CPUKind>(CPU) 1728 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1729 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1730 #include "clang/Basic/X86Target.def" 1731 .Default(CK_Generic); 1732 } 1733 1734 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1735 return llvm::makeArrayRef(GCCRegNames); 1736 } 1737 1738 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1739 return llvm::makeArrayRef(AddlRegNames); 1740 } 1741 1742 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1743 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1744 Builtin::FirstTSBuiltin + 1); 1745 } 1746 1747 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1748 return llvm::makeArrayRef(BuiltinInfoX86, 1749 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1750 } 1751