1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 }; 64 65 const TargetInfo::AddlRegName AddlRegNames[] = { 66 {{"al", "ah", "eax", "rax"}, 0}, 67 {{"bl", "bh", "ebx", "rbx"}, 3}, 68 {{"cl", "ch", "ecx", "rcx"}, 2}, 69 {{"dl", "dh", "edx", "rdx"}, 1}, 70 {{"esi", "rsi"}, 4}, 71 {{"edi", "rdi"}, 5}, 72 {{"esp", "rsp"}, 7}, 73 {{"ebp", "rbp"}, 6}, 74 {{"r8d", "r8w", "r8b"}, 38}, 75 {{"r9d", "r9w", "r9b"}, 39}, 76 {{"r10d", "r10w", "r10b"}, 40}, 77 {{"r11d", "r11w", "r11b"}, 41}, 78 {{"r12d", "r12w", "r12b"}, 42}, 79 {{"r13d", "r13w", "r13b"}, 43}, 80 {{"r14d", "r14w", "r14b"}, 44}, 81 {{"r15d", "r15w", "r15b"}, 45}, 82 }; 83 84 } // namespace targets 85 } // namespace clang 86 87 using namespace clang; 88 using namespace clang::targets; 89 90 bool X86TargetInfo::setFPMath(StringRef Name) { 91 if (Name == "387") { 92 FPMath = FP_387; 93 return true; 94 } 95 if (Name == "sse") { 96 FPMath = FP_SSE; 97 return true; 98 } 99 return false; 100 } 101 102 bool X86TargetInfo::initFeatureMap( 103 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 104 const std::vector<std::string> &FeaturesVec) const { 105 // FIXME: This *really* should not be here. 106 // X86_64 always has SSE2. 107 if (getTriple().getArch() == llvm::Triple::x86_64) 108 setFeatureEnabledImpl(Features, "sse2", true); 109 110 const CPUKind Kind = getCPUKind(CPU); 111 112 // Enable X87 for all X86 processors but Lakemont. 113 if (Kind != CK_Lakemont) 114 setFeatureEnabledImpl(Features, "x87", true); 115 116 switch (Kind) { 117 case CK_Generic: 118 case CK_i386: 119 case CK_i486: 120 case CK_i586: 121 case CK_Pentium: 122 case CK_i686: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 127 case CK_PentiumMMX: 128 case CK_Pentium2: 129 case CK_K6: 130 case CK_WinChipC6: 131 setFeatureEnabledImpl(Features, "mmx", true); 132 break; 133 134 case CK_Cannonlake: 135 setFeatureEnabledImpl(Features, "avx512ifma", true); 136 setFeatureEnabledImpl(Features, "avx512vbmi", true); 137 setFeatureEnabledImpl(Features, "sha", true); 138 LLVM_FALLTHROUGH; 139 case CK_SkylakeServer: 140 setFeatureEnabledImpl(Features, "avx512f", true); 141 setFeatureEnabledImpl(Features, "avx512cd", true); 142 setFeatureEnabledImpl(Features, "avx512dq", true); 143 setFeatureEnabledImpl(Features, "avx512bw", true); 144 setFeatureEnabledImpl(Features, "avx512vl", true); 145 setFeatureEnabledImpl(Features, "pku", true); 146 setFeatureEnabledImpl(Features, "clwb", true); 147 LLVM_FALLTHROUGH; 148 case CK_SkylakeClient: 149 setFeatureEnabledImpl(Features, "xsavec", true); 150 setFeatureEnabledImpl(Features, "xsaves", true); 151 setFeatureEnabledImpl(Features, "mpx", true); 152 setFeatureEnabledImpl(Features, "sgx", true); 153 setFeatureEnabledImpl(Features, "clflushopt", true); 154 setFeatureEnabledImpl(Features, "rtm", true); 155 LLVM_FALLTHROUGH; 156 case CK_Broadwell: 157 setFeatureEnabledImpl(Features, "rdseed", true); 158 setFeatureEnabledImpl(Features, "adx", true); 159 LLVM_FALLTHROUGH; 160 case CK_Haswell: 161 setFeatureEnabledImpl(Features, "avx2", true); 162 setFeatureEnabledImpl(Features, "lzcnt", true); 163 setFeatureEnabledImpl(Features, "bmi", true); 164 setFeatureEnabledImpl(Features, "bmi2", true); 165 setFeatureEnabledImpl(Features, "fma", true); 166 setFeatureEnabledImpl(Features, "movbe", true); 167 LLVM_FALLTHROUGH; 168 case CK_IvyBridge: 169 setFeatureEnabledImpl(Features, "rdrnd", true); 170 setFeatureEnabledImpl(Features, "f16c", true); 171 setFeatureEnabledImpl(Features, "fsgsbase", true); 172 LLVM_FALLTHROUGH; 173 case CK_SandyBridge: 174 setFeatureEnabledImpl(Features, "avx", true); 175 setFeatureEnabledImpl(Features, "xsave", true); 176 setFeatureEnabledImpl(Features, "xsaveopt", true); 177 LLVM_FALLTHROUGH; 178 case CK_Westmere: 179 setFeatureEnabledImpl(Features, "aes", true); 180 setFeatureEnabledImpl(Features, "pclmul", true); 181 LLVM_FALLTHROUGH; 182 case CK_Nehalem: 183 setFeatureEnabledImpl(Features, "sse4.2", true); 184 LLVM_FALLTHROUGH; 185 case CK_Penryn: 186 setFeatureEnabledImpl(Features, "sse4.1", true); 187 LLVM_FALLTHROUGH; 188 case CK_Core2: 189 setFeatureEnabledImpl(Features, "ssse3", true); 190 LLVM_FALLTHROUGH; 191 case CK_Yonah: 192 case CK_Prescott: 193 case CK_Nocona: 194 setFeatureEnabledImpl(Features, "sse3", true); 195 setFeatureEnabledImpl(Features, "cx16", true); 196 LLVM_FALLTHROUGH; 197 case CK_PentiumM: 198 case CK_Pentium4: 199 case CK_x86_64: 200 setFeatureEnabledImpl(Features, "sse2", true); 201 LLVM_FALLTHROUGH; 202 case CK_Pentium3: 203 case CK_C3_2: 204 setFeatureEnabledImpl(Features, "sse", true); 205 setFeatureEnabledImpl(Features, "fxsr", true); 206 break; 207 208 case CK_Goldmont: 209 setFeatureEnabledImpl(Features, "sha", true); 210 setFeatureEnabledImpl(Features, "rdrnd", true); 211 setFeatureEnabledImpl(Features, "rdseed", true); 212 setFeatureEnabledImpl(Features, "xsave", true); 213 setFeatureEnabledImpl(Features, "xsaveopt", true); 214 setFeatureEnabledImpl(Features, "xsavec", true); 215 setFeatureEnabledImpl(Features, "xsaves", true); 216 setFeatureEnabledImpl(Features, "clflushopt", true); 217 setFeatureEnabledImpl(Features, "mpx", true); 218 setFeatureEnabledImpl(Features, "fsgsbase", true); 219 LLVM_FALLTHROUGH; 220 case CK_Silvermont: 221 setFeatureEnabledImpl(Features, "aes", true); 222 setFeatureEnabledImpl(Features, "pclmul", true); 223 setFeatureEnabledImpl(Features, "sse4.2", true); 224 LLVM_FALLTHROUGH; 225 case CK_Bonnell: 226 setFeatureEnabledImpl(Features, "movbe", true); 227 setFeatureEnabledImpl(Features, "ssse3", true); 228 setFeatureEnabledImpl(Features, "fxsr", true); 229 setFeatureEnabledImpl(Features, "cx16", true); 230 break; 231 232 case CK_KNL: 233 setFeatureEnabledImpl(Features, "avx512f", true); 234 setFeatureEnabledImpl(Features, "avx512cd", true); 235 setFeatureEnabledImpl(Features, "avx512er", true); 236 setFeatureEnabledImpl(Features, "avx512pf", true); 237 setFeatureEnabledImpl(Features, "prefetchwt1", true); 238 setFeatureEnabledImpl(Features, "fxsr", true); 239 setFeatureEnabledImpl(Features, "rdseed", true); 240 setFeatureEnabledImpl(Features, "adx", true); 241 setFeatureEnabledImpl(Features, "lzcnt", true); 242 setFeatureEnabledImpl(Features, "bmi", true); 243 setFeatureEnabledImpl(Features, "bmi2", true); 244 setFeatureEnabledImpl(Features, "rtm", true); 245 setFeatureEnabledImpl(Features, "fma", true); 246 setFeatureEnabledImpl(Features, "rdrnd", true); 247 setFeatureEnabledImpl(Features, "f16c", true); 248 setFeatureEnabledImpl(Features, "fsgsbase", true); 249 setFeatureEnabledImpl(Features, "aes", true); 250 setFeatureEnabledImpl(Features, "pclmul", true); 251 setFeatureEnabledImpl(Features, "cx16", true); 252 setFeatureEnabledImpl(Features, "xsaveopt", true); 253 setFeatureEnabledImpl(Features, "xsave", true); 254 setFeatureEnabledImpl(Features, "movbe", true); 255 break; 256 257 case CK_K6_2: 258 case CK_K6_3: 259 case CK_WinChip2: 260 case CK_C3: 261 setFeatureEnabledImpl(Features, "3dnow", true); 262 break; 263 264 case CK_AMDFAM10: 265 setFeatureEnabledImpl(Features, "sse4a", true); 266 setFeatureEnabledImpl(Features, "lzcnt", true); 267 setFeatureEnabledImpl(Features, "popcnt", true); 268 LLVM_FALLTHROUGH; 269 case CK_K8SSE3: 270 setFeatureEnabledImpl(Features, "sse3", true); 271 LLVM_FALLTHROUGH; 272 case CK_K8: 273 setFeatureEnabledImpl(Features, "sse2", true); 274 LLVM_FALLTHROUGH; 275 case CK_AthlonXP: 276 setFeatureEnabledImpl(Features, "sse", true); 277 setFeatureEnabledImpl(Features, "fxsr", true); 278 LLVM_FALLTHROUGH; 279 case CK_Athlon: 280 case CK_Geode: 281 setFeatureEnabledImpl(Features, "3dnowa", true); 282 break; 283 284 case CK_BTVER2: 285 setFeatureEnabledImpl(Features, "avx", true); 286 setFeatureEnabledImpl(Features, "aes", true); 287 setFeatureEnabledImpl(Features, "pclmul", true); 288 setFeatureEnabledImpl(Features, "bmi", true); 289 setFeatureEnabledImpl(Features, "f16c", true); 290 setFeatureEnabledImpl(Features, "xsaveopt", true); 291 setFeatureEnabledImpl(Features, "movbe", true); 292 LLVM_FALLTHROUGH; 293 case CK_BTVER1: 294 setFeatureEnabledImpl(Features, "ssse3", true); 295 setFeatureEnabledImpl(Features, "sse4a", true); 296 setFeatureEnabledImpl(Features, "lzcnt", true); 297 setFeatureEnabledImpl(Features, "popcnt", true); 298 setFeatureEnabledImpl(Features, "prfchw", true); 299 setFeatureEnabledImpl(Features, "cx16", true); 300 setFeatureEnabledImpl(Features, "fxsr", true); 301 break; 302 303 case CK_ZNVER1: 304 setFeatureEnabledImpl(Features, "adx", true); 305 setFeatureEnabledImpl(Features, "aes", true); 306 setFeatureEnabledImpl(Features, "avx2", true); 307 setFeatureEnabledImpl(Features, "bmi", true); 308 setFeatureEnabledImpl(Features, "bmi2", true); 309 setFeatureEnabledImpl(Features, "clflushopt", true); 310 setFeatureEnabledImpl(Features, "clzero", true); 311 setFeatureEnabledImpl(Features, "cx16", true); 312 setFeatureEnabledImpl(Features, "f16c", true); 313 setFeatureEnabledImpl(Features, "fma", true); 314 setFeatureEnabledImpl(Features, "fsgsbase", true); 315 setFeatureEnabledImpl(Features, "fxsr", true); 316 setFeatureEnabledImpl(Features, "lzcnt", true); 317 setFeatureEnabledImpl(Features, "mwaitx", true); 318 setFeatureEnabledImpl(Features, "movbe", true); 319 setFeatureEnabledImpl(Features, "pclmul", true); 320 setFeatureEnabledImpl(Features, "popcnt", true); 321 setFeatureEnabledImpl(Features, "prfchw", true); 322 setFeatureEnabledImpl(Features, "rdrnd", true); 323 setFeatureEnabledImpl(Features, "rdseed", true); 324 setFeatureEnabledImpl(Features, "sha", true); 325 setFeatureEnabledImpl(Features, "sse4a", true); 326 setFeatureEnabledImpl(Features, "xsave", true); 327 setFeatureEnabledImpl(Features, "xsavec", true); 328 setFeatureEnabledImpl(Features, "xsaveopt", true); 329 setFeatureEnabledImpl(Features, "xsaves", true); 330 break; 331 332 case CK_BDVER4: 333 setFeatureEnabledImpl(Features, "avx2", true); 334 setFeatureEnabledImpl(Features, "bmi2", true); 335 setFeatureEnabledImpl(Features, "mwaitx", true); 336 LLVM_FALLTHROUGH; 337 case CK_BDVER3: 338 setFeatureEnabledImpl(Features, "fsgsbase", true); 339 setFeatureEnabledImpl(Features, "xsaveopt", true); 340 LLVM_FALLTHROUGH; 341 case CK_BDVER2: 342 setFeatureEnabledImpl(Features, "bmi", true); 343 setFeatureEnabledImpl(Features, "fma", true); 344 setFeatureEnabledImpl(Features, "f16c", true); 345 setFeatureEnabledImpl(Features, "tbm", true); 346 LLVM_FALLTHROUGH; 347 case CK_BDVER1: 348 // xop implies avx, sse4a and fma4. 349 setFeatureEnabledImpl(Features, "xop", true); 350 setFeatureEnabledImpl(Features, "lwp", true); 351 setFeatureEnabledImpl(Features, "lzcnt", true); 352 setFeatureEnabledImpl(Features, "aes", true); 353 setFeatureEnabledImpl(Features, "pclmul", true); 354 setFeatureEnabledImpl(Features, "prfchw", true); 355 setFeatureEnabledImpl(Features, "cx16", true); 356 setFeatureEnabledImpl(Features, "fxsr", true); 357 setFeatureEnabledImpl(Features, "xsave", true); 358 break; 359 } 360 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 361 return false; 362 363 // Can't do this earlier because we need to be able to explicitly enable 364 // or disable these features and the things that they depend upon. 365 366 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 367 auto I = Features.find("sse4.2"); 368 if (I != Features.end() && I->getValue() && 369 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 370 FeaturesVec.end()) 371 Features["popcnt"] = true; 372 373 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 374 I = Features.find("3dnow"); 375 if (I != Features.end() && I->getValue() && 376 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 377 FeaturesVec.end()) 378 Features["prfchw"] = true; 379 380 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 381 // then enable MMX. 382 I = Features.find("sse"); 383 if (I != Features.end() && I->getValue() && 384 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 385 FeaturesVec.end()) 386 Features["mmx"] = true; 387 388 return true; 389 } 390 391 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 392 X86SSEEnum Level, bool Enabled) { 393 if (Enabled) { 394 switch (Level) { 395 case AVX512F: 396 Features["avx512f"] = true; 397 LLVM_FALLTHROUGH; 398 case AVX2: 399 Features["avx2"] = true; 400 LLVM_FALLTHROUGH; 401 case AVX: 402 Features["avx"] = true; 403 Features["xsave"] = true; 404 LLVM_FALLTHROUGH; 405 case SSE42: 406 Features["sse4.2"] = true; 407 LLVM_FALLTHROUGH; 408 case SSE41: 409 Features["sse4.1"] = true; 410 LLVM_FALLTHROUGH; 411 case SSSE3: 412 Features["ssse3"] = true; 413 LLVM_FALLTHROUGH; 414 case SSE3: 415 Features["sse3"] = true; 416 LLVM_FALLTHROUGH; 417 case SSE2: 418 Features["sse2"] = true; 419 LLVM_FALLTHROUGH; 420 case SSE1: 421 Features["sse"] = true; 422 LLVM_FALLTHROUGH; 423 case NoSSE: 424 break; 425 } 426 return; 427 } 428 429 switch (Level) { 430 case NoSSE: 431 case SSE1: 432 Features["sse"] = false; 433 LLVM_FALLTHROUGH; 434 case SSE2: 435 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 436 false; 437 LLVM_FALLTHROUGH; 438 case SSE3: 439 Features["sse3"] = false; 440 setXOPLevel(Features, NoXOP, false); 441 LLVM_FALLTHROUGH; 442 case SSSE3: 443 Features["ssse3"] = false; 444 LLVM_FALLTHROUGH; 445 case SSE41: 446 Features["sse4.1"] = false; 447 LLVM_FALLTHROUGH; 448 case SSE42: 449 Features["sse4.2"] = false; 450 LLVM_FALLTHROUGH; 451 case AVX: 452 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 453 Features["xsaveopt"] = false; 454 setXOPLevel(Features, FMA4, false); 455 LLVM_FALLTHROUGH; 456 case AVX2: 457 Features["avx2"] = false; 458 LLVM_FALLTHROUGH; 459 case AVX512F: 460 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 461 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 462 Features["avx512vl"] = Features["avx512vbmi"] = 463 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 464 break; 465 } 466 } 467 468 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 469 MMX3DNowEnum Level, bool Enabled) { 470 if (Enabled) { 471 switch (Level) { 472 case AMD3DNowAthlon: 473 Features["3dnowa"] = true; 474 LLVM_FALLTHROUGH; 475 case AMD3DNow: 476 Features["3dnow"] = true; 477 LLVM_FALLTHROUGH; 478 case MMX: 479 Features["mmx"] = true; 480 LLVM_FALLTHROUGH; 481 case NoMMX3DNow: 482 break; 483 } 484 return; 485 } 486 487 switch (Level) { 488 case NoMMX3DNow: 489 case MMX: 490 Features["mmx"] = false; 491 LLVM_FALLTHROUGH; 492 case AMD3DNow: 493 Features["3dnow"] = false; 494 LLVM_FALLTHROUGH; 495 case AMD3DNowAthlon: 496 Features["3dnowa"] = false; 497 break; 498 } 499 } 500 501 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 502 bool Enabled) { 503 if (Enabled) { 504 switch (Level) { 505 case XOP: 506 Features["xop"] = true; 507 LLVM_FALLTHROUGH; 508 case FMA4: 509 Features["fma4"] = true; 510 setSSELevel(Features, AVX, true); 511 LLVM_FALLTHROUGH; 512 case SSE4A: 513 Features["sse4a"] = true; 514 setSSELevel(Features, SSE3, true); 515 LLVM_FALLTHROUGH; 516 case NoXOP: 517 break; 518 } 519 return; 520 } 521 522 switch (Level) { 523 case NoXOP: 524 case SSE4A: 525 Features["sse4a"] = false; 526 LLVM_FALLTHROUGH; 527 case FMA4: 528 Features["fma4"] = false; 529 LLVM_FALLTHROUGH; 530 case XOP: 531 Features["xop"] = false; 532 break; 533 } 534 } 535 536 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 537 StringRef Name, bool Enabled) { 538 // This is a bit of a hack to deal with the sse4 target feature when used 539 // as part of the target attribute. We handle sse4 correctly everywhere 540 // else. See below for more information on how we handle the sse4 options. 541 if (Name != "sse4") 542 Features[Name] = Enabled; 543 544 if (Name == "mmx") { 545 setMMXLevel(Features, MMX, Enabled); 546 } else if (Name == "sse") { 547 setSSELevel(Features, SSE1, Enabled); 548 } else if (Name == "sse2") { 549 setSSELevel(Features, SSE2, Enabled); 550 } else if (Name == "sse3") { 551 setSSELevel(Features, SSE3, Enabled); 552 } else if (Name == "ssse3") { 553 setSSELevel(Features, SSSE3, Enabled); 554 } else if (Name == "sse4.2") { 555 setSSELevel(Features, SSE42, Enabled); 556 } else if (Name == "sse4.1") { 557 setSSELevel(Features, SSE41, Enabled); 558 } else if (Name == "3dnow") { 559 setMMXLevel(Features, AMD3DNow, Enabled); 560 } else if (Name == "3dnowa") { 561 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 562 } else if (Name == "aes") { 563 if (Enabled) 564 setSSELevel(Features, SSE2, Enabled); 565 } else if (Name == "pclmul") { 566 if (Enabled) 567 setSSELevel(Features, SSE2, Enabled); 568 } else if (Name == "avx") { 569 setSSELevel(Features, AVX, Enabled); 570 } else if (Name == "avx2") { 571 setSSELevel(Features, AVX2, Enabled); 572 } else if (Name == "avx512f") { 573 setSSELevel(Features, AVX512F, Enabled); 574 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 575 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 576 Name == "avx512vbmi" || Name == "avx512ifma" || 577 Name == "avx512vpopcntdq") { 578 if (Enabled) 579 setSSELevel(Features, AVX512F, Enabled); 580 // Enable BWI instruction if VBMI is being enabled. 581 if (Name == "avx512vbmi" && Enabled) 582 Features["avx512bw"] = true; 583 // Also disable VBMI if BWI is being disabled. 584 if (Name == "avx512bw" && !Enabled) 585 Features["avx512vbmi"] = false; 586 } else if (Name == "fma") { 587 if (Enabled) 588 setSSELevel(Features, AVX, Enabled); 589 } else if (Name == "fma4") { 590 setXOPLevel(Features, FMA4, Enabled); 591 } else if (Name == "xop") { 592 setXOPLevel(Features, XOP, Enabled); 593 } else if (Name == "sse4a") { 594 setXOPLevel(Features, SSE4A, Enabled); 595 } else if (Name == "f16c") { 596 if (Enabled) 597 setSSELevel(Features, AVX, Enabled); 598 } else if (Name == "sha") { 599 if (Enabled) 600 setSSELevel(Features, SSE2, Enabled); 601 } else if (Name == "sse4") { 602 // We can get here via the __target__ attribute since that's not controlled 603 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 604 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 605 // disabled. 606 if (Enabled) 607 setSSELevel(Features, SSE42, Enabled); 608 else 609 setSSELevel(Features, SSE41, Enabled); 610 } else if (Name == "xsave") { 611 if (!Enabled) 612 Features["xsaveopt"] = false; 613 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 614 if (Enabled) 615 Features["xsave"] = true; 616 } 617 } 618 619 /// handleTargetFeatures - Perform initialization based on the user 620 /// configured set of features. 621 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 622 DiagnosticsEngine &Diags) { 623 for (const auto &Feature : Features) { 624 if (Feature[0] != '+') 625 continue; 626 627 if (Feature == "+aes") { 628 HasAES = true; 629 } else if (Feature == "+pclmul") { 630 HasPCLMUL = true; 631 } else if (Feature == "+lzcnt") { 632 HasLZCNT = true; 633 } else if (Feature == "+rdrnd") { 634 HasRDRND = true; 635 } else if (Feature == "+fsgsbase") { 636 HasFSGSBASE = true; 637 } else if (Feature == "+bmi") { 638 HasBMI = true; 639 } else if (Feature == "+bmi2") { 640 HasBMI2 = true; 641 } else if (Feature == "+popcnt") { 642 HasPOPCNT = true; 643 } else if (Feature == "+rtm") { 644 HasRTM = true; 645 } else if (Feature == "+prfchw") { 646 HasPRFCHW = true; 647 } else if (Feature == "+rdseed") { 648 HasRDSEED = true; 649 } else if (Feature == "+adx") { 650 HasADX = true; 651 } else if (Feature == "+tbm") { 652 HasTBM = true; 653 } else if (Feature == "+lwp") { 654 HasLWP = true; 655 } else if (Feature == "+fma") { 656 HasFMA = true; 657 } else if (Feature == "+f16c") { 658 HasF16C = true; 659 } else if (Feature == "+avx512cd") { 660 HasAVX512CD = true; 661 } else if (Feature == "+avx512vpopcntdq") { 662 HasAVX512VPOPCNTDQ = true; 663 } else if (Feature == "+avx512er") { 664 HasAVX512ER = true; 665 } else if (Feature == "+avx512pf") { 666 HasAVX512PF = true; 667 } else if (Feature == "+avx512dq") { 668 HasAVX512DQ = true; 669 } else if (Feature == "+avx512bw") { 670 HasAVX512BW = true; 671 } else if (Feature == "+avx512vl") { 672 HasAVX512VL = true; 673 } else if (Feature == "+avx512vbmi") { 674 HasAVX512VBMI = true; 675 } else if (Feature == "+avx512ifma") { 676 HasAVX512IFMA = true; 677 } else if (Feature == "+sha") { 678 HasSHA = true; 679 } else if (Feature == "+mpx") { 680 HasMPX = true; 681 } else if (Feature == "+movbe") { 682 HasMOVBE = true; 683 } else if (Feature == "+sgx") { 684 HasSGX = true; 685 } else if (Feature == "+cx16") { 686 HasCX16 = true; 687 } else if (Feature == "+fxsr") { 688 HasFXSR = true; 689 } else if (Feature == "+xsave") { 690 HasXSAVE = true; 691 } else if (Feature == "+xsaveopt") { 692 HasXSAVEOPT = true; 693 } else if (Feature == "+xsavec") { 694 HasXSAVEC = true; 695 } else if (Feature == "+xsaves") { 696 HasXSAVES = true; 697 } else if (Feature == "+mwaitx") { 698 HasMWAITX = true; 699 } else if (Feature == "+pku") { 700 HasPKU = true; 701 } else if (Feature == "+clflushopt") { 702 HasCLFLUSHOPT = true; 703 } else if (Feature == "+clwb") { 704 HasCLWB = true; 705 } else if (Feature == "+prefetchwt1") { 706 HasPREFETCHWT1 = true; 707 } else if (Feature == "+clzero") { 708 HasCLZERO = true; 709 } 710 711 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 712 .Case("+avx512f", AVX512F) 713 .Case("+avx2", AVX2) 714 .Case("+avx", AVX) 715 .Case("+sse4.2", SSE42) 716 .Case("+sse4.1", SSE41) 717 .Case("+ssse3", SSSE3) 718 .Case("+sse3", SSE3) 719 .Case("+sse2", SSE2) 720 .Case("+sse", SSE1) 721 .Default(NoSSE); 722 SSELevel = std::max(SSELevel, Level); 723 724 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 725 .Case("+3dnowa", AMD3DNowAthlon) 726 .Case("+3dnow", AMD3DNow) 727 .Case("+mmx", MMX) 728 .Default(NoMMX3DNow); 729 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 730 731 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 732 .Case("+xop", XOP) 733 .Case("+fma4", FMA4) 734 .Case("+sse4a", SSE4A) 735 .Default(NoXOP); 736 XOPLevel = std::max(XOPLevel, XLevel); 737 } 738 739 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 740 // matches the selected sse level. 741 if ((FPMath == FP_SSE && SSELevel < SSE1) || 742 (FPMath == FP_387 && SSELevel >= SSE1)) { 743 Diags.Report(diag::err_target_unsupported_fpmath) 744 << (FPMath == FP_SSE ? "sse" : "387"); 745 return false; 746 } 747 748 SimdDefaultAlign = 749 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 750 return true; 751 } 752 753 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 754 /// definitions for this particular subtarget. 755 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const { 757 // Target identification. 758 if (getTriple().getArch() == llvm::Triple::x86_64) { 759 Builder.defineMacro("__amd64__"); 760 Builder.defineMacro("__amd64"); 761 Builder.defineMacro("__x86_64"); 762 Builder.defineMacro("__x86_64__"); 763 if (getTriple().getArchName() == "x86_64h") { 764 Builder.defineMacro("__x86_64h"); 765 Builder.defineMacro("__x86_64h__"); 766 } 767 } else { 768 DefineStd(Builder, "i386", Opts); 769 } 770 771 // Subtarget options. 772 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 773 // truly should be based on -mtune options. 774 switch (CPU) { 775 case CK_Generic: 776 break; 777 case CK_i386: 778 // The rest are coming from the i386 define above. 779 Builder.defineMacro("__tune_i386__"); 780 break; 781 case CK_i486: 782 case CK_WinChipC6: 783 case CK_WinChip2: 784 case CK_C3: 785 defineCPUMacros(Builder, "i486"); 786 break; 787 case CK_PentiumMMX: 788 Builder.defineMacro("__pentium_mmx__"); 789 Builder.defineMacro("__tune_pentium_mmx__"); 790 LLVM_FALLTHROUGH; 791 case CK_i586: 792 case CK_Pentium: 793 defineCPUMacros(Builder, "i586"); 794 defineCPUMacros(Builder, "pentium"); 795 break; 796 case CK_Pentium3: 797 case CK_PentiumM: 798 Builder.defineMacro("__tune_pentium3__"); 799 LLVM_FALLTHROUGH; 800 case CK_Pentium2: 801 case CK_C3_2: 802 Builder.defineMacro("__tune_pentium2__"); 803 LLVM_FALLTHROUGH; 804 case CK_PentiumPro: 805 Builder.defineMacro("__tune_i686__"); 806 Builder.defineMacro("__tune_pentiumpro__"); 807 LLVM_FALLTHROUGH; 808 case CK_i686: 809 Builder.defineMacro("__i686"); 810 Builder.defineMacro("__i686__"); 811 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 812 Builder.defineMacro("__pentiumpro"); 813 Builder.defineMacro("__pentiumpro__"); 814 break; 815 case CK_Pentium4: 816 defineCPUMacros(Builder, "pentium4"); 817 break; 818 case CK_Yonah: 819 case CK_Prescott: 820 case CK_Nocona: 821 defineCPUMacros(Builder, "nocona"); 822 break; 823 case CK_Core2: 824 case CK_Penryn: 825 defineCPUMacros(Builder, "core2"); 826 break; 827 case CK_Bonnell: 828 defineCPUMacros(Builder, "atom"); 829 break; 830 case CK_Silvermont: 831 defineCPUMacros(Builder, "slm"); 832 break; 833 case CK_Goldmont: 834 defineCPUMacros(Builder, "goldmont"); 835 break; 836 case CK_Nehalem: 837 case CK_Westmere: 838 case CK_SandyBridge: 839 case CK_IvyBridge: 840 case CK_Haswell: 841 case CK_Broadwell: 842 case CK_SkylakeClient: 843 // FIXME: Historically, we defined this legacy name, it would be nice to 844 // remove it at some point. We've never exposed fine-grained names for 845 // recent primary x86 CPUs, and we should keep it that way. 846 defineCPUMacros(Builder, "corei7"); 847 break; 848 case CK_SkylakeServer: 849 defineCPUMacros(Builder, "skx"); 850 break; 851 case CK_Cannonlake: 852 break; 853 case CK_KNL: 854 defineCPUMacros(Builder, "knl"); 855 break; 856 case CK_Lakemont: 857 Builder.defineMacro("__tune_lakemont__"); 858 break; 859 case CK_K6_2: 860 Builder.defineMacro("__k6_2__"); 861 Builder.defineMacro("__tune_k6_2__"); 862 LLVM_FALLTHROUGH; 863 case CK_K6_3: 864 if (CPU != CK_K6_2) { // In case of fallthrough 865 // FIXME: GCC may be enabling these in cases where some other k6 866 // architecture is specified but -m3dnow is explicitly provided. The 867 // exact semantics need to be determined and emulated here. 868 Builder.defineMacro("__k6_3__"); 869 Builder.defineMacro("__tune_k6_3__"); 870 } 871 LLVM_FALLTHROUGH; 872 case CK_K6: 873 defineCPUMacros(Builder, "k6"); 874 break; 875 case CK_Athlon: 876 case CK_AthlonXP: 877 defineCPUMacros(Builder, "athlon"); 878 if (SSELevel != NoSSE) { 879 Builder.defineMacro("__athlon_sse__"); 880 Builder.defineMacro("__tune_athlon_sse__"); 881 } 882 break; 883 case CK_K8: 884 case CK_K8SSE3: 885 case CK_x86_64: 886 defineCPUMacros(Builder, "k8"); 887 break; 888 case CK_AMDFAM10: 889 defineCPUMacros(Builder, "amdfam10"); 890 break; 891 case CK_BTVER1: 892 defineCPUMacros(Builder, "btver1"); 893 break; 894 case CK_BTVER2: 895 defineCPUMacros(Builder, "btver2"); 896 break; 897 case CK_BDVER1: 898 defineCPUMacros(Builder, "bdver1"); 899 break; 900 case CK_BDVER2: 901 defineCPUMacros(Builder, "bdver2"); 902 break; 903 case CK_BDVER3: 904 defineCPUMacros(Builder, "bdver3"); 905 break; 906 case CK_BDVER4: 907 defineCPUMacros(Builder, "bdver4"); 908 break; 909 case CK_ZNVER1: 910 defineCPUMacros(Builder, "znver1"); 911 break; 912 case CK_Geode: 913 defineCPUMacros(Builder, "geode"); 914 break; 915 } 916 917 // Target properties. 918 Builder.defineMacro("__REGISTER_PREFIX__", ""); 919 920 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 921 // functions in glibc header files that use FP Stack inline asm which the 922 // backend can't deal with (PR879). 923 Builder.defineMacro("__NO_MATH_INLINES"); 924 925 if (HasAES) 926 Builder.defineMacro("__AES__"); 927 928 if (HasPCLMUL) 929 Builder.defineMacro("__PCLMUL__"); 930 931 if (HasLZCNT) 932 Builder.defineMacro("__LZCNT__"); 933 934 if (HasRDRND) 935 Builder.defineMacro("__RDRND__"); 936 937 if (HasFSGSBASE) 938 Builder.defineMacro("__FSGSBASE__"); 939 940 if (HasBMI) 941 Builder.defineMacro("__BMI__"); 942 943 if (HasBMI2) 944 Builder.defineMacro("__BMI2__"); 945 946 if (HasPOPCNT) 947 Builder.defineMacro("__POPCNT__"); 948 949 if (HasRTM) 950 Builder.defineMacro("__RTM__"); 951 952 if (HasPRFCHW) 953 Builder.defineMacro("__PRFCHW__"); 954 955 if (HasRDSEED) 956 Builder.defineMacro("__RDSEED__"); 957 958 if (HasADX) 959 Builder.defineMacro("__ADX__"); 960 961 if (HasTBM) 962 Builder.defineMacro("__TBM__"); 963 964 if (HasLWP) 965 Builder.defineMacro("__LWP__"); 966 967 if (HasMWAITX) 968 Builder.defineMacro("__MWAITX__"); 969 970 switch (XOPLevel) { 971 case XOP: 972 Builder.defineMacro("__XOP__"); 973 LLVM_FALLTHROUGH; 974 case FMA4: 975 Builder.defineMacro("__FMA4__"); 976 LLVM_FALLTHROUGH; 977 case SSE4A: 978 Builder.defineMacro("__SSE4A__"); 979 LLVM_FALLTHROUGH; 980 case NoXOP: 981 break; 982 } 983 984 if (HasFMA) 985 Builder.defineMacro("__FMA__"); 986 987 if (HasF16C) 988 Builder.defineMacro("__F16C__"); 989 990 if (HasAVX512CD) 991 Builder.defineMacro("__AVX512CD__"); 992 if (HasAVX512VPOPCNTDQ) 993 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 994 if (HasAVX512ER) 995 Builder.defineMacro("__AVX512ER__"); 996 if (HasAVX512PF) 997 Builder.defineMacro("__AVX512PF__"); 998 if (HasAVX512DQ) 999 Builder.defineMacro("__AVX512DQ__"); 1000 if (HasAVX512BW) 1001 Builder.defineMacro("__AVX512BW__"); 1002 if (HasAVX512VL) 1003 Builder.defineMacro("__AVX512VL__"); 1004 if (HasAVX512VBMI) 1005 Builder.defineMacro("__AVX512VBMI__"); 1006 if (HasAVX512IFMA) 1007 Builder.defineMacro("__AVX512IFMA__"); 1008 1009 if (HasSHA) 1010 Builder.defineMacro("__SHA__"); 1011 1012 if (HasFXSR) 1013 Builder.defineMacro("__FXSR__"); 1014 if (HasXSAVE) 1015 Builder.defineMacro("__XSAVE__"); 1016 if (HasXSAVEOPT) 1017 Builder.defineMacro("__XSAVEOPT__"); 1018 if (HasXSAVEC) 1019 Builder.defineMacro("__XSAVEC__"); 1020 if (HasXSAVES) 1021 Builder.defineMacro("__XSAVES__"); 1022 if (HasPKU) 1023 Builder.defineMacro("__PKU__"); 1024 if (HasCX16) 1025 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1026 if (HasCLFLUSHOPT) 1027 Builder.defineMacro("__CLFLUSHOPT__"); 1028 if (HasCLWB) 1029 Builder.defineMacro("__CLWB__"); 1030 if (HasMPX) 1031 Builder.defineMacro("__MPX__"); 1032 if (HasSGX) 1033 Builder.defineMacro("__SGX__"); 1034 if (HasPREFETCHWT1) 1035 Builder.defineMacro("__PREFETCHWT1__"); 1036 if (HasCLZERO) 1037 Builder.defineMacro("__CLZERO__"); 1038 1039 // Each case falls through to the previous one here. 1040 switch (SSELevel) { 1041 case AVX512F: 1042 Builder.defineMacro("__AVX512F__"); 1043 LLVM_FALLTHROUGH; 1044 case AVX2: 1045 Builder.defineMacro("__AVX2__"); 1046 LLVM_FALLTHROUGH; 1047 case AVX: 1048 Builder.defineMacro("__AVX__"); 1049 LLVM_FALLTHROUGH; 1050 case SSE42: 1051 Builder.defineMacro("__SSE4_2__"); 1052 LLVM_FALLTHROUGH; 1053 case SSE41: 1054 Builder.defineMacro("__SSE4_1__"); 1055 LLVM_FALLTHROUGH; 1056 case SSSE3: 1057 Builder.defineMacro("__SSSE3__"); 1058 LLVM_FALLTHROUGH; 1059 case SSE3: 1060 Builder.defineMacro("__SSE3__"); 1061 LLVM_FALLTHROUGH; 1062 case SSE2: 1063 Builder.defineMacro("__SSE2__"); 1064 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1065 LLVM_FALLTHROUGH; 1066 case SSE1: 1067 Builder.defineMacro("__SSE__"); 1068 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1069 LLVM_FALLTHROUGH; 1070 case NoSSE: 1071 break; 1072 } 1073 1074 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1075 switch (SSELevel) { 1076 case AVX512F: 1077 case AVX2: 1078 case AVX: 1079 case SSE42: 1080 case SSE41: 1081 case SSSE3: 1082 case SSE3: 1083 case SSE2: 1084 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1085 break; 1086 case SSE1: 1087 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1088 break; 1089 default: 1090 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1091 break; 1092 } 1093 } 1094 1095 // Each case falls through to the previous one here. 1096 switch (MMX3DNowLevel) { 1097 case AMD3DNowAthlon: 1098 Builder.defineMacro("__3dNOW_A__"); 1099 LLVM_FALLTHROUGH; 1100 case AMD3DNow: 1101 Builder.defineMacro("__3dNOW__"); 1102 LLVM_FALLTHROUGH; 1103 case MMX: 1104 Builder.defineMacro("__MMX__"); 1105 LLVM_FALLTHROUGH; 1106 case NoMMX3DNow: 1107 break; 1108 } 1109 1110 if (CPU >= CK_i486) { 1111 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1112 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1113 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1114 } 1115 if (CPU >= CK_i586) 1116 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1117 1118 if (HasFloat128) 1119 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1120 } 1121 1122 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1123 return llvm::StringSwitch<bool>(Name) 1124 .Case("aes", true) 1125 .Case("avx", true) 1126 .Case("avx2", true) 1127 .Case("avx512f", true) 1128 .Case("avx512cd", true) 1129 .Case("avx512vpopcntdq", true) 1130 .Case("avx512er", true) 1131 .Case("avx512pf", true) 1132 .Case("avx512dq", true) 1133 .Case("avx512bw", true) 1134 .Case("avx512vl", true) 1135 .Case("avx512vbmi", true) 1136 .Case("avx512ifma", true) 1137 .Case("bmi", true) 1138 .Case("bmi2", true) 1139 .Case("clflushopt", true) 1140 .Case("clwb", true) 1141 .Case("clzero", true) 1142 .Case("cx16", true) 1143 .Case("f16c", true) 1144 .Case("fma", true) 1145 .Case("fma4", true) 1146 .Case("fsgsbase", true) 1147 .Case("fxsr", true) 1148 .Case("lwp", true) 1149 .Case("lzcnt", true) 1150 .Case("mm3dnow", true) 1151 .Case("mm3dnowa", true) 1152 .Case("mmx", true) 1153 .Case("movbe", true) 1154 .Case("mpx", true) 1155 .Case("pclmul", true) 1156 .Case("pku", true) 1157 .Case("popcnt", true) 1158 .Case("prefetchwt1", true) 1159 .Case("prfchw", true) 1160 .Case("rdrnd", true) 1161 .Case("rdseed", true) 1162 .Case("rtm", true) 1163 .Case("sgx", true) 1164 .Case("sha", true) 1165 .Case("sse", true) 1166 .Case("sse2", true) 1167 .Case("sse3", true) 1168 .Case("ssse3", true) 1169 .Case("sse4.1", true) 1170 .Case("sse4.2", true) 1171 .Case("sse4a", true) 1172 .Case("tbm", true) 1173 .Case("x86", true) 1174 .Case("x86_32", true) 1175 .Case("x86_64", true) 1176 .Case("xop", true) 1177 .Case("xsave", true) 1178 .Case("xsavec", true) 1179 .Case("xsaves", true) 1180 .Case("xsaveopt", true) 1181 .Default(false); 1182 } 1183 1184 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1185 return llvm::StringSwitch<bool>(Feature) 1186 .Case("aes", HasAES) 1187 .Case("avx", SSELevel >= AVX) 1188 .Case("avx2", SSELevel >= AVX2) 1189 .Case("avx512f", SSELevel >= AVX512F) 1190 .Case("avx512cd", HasAVX512CD) 1191 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1192 .Case("avx512er", HasAVX512ER) 1193 .Case("avx512pf", HasAVX512PF) 1194 .Case("avx512dq", HasAVX512DQ) 1195 .Case("avx512bw", HasAVX512BW) 1196 .Case("avx512vl", HasAVX512VL) 1197 .Case("avx512vbmi", HasAVX512VBMI) 1198 .Case("avx512ifma", HasAVX512IFMA) 1199 .Case("bmi", HasBMI) 1200 .Case("bmi2", HasBMI2) 1201 .Case("clflushopt", HasCLFLUSHOPT) 1202 .Case("clwb", HasCLWB) 1203 .Case("clzero", HasCLZERO) 1204 .Case("cx16", HasCX16) 1205 .Case("f16c", HasF16C) 1206 .Case("fma", HasFMA) 1207 .Case("fma4", XOPLevel >= FMA4) 1208 .Case("fsgsbase", HasFSGSBASE) 1209 .Case("fxsr", HasFXSR) 1210 .Case("lwp", HasLWP) 1211 .Case("lzcnt", HasLZCNT) 1212 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1213 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1214 .Case("mmx", MMX3DNowLevel >= MMX) 1215 .Case("movbe", HasMOVBE) 1216 .Case("mpx", HasMPX) 1217 .Case("pclmul", HasPCLMUL) 1218 .Case("pku", HasPKU) 1219 .Case("popcnt", HasPOPCNT) 1220 .Case("prefetchwt1", HasPREFETCHWT1) 1221 .Case("prfchw", HasPRFCHW) 1222 .Case("rdrnd", HasRDRND) 1223 .Case("rdseed", HasRDSEED) 1224 .Case("rtm", HasRTM) 1225 .Case("sgx", HasSGX) 1226 .Case("sha", HasSHA) 1227 .Case("sse", SSELevel >= SSE1) 1228 .Case("sse2", SSELevel >= SSE2) 1229 .Case("sse3", SSELevel >= SSE3) 1230 .Case("ssse3", SSELevel >= SSSE3) 1231 .Case("sse4.1", SSELevel >= SSE41) 1232 .Case("sse4.2", SSELevel >= SSE42) 1233 .Case("sse4a", XOPLevel >= SSE4A) 1234 .Case("tbm", HasTBM) 1235 .Case("x86", true) 1236 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1237 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1238 .Case("xop", XOPLevel >= XOP) 1239 .Case("xsave", HasXSAVE) 1240 .Case("xsavec", HasXSAVEC) 1241 .Case("xsaves", HasXSAVES) 1242 .Case("xsaveopt", HasXSAVEOPT) 1243 .Default(false); 1244 } 1245 1246 // We can't use a generic validation scheme for the features accepted here 1247 // versus subtarget features accepted in the target attribute because the 1248 // bitfield structure that's initialized in the runtime only supports the 1249 // below currently rather than the full range of subtarget features. (See 1250 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1251 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1252 return llvm::StringSwitch<bool>(FeatureStr) 1253 .Case("cmov", true) 1254 .Case("mmx", true) 1255 .Case("popcnt", true) 1256 .Case("sse", true) 1257 .Case("sse2", true) 1258 .Case("sse3", true) 1259 .Case("ssse3", true) 1260 .Case("sse4.1", true) 1261 .Case("sse4.2", true) 1262 .Case("avx", true) 1263 .Case("avx2", true) 1264 .Case("sse4a", true) 1265 .Case("fma4", true) 1266 .Case("xop", true) 1267 .Case("fma", true) 1268 .Case("avx512f", true) 1269 .Case("bmi", true) 1270 .Case("bmi2", true) 1271 .Case("aes", true) 1272 .Case("pclmul", true) 1273 .Case("avx512vl", true) 1274 .Case("avx512bw", true) 1275 .Case("avx512dq", true) 1276 .Case("avx512cd", true) 1277 .Case("avx512er", true) 1278 .Case("avx512pf", true) 1279 .Case("avx512vbmi", true) 1280 .Case("avx512ifma", true) 1281 .Case("avx5124vnniw", true) 1282 .Case("avx5124fmaps", true) 1283 .Case("avx512vpopcntdq", true) 1284 .Default(false); 1285 } 1286 1287 // We can't use a generic validation scheme for the cpus accepted here 1288 // versus subtarget cpus accepted in the target attribute because the 1289 // variables intitialized by the runtime only support the below currently 1290 // rather than the full range of cpus. 1291 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1292 return llvm::StringSwitch<bool>(FeatureStr) 1293 .Case("amd", true) 1294 .Case("amdfam10h", true) 1295 .Case("amdfam15h", true) 1296 .Case("atom", true) 1297 .Case("barcelona", true) 1298 .Case("bdver1", true) 1299 .Case("bdver2", true) 1300 .Case("bdver3", true) 1301 .Case("bdver4", true) 1302 .Case("bonnell", true) 1303 .Case("broadwell", true) 1304 .Case("btver1", true) 1305 .Case("btver2", true) 1306 .Case("core2", true) 1307 .Case("corei7", true) 1308 .Case("haswell", true) 1309 .Case("intel", true) 1310 .Case("istanbul", true) 1311 .Case("ivybridge", true) 1312 .Case("knl", true) 1313 .Case("nehalem", true) 1314 .Case("sandybridge", true) 1315 .Case("shanghai", true) 1316 .Case("silvermont", true) 1317 .Case("skylake", true) 1318 .Case("skylake-avx512", true) 1319 .Case("slm", true) 1320 .Case("westmere", true) 1321 .Case("znver1", true) 1322 .Default(false); 1323 } 1324 1325 bool X86TargetInfo::validateAsmConstraint( 1326 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1327 switch (*Name) { 1328 default: 1329 return false; 1330 // Constant constraints. 1331 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1332 // instructions. 1333 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1334 // x86_64 instructions. 1335 case 's': 1336 Info.setRequiresImmediate(); 1337 return true; 1338 case 'I': 1339 Info.setRequiresImmediate(0, 31); 1340 return true; 1341 case 'J': 1342 Info.setRequiresImmediate(0, 63); 1343 return true; 1344 case 'K': 1345 Info.setRequiresImmediate(-128, 127); 1346 return true; 1347 case 'L': 1348 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1349 return true; 1350 case 'M': 1351 Info.setRequiresImmediate(0, 3); 1352 return true; 1353 case 'N': 1354 Info.setRequiresImmediate(0, 255); 1355 return true; 1356 case 'O': 1357 Info.setRequiresImmediate(0, 127); 1358 return true; 1359 // Register constraints. 1360 case 'Y': // 'Y' is the first character for several 2-character constraints. 1361 // Shift the pointer to the second character of the constraint. 1362 Name++; 1363 switch (*Name) { 1364 default: 1365 return false; 1366 case 'z': 1367 case '0': // First SSE register. 1368 case '2': 1369 case 't': // Any SSE register, when SSE2 is enabled. 1370 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1371 case 'm': // Any MMX register, when inter-unit moves enabled. 1372 case 'k': // AVX512 arch mask registers: k1-k7. 1373 Info.setAllowsRegister(); 1374 return true; 1375 } 1376 case 'f': // Any x87 floating point stack register. 1377 // Constraint 'f' cannot be used for output operands. 1378 if (Info.ConstraintStr[0] == '=') 1379 return false; 1380 Info.setAllowsRegister(); 1381 return true; 1382 case 'a': // eax. 1383 case 'b': // ebx. 1384 case 'c': // ecx. 1385 case 'd': // edx. 1386 case 'S': // esi. 1387 case 'D': // edi. 1388 case 'A': // edx:eax. 1389 case 't': // Top of floating point stack. 1390 case 'u': // Second from top of floating point stack. 1391 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1392 case 'y': // Any MMX register. 1393 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1394 case 'x': // Any SSE register. 1395 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1396 // for intermideate k reg operations). 1397 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1398 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1399 case 'l': // "Index" registers: any general register that can be used as an 1400 // index in a base+index memory access. 1401 Info.setAllowsRegister(); 1402 return true; 1403 // Floating point constant constraints. 1404 case 'C': // SSE floating point constant. 1405 case 'G': // x87 floating point constant. 1406 return true; 1407 } 1408 } 1409 1410 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1411 unsigned Size) const { 1412 // Strip off constraint modifiers. 1413 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1414 Constraint = Constraint.substr(1); 1415 1416 return validateOperandSize(Constraint, Size); 1417 } 1418 1419 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1420 unsigned Size) const { 1421 return validateOperandSize(Constraint, Size); 1422 } 1423 1424 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1425 unsigned Size) const { 1426 switch (Constraint[0]) { 1427 default: 1428 break; 1429 case 'k': 1430 // Registers k0-k7 (AVX512) size limit is 64 bit. 1431 case 'y': 1432 return Size <= 64; 1433 case 'f': 1434 case 't': 1435 case 'u': 1436 return Size <= 128; 1437 case 'Y': 1438 // 'Y' is the first character for several 2-character constraints. 1439 switch (Constraint[1]) { 1440 default: 1441 return false; 1442 case 'm': 1443 // 'Ym' is synonymous with 'y'. 1444 case 'k': 1445 return Size <= 64; 1446 case 'z': 1447 case '0': 1448 // XMM0 1449 if (SSELevel >= SSE1) 1450 return Size <= 128U; 1451 return false; 1452 case 'i': 1453 case 't': 1454 case '2': 1455 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1456 if (SSELevel < SSE2) 1457 return false; 1458 break; 1459 } 1460 case 'v': 1461 case 'x': 1462 if (SSELevel >= AVX512F) 1463 // 512-bit zmm registers can be used if target supports AVX512F. 1464 return Size <= 512U; 1465 else if (SSELevel >= AVX) 1466 // 256-bit ymm registers can be used if target supports AVX. 1467 return Size <= 256U; 1468 return Size <= 128U; 1469 1470 } 1471 1472 return true; 1473 } 1474 1475 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1476 switch (*Constraint) { 1477 case 'a': 1478 return std::string("{ax}"); 1479 case 'b': 1480 return std::string("{bx}"); 1481 case 'c': 1482 return std::string("{cx}"); 1483 case 'd': 1484 return std::string("{dx}"); 1485 case 'S': 1486 return std::string("{si}"); 1487 case 'D': 1488 return std::string("{di}"); 1489 case 'p': // address 1490 return std::string("im"); 1491 case 't': // top of floating point stack. 1492 return std::string("{st}"); 1493 case 'u': // second from top of floating point stack. 1494 return std::string("{st(1)}"); // second from top of floating point stack. 1495 case 'Y': 1496 switch (Constraint[1]) { 1497 default: 1498 // Break from inner switch and fall through (copy single char), 1499 // continue parsing after copying the current constraint into 1500 // the return string. 1501 break; 1502 case 'k': 1503 case 'm': 1504 case 'i': 1505 case 't': 1506 case 'z': 1507 case '0': 1508 case '2': 1509 // "^" hints llvm that this is a 2 letter constraint. 1510 // "Constraint++" is used to promote the string iterator 1511 // to the next constraint. 1512 return std::string("^") + std::string(Constraint++, 2); 1513 } 1514 LLVM_FALLTHROUGH; 1515 default: 1516 return std::string(1, *Constraint); 1517 } 1518 } 1519 1520 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1521 return llvm::StringSwitch<CPUKind>(CPU) 1522 .Case("i386", CK_i386) 1523 .Case("i486", CK_i486) 1524 .Case("winchip-c6", CK_WinChipC6) 1525 .Case("winchip2", CK_WinChip2) 1526 .Case("c3", CK_C3) 1527 .Case("i586", CK_i586) 1528 .Case("pentium", CK_Pentium) 1529 .Case("pentium-mmx", CK_PentiumMMX) 1530 .Case("i686", CK_i686) 1531 .Case("pentiumpro", CK_PentiumPro) 1532 .Case("pentium2", CK_Pentium2) 1533 .Cases("pentium3", "pentium3m", CK_Pentium3) 1534 .Case("pentium-m", CK_PentiumM) 1535 .Case("c3-2", CK_C3_2) 1536 .Case("yonah", CK_Yonah) 1537 .Cases("pentium4", "pentium4m", CK_Pentium4) 1538 .Case("prescott", CK_Prescott) 1539 .Case("nocona", CK_Nocona) 1540 .Case("core2", CK_Core2) 1541 .Case("penryn", CK_Penryn) 1542 .Cases("bonnell", "atom", CK_Bonnell) 1543 .Cases("silvermont", "slm", CK_Silvermont) 1544 .Case("goldmont", CK_Goldmont) 1545 .Cases("nehalem", "corei7", CK_Nehalem) 1546 .Case("westmere", CK_Westmere) 1547 .Cases("sandybridge", "corei7-avx", CK_SandyBridge) 1548 .Cases("ivybridge", "core-avx-i", CK_IvyBridge) 1549 .Cases("haswell", "core-avx2", CK_Haswell) 1550 .Case("broadwell", CK_Broadwell) 1551 .Case("skylake", CK_SkylakeClient) 1552 .Cases("skylake-avx512", "skx", CK_SkylakeServer) 1553 .Case("cannonlake", CK_Cannonlake) 1554 .Case("knl", CK_KNL) 1555 .Case("lakemont", CK_Lakemont) 1556 .Case("k6", CK_K6) 1557 .Case("k6-2", CK_K6_2) 1558 .Case("k6-3", CK_K6_3) 1559 .Cases("athlon", "athlon-tbird", CK_Athlon) 1560 .Cases("athlon-xp", "athlon-mp", "athlon-4", CK_AthlonXP) 1561 .Cases("k8", "athlon64", "athlon-fx", "opteron", CK_K8) 1562 .Cases("k8-sse3", "athlon64-sse3", "opteron-sse3", CK_K8SSE3) 1563 .Cases("amdfam10", "barcelona", CK_AMDFAM10) 1564 .Case("btver1", CK_BTVER1) 1565 .Case("btver2", CK_BTVER2) 1566 .Case("bdver1", CK_BDVER1) 1567 .Case("bdver2", CK_BDVER2) 1568 .Case("bdver3", CK_BDVER3) 1569 .Case("bdver4", CK_BDVER4) 1570 .Case("znver1", CK_ZNVER1) 1571 .Case("x86-64", CK_x86_64) 1572 .Case("geode", CK_Geode) 1573 .Default(CK_Generic); 1574 } 1575 1576 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1577 return llvm::makeArrayRef(GCCRegNames); 1578 } 1579 1580 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1581 return llvm::makeArrayRef(AddlRegNames); 1582 } 1583 1584 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1585 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1586 Builtin::FirstTSBuiltin + 1); 1587 } 1588 1589 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1590 return llvm::makeArrayRef(BuiltinInfoX86, 1591 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1592 } 1593