1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 }; 64 65 const TargetInfo::AddlRegName AddlRegNames[] = { 66 {{"al", "ah", "eax", "rax"}, 0}, 67 {{"bl", "bh", "ebx", "rbx"}, 3}, 68 {{"cl", "ch", "ecx", "rcx"}, 2}, 69 {{"dl", "dh", "edx", "rdx"}, 1}, 70 {{"esi", "rsi"}, 4}, 71 {{"edi", "rdi"}, 5}, 72 {{"esp", "rsp"}, 7}, 73 {{"ebp", "rbp"}, 6}, 74 {{"r8d", "r8w", "r8b"}, 38}, 75 {{"r9d", "r9w", "r9b"}, 39}, 76 {{"r10d", "r10w", "r10b"}, 40}, 77 {{"r11d", "r11w", "r11b"}, 41}, 78 {{"r12d", "r12w", "r12b"}, 42}, 79 {{"r13d", "r13w", "r13b"}, 43}, 80 {{"r14d", "r14w", "r14b"}, 44}, 81 {{"r15d", "r15w", "r15b"}, 45}, 82 }; 83 84 } // namespace targets 85 } // namespace clang 86 87 using namespace clang; 88 using namespace clang::targets; 89 90 bool X86TargetInfo::setFPMath(StringRef Name) { 91 if (Name == "387") { 92 FPMath = FP_387; 93 return true; 94 } 95 if (Name == "sse") { 96 FPMath = FP_SSE; 97 return true; 98 } 99 return false; 100 } 101 102 bool X86TargetInfo::initFeatureMap( 103 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 104 const std::vector<std::string> &FeaturesVec) const { 105 // FIXME: This *really* should not be here. 106 // X86_64 always has SSE2. 107 if (getTriple().getArch() == llvm::Triple::x86_64) 108 setFeatureEnabledImpl(Features, "sse2", true); 109 110 const CPUKind Kind = getCPUKind(CPU); 111 112 // Enable X87 for all X86 processors but Lakemont. 113 if (Kind != CK_Lakemont) 114 setFeatureEnabledImpl(Features, "x87", true); 115 116 switch (Kind) { 117 case CK_Generic: 118 case CK_i386: 119 case CK_i486: 120 case CK_i586: 121 case CK_Pentium: 122 case CK_i686: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 127 case CK_PentiumMMX: 128 case CK_Pentium2: 129 case CK_K6: 130 case CK_WinChipC6: 131 setFeatureEnabledImpl(Features, "mmx", true); 132 break; 133 134 case CK_Cannonlake: 135 setFeatureEnabledImpl(Features, "avx512ifma", true); 136 setFeatureEnabledImpl(Features, "avx512vbmi", true); 137 setFeatureEnabledImpl(Features, "sha", true); 138 LLVM_FALLTHROUGH; 139 case CK_SkylakeServer: 140 setFeatureEnabledImpl(Features, "avx512f", true); 141 setFeatureEnabledImpl(Features, "avx512cd", true); 142 setFeatureEnabledImpl(Features, "avx512dq", true); 143 setFeatureEnabledImpl(Features, "avx512bw", true); 144 setFeatureEnabledImpl(Features, "avx512vl", true); 145 setFeatureEnabledImpl(Features, "pku", true); 146 setFeatureEnabledImpl(Features, "clwb", true); 147 LLVM_FALLTHROUGH; 148 case CK_SkylakeClient: 149 setFeatureEnabledImpl(Features, "xsavec", true); 150 setFeatureEnabledImpl(Features, "xsaves", true); 151 setFeatureEnabledImpl(Features, "mpx", true); 152 setFeatureEnabledImpl(Features, "sgx", true); 153 setFeatureEnabledImpl(Features, "clflushopt", true); 154 setFeatureEnabledImpl(Features, "rtm", true); 155 LLVM_FALLTHROUGH; 156 case CK_Broadwell: 157 setFeatureEnabledImpl(Features, "rdseed", true); 158 setFeatureEnabledImpl(Features, "adx", true); 159 LLVM_FALLTHROUGH; 160 case CK_Haswell: 161 setFeatureEnabledImpl(Features, "avx2", true); 162 setFeatureEnabledImpl(Features, "lzcnt", true); 163 setFeatureEnabledImpl(Features, "bmi", true); 164 setFeatureEnabledImpl(Features, "bmi2", true); 165 setFeatureEnabledImpl(Features, "fma", true); 166 setFeatureEnabledImpl(Features, "movbe", true); 167 LLVM_FALLTHROUGH; 168 case CK_IvyBridge: 169 setFeatureEnabledImpl(Features, "rdrnd", true); 170 setFeatureEnabledImpl(Features, "f16c", true); 171 setFeatureEnabledImpl(Features, "fsgsbase", true); 172 LLVM_FALLTHROUGH; 173 case CK_SandyBridge: 174 setFeatureEnabledImpl(Features, "avx", true); 175 setFeatureEnabledImpl(Features, "xsave", true); 176 setFeatureEnabledImpl(Features, "xsaveopt", true); 177 LLVM_FALLTHROUGH; 178 case CK_Westmere: 179 setFeatureEnabledImpl(Features, "aes", true); 180 setFeatureEnabledImpl(Features, "pclmul", true); 181 LLVM_FALLTHROUGH; 182 case CK_Nehalem: 183 setFeatureEnabledImpl(Features, "sse4.2", true); 184 LLVM_FALLTHROUGH; 185 case CK_Penryn: 186 setFeatureEnabledImpl(Features, "sse4.1", true); 187 LLVM_FALLTHROUGH; 188 case CK_Core2: 189 setFeatureEnabledImpl(Features, "ssse3", true); 190 LLVM_FALLTHROUGH; 191 case CK_Yonah: 192 case CK_Prescott: 193 case CK_Nocona: 194 setFeatureEnabledImpl(Features, "sse3", true); 195 setFeatureEnabledImpl(Features, "cx16", true); 196 LLVM_FALLTHROUGH; 197 case CK_PentiumM: 198 case CK_Pentium4: 199 case CK_x86_64: 200 setFeatureEnabledImpl(Features, "sse2", true); 201 LLVM_FALLTHROUGH; 202 case CK_Pentium3: 203 case CK_C3_2: 204 setFeatureEnabledImpl(Features, "sse", true); 205 setFeatureEnabledImpl(Features, "fxsr", true); 206 break; 207 208 case CK_Goldmont: 209 setFeatureEnabledImpl(Features, "sha", true); 210 setFeatureEnabledImpl(Features, "rdrnd", true); 211 setFeatureEnabledImpl(Features, "rdseed", true); 212 setFeatureEnabledImpl(Features, "xsave", true); 213 setFeatureEnabledImpl(Features, "xsaveopt", true); 214 setFeatureEnabledImpl(Features, "xsavec", true); 215 setFeatureEnabledImpl(Features, "xsaves", true); 216 setFeatureEnabledImpl(Features, "clflushopt", true); 217 setFeatureEnabledImpl(Features, "mpx", true); 218 setFeatureEnabledImpl(Features, "fsgsbase", true); 219 LLVM_FALLTHROUGH; 220 case CK_Silvermont: 221 setFeatureEnabledImpl(Features, "aes", true); 222 setFeatureEnabledImpl(Features, "pclmul", true); 223 setFeatureEnabledImpl(Features, "sse4.2", true); 224 LLVM_FALLTHROUGH; 225 case CK_Bonnell: 226 setFeatureEnabledImpl(Features, "movbe", true); 227 setFeatureEnabledImpl(Features, "ssse3", true); 228 setFeatureEnabledImpl(Features, "fxsr", true); 229 setFeatureEnabledImpl(Features, "cx16", true); 230 break; 231 232 case CK_KNM: 233 // TODO: Add avx5124fmaps/avx5124vnniw. 234 case CK_KNL: 235 setFeatureEnabledImpl(Features, "avx512f", true); 236 setFeatureEnabledImpl(Features, "avx512cd", true); 237 setFeatureEnabledImpl(Features, "avx512er", true); 238 setFeatureEnabledImpl(Features, "avx512pf", true); 239 setFeatureEnabledImpl(Features, "prefetchwt1", true); 240 setFeatureEnabledImpl(Features, "fxsr", true); 241 setFeatureEnabledImpl(Features, "rdseed", true); 242 setFeatureEnabledImpl(Features, "adx", true); 243 setFeatureEnabledImpl(Features, "lzcnt", true); 244 setFeatureEnabledImpl(Features, "bmi", true); 245 setFeatureEnabledImpl(Features, "bmi2", true); 246 setFeatureEnabledImpl(Features, "rtm", true); 247 setFeatureEnabledImpl(Features, "fma", true); 248 setFeatureEnabledImpl(Features, "rdrnd", true); 249 setFeatureEnabledImpl(Features, "f16c", true); 250 setFeatureEnabledImpl(Features, "fsgsbase", true); 251 setFeatureEnabledImpl(Features, "aes", true); 252 setFeatureEnabledImpl(Features, "pclmul", true); 253 setFeatureEnabledImpl(Features, "cx16", true); 254 setFeatureEnabledImpl(Features, "xsaveopt", true); 255 setFeatureEnabledImpl(Features, "xsave", true); 256 setFeatureEnabledImpl(Features, "movbe", true); 257 break; 258 259 case CK_K6_2: 260 case CK_K6_3: 261 case CK_WinChip2: 262 case CK_C3: 263 setFeatureEnabledImpl(Features, "3dnow", true); 264 break; 265 266 case CK_AMDFAM10: 267 setFeatureEnabledImpl(Features, "sse4a", true); 268 setFeatureEnabledImpl(Features, "lzcnt", true); 269 setFeatureEnabledImpl(Features, "popcnt", true); 270 LLVM_FALLTHROUGH; 271 case CK_K8SSE3: 272 setFeatureEnabledImpl(Features, "sse3", true); 273 LLVM_FALLTHROUGH; 274 case CK_K8: 275 setFeatureEnabledImpl(Features, "sse2", true); 276 LLVM_FALLTHROUGH; 277 case CK_AthlonXP: 278 setFeatureEnabledImpl(Features, "sse", true); 279 setFeatureEnabledImpl(Features, "fxsr", true); 280 LLVM_FALLTHROUGH; 281 case CK_Athlon: 282 case CK_Geode: 283 setFeatureEnabledImpl(Features, "3dnowa", true); 284 break; 285 286 case CK_BTVER2: 287 setFeatureEnabledImpl(Features, "avx", true); 288 setFeatureEnabledImpl(Features, "aes", true); 289 setFeatureEnabledImpl(Features, "pclmul", true); 290 setFeatureEnabledImpl(Features, "bmi", true); 291 setFeatureEnabledImpl(Features, "f16c", true); 292 setFeatureEnabledImpl(Features, "xsaveopt", true); 293 setFeatureEnabledImpl(Features, "movbe", true); 294 LLVM_FALLTHROUGH; 295 case CK_BTVER1: 296 setFeatureEnabledImpl(Features, "ssse3", true); 297 setFeatureEnabledImpl(Features, "sse4a", true); 298 setFeatureEnabledImpl(Features, "lzcnt", true); 299 setFeatureEnabledImpl(Features, "popcnt", true); 300 setFeatureEnabledImpl(Features, "prfchw", true); 301 setFeatureEnabledImpl(Features, "cx16", true); 302 setFeatureEnabledImpl(Features, "fxsr", true); 303 break; 304 305 case CK_ZNVER1: 306 setFeatureEnabledImpl(Features, "adx", true); 307 setFeatureEnabledImpl(Features, "aes", true); 308 setFeatureEnabledImpl(Features, "avx2", true); 309 setFeatureEnabledImpl(Features, "bmi", true); 310 setFeatureEnabledImpl(Features, "bmi2", true); 311 setFeatureEnabledImpl(Features, "clflushopt", true); 312 setFeatureEnabledImpl(Features, "clzero", true); 313 setFeatureEnabledImpl(Features, "cx16", true); 314 setFeatureEnabledImpl(Features, "f16c", true); 315 setFeatureEnabledImpl(Features, "fma", true); 316 setFeatureEnabledImpl(Features, "fsgsbase", true); 317 setFeatureEnabledImpl(Features, "fxsr", true); 318 setFeatureEnabledImpl(Features, "lzcnt", true); 319 setFeatureEnabledImpl(Features, "mwaitx", true); 320 setFeatureEnabledImpl(Features, "movbe", true); 321 setFeatureEnabledImpl(Features, "pclmul", true); 322 setFeatureEnabledImpl(Features, "popcnt", true); 323 setFeatureEnabledImpl(Features, "prfchw", true); 324 setFeatureEnabledImpl(Features, "rdrnd", true); 325 setFeatureEnabledImpl(Features, "rdseed", true); 326 setFeatureEnabledImpl(Features, "sha", true); 327 setFeatureEnabledImpl(Features, "sse4a", true); 328 setFeatureEnabledImpl(Features, "xsave", true); 329 setFeatureEnabledImpl(Features, "xsavec", true); 330 setFeatureEnabledImpl(Features, "xsaveopt", true); 331 setFeatureEnabledImpl(Features, "xsaves", true); 332 break; 333 334 case CK_BDVER4: 335 setFeatureEnabledImpl(Features, "avx2", true); 336 setFeatureEnabledImpl(Features, "bmi2", true); 337 setFeatureEnabledImpl(Features, "mwaitx", true); 338 LLVM_FALLTHROUGH; 339 case CK_BDVER3: 340 setFeatureEnabledImpl(Features, "fsgsbase", true); 341 setFeatureEnabledImpl(Features, "xsaveopt", true); 342 LLVM_FALLTHROUGH; 343 case CK_BDVER2: 344 setFeatureEnabledImpl(Features, "bmi", true); 345 setFeatureEnabledImpl(Features, "fma", true); 346 setFeatureEnabledImpl(Features, "f16c", true); 347 setFeatureEnabledImpl(Features, "tbm", true); 348 LLVM_FALLTHROUGH; 349 case CK_BDVER1: 350 // xop implies avx, sse4a and fma4. 351 setFeatureEnabledImpl(Features, "xop", true); 352 setFeatureEnabledImpl(Features, "lwp", true); 353 setFeatureEnabledImpl(Features, "lzcnt", true); 354 setFeatureEnabledImpl(Features, "aes", true); 355 setFeatureEnabledImpl(Features, "pclmul", true); 356 setFeatureEnabledImpl(Features, "prfchw", true); 357 setFeatureEnabledImpl(Features, "cx16", true); 358 setFeatureEnabledImpl(Features, "fxsr", true); 359 setFeatureEnabledImpl(Features, "xsave", true); 360 break; 361 } 362 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 363 return false; 364 365 // Can't do this earlier because we need to be able to explicitly enable 366 // or disable these features and the things that they depend upon. 367 368 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 369 auto I = Features.find("sse4.2"); 370 if (I != Features.end() && I->getValue() && 371 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 372 FeaturesVec.end()) 373 Features["popcnt"] = true; 374 375 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 376 I = Features.find("3dnow"); 377 if (I != Features.end() && I->getValue() && 378 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 379 FeaturesVec.end()) 380 Features["prfchw"] = true; 381 382 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 383 // then enable MMX. 384 I = Features.find("sse"); 385 if (I != Features.end() && I->getValue() && 386 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 387 FeaturesVec.end()) 388 Features["mmx"] = true; 389 390 return true; 391 } 392 393 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 394 X86SSEEnum Level, bool Enabled) { 395 if (Enabled) { 396 switch (Level) { 397 case AVX512F: 398 Features["avx512f"] = true; 399 LLVM_FALLTHROUGH; 400 case AVX2: 401 Features["avx2"] = true; 402 LLVM_FALLTHROUGH; 403 case AVX: 404 Features["avx"] = true; 405 Features["xsave"] = true; 406 LLVM_FALLTHROUGH; 407 case SSE42: 408 Features["sse4.2"] = true; 409 LLVM_FALLTHROUGH; 410 case SSE41: 411 Features["sse4.1"] = true; 412 LLVM_FALLTHROUGH; 413 case SSSE3: 414 Features["ssse3"] = true; 415 LLVM_FALLTHROUGH; 416 case SSE3: 417 Features["sse3"] = true; 418 LLVM_FALLTHROUGH; 419 case SSE2: 420 Features["sse2"] = true; 421 LLVM_FALLTHROUGH; 422 case SSE1: 423 Features["sse"] = true; 424 LLVM_FALLTHROUGH; 425 case NoSSE: 426 break; 427 } 428 return; 429 } 430 431 switch (Level) { 432 case NoSSE: 433 case SSE1: 434 Features["sse"] = false; 435 LLVM_FALLTHROUGH; 436 case SSE2: 437 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 438 false; 439 LLVM_FALLTHROUGH; 440 case SSE3: 441 Features["sse3"] = false; 442 setXOPLevel(Features, NoXOP, false); 443 LLVM_FALLTHROUGH; 444 case SSSE3: 445 Features["ssse3"] = false; 446 LLVM_FALLTHROUGH; 447 case SSE41: 448 Features["sse4.1"] = false; 449 LLVM_FALLTHROUGH; 450 case SSE42: 451 Features["sse4.2"] = false; 452 LLVM_FALLTHROUGH; 453 case AVX: 454 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 455 Features["xsaveopt"] = false; 456 setXOPLevel(Features, FMA4, false); 457 LLVM_FALLTHROUGH; 458 case AVX2: 459 Features["avx2"] = false; 460 LLVM_FALLTHROUGH; 461 case AVX512F: 462 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 463 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 464 Features["avx512vl"] = Features["avx512vbmi"] = 465 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 466 break; 467 } 468 } 469 470 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 471 MMX3DNowEnum Level, bool Enabled) { 472 if (Enabled) { 473 switch (Level) { 474 case AMD3DNowAthlon: 475 Features["3dnowa"] = true; 476 LLVM_FALLTHROUGH; 477 case AMD3DNow: 478 Features["3dnow"] = true; 479 LLVM_FALLTHROUGH; 480 case MMX: 481 Features["mmx"] = true; 482 LLVM_FALLTHROUGH; 483 case NoMMX3DNow: 484 break; 485 } 486 return; 487 } 488 489 switch (Level) { 490 case NoMMX3DNow: 491 case MMX: 492 Features["mmx"] = false; 493 LLVM_FALLTHROUGH; 494 case AMD3DNow: 495 Features["3dnow"] = false; 496 LLVM_FALLTHROUGH; 497 case AMD3DNowAthlon: 498 Features["3dnowa"] = false; 499 break; 500 } 501 } 502 503 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 504 bool Enabled) { 505 if (Enabled) { 506 switch (Level) { 507 case XOP: 508 Features["xop"] = true; 509 LLVM_FALLTHROUGH; 510 case FMA4: 511 Features["fma4"] = true; 512 setSSELevel(Features, AVX, true); 513 LLVM_FALLTHROUGH; 514 case SSE4A: 515 Features["sse4a"] = true; 516 setSSELevel(Features, SSE3, true); 517 LLVM_FALLTHROUGH; 518 case NoXOP: 519 break; 520 } 521 return; 522 } 523 524 switch (Level) { 525 case NoXOP: 526 case SSE4A: 527 Features["sse4a"] = false; 528 LLVM_FALLTHROUGH; 529 case FMA4: 530 Features["fma4"] = false; 531 LLVM_FALLTHROUGH; 532 case XOP: 533 Features["xop"] = false; 534 break; 535 } 536 } 537 538 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 539 StringRef Name, bool Enabled) { 540 // This is a bit of a hack to deal with the sse4 target feature when used 541 // as part of the target attribute. We handle sse4 correctly everywhere 542 // else. See below for more information on how we handle the sse4 options. 543 if (Name != "sse4") 544 Features[Name] = Enabled; 545 546 if (Name == "mmx") { 547 setMMXLevel(Features, MMX, Enabled); 548 } else if (Name == "sse") { 549 setSSELevel(Features, SSE1, Enabled); 550 } else if (Name == "sse2") { 551 setSSELevel(Features, SSE2, Enabled); 552 } else if (Name == "sse3") { 553 setSSELevel(Features, SSE3, Enabled); 554 } else if (Name == "ssse3") { 555 setSSELevel(Features, SSSE3, Enabled); 556 } else if (Name == "sse4.2") { 557 setSSELevel(Features, SSE42, Enabled); 558 } else if (Name == "sse4.1") { 559 setSSELevel(Features, SSE41, Enabled); 560 } else if (Name == "3dnow") { 561 setMMXLevel(Features, AMD3DNow, Enabled); 562 } else if (Name == "3dnowa") { 563 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 564 } else if (Name == "aes") { 565 if (Enabled) 566 setSSELevel(Features, SSE2, Enabled); 567 } else if (Name == "pclmul") { 568 if (Enabled) 569 setSSELevel(Features, SSE2, Enabled); 570 } else if (Name == "avx") { 571 setSSELevel(Features, AVX, Enabled); 572 } else if (Name == "avx2") { 573 setSSELevel(Features, AVX2, Enabled); 574 } else if (Name == "avx512f") { 575 setSSELevel(Features, AVX512F, Enabled); 576 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 577 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 578 Name == "avx512vbmi" || Name == "avx512ifma" || 579 Name == "avx512vpopcntdq") { 580 if (Enabled) 581 setSSELevel(Features, AVX512F, Enabled); 582 // Enable BWI instruction if VBMI is being enabled. 583 if (Name == "avx512vbmi" && Enabled) 584 Features["avx512bw"] = true; 585 // Also disable VBMI if BWI is being disabled. 586 if (Name == "avx512bw" && !Enabled) 587 Features["avx512vbmi"] = false; 588 } else if (Name == "fma") { 589 if (Enabled) 590 setSSELevel(Features, AVX, Enabled); 591 } else if (Name == "fma4") { 592 setXOPLevel(Features, FMA4, Enabled); 593 } else if (Name == "xop") { 594 setXOPLevel(Features, XOP, Enabled); 595 } else if (Name == "sse4a") { 596 setXOPLevel(Features, SSE4A, Enabled); 597 } else if (Name == "f16c") { 598 if (Enabled) 599 setSSELevel(Features, AVX, Enabled); 600 } else if (Name == "sha") { 601 if (Enabled) 602 setSSELevel(Features, SSE2, Enabled); 603 } else if (Name == "sse4") { 604 // We can get here via the __target__ attribute since that's not controlled 605 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 606 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 607 // disabled. 608 if (Enabled) 609 setSSELevel(Features, SSE42, Enabled); 610 else 611 setSSELevel(Features, SSE41, Enabled); 612 } else if (Name == "xsave") { 613 if (!Enabled) 614 Features["xsaveopt"] = false; 615 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 616 if (Enabled) 617 Features["xsave"] = true; 618 } 619 } 620 621 /// handleTargetFeatures - Perform initialization based on the user 622 /// configured set of features. 623 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 624 DiagnosticsEngine &Diags) { 625 for (const auto &Feature : Features) { 626 if (Feature[0] != '+') 627 continue; 628 629 if (Feature == "+aes") { 630 HasAES = true; 631 } else if (Feature == "+pclmul") { 632 HasPCLMUL = true; 633 } else if (Feature == "+lzcnt") { 634 HasLZCNT = true; 635 } else if (Feature == "+rdrnd") { 636 HasRDRND = true; 637 } else if (Feature == "+fsgsbase") { 638 HasFSGSBASE = true; 639 } else if (Feature == "+bmi") { 640 HasBMI = true; 641 } else if (Feature == "+bmi2") { 642 HasBMI2 = true; 643 } else if (Feature == "+popcnt") { 644 HasPOPCNT = true; 645 } else if (Feature == "+rtm") { 646 HasRTM = true; 647 } else if (Feature == "+prfchw") { 648 HasPRFCHW = true; 649 } else if (Feature == "+rdseed") { 650 HasRDSEED = true; 651 } else if (Feature == "+adx") { 652 HasADX = true; 653 } else if (Feature == "+tbm") { 654 HasTBM = true; 655 } else if (Feature == "+lwp") { 656 HasLWP = true; 657 } else if (Feature == "+fma") { 658 HasFMA = true; 659 } else if (Feature == "+f16c") { 660 HasF16C = true; 661 } else if (Feature == "+avx512cd") { 662 HasAVX512CD = true; 663 } else if (Feature == "+avx512vpopcntdq") { 664 HasAVX512VPOPCNTDQ = true; 665 } else if (Feature == "+avx512er") { 666 HasAVX512ER = true; 667 } else if (Feature == "+avx512pf") { 668 HasAVX512PF = true; 669 } else if (Feature == "+avx512dq") { 670 HasAVX512DQ = true; 671 } else if (Feature == "+avx512bw") { 672 HasAVX512BW = true; 673 } else if (Feature == "+avx512vl") { 674 HasAVX512VL = true; 675 } else if (Feature == "+avx512vbmi") { 676 HasAVX512VBMI = true; 677 } else if (Feature == "+avx512ifma") { 678 HasAVX512IFMA = true; 679 } else if (Feature == "+sha") { 680 HasSHA = true; 681 } else if (Feature == "+mpx") { 682 HasMPX = true; 683 } else if (Feature == "+movbe") { 684 HasMOVBE = true; 685 } else if (Feature == "+sgx") { 686 HasSGX = true; 687 } else if (Feature == "+cx16") { 688 HasCX16 = true; 689 } else if (Feature == "+fxsr") { 690 HasFXSR = true; 691 } else if (Feature == "+xsave") { 692 HasXSAVE = true; 693 } else if (Feature == "+xsaveopt") { 694 HasXSAVEOPT = true; 695 } else if (Feature == "+xsavec") { 696 HasXSAVEC = true; 697 } else if (Feature == "+xsaves") { 698 HasXSAVES = true; 699 } else if (Feature == "+mwaitx") { 700 HasMWAITX = true; 701 } else if (Feature == "+pku") { 702 HasPKU = true; 703 } else if (Feature == "+clflushopt") { 704 HasCLFLUSHOPT = true; 705 } else if (Feature == "+clwb") { 706 HasCLWB = true; 707 } else if (Feature == "+prefetchwt1") { 708 HasPREFETCHWT1 = true; 709 } else if (Feature == "+clzero") { 710 HasCLZERO = true; 711 } 712 713 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 714 .Case("+avx512f", AVX512F) 715 .Case("+avx2", AVX2) 716 .Case("+avx", AVX) 717 .Case("+sse4.2", SSE42) 718 .Case("+sse4.1", SSE41) 719 .Case("+ssse3", SSSE3) 720 .Case("+sse3", SSE3) 721 .Case("+sse2", SSE2) 722 .Case("+sse", SSE1) 723 .Default(NoSSE); 724 SSELevel = std::max(SSELevel, Level); 725 726 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 727 .Case("+3dnowa", AMD3DNowAthlon) 728 .Case("+3dnow", AMD3DNow) 729 .Case("+mmx", MMX) 730 .Default(NoMMX3DNow); 731 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 732 733 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 734 .Case("+xop", XOP) 735 .Case("+fma4", FMA4) 736 .Case("+sse4a", SSE4A) 737 .Default(NoXOP); 738 XOPLevel = std::max(XOPLevel, XLevel); 739 } 740 741 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 742 // matches the selected sse level. 743 if ((FPMath == FP_SSE && SSELevel < SSE1) || 744 (FPMath == FP_387 && SSELevel >= SSE1)) { 745 Diags.Report(diag::err_target_unsupported_fpmath) 746 << (FPMath == FP_SSE ? "sse" : "387"); 747 return false; 748 } 749 750 SimdDefaultAlign = 751 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 752 return true; 753 } 754 755 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 756 /// definitions for this particular subtarget. 757 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 758 MacroBuilder &Builder) const { 759 // Target identification. 760 if (getTriple().getArch() == llvm::Triple::x86_64) { 761 Builder.defineMacro("__amd64__"); 762 Builder.defineMacro("__amd64"); 763 Builder.defineMacro("__x86_64"); 764 Builder.defineMacro("__x86_64__"); 765 if (getTriple().getArchName() == "x86_64h") { 766 Builder.defineMacro("__x86_64h"); 767 Builder.defineMacro("__x86_64h__"); 768 } 769 } else { 770 DefineStd(Builder, "i386", Opts); 771 } 772 773 // Subtarget options. 774 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 775 // truly should be based on -mtune options. 776 switch (CPU) { 777 case CK_Generic: 778 break; 779 case CK_i386: 780 // The rest are coming from the i386 define above. 781 Builder.defineMacro("__tune_i386__"); 782 break; 783 case CK_i486: 784 case CK_WinChipC6: 785 case CK_WinChip2: 786 case CK_C3: 787 defineCPUMacros(Builder, "i486"); 788 break; 789 case CK_PentiumMMX: 790 Builder.defineMacro("__pentium_mmx__"); 791 Builder.defineMacro("__tune_pentium_mmx__"); 792 LLVM_FALLTHROUGH; 793 case CK_i586: 794 case CK_Pentium: 795 defineCPUMacros(Builder, "i586"); 796 defineCPUMacros(Builder, "pentium"); 797 break; 798 case CK_Pentium3: 799 case CK_PentiumM: 800 Builder.defineMacro("__tune_pentium3__"); 801 LLVM_FALLTHROUGH; 802 case CK_Pentium2: 803 case CK_C3_2: 804 Builder.defineMacro("__tune_pentium2__"); 805 LLVM_FALLTHROUGH; 806 case CK_PentiumPro: 807 Builder.defineMacro("__tune_i686__"); 808 Builder.defineMacro("__tune_pentiumpro__"); 809 LLVM_FALLTHROUGH; 810 case CK_i686: 811 Builder.defineMacro("__i686"); 812 Builder.defineMacro("__i686__"); 813 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 814 Builder.defineMacro("__pentiumpro"); 815 Builder.defineMacro("__pentiumpro__"); 816 break; 817 case CK_Pentium4: 818 defineCPUMacros(Builder, "pentium4"); 819 break; 820 case CK_Yonah: 821 case CK_Prescott: 822 case CK_Nocona: 823 defineCPUMacros(Builder, "nocona"); 824 break; 825 case CK_Core2: 826 case CK_Penryn: 827 defineCPUMacros(Builder, "core2"); 828 break; 829 case CK_Bonnell: 830 defineCPUMacros(Builder, "atom"); 831 break; 832 case CK_Silvermont: 833 defineCPUMacros(Builder, "slm"); 834 break; 835 case CK_Goldmont: 836 defineCPUMacros(Builder, "goldmont"); 837 break; 838 case CK_Nehalem: 839 case CK_Westmere: 840 case CK_SandyBridge: 841 case CK_IvyBridge: 842 case CK_Haswell: 843 case CK_Broadwell: 844 case CK_SkylakeClient: 845 // FIXME: Historically, we defined this legacy name, it would be nice to 846 // remove it at some point. We've never exposed fine-grained names for 847 // recent primary x86 CPUs, and we should keep it that way. 848 defineCPUMacros(Builder, "corei7"); 849 break; 850 case CK_SkylakeServer: 851 defineCPUMacros(Builder, "skx"); 852 break; 853 case CK_Cannonlake: 854 break; 855 case CK_KNL: 856 defineCPUMacros(Builder, "knl"); 857 break; 858 case CK_KNM: 859 break; 860 case CK_Lakemont: 861 Builder.defineMacro("__tune_lakemont__"); 862 break; 863 case CK_K6_2: 864 Builder.defineMacro("__k6_2__"); 865 Builder.defineMacro("__tune_k6_2__"); 866 LLVM_FALLTHROUGH; 867 case CK_K6_3: 868 if (CPU != CK_K6_2) { // In case of fallthrough 869 // FIXME: GCC may be enabling these in cases where some other k6 870 // architecture is specified but -m3dnow is explicitly provided. The 871 // exact semantics need to be determined and emulated here. 872 Builder.defineMacro("__k6_3__"); 873 Builder.defineMacro("__tune_k6_3__"); 874 } 875 LLVM_FALLTHROUGH; 876 case CK_K6: 877 defineCPUMacros(Builder, "k6"); 878 break; 879 case CK_Athlon: 880 case CK_AthlonXP: 881 defineCPUMacros(Builder, "athlon"); 882 if (SSELevel != NoSSE) { 883 Builder.defineMacro("__athlon_sse__"); 884 Builder.defineMacro("__tune_athlon_sse__"); 885 } 886 break; 887 case CK_K8: 888 case CK_K8SSE3: 889 case CK_x86_64: 890 defineCPUMacros(Builder, "k8"); 891 break; 892 case CK_AMDFAM10: 893 defineCPUMacros(Builder, "amdfam10"); 894 break; 895 case CK_BTVER1: 896 defineCPUMacros(Builder, "btver1"); 897 break; 898 case CK_BTVER2: 899 defineCPUMacros(Builder, "btver2"); 900 break; 901 case CK_BDVER1: 902 defineCPUMacros(Builder, "bdver1"); 903 break; 904 case CK_BDVER2: 905 defineCPUMacros(Builder, "bdver2"); 906 break; 907 case CK_BDVER3: 908 defineCPUMacros(Builder, "bdver3"); 909 break; 910 case CK_BDVER4: 911 defineCPUMacros(Builder, "bdver4"); 912 break; 913 case CK_ZNVER1: 914 defineCPUMacros(Builder, "znver1"); 915 break; 916 case CK_Geode: 917 defineCPUMacros(Builder, "geode"); 918 break; 919 } 920 921 // Target properties. 922 Builder.defineMacro("__REGISTER_PREFIX__", ""); 923 924 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 925 // functions in glibc header files that use FP Stack inline asm which the 926 // backend can't deal with (PR879). 927 Builder.defineMacro("__NO_MATH_INLINES"); 928 929 if (HasAES) 930 Builder.defineMacro("__AES__"); 931 932 if (HasPCLMUL) 933 Builder.defineMacro("__PCLMUL__"); 934 935 if (HasLZCNT) 936 Builder.defineMacro("__LZCNT__"); 937 938 if (HasRDRND) 939 Builder.defineMacro("__RDRND__"); 940 941 if (HasFSGSBASE) 942 Builder.defineMacro("__FSGSBASE__"); 943 944 if (HasBMI) 945 Builder.defineMacro("__BMI__"); 946 947 if (HasBMI2) 948 Builder.defineMacro("__BMI2__"); 949 950 if (HasPOPCNT) 951 Builder.defineMacro("__POPCNT__"); 952 953 if (HasRTM) 954 Builder.defineMacro("__RTM__"); 955 956 if (HasPRFCHW) 957 Builder.defineMacro("__PRFCHW__"); 958 959 if (HasRDSEED) 960 Builder.defineMacro("__RDSEED__"); 961 962 if (HasADX) 963 Builder.defineMacro("__ADX__"); 964 965 if (HasTBM) 966 Builder.defineMacro("__TBM__"); 967 968 if (HasLWP) 969 Builder.defineMacro("__LWP__"); 970 971 if (HasMWAITX) 972 Builder.defineMacro("__MWAITX__"); 973 974 switch (XOPLevel) { 975 case XOP: 976 Builder.defineMacro("__XOP__"); 977 LLVM_FALLTHROUGH; 978 case FMA4: 979 Builder.defineMacro("__FMA4__"); 980 LLVM_FALLTHROUGH; 981 case SSE4A: 982 Builder.defineMacro("__SSE4A__"); 983 LLVM_FALLTHROUGH; 984 case NoXOP: 985 break; 986 } 987 988 if (HasFMA) 989 Builder.defineMacro("__FMA__"); 990 991 if (HasF16C) 992 Builder.defineMacro("__F16C__"); 993 994 if (HasAVX512CD) 995 Builder.defineMacro("__AVX512CD__"); 996 if (HasAVX512VPOPCNTDQ) 997 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 998 if (HasAVX512ER) 999 Builder.defineMacro("__AVX512ER__"); 1000 if (HasAVX512PF) 1001 Builder.defineMacro("__AVX512PF__"); 1002 if (HasAVX512DQ) 1003 Builder.defineMacro("__AVX512DQ__"); 1004 if (HasAVX512BW) 1005 Builder.defineMacro("__AVX512BW__"); 1006 if (HasAVX512VL) 1007 Builder.defineMacro("__AVX512VL__"); 1008 if (HasAVX512VBMI) 1009 Builder.defineMacro("__AVX512VBMI__"); 1010 if (HasAVX512IFMA) 1011 Builder.defineMacro("__AVX512IFMA__"); 1012 1013 if (HasSHA) 1014 Builder.defineMacro("__SHA__"); 1015 1016 if (HasFXSR) 1017 Builder.defineMacro("__FXSR__"); 1018 if (HasXSAVE) 1019 Builder.defineMacro("__XSAVE__"); 1020 if (HasXSAVEOPT) 1021 Builder.defineMacro("__XSAVEOPT__"); 1022 if (HasXSAVEC) 1023 Builder.defineMacro("__XSAVEC__"); 1024 if (HasXSAVES) 1025 Builder.defineMacro("__XSAVES__"); 1026 if (HasPKU) 1027 Builder.defineMacro("__PKU__"); 1028 if (HasCX16) 1029 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1030 if (HasCLFLUSHOPT) 1031 Builder.defineMacro("__CLFLUSHOPT__"); 1032 if (HasCLWB) 1033 Builder.defineMacro("__CLWB__"); 1034 if (HasMPX) 1035 Builder.defineMacro("__MPX__"); 1036 if (HasSGX) 1037 Builder.defineMacro("__SGX__"); 1038 if (HasPREFETCHWT1) 1039 Builder.defineMacro("__PREFETCHWT1__"); 1040 if (HasCLZERO) 1041 Builder.defineMacro("__CLZERO__"); 1042 1043 // Each case falls through to the previous one here. 1044 switch (SSELevel) { 1045 case AVX512F: 1046 Builder.defineMacro("__AVX512F__"); 1047 LLVM_FALLTHROUGH; 1048 case AVX2: 1049 Builder.defineMacro("__AVX2__"); 1050 LLVM_FALLTHROUGH; 1051 case AVX: 1052 Builder.defineMacro("__AVX__"); 1053 LLVM_FALLTHROUGH; 1054 case SSE42: 1055 Builder.defineMacro("__SSE4_2__"); 1056 LLVM_FALLTHROUGH; 1057 case SSE41: 1058 Builder.defineMacro("__SSE4_1__"); 1059 LLVM_FALLTHROUGH; 1060 case SSSE3: 1061 Builder.defineMacro("__SSSE3__"); 1062 LLVM_FALLTHROUGH; 1063 case SSE3: 1064 Builder.defineMacro("__SSE3__"); 1065 LLVM_FALLTHROUGH; 1066 case SSE2: 1067 Builder.defineMacro("__SSE2__"); 1068 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1069 LLVM_FALLTHROUGH; 1070 case SSE1: 1071 Builder.defineMacro("__SSE__"); 1072 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1073 LLVM_FALLTHROUGH; 1074 case NoSSE: 1075 break; 1076 } 1077 1078 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1079 switch (SSELevel) { 1080 case AVX512F: 1081 case AVX2: 1082 case AVX: 1083 case SSE42: 1084 case SSE41: 1085 case SSSE3: 1086 case SSE3: 1087 case SSE2: 1088 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1089 break; 1090 case SSE1: 1091 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1092 break; 1093 default: 1094 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1095 break; 1096 } 1097 } 1098 1099 // Each case falls through to the previous one here. 1100 switch (MMX3DNowLevel) { 1101 case AMD3DNowAthlon: 1102 Builder.defineMacro("__3dNOW_A__"); 1103 LLVM_FALLTHROUGH; 1104 case AMD3DNow: 1105 Builder.defineMacro("__3dNOW__"); 1106 LLVM_FALLTHROUGH; 1107 case MMX: 1108 Builder.defineMacro("__MMX__"); 1109 LLVM_FALLTHROUGH; 1110 case NoMMX3DNow: 1111 break; 1112 } 1113 1114 if (CPU >= CK_i486) { 1115 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1116 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1117 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1118 } 1119 if (CPU >= CK_i586) 1120 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1121 1122 if (HasFloat128) 1123 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1124 } 1125 1126 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1127 return llvm::StringSwitch<bool>(Name) 1128 .Case("aes", true) 1129 .Case("avx", true) 1130 .Case("avx2", true) 1131 .Case("avx512f", true) 1132 .Case("avx512cd", true) 1133 .Case("avx512vpopcntdq", true) 1134 .Case("avx512er", true) 1135 .Case("avx512pf", true) 1136 .Case("avx512dq", true) 1137 .Case("avx512bw", true) 1138 .Case("avx512vl", true) 1139 .Case("avx512vbmi", true) 1140 .Case("avx512ifma", true) 1141 .Case("bmi", true) 1142 .Case("bmi2", true) 1143 .Case("clflushopt", true) 1144 .Case("clwb", true) 1145 .Case("clzero", true) 1146 .Case("cx16", true) 1147 .Case("f16c", true) 1148 .Case("fma", true) 1149 .Case("fma4", true) 1150 .Case("fsgsbase", true) 1151 .Case("fxsr", true) 1152 .Case("lwp", true) 1153 .Case("lzcnt", true) 1154 .Case("mm3dnow", true) 1155 .Case("mm3dnowa", true) 1156 .Case("mmx", true) 1157 .Case("movbe", true) 1158 .Case("mpx", true) 1159 .Case("pclmul", true) 1160 .Case("pku", true) 1161 .Case("popcnt", true) 1162 .Case("prefetchwt1", true) 1163 .Case("prfchw", true) 1164 .Case("rdrnd", true) 1165 .Case("rdseed", true) 1166 .Case("rtm", true) 1167 .Case("sgx", true) 1168 .Case("sha", true) 1169 .Case("sse", true) 1170 .Case("sse2", true) 1171 .Case("sse3", true) 1172 .Case("ssse3", true) 1173 .Case("sse4.1", true) 1174 .Case("sse4.2", true) 1175 .Case("sse4a", true) 1176 .Case("tbm", true) 1177 .Case("x86", true) 1178 .Case("x86_32", true) 1179 .Case("x86_64", true) 1180 .Case("xop", true) 1181 .Case("xsave", true) 1182 .Case("xsavec", true) 1183 .Case("xsaves", true) 1184 .Case("xsaveopt", true) 1185 .Default(false); 1186 } 1187 1188 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1189 return llvm::StringSwitch<bool>(Feature) 1190 .Case("aes", HasAES) 1191 .Case("avx", SSELevel >= AVX) 1192 .Case("avx2", SSELevel >= AVX2) 1193 .Case("avx512f", SSELevel >= AVX512F) 1194 .Case("avx512cd", HasAVX512CD) 1195 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1196 .Case("avx512er", HasAVX512ER) 1197 .Case("avx512pf", HasAVX512PF) 1198 .Case("avx512dq", HasAVX512DQ) 1199 .Case("avx512bw", HasAVX512BW) 1200 .Case("avx512vl", HasAVX512VL) 1201 .Case("avx512vbmi", HasAVX512VBMI) 1202 .Case("avx512ifma", HasAVX512IFMA) 1203 .Case("bmi", HasBMI) 1204 .Case("bmi2", HasBMI2) 1205 .Case("clflushopt", HasCLFLUSHOPT) 1206 .Case("clwb", HasCLWB) 1207 .Case("clzero", HasCLZERO) 1208 .Case("cx16", HasCX16) 1209 .Case("f16c", HasF16C) 1210 .Case("fma", HasFMA) 1211 .Case("fma4", XOPLevel >= FMA4) 1212 .Case("fsgsbase", HasFSGSBASE) 1213 .Case("fxsr", HasFXSR) 1214 .Case("lwp", HasLWP) 1215 .Case("lzcnt", HasLZCNT) 1216 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1217 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1218 .Case("mmx", MMX3DNowLevel >= MMX) 1219 .Case("movbe", HasMOVBE) 1220 .Case("mpx", HasMPX) 1221 .Case("pclmul", HasPCLMUL) 1222 .Case("pku", HasPKU) 1223 .Case("popcnt", HasPOPCNT) 1224 .Case("prefetchwt1", HasPREFETCHWT1) 1225 .Case("prfchw", HasPRFCHW) 1226 .Case("rdrnd", HasRDRND) 1227 .Case("rdseed", HasRDSEED) 1228 .Case("rtm", HasRTM) 1229 .Case("sgx", HasSGX) 1230 .Case("sha", HasSHA) 1231 .Case("sse", SSELevel >= SSE1) 1232 .Case("sse2", SSELevel >= SSE2) 1233 .Case("sse3", SSELevel >= SSE3) 1234 .Case("ssse3", SSELevel >= SSSE3) 1235 .Case("sse4.1", SSELevel >= SSE41) 1236 .Case("sse4.2", SSELevel >= SSE42) 1237 .Case("sse4a", XOPLevel >= SSE4A) 1238 .Case("tbm", HasTBM) 1239 .Case("x86", true) 1240 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1241 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1242 .Case("xop", XOPLevel >= XOP) 1243 .Case("xsave", HasXSAVE) 1244 .Case("xsavec", HasXSAVEC) 1245 .Case("xsaves", HasXSAVES) 1246 .Case("xsaveopt", HasXSAVEOPT) 1247 .Default(false); 1248 } 1249 1250 // We can't use a generic validation scheme for the features accepted here 1251 // versus subtarget features accepted in the target attribute because the 1252 // bitfield structure that's initialized in the runtime only supports the 1253 // below currently rather than the full range of subtarget features. (See 1254 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1255 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1256 return llvm::StringSwitch<bool>(FeatureStr) 1257 .Case("cmov", true) 1258 .Case("mmx", true) 1259 .Case("popcnt", true) 1260 .Case("sse", true) 1261 .Case("sse2", true) 1262 .Case("sse3", true) 1263 .Case("ssse3", true) 1264 .Case("sse4.1", true) 1265 .Case("sse4.2", true) 1266 .Case("avx", true) 1267 .Case("avx2", true) 1268 .Case("sse4a", true) 1269 .Case("fma4", true) 1270 .Case("xop", true) 1271 .Case("fma", true) 1272 .Case("avx512f", true) 1273 .Case("bmi", true) 1274 .Case("bmi2", true) 1275 .Case("aes", true) 1276 .Case("pclmul", true) 1277 .Case("avx512vl", true) 1278 .Case("avx512bw", true) 1279 .Case("avx512dq", true) 1280 .Case("avx512cd", true) 1281 .Case("avx512er", true) 1282 .Case("avx512pf", true) 1283 .Case("avx512vbmi", true) 1284 .Case("avx512ifma", true) 1285 .Case("avx5124vnniw", true) 1286 .Case("avx5124fmaps", true) 1287 .Case("avx512vpopcntdq", true) 1288 .Default(false); 1289 } 1290 1291 // We can't use a generic validation scheme for the cpus accepted here 1292 // versus subtarget cpus accepted in the target attribute because the 1293 // variables intitialized by the runtime only support the below currently 1294 // rather than the full range of cpus. 1295 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1296 return llvm::StringSwitch<bool>(FeatureStr) 1297 .Case("amd", true) 1298 .Case("amdfam10h", true) 1299 .Case("amdfam15h", true) 1300 .Case("amdfam17h", true) 1301 .Case("atom", true) 1302 .Case("barcelona", true) 1303 .Case("bdver1", true) 1304 .Case("bdver2", true) 1305 .Case("bdver3", true) 1306 .Case("bdver4", true) 1307 .Case("bonnell", true) 1308 .Case("broadwell", true) 1309 .Case("btver1", true) 1310 .Case("btver2", true) 1311 .Case("core2", true) 1312 .Case("corei7", true) 1313 .Case("haswell", true) 1314 .Case("intel", true) 1315 .Case("istanbul", true) 1316 .Case("ivybridge", true) 1317 .Case("knl", true) 1318 .Case("nehalem", true) 1319 .Case("sandybridge", true) 1320 .Case("shanghai", true) 1321 .Case("silvermont", true) 1322 .Case("skylake", true) 1323 .Case("skylake-avx512", true) 1324 .Case("slm", true) 1325 .Case("westmere", true) 1326 .Case("znver1", true) 1327 .Default(false); 1328 } 1329 1330 bool X86TargetInfo::validateAsmConstraint( 1331 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1332 switch (*Name) { 1333 default: 1334 return false; 1335 // Constant constraints. 1336 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1337 // instructions. 1338 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1339 // x86_64 instructions. 1340 case 's': 1341 Info.setRequiresImmediate(); 1342 return true; 1343 case 'I': 1344 Info.setRequiresImmediate(0, 31); 1345 return true; 1346 case 'J': 1347 Info.setRequiresImmediate(0, 63); 1348 return true; 1349 case 'K': 1350 Info.setRequiresImmediate(-128, 127); 1351 return true; 1352 case 'L': 1353 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1354 return true; 1355 case 'M': 1356 Info.setRequiresImmediate(0, 3); 1357 return true; 1358 case 'N': 1359 Info.setRequiresImmediate(0, 255); 1360 return true; 1361 case 'O': 1362 Info.setRequiresImmediate(0, 127); 1363 return true; 1364 // Register constraints. 1365 case 'Y': // 'Y' is the first character for several 2-character constraints. 1366 // Shift the pointer to the second character of the constraint. 1367 Name++; 1368 switch (*Name) { 1369 default: 1370 return false; 1371 case 'z': 1372 case '0': // First SSE register. 1373 case '2': 1374 case 't': // Any SSE register, when SSE2 is enabled. 1375 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1376 case 'm': // Any MMX register, when inter-unit moves enabled. 1377 case 'k': // AVX512 arch mask registers: k1-k7. 1378 Info.setAllowsRegister(); 1379 return true; 1380 } 1381 case 'f': // Any x87 floating point stack register. 1382 // Constraint 'f' cannot be used for output operands. 1383 if (Info.ConstraintStr[0] == '=') 1384 return false; 1385 Info.setAllowsRegister(); 1386 return true; 1387 case 'a': // eax. 1388 case 'b': // ebx. 1389 case 'c': // ecx. 1390 case 'd': // edx. 1391 case 'S': // esi. 1392 case 'D': // edi. 1393 case 'A': // edx:eax. 1394 case 't': // Top of floating point stack. 1395 case 'u': // Second from top of floating point stack. 1396 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1397 case 'y': // Any MMX register. 1398 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1399 case 'x': // Any SSE register. 1400 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1401 // for intermideate k reg operations). 1402 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1403 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1404 case 'l': // "Index" registers: any general register that can be used as an 1405 // index in a base+index memory access. 1406 Info.setAllowsRegister(); 1407 return true; 1408 // Floating point constant constraints. 1409 case 'C': // SSE floating point constant. 1410 case 'G': // x87 floating point constant. 1411 return true; 1412 } 1413 } 1414 1415 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1416 unsigned Size) const { 1417 // Strip off constraint modifiers. 1418 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1419 Constraint = Constraint.substr(1); 1420 1421 return validateOperandSize(Constraint, Size); 1422 } 1423 1424 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1425 unsigned Size) const { 1426 return validateOperandSize(Constraint, Size); 1427 } 1428 1429 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1430 unsigned Size) const { 1431 switch (Constraint[0]) { 1432 default: 1433 break; 1434 case 'k': 1435 // Registers k0-k7 (AVX512) size limit is 64 bit. 1436 case 'y': 1437 return Size <= 64; 1438 case 'f': 1439 case 't': 1440 case 'u': 1441 return Size <= 128; 1442 case 'Y': 1443 // 'Y' is the first character for several 2-character constraints. 1444 switch (Constraint[1]) { 1445 default: 1446 return false; 1447 case 'm': 1448 // 'Ym' is synonymous with 'y'. 1449 case 'k': 1450 return Size <= 64; 1451 case 'z': 1452 case '0': 1453 // XMM0 1454 if (SSELevel >= SSE1) 1455 return Size <= 128U; 1456 return false; 1457 case 'i': 1458 case 't': 1459 case '2': 1460 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1461 if (SSELevel < SSE2) 1462 return false; 1463 break; 1464 } 1465 case 'v': 1466 case 'x': 1467 if (SSELevel >= AVX512F) 1468 // 512-bit zmm registers can be used if target supports AVX512F. 1469 return Size <= 512U; 1470 else if (SSELevel >= AVX) 1471 // 256-bit ymm registers can be used if target supports AVX. 1472 return Size <= 256U; 1473 return Size <= 128U; 1474 1475 } 1476 1477 return true; 1478 } 1479 1480 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1481 switch (*Constraint) { 1482 case 'a': 1483 return std::string("{ax}"); 1484 case 'b': 1485 return std::string("{bx}"); 1486 case 'c': 1487 return std::string("{cx}"); 1488 case 'd': 1489 return std::string("{dx}"); 1490 case 'S': 1491 return std::string("{si}"); 1492 case 'D': 1493 return std::string("{di}"); 1494 case 'p': // address 1495 return std::string("im"); 1496 case 't': // top of floating point stack. 1497 return std::string("{st}"); 1498 case 'u': // second from top of floating point stack. 1499 return std::string("{st(1)}"); // second from top of floating point stack. 1500 case 'Y': 1501 switch (Constraint[1]) { 1502 default: 1503 // Break from inner switch and fall through (copy single char), 1504 // continue parsing after copying the current constraint into 1505 // the return string. 1506 break; 1507 case 'k': 1508 case 'm': 1509 case 'i': 1510 case 't': 1511 case 'z': 1512 case '0': 1513 case '2': 1514 // "^" hints llvm that this is a 2 letter constraint. 1515 // "Constraint++" is used to promote the string iterator 1516 // to the next constraint. 1517 return std::string("^") + std::string(Constraint++, 2); 1518 } 1519 LLVM_FALLTHROUGH; 1520 default: 1521 return std::string(1, *Constraint); 1522 } 1523 } 1524 1525 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1526 // Perform any per-CPU checks necessary to determine if this CPU is 1527 // acceptable. 1528 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1529 // invalid without explaining *why*. 1530 switch (Kind) { 1531 case CK_Generic: 1532 // No processor selected! 1533 return false; 1534 1535 case CK_i386: 1536 case CK_i486: 1537 case CK_WinChipC6: 1538 case CK_WinChip2: 1539 case CK_C3: 1540 case CK_i586: 1541 case CK_Pentium: 1542 case CK_PentiumMMX: 1543 case CK_i686: 1544 case CK_PentiumPro: 1545 case CK_Pentium2: 1546 case CK_Pentium3: 1547 case CK_PentiumM: 1548 case CK_Yonah: 1549 case CK_C3_2: 1550 case CK_Pentium4: 1551 case CK_Lakemont: 1552 case CK_Prescott: 1553 case CK_K6: 1554 case CK_K6_2: 1555 case CK_K6_3: 1556 case CK_Athlon: 1557 case CK_AthlonXP: 1558 case CK_Geode: 1559 // Only accept certain architectures when compiling in 32-bit mode. 1560 if (getTriple().getArch() != llvm::Triple::x86) 1561 return false; 1562 1563 LLVM_FALLTHROUGH; 1564 case CK_Nocona: 1565 case CK_Core2: 1566 case CK_Penryn: 1567 case CK_Bonnell: 1568 case CK_Silvermont: 1569 case CK_Goldmont: 1570 case CK_Nehalem: 1571 case CK_Westmere: 1572 case CK_SandyBridge: 1573 case CK_IvyBridge: 1574 case CK_Haswell: 1575 case CK_Broadwell: 1576 case CK_SkylakeClient: 1577 case CK_SkylakeServer: 1578 case CK_Cannonlake: 1579 case CK_KNL: 1580 case CK_KNM: 1581 case CK_K8: 1582 case CK_K8SSE3: 1583 case CK_AMDFAM10: 1584 case CK_BTVER1: 1585 case CK_BTVER2: 1586 case CK_BDVER1: 1587 case CK_BDVER2: 1588 case CK_BDVER3: 1589 case CK_BDVER4: 1590 case CK_ZNVER1: 1591 case CK_x86_64: 1592 return true; 1593 } 1594 llvm_unreachable("Unhandled CPU kind"); 1595 } 1596 1597 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1598 return llvm::StringSwitch<CPUKind>(CPU) 1599 .Case("i386", CK_i386) 1600 .Case("i486", CK_i486) 1601 .Case("winchip-c6", CK_WinChipC6) 1602 .Case("winchip2", CK_WinChip2) 1603 .Case("c3", CK_C3) 1604 .Case("i586", CK_i586) 1605 .Case("pentium", CK_Pentium) 1606 .Case("pentium-mmx", CK_PentiumMMX) 1607 .Case("i686", CK_i686) 1608 .Case("pentiumpro", CK_PentiumPro) 1609 .Case("pentium2", CK_Pentium2) 1610 .Cases("pentium3", "pentium3m", CK_Pentium3) 1611 .Case("pentium-m", CK_PentiumM) 1612 .Case("c3-2", CK_C3_2) 1613 .Case("yonah", CK_Yonah) 1614 .Cases("pentium4", "pentium4m", CK_Pentium4) 1615 .Case("prescott", CK_Prescott) 1616 .Case("nocona", CK_Nocona) 1617 .Case("core2", CK_Core2) 1618 .Case("penryn", CK_Penryn) 1619 .Cases("bonnell", "atom", CK_Bonnell) 1620 .Cases("silvermont", "slm", CK_Silvermont) 1621 .Case("goldmont", CK_Goldmont) 1622 .Cases("nehalem", "corei7", CK_Nehalem) 1623 .Case("westmere", CK_Westmere) 1624 .Cases("sandybridge", "corei7-avx", CK_SandyBridge) 1625 .Cases("ivybridge", "core-avx-i", CK_IvyBridge) 1626 .Cases("haswell", "core-avx2", CK_Haswell) 1627 .Case("broadwell", CK_Broadwell) 1628 .Case("skylake", CK_SkylakeClient) 1629 .Cases("skylake-avx512", "skx", CK_SkylakeServer) 1630 .Case("cannonlake", CK_Cannonlake) 1631 .Case("knl", CK_KNL) 1632 .Case("knm", CK_KNM) 1633 .Case("lakemont", CK_Lakemont) 1634 .Case("k6", CK_K6) 1635 .Case("k6-2", CK_K6_2) 1636 .Case("k6-3", CK_K6_3) 1637 .Cases("athlon", "athlon-tbird", CK_Athlon) 1638 .Cases("athlon-xp", "athlon-mp", "athlon-4", CK_AthlonXP) 1639 .Cases("k8", "athlon64", "athlon-fx", "opteron", CK_K8) 1640 .Cases("k8-sse3", "athlon64-sse3", "opteron-sse3", CK_K8SSE3) 1641 .Cases("amdfam10", "barcelona", CK_AMDFAM10) 1642 .Case("btver1", CK_BTVER1) 1643 .Case("btver2", CK_BTVER2) 1644 .Case("bdver1", CK_BDVER1) 1645 .Case("bdver2", CK_BDVER2) 1646 .Case("bdver3", CK_BDVER3) 1647 .Case("bdver4", CK_BDVER4) 1648 .Case("znver1", CK_ZNVER1) 1649 .Case("x86-64", CK_x86_64) 1650 .Case("geode", CK_Geode) 1651 .Default(CK_Generic); 1652 } 1653 1654 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1655 return llvm::makeArrayRef(GCCRegNames); 1656 } 1657 1658 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1659 return llvm::makeArrayRef(AddlRegNames); 1660 } 1661 1662 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1663 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1664 Builtin::FirstTSBuiltin + 1); 1665 } 1666 1667 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1668 return llvm::makeArrayRef(BuiltinInfoX86, 1669 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1670 } 1671