1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+avxvnni") { 310 HasAVXVNNI = true; 311 } else if (Feature == "+serialize") { 312 HasSERIALIZE = true; 313 } else if (Feature == "+tsxldtrk") { 314 HasTSXLDTRK = true; 315 } else if (Feature == "+uintr") { 316 HasUINTR = true; 317 } 318 319 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 320 .Case("+avx512f", AVX512F) 321 .Case("+avx2", AVX2) 322 .Case("+avx", AVX) 323 .Case("+sse4.2", SSE42) 324 .Case("+sse4.1", SSE41) 325 .Case("+ssse3", SSSE3) 326 .Case("+sse3", SSE3) 327 .Case("+sse2", SSE2) 328 .Case("+sse", SSE1) 329 .Default(NoSSE); 330 SSELevel = std::max(SSELevel, Level); 331 332 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 333 .Case("+3dnowa", AMD3DNowAthlon) 334 .Case("+3dnow", AMD3DNow) 335 .Case("+mmx", MMX) 336 .Default(NoMMX3DNow); 337 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 338 339 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 340 .Case("+xop", XOP) 341 .Case("+fma4", FMA4) 342 .Case("+sse4a", SSE4A) 343 .Default(NoXOP); 344 XOPLevel = std::max(XOPLevel, XLevel); 345 } 346 347 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 348 // matches the selected sse level. 349 if ((FPMath == FP_SSE && SSELevel < SSE1) || 350 (FPMath == FP_387 && SSELevel >= SSE1)) { 351 Diags.Report(diag::err_target_unsupported_fpmath) 352 << (FPMath == FP_SSE ? "sse" : "387"); 353 return false; 354 } 355 356 SimdDefaultAlign = 357 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 358 return true; 359 } 360 361 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 362 /// definitions for this particular subtarget. 363 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 364 MacroBuilder &Builder) const { 365 // Inline assembly supports X86 flag outputs. 366 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 367 368 std::string CodeModel = getTargetOpts().CodeModel; 369 if (CodeModel == "default") 370 CodeModel = "small"; 371 Builder.defineMacro("__code_model_" + CodeModel + "__"); 372 373 // Target identification. 374 if (getTriple().getArch() == llvm::Triple::x86_64) { 375 Builder.defineMacro("__amd64__"); 376 Builder.defineMacro("__amd64"); 377 Builder.defineMacro("__x86_64"); 378 Builder.defineMacro("__x86_64__"); 379 if (getTriple().getArchName() == "x86_64h") { 380 Builder.defineMacro("__x86_64h"); 381 Builder.defineMacro("__x86_64h__"); 382 } 383 } else { 384 DefineStd(Builder, "i386", Opts); 385 } 386 387 Builder.defineMacro("__SEG_GS"); 388 Builder.defineMacro("__SEG_FS"); 389 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 390 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 391 392 // Subtarget options. 393 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 394 // truly should be based on -mtune options. 395 using namespace llvm::X86; 396 switch (CPU) { 397 case CK_None: 398 break; 399 case CK_i386: 400 // The rest are coming from the i386 define above. 401 Builder.defineMacro("__tune_i386__"); 402 break; 403 case CK_i486: 404 case CK_WinChipC6: 405 case CK_WinChip2: 406 case CK_C3: 407 defineCPUMacros(Builder, "i486"); 408 break; 409 case CK_PentiumMMX: 410 Builder.defineMacro("__pentium_mmx__"); 411 Builder.defineMacro("__tune_pentium_mmx__"); 412 LLVM_FALLTHROUGH; 413 case CK_i586: 414 case CK_Pentium: 415 defineCPUMacros(Builder, "i586"); 416 defineCPUMacros(Builder, "pentium"); 417 break; 418 case CK_Pentium3: 419 case CK_PentiumM: 420 Builder.defineMacro("__tune_pentium3__"); 421 LLVM_FALLTHROUGH; 422 case CK_Pentium2: 423 case CK_C3_2: 424 Builder.defineMacro("__tune_pentium2__"); 425 LLVM_FALLTHROUGH; 426 case CK_PentiumPro: 427 case CK_i686: 428 defineCPUMacros(Builder, "i686"); 429 defineCPUMacros(Builder, "pentiumpro"); 430 break; 431 case CK_Pentium4: 432 defineCPUMacros(Builder, "pentium4"); 433 break; 434 case CK_Yonah: 435 case CK_Prescott: 436 case CK_Nocona: 437 defineCPUMacros(Builder, "nocona"); 438 break; 439 case CK_Core2: 440 case CK_Penryn: 441 defineCPUMacros(Builder, "core2"); 442 break; 443 case CK_Bonnell: 444 defineCPUMacros(Builder, "atom"); 445 break; 446 case CK_Silvermont: 447 defineCPUMacros(Builder, "slm"); 448 break; 449 case CK_Goldmont: 450 defineCPUMacros(Builder, "goldmont"); 451 break; 452 case CK_GoldmontPlus: 453 defineCPUMacros(Builder, "goldmont_plus"); 454 break; 455 case CK_Tremont: 456 defineCPUMacros(Builder, "tremont"); 457 break; 458 case CK_Nehalem: 459 case CK_Westmere: 460 case CK_SandyBridge: 461 case CK_IvyBridge: 462 case CK_Haswell: 463 case CK_Broadwell: 464 case CK_SkylakeClient: 465 case CK_SkylakeServer: 466 case CK_Cascadelake: 467 case CK_Cooperlake: 468 case CK_Cannonlake: 469 case CK_IcelakeClient: 470 case CK_Rocketlake: 471 case CK_IcelakeServer: 472 case CK_Tigerlake: 473 case CK_SapphireRapids: 474 case CK_Alderlake: 475 // FIXME: Historically, we defined this legacy name, it would be nice to 476 // remove it at some point. We've never exposed fine-grained names for 477 // recent primary x86 CPUs, and we should keep it that way. 478 defineCPUMacros(Builder, "corei7"); 479 break; 480 case CK_KNL: 481 defineCPUMacros(Builder, "knl"); 482 break; 483 case CK_KNM: 484 break; 485 case CK_Lakemont: 486 defineCPUMacros(Builder, "i586", /*Tuning*/false); 487 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 488 Builder.defineMacro("__tune_lakemont__"); 489 break; 490 case CK_K6_2: 491 Builder.defineMacro("__k6_2__"); 492 Builder.defineMacro("__tune_k6_2__"); 493 LLVM_FALLTHROUGH; 494 case CK_K6_3: 495 if (CPU != CK_K6_2) { // In case of fallthrough 496 // FIXME: GCC may be enabling these in cases where some other k6 497 // architecture is specified but -m3dnow is explicitly provided. The 498 // exact semantics need to be determined and emulated here. 499 Builder.defineMacro("__k6_3__"); 500 Builder.defineMacro("__tune_k6_3__"); 501 } 502 LLVM_FALLTHROUGH; 503 case CK_K6: 504 defineCPUMacros(Builder, "k6"); 505 break; 506 case CK_Athlon: 507 case CK_AthlonXP: 508 defineCPUMacros(Builder, "athlon"); 509 if (SSELevel != NoSSE) { 510 Builder.defineMacro("__athlon_sse__"); 511 Builder.defineMacro("__tune_athlon_sse__"); 512 } 513 break; 514 case CK_K8: 515 case CK_K8SSE3: 516 case CK_x86_64: 517 defineCPUMacros(Builder, "k8"); 518 break; 519 case CK_AMDFAM10: 520 defineCPUMacros(Builder, "amdfam10"); 521 break; 522 case CK_BTVER1: 523 defineCPUMacros(Builder, "btver1"); 524 break; 525 case CK_BTVER2: 526 defineCPUMacros(Builder, "btver2"); 527 break; 528 case CK_BDVER1: 529 defineCPUMacros(Builder, "bdver1"); 530 break; 531 case CK_BDVER2: 532 defineCPUMacros(Builder, "bdver2"); 533 break; 534 case CK_BDVER3: 535 defineCPUMacros(Builder, "bdver3"); 536 break; 537 case CK_BDVER4: 538 defineCPUMacros(Builder, "bdver4"); 539 break; 540 case CK_ZNVER1: 541 defineCPUMacros(Builder, "znver1"); 542 break; 543 case CK_ZNVER2: 544 defineCPUMacros(Builder, "znver2"); 545 break; 546 case CK_ZNVER3: 547 defineCPUMacros(Builder, "znver3"); 548 break; 549 case CK_Geode: 550 defineCPUMacros(Builder, "geode"); 551 break; 552 } 553 554 // Target properties. 555 Builder.defineMacro("__REGISTER_PREFIX__", ""); 556 557 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 558 // functions in glibc header files that use FP Stack inline asm which the 559 // backend can't deal with (PR879). 560 Builder.defineMacro("__NO_MATH_INLINES"); 561 562 if (HasAES) 563 Builder.defineMacro("__AES__"); 564 565 if (HasVAES) 566 Builder.defineMacro("__VAES__"); 567 568 if (HasPCLMUL) 569 Builder.defineMacro("__PCLMUL__"); 570 571 if (HasVPCLMULQDQ) 572 Builder.defineMacro("__VPCLMULQDQ__"); 573 574 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 575 // the feature flag only applies to 64-bit mode. 576 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 577 Builder.defineMacro("__LAHF_SAHF__"); 578 579 if (HasLZCNT) 580 Builder.defineMacro("__LZCNT__"); 581 582 if (HasRDRND) 583 Builder.defineMacro("__RDRND__"); 584 585 if (HasFSGSBASE) 586 Builder.defineMacro("__FSGSBASE__"); 587 588 if (HasBMI) 589 Builder.defineMacro("__BMI__"); 590 591 if (HasBMI2) 592 Builder.defineMacro("__BMI2__"); 593 594 if (HasPOPCNT) 595 Builder.defineMacro("__POPCNT__"); 596 597 if (HasRTM) 598 Builder.defineMacro("__RTM__"); 599 600 if (HasPRFCHW) 601 Builder.defineMacro("__PRFCHW__"); 602 603 if (HasRDSEED) 604 Builder.defineMacro("__RDSEED__"); 605 606 if (HasADX) 607 Builder.defineMacro("__ADX__"); 608 609 if (HasTBM) 610 Builder.defineMacro("__TBM__"); 611 612 if (HasLWP) 613 Builder.defineMacro("__LWP__"); 614 615 if (HasMWAITX) 616 Builder.defineMacro("__MWAITX__"); 617 618 if (HasMOVBE) 619 Builder.defineMacro("__MOVBE__"); 620 621 switch (XOPLevel) { 622 case XOP: 623 Builder.defineMacro("__XOP__"); 624 LLVM_FALLTHROUGH; 625 case FMA4: 626 Builder.defineMacro("__FMA4__"); 627 LLVM_FALLTHROUGH; 628 case SSE4A: 629 Builder.defineMacro("__SSE4A__"); 630 LLVM_FALLTHROUGH; 631 case NoXOP: 632 break; 633 } 634 635 if (HasFMA) 636 Builder.defineMacro("__FMA__"); 637 638 if (HasF16C) 639 Builder.defineMacro("__F16C__"); 640 641 if (HasGFNI) 642 Builder.defineMacro("__GFNI__"); 643 644 if (HasAVX512CD) 645 Builder.defineMacro("__AVX512CD__"); 646 if (HasAVX512VPOPCNTDQ) 647 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 648 if (HasAVX512VNNI) 649 Builder.defineMacro("__AVX512VNNI__"); 650 if (HasAVX512BF16) 651 Builder.defineMacro("__AVX512BF16__"); 652 if (HasAVX512ER) 653 Builder.defineMacro("__AVX512ER__"); 654 if (HasAVX512PF) 655 Builder.defineMacro("__AVX512PF__"); 656 if (HasAVX512DQ) 657 Builder.defineMacro("__AVX512DQ__"); 658 if (HasAVX512BITALG) 659 Builder.defineMacro("__AVX512BITALG__"); 660 if (HasAVX512BW) 661 Builder.defineMacro("__AVX512BW__"); 662 if (HasAVX512VL) 663 Builder.defineMacro("__AVX512VL__"); 664 if (HasAVX512VBMI) 665 Builder.defineMacro("__AVX512VBMI__"); 666 if (HasAVX512VBMI2) 667 Builder.defineMacro("__AVX512VBMI2__"); 668 if (HasAVX512IFMA) 669 Builder.defineMacro("__AVX512IFMA__"); 670 if (HasAVX512VP2INTERSECT) 671 Builder.defineMacro("__AVX512VP2INTERSECT__"); 672 if (HasSHA) 673 Builder.defineMacro("__SHA__"); 674 675 if (HasFXSR) 676 Builder.defineMacro("__FXSR__"); 677 if (HasXSAVE) 678 Builder.defineMacro("__XSAVE__"); 679 if (HasXSAVEOPT) 680 Builder.defineMacro("__XSAVEOPT__"); 681 if (HasXSAVEC) 682 Builder.defineMacro("__XSAVEC__"); 683 if (HasXSAVES) 684 Builder.defineMacro("__XSAVES__"); 685 if (HasPKU) 686 Builder.defineMacro("__PKU__"); 687 if (HasCLFLUSHOPT) 688 Builder.defineMacro("__CLFLUSHOPT__"); 689 if (HasCLWB) 690 Builder.defineMacro("__CLWB__"); 691 if (HasWBNOINVD) 692 Builder.defineMacro("__WBNOINVD__"); 693 if (HasSHSTK) 694 Builder.defineMacro("__SHSTK__"); 695 if (HasSGX) 696 Builder.defineMacro("__SGX__"); 697 if (HasPREFETCHWT1) 698 Builder.defineMacro("__PREFETCHWT1__"); 699 if (HasCLZERO) 700 Builder.defineMacro("__CLZERO__"); 701 if (HasKL) 702 Builder.defineMacro("__KL__"); 703 if (HasWIDEKL) 704 Builder.defineMacro("__WIDEKL__"); 705 if (HasRDPID) 706 Builder.defineMacro("__RDPID__"); 707 if (HasCLDEMOTE) 708 Builder.defineMacro("__CLDEMOTE__"); 709 if (HasWAITPKG) 710 Builder.defineMacro("__WAITPKG__"); 711 if (HasMOVDIRI) 712 Builder.defineMacro("__MOVDIRI__"); 713 if (HasMOVDIR64B) 714 Builder.defineMacro("__MOVDIR64B__"); 715 if (HasPCONFIG) 716 Builder.defineMacro("__PCONFIG__"); 717 if (HasPTWRITE) 718 Builder.defineMacro("__PTWRITE__"); 719 if (HasINVPCID) 720 Builder.defineMacro("__INVPCID__"); 721 if (HasENQCMD) 722 Builder.defineMacro("__ENQCMD__"); 723 if (HasHRESET) 724 Builder.defineMacro("__HRESET__"); 725 if (HasAMXTILE) 726 Builder.defineMacro("__AMXTILE__"); 727 if (HasAMXINT8) 728 Builder.defineMacro("__AMXINT8__"); 729 if (HasAMXBF16) 730 Builder.defineMacro("__AMXBF16__"); 731 if (HasAVXVNNI) 732 Builder.defineMacro("__AVXVNNI__"); 733 if (HasSERIALIZE) 734 Builder.defineMacro("__SERIALIZE__"); 735 if (HasTSXLDTRK) 736 Builder.defineMacro("__TSXLDTRK__"); 737 if (HasUINTR) 738 Builder.defineMacro("__UINTR__"); 739 740 // Each case falls through to the previous one here. 741 switch (SSELevel) { 742 case AVX512F: 743 Builder.defineMacro("__AVX512F__"); 744 LLVM_FALLTHROUGH; 745 case AVX2: 746 Builder.defineMacro("__AVX2__"); 747 LLVM_FALLTHROUGH; 748 case AVX: 749 Builder.defineMacro("__AVX__"); 750 LLVM_FALLTHROUGH; 751 case SSE42: 752 Builder.defineMacro("__SSE4_2__"); 753 LLVM_FALLTHROUGH; 754 case SSE41: 755 Builder.defineMacro("__SSE4_1__"); 756 LLVM_FALLTHROUGH; 757 case SSSE3: 758 Builder.defineMacro("__SSSE3__"); 759 LLVM_FALLTHROUGH; 760 case SSE3: 761 Builder.defineMacro("__SSE3__"); 762 LLVM_FALLTHROUGH; 763 case SSE2: 764 Builder.defineMacro("__SSE2__"); 765 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 766 LLVM_FALLTHROUGH; 767 case SSE1: 768 Builder.defineMacro("__SSE__"); 769 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 770 LLVM_FALLTHROUGH; 771 case NoSSE: 772 break; 773 } 774 775 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 776 switch (SSELevel) { 777 case AVX512F: 778 case AVX2: 779 case AVX: 780 case SSE42: 781 case SSE41: 782 case SSSE3: 783 case SSE3: 784 case SSE2: 785 Builder.defineMacro("_M_IX86_FP", Twine(2)); 786 break; 787 case SSE1: 788 Builder.defineMacro("_M_IX86_FP", Twine(1)); 789 break; 790 default: 791 Builder.defineMacro("_M_IX86_FP", Twine(0)); 792 break; 793 } 794 } 795 796 // Each case falls through to the previous one here. 797 switch (MMX3DNowLevel) { 798 case AMD3DNowAthlon: 799 Builder.defineMacro("__3dNOW_A__"); 800 LLVM_FALLTHROUGH; 801 case AMD3DNow: 802 Builder.defineMacro("__3dNOW__"); 803 LLVM_FALLTHROUGH; 804 case MMX: 805 Builder.defineMacro("__MMX__"); 806 LLVM_FALLTHROUGH; 807 case NoMMX3DNow: 808 break; 809 } 810 811 if (CPU >= CK_i486 || CPU == CK_None) { 812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 815 } 816 if (HasCX8) 817 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 818 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 819 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 820 821 if (HasFloat128) 822 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 823 } 824 825 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 826 return llvm::StringSwitch<bool>(Name) 827 .Case("3dnow", true) 828 .Case("3dnowa", true) 829 .Case("adx", true) 830 .Case("aes", true) 831 .Case("amx-bf16", true) 832 .Case("amx-int8", true) 833 .Case("amx-tile", true) 834 .Case("avx", true) 835 .Case("avx2", true) 836 .Case("avx512f", true) 837 .Case("avx512cd", true) 838 .Case("avx512vpopcntdq", true) 839 .Case("avx512vnni", true) 840 .Case("avx512bf16", true) 841 .Case("avx512er", true) 842 .Case("avx512pf", true) 843 .Case("avx512dq", true) 844 .Case("avx512bitalg", true) 845 .Case("avx512bw", true) 846 .Case("avx512vl", true) 847 .Case("avx512vbmi", true) 848 .Case("avx512vbmi2", true) 849 .Case("avx512ifma", true) 850 .Case("avx512vp2intersect", true) 851 .Case("avxvnni", true) 852 .Case("bmi", true) 853 .Case("bmi2", true) 854 .Case("cldemote", true) 855 .Case("clflushopt", true) 856 .Case("clwb", true) 857 .Case("clzero", true) 858 .Case("cx16", true) 859 .Case("enqcmd", true) 860 .Case("f16c", true) 861 .Case("fma", true) 862 .Case("fma4", true) 863 .Case("fsgsbase", true) 864 .Case("fxsr", true) 865 .Case("gfni", true) 866 .Case("hreset", true) 867 .Case("invpcid", true) 868 .Case("kl", true) 869 .Case("widekl", true) 870 .Case("lwp", true) 871 .Case("lzcnt", true) 872 .Case("mmx", true) 873 .Case("movbe", true) 874 .Case("movdiri", true) 875 .Case("movdir64b", true) 876 .Case("mwaitx", true) 877 .Case("pclmul", true) 878 .Case("pconfig", true) 879 .Case("pku", true) 880 .Case("popcnt", true) 881 .Case("prefetchwt1", true) 882 .Case("prfchw", true) 883 .Case("ptwrite", true) 884 .Case("rdpid", true) 885 .Case("rdrnd", true) 886 .Case("rdseed", true) 887 .Case("rtm", true) 888 .Case("sahf", true) 889 .Case("serialize", true) 890 .Case("sgx", true) 891 .Case("sha", true) 892 .Case("shstk", true) 893 .Case("sse", true) 894 .Case("sse2", true) 895 .Case("sse3", true) 896 .Case("ssse3", true) 897 .Case("sse4", true) 898 .Case("sse4.1", true) 899 .Case("sse4.2", true) 900 .Case("sse4a", true) 901 .Case("tbm", true) 902 .Case("tsxldtrk", true) 903 .Case("uintr", true) 904 .Case("vaes", true) 905 .Case("vpclmulqdq", true) 906 .Case("wbnoinvd", true) 907 .Case("waitpkg", true) 908 .Case("x87", true) 909 .Case("xop", true) 910 .Case("xsave", true) 911 .Case("xsavec", true) 912 .Case("xsaves", true) 913 .Case("xsaveopt", true) 914 .Default(false); 915 } 916 917 bool X86TargetInfo::hasFeature(StringRef Feature) const { 918 return llvm::StringSwitch<bool>(Feature) 919 .Case("adx", HasADX) 920 .Case("aes", HasAES) 921 .Case("amx-bf16", HasAMXBF16) 922 .Case("amx-int8", HasAMXINT8) 923 .Case("amx-tile", HasAMXTILE) 924 .Case("avxvnni", HasAVXVNNI) 925 .Case("avx", SSELevel >= AVX) 926 .Case("avx2", SSELevel >= AVX2) 927 .Case("avx512f", SSELevel >= AVX512F) 928 .Case("avx512cd", HasAVX512CD) 929 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 930 .Case("avx512vnni", HasAVX512VNNI) 931 .Case("avx512bf16", HasAVX512BF16) 932 .Case("avx512er", HasAVX512ER) 933 .Case("avx512pf", HasAVX512PF) 934 .Case("avx512dq", HasAVX512DQ) 935 .Case("avx512bitalg", HasAVX512BITALG) 936 .Case("avx512bw", HasAVX512BW) 937 .Case("avx512vl", HasAVX512VL) 938 .Case("avx512vbmi", HasAVX512VBMI) 939 .Case("avx512vbmi2", HasAVX512VBMI2) 940 .Case("avx512ifma", HasAVX512IFMA) 941 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 942 .Case("bmi", HasBMI) 943 .Case("bmi2", HasBMI2) 944 .Case("cldemote", HasCLDEMOTE) 945 .Case("clflushopt", HasCLFLUSHOPT) 946 .Case("clwb", HasCLWB) 947 .Case("clzero", HasCLZERO) 948 .Case("cx8", HasCX8) 949 .Case("cx16", HasCX16) 950 .Case("enqcmd", HasENQCMD) 951 .Case("f16c", HasF16C) 952 .Case("fma", HasFMA) 953 .Case("fma4", XOPLevel >= FMA4) 954 .Case("fsgsbase", HasFSGSBASE) 955 .Case("fxsr", HasFXSR) 956 .Case("gfni", HasGFNI) 957 .Case("hreset", HasHRESET) 958 .Case("invpcid", HasINVPCID) 959 .Case("kl", HasKL) 960 .Case("widekl", HasWIDEKL) 961 .Case("lwp", HasLWP) 962 .Case("lzcnt", HasLZCNT) 963 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 964 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 965 .Case("mmx", MMX3DNowLevel >= MMX) 966 .Case("movbe", HasMOVBE) 967 .Case("movdiri", HasMOVDIRI) 968 .Case("movdir64b", HasMOVDIR64B) 969 .Case("mwaitx", HasMWAITX) 970 .Case("pclmul", HasPCLMUL) 971 .Case("pconfig", HasPCONFIG) 972 .Case("pku", HasPKU) 973 .Case("popcnt", HasPOPCNT) 974 .Case("prefetchwt1", HasPREFETCHWT1) 975 .Case("prfchw", HasPRFCHW) 976 .Case("ptwrite", HasPTWRITE) 977 .Case("rdpid", HasRDPID) 978 .Case("rdrnd", HasRDRND) 979 .Case("rdseed", HasRDSEED) 980 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 981 .Case("rtm", HasRTM) 982 .Case("sahf", HasLAHFSAHF) 983 .Case("serialize", HasSERIALIZE) 984 .Case("sgx", HasSGX) 985 .Case("sha", HasSHA) 986 .Case("shstk", HasSHSTK) 987 .Case("sse", SSELevel >= SSE1) 988 .Case("sse2", SSELevel >= SSE2) 989 .Case("sse3", SSELevel >= SSE3) 990 .Case("ssse3", SSELevel >= SSSE3) 991 .Case("sse4.1", SSELevel >= SSE41) 992 .Case("sse4.2", SSELevel >= SSE42) 993 .Case("sse4a", XOPLevel >= SSE4A) 994 .Case("tbm", HasTBM) 995 .Case("tsxldtrk", HasTSXLDTRK) 996 .Case("uintr", HasUINTR) 997 .Case("vaes", HasVAES) 998 .Case("vpclmulqdq", HasVPCLMULQDQ) 999 .Case("wbnoinvd", HasWBNOINVD) 1000 .Case("waitpkg", HasWAITPKG) 1001 .Case("x86", true) 1002 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1003 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1004 .Case("xop", XOPLevel >= XOP) 1005 .Case("xsave", HasXSAVE) 1006 .Case("xsavec", HasXSAVEC) 1007 .Case("xsaves", HasXSAVES) 1008 .Case("xsaveopt", HasXSAVEOPT) 1009 .Default(false); 1010 } 1011 1012 // We can't use a generic validation scheme for the features accepted here 1013 // versus subtarget features accepted in the target attribute because the 1014 // bitfield structure that's initialized in the runtime only supports the 1015 // below currently rather than the full range of subtarget features. (See 1016 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1017 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1018 return llvm::StringSwitch<bool>(FeatureStr) 1019 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1020 #include "llvm/Support/X86TargetParser.def" 1021 .Default(false); 1022 } 1023 1024 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1025 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1026 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1027 #include "llvm/Support/X86TargetParser.def" 1028 ; 1029 // Note, this function should only be used after ensuring the value is 1030 // correct, so it asserts if the value is out of range. 1031 } 1032 1033 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1034 enum class FeatPriority { 1035 #define FEATURE(FEAT) FEAT, 1036 #include "clang/Basic/X86Target.def" 1037 }; 1038 switch (Feat) { 1039 #define FEATURE(FEAT) \ 1040 case llvm::X86::FEAT: \ 1041 return static_cast<unsigned>(FeatPriority::FEAT); 1042 #include "clang/Basic/X86Target.def" 1043 default: 1044 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1045 } 1046 } 1047 1048 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1049 // Valid CPUs have a 'key feature' that compares just better than its key 1050 // feature. 1051 using namespace llvm::X86; 1052 CPUKind Kind = parseArchX86(Name); 1053 if (Kind != CK_None) { 1054 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1055 return (getFeaturePriority(KeyFeature) << 1) + 1; 1056 } 1057 1058 // Now we know we have a feature, so get its priority and shift it a few so 1059 // that we have sufficient room for the CPUs (above). 1060 return getFeaturePriority(getFeature(Name)) << 1; 1061 } 1062 1063 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1064 return llvm::StringSwitch<bool>(Name) 1065 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1066 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1067 #include "clang/Basic/X86Target.def" 1068 .Default(false); 1069 } 1070 1071 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1072 return llvm::StringSwitch<StringRef>(Name) 1073 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1074 #include "clang/Basic/X86Target.def" 1075 .Default(Name); 1076 } 1077 1078 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1079 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1080 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1081 #include "clang/Basic/X86Target.def" 1082 .Default(0); 1083 } 1084 1085 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1086 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1087 StringRef WholeList = 1088 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1089 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1090 #include "clang/Basic/X86Target.def" 1091 .Default(""); 1092 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1093 } 1094 1095 // We can't use a generic validation scheme for the cpus accepted here 1096 // versus subtarget cpus accepted in the target attribute because the 1097 // variables intitialized by the runtime only support the below currently 1098 // rather than the full range of cpus. 1099 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1100 return llvm::StringSwitch<bool>(FeatureStr) 1101 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1102 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1103 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1104 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1105 #include "llvm/Support/X86TargetParser.def" 1106 .Default(false); 1107 } 1108 1109 static unsigned matchAsmCCConstraint(const char *&Name) { 1110 auto RV = llvm::StringSwitch<unsigned>(Name) 1111 .Case("@cca", 4) 1112 .Case("@ccae", 5) 1113 .Case("@ccb", 4) 1114 .Case("@ccbe", 5) 1115 .Case("@ccc", 4) 1116 .Case("@cce", 4) 1117 .Case("@ccz", 4) 1118 .Case("@ccg", 4) 1119 .Case("@ccge", 5) 1120 .Case("@ccl", 4) 1121 .Case("@ccle", 5) 1122 .Case("@ccna", 5) 1123 .Case("@ccnae", 6) 1124 .Case("@ccnb", 5) 1125 .Case("@ccnbe", 6) 1126 .Case("@ccnc", 5) 1127 .Case("@ccne", 5) 1128 .Case("@ccnz", 5) 1129 .Case("@ccng", 5) 1130 .Case("@ccnge", 6) 1131 .Case("@ccnl", 5) 1132 .Case("@ccnle", 6) 1133 .Case("@ccno", 5) 1134 .Case("@ccnp", 5) 1135 .Case("@ccns", 5) 1136 .Case("@cco", 4) 1137 .Case("@ccp", 4) 1138 .Case("@ccs", 4) 1139 .Default(0); 1140 return RV; 1141 } 1142 1143 bool X86TargetInfo::validateAsmConstraint( 1144 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1145 switch (*Name) { 1146 default: 1147 return false; 1148 // Constant constraints. 1149 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1150 // instructions. 1151 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1152 // x86_64 instructions. 1153 case 's': 1154 Info.setRequiresImmediate(); 1155 return true; 1156 case 'I': 1157 Info.setRequiresImmediate(0, 31); 1158 return true; 1159 case 'J': 1160 Info.setRequiresImmediate(0, 63); 1161 return true; 1162 case 'K': 1163 Info.setRequiresImmediate(-128, 127); 1164 return true; 1165 case 'L': 1166 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1167 return true; 1168 case 'M': 1169 Info.setRequiresImmediate(0, 3); 1170 return true; 1171 case 'N': 1172 Info.setRequiresImmediate(0, 255); 1173 return true; 1174 case 'O': 1175 Info.setRequiresImmediate(0, 127); 1176 return true; 1177 // Register constraints. 1178 case 'Y': // 'Y' is the first character for several 2-character constraints. 1179 // Shift the pointer to the second character of the constraint. 1180 Name++; 1181 switch (*Name) { 1182 default: 1183 return false; 1184 case 'z': // First SSE register. 1185 case '2': 1186 case 't': // Any SSE register, when SSE2 is enabled. 1187 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1188 case 'm': // Any MMX register, when inter-unit moves enabled. 1189 case 'k': // AVX512 arch mask registers: k1-k7. 1190 Info.setAllowsRegister(); 1191 return true; 1192 } 1193 case 'f': // Any x87 floating point stack register. 1194 // Constraint 'f' cannot be used for output operands. 1195 if (Info.ConstraintStr[0] == '=') 1196 return false; 1197 Info.setAllowsRegister(); 1198 return true; 1199 case 'a': // eax. 1200 case 'b': // ebx. 1201 case 'c': // ecx. 1202 case 'd': // edx. 1203 case 'S': // esi. 1204 case 'D': // edi. 1205 case 'A': // edx:eax. 1206 case 't': // Top of floating point stack. 1207 case 'u': // Second from top of floating point stack. 1208 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1209 case 'y': // Any MMX register. 1210 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1211 case 'x': // Any SSE register. 1212 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1213 // for intermideate k reg operations). 1214 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1215 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1216 case 'l': // "Index" registers: any general register that can be used as an 1217 // index in a base+index memory access. 1218 Info.setAllowsRegister(); 1219 return true; 1220 // Floating point constant constraints. 1221 case 'C': // SSE floating point constant. 1222 case 'G': // x87 floating point constant. 1223 return true; 1224 case '@': 1225 // CC condition changes. 1226 if (auto Len = matchAsmCCConstraint(Name)) { 1227 Name += Len - 1; 1228 Info.setAllowsRegister(); 1229 return true; 1230 } 1231 return false; 1232 } 1233 } 1234 1235 // Below is based on the following information: 1236 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1237 // | Processor Name | Cache Line Size (Bytes) | Source | 1238 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1239 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1240 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1241 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1242 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1243 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1244 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1245 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1246 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1247 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1248 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1249 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1250 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1251 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1252 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1253 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1254 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1255 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1256 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1257 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1258 using namespace llvm::X86; 1259 switch (CPU) { 1260 // i386 1261 case CK_i386: 1262 // i486 1263 case CK_i486: 1264 case CK_WinChipC6: 1265 case CK_WinChip2: 1266 case CK_C3: 1267 // Lakemont 1268 case CK_Lakemont: 1269 return 16; 1270 1271 // i586 1272 case CK_i586: 1273 case CK_Pentium: 1274 case CK_PentiumMMX: 1275 // i686 1276 case CK_PentiumPro: 1277 case CK_i686: 1278 case CK_Pentium2: 1279 case CK_Pentium3: 1280 case CK_PentiumM: 1281 case CK_C3_2: 1282 // K6 1283 case CK_K6: 1284 case CK_K6_2: 1285 case CK_K6_3: 1286 // Geode 1287 case CK_Geode: 1288 return 32; 1289 1290 // Netburst 1291 case CK_Pentium4: 1292 case CK_Prescott: 1293 case CK_Nocona: 1294 // Atom 1295 case CK_Bonnell: 1296 case CK_Silvermont: 1297 case CK_Goldmont: 1298 case CK_GoldmontPlus: 1299 case CK_Tremont: 1300 1301 case CK_Westmere: 1302 case CK_SandyBridge: 1303 case CK_IvyBridge: 1304 case CK_Haswell: 1305 case CK_Broadwell: 1306 case CK_SkylakeClient: 1307 case CK_SkylakeServer: 1308 case CK_Cascadelake: 1309 case CK_Nehalem: 1310 case CK_Cooperlake: 1311 case CK_Cannonlake: 1312 case CK_Tigerlake: 1313 case CK_SapphireRapids: 1314 case CK_IcelakeClient: 1315 case CK_Rocketlake: 1316 case CK_IcelakeServer: 1317 case CK_Alderlake: 1318 case CK_KNL: 1319 case CK_KNM: 1320 // K7 1321 case CK_Athlon: 1322 case CK_AthlonXP: 1323 // K8 1324 case CK_K8: 1325 case CK_K8SSE3: 1326 case CK_AMDFAM10: 1327 // Bobcat 1328 case CK_BTVER1: 1329 case CK_BTVER2: 1330 // Bulldozer 1331 case CK_BDVER1: 1332 case CK_BDVER2: 1333 case CK_BDVER3: 1334 case CK_BDVER4: 1335 // Zen 1336 case CK_ZNVER1: 1337 case CK_ZNVER2: 1338 case CK_ZNVER3: 1339 // Deprecated 1340 case CK_x86_64: 1341 case CK_x86_64_v2: 1342 case CK_x86_64_v3: 1343 case CK_x86_64_v4: 1344 case CK_Yonah: 1345 case CK_Penryn: 1346 case CK_Core2: 1347 return 64; 1348 1349 // The following currently have unknown cache line sizes (but they are probably all 64): 1350 // Core 1351 case CK_None: 1352 return None; 1353 } 1354 llvm_unreachable("Unknown CPU kind"); 1355 } 1356 1357 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1358 StringRef Constraint, 1359 unsigned Size) const { 1360 // Strip off constraint modifiers. 1361 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1362 Constraint = Constraint.substr(1); 1363 1364 return validateOperandSize(FeatureMap, Constraint, Size); 1365 } 1366 1367 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1368 StringRef Constraint, 1369 unsigned Size) const { 1370 return validateOperandSize(FeatureMap, Constraint, Size); 1371 } 1372 1373 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1374 StringRef Constraint, 1375 unsigned Size) const { 1376 switch (Constraint[0]) { 1377 default: 1378 break; 1379 case 'k': 1380 // Registers k0-k7 (AVX512) size limit is 64 bit. 1381 case 'y': 1382 return Size <= 64; 1383 case 'f': 1384 case 't': 1385 case 'u': 1386 return Size <= 128; 1387 case 'Y': 1388 // 'Y' is the first character for several 2-character constraints. 1389 switch (Constraint[1]) { 1390 default: 1391 return false; 1392 case 'm': 1393 // 'Ym' is synonymous with 'y'. 1394 case 'k': 1395 return Size <= 64; 1396 case 'z': 1397 // XMM0/YMM/ZMM0 1398 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1399 // ZMM0 can be used if target supports AVX512F. 1400 return Size <= 512U; 1401 else if (hasFeatureEnabled(FeatureMap, "avx")) 1402 // YMM0 can be used if target supports AVX. 1403 return Size <= 256U; 1404 else if (hasFeatureEnabled(FeatureMap, "sse")) 1405 return Size <= 128U; 1406 return false; 1407 case 'i': 1408 case 't': 1409 case '2': 1410 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1411 if (SSELevel < SSE2) 1412 return false; 1413 break; 1414 } 1415 break; 1416 case 'v': 1417 case 'x': 1418 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1419 // 512-bit zmm registers can be used if target supports AVX512F. 1420 return Size <= 512U; 1421 else if (hasFeatureEnabled(FeatureMap, "avx")) 1422 // 256-bit ymm registers can be used if target supports AVX. 1423 return Size <= 256U; 1424 return Size <= 128U; 1425 1426 } 1427 1428 return true; 1429 } 1430 1431 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1432 switch (*Constraint) { 1433 case '@': 1434 if (auto Len = matchAsmCCConstraint(Constraint)) { 1435 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1436 Constraint += Len - 1; 1437 return Converted; 1438 } 1439 return std::string(1, *Constraint); 1440 case 'a': 1441 return std::string("{ax}"); 1442 case 'b': 1443 return std::string("{bx}"); 1444 case 'c': 1445 return std::string("{cx}"); 1446 case 'd': 1447 return std::string("{dx}"); 1448 case 'S': 1449 return std::string("{si}"); 1450 case 'D': 1451 return std::string("{di}"); 1452 case 'p': // address 1453 return std::string("im"); 1454 case 't': // top of floating point stack. 1455 return std::string("{st}"); 1456 case 'u': // second from top of floating point stack. 1457 return std::string("{st(1)}"); // second from top of floating point stack. 1458 case 'Y': 1459 switch (Constraint[1]) { 1460 default: 1461 // Break from inner switch and fall through (copy single char), 1462 // continue parsing after copying the current constraint into 1463 // the return string. 1464 break; 1465 case 'k': 1466 case 'm': 1467 case 'i': 1468 case 't': 1469 case 'z': 1470 case '2': 1471 // "^" hints llvm that this is a 2 letter constraint. 1472 // "Constraint++" is used to promote the string iterator 1473 // to the next constraint. 1474 return std::string("^") + std::string(Constraint++, 2); 1475 } 1476 LLVM_FALLTHROUGH; 1477 default: 1478 return std::string(1, *Constraint); 1479 } 1480 } 1481 1482 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1483 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1484 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1485 } 1486 1487 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1488 llvm::X86::fillValidTuneCPUList(Values); 1489 } 1490 1491 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1492 return llvm::makeArrayRef(GCCRegNames); 1493 } 1494 1495 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1496 return llvm::makeArrayRef(AddlRegNames); 1497 } 1498 1499 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1500 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1501 Builtin::FirstTSBuiltin + 1); 1502 } 1503 1504 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1505 return llvm::makeArrayRef(BuiltinInfoX86, 1506 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1507 } 1508