1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_Cooperlake: 135 // CPX inherits all CLX features plus AVX512BF16 136 setFeatureEnabledImpl(Features, "avx512bf16", true); 137 LLVM_FALLTHROUGH; 138 case CK_Cascadelake: 139 // CLX inherits all SKX features plus AVX512VNNI 140 setFeatureEnabledImpl(Features, "avx512vnni", true); 141 LLVM_FALLTHROUGH; 142 case CK_SkylakeServer: 143 setFeatureEnabledImpl(Features, "avx512f", true); 144 setFeatureEnabledImpl(Features, "avx512cd", true); 145 setFeatureEnabledImpl(Features, "avx512dq", true); 146 setFeatureEnabledImpl(Features, "avx512bw", true); 147 setFeatureEnabledImpl(Features, "avx512vl", true); 148 setFeatureEnabledImpl(Features, "clwb", true); 149 setFeatureEnabledImpl(Features, "pku", true); 150 // SkylakeServer cores inherits all SKL features, except SGX 151 goto SkylakeCommon; 152 153 case CK_Tigerlake: 154 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 155 setFeatureEnabledImpl(Features, "movdiri", true); 156 setFeatureEnabledImpl(Features, "movdir64b", true); 157 setFeatureEnabledImpl(Features, "shstk", true); 158 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 159 goto IcelakeCommon; 160 161 case CK_IcelakeServer: 162 setFeatureEnabledImpl(Features, "pconfig", true); 163 setFeatureEnabledImpl(Features, "wbnoinvd", true); 164 LLVM_FALLTHROUGH; 165 case CK_IcelakeClient: 166 IcelakeCommon: 167 setFeatureEnabledImpl(Features, "vaes", true); 168 setFeatureEnabledImpl(Features, "gfni", true); 169 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 170 setFeatureEnabledImpl(Features, "avx512bitalg", true); 171 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 172 setFeatureEnabledImpl(Features, "avx512vnni", true); 173 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 174 setFeatureEnabledImpl(Features, "rdpid", true); 175 setFeatureEnabledImpl(Features, "clwb", true); 176 LLVM_FALLTHROUGH; 177 case CK_Cannonlake: 178 setFeatureEnabledImpl(Features, "avx512f", true); 179 setFeatureEnabledImpl(Features, "avx512cd", true); 180 setFeatureEnabledImpl(Features, "avx512dq", true); 181 setFeatureEnabledImpl(Features, "avx512bw", true); 182 setFeatureEnabledImpl(Features, "avx512vl", true); 183 setFeatureEnabledImpl(Features, "avx512ifma", true); 184 setFeatureEnabledImpl(Features, "avx512vbmi", true); 185 setFeatureEnabledImpl(Features, "pku", true); 186 setFeatureEnabledImpl(Features, "sha", true); 187 LLVM_FALLTHROUGH; 188 case CK_SkylakeClient: 189 setFeatureEnabledImpl(Features, "sgx", true); 190 // SkylakeServer cores inherits all SKL features, except SGX 191 SkylakeCommon: 192 setFeatureEnabledImpl(Features, "xsavec", true); 193 setFeatureEnabledImpl(Features, "xsaves", true); 194 setFeatureEnabledImpl(Features, "clflushopt", true); 195 setFeatureEnabledImpl(Features, "aes", true); 196 LLVM_FALLTHROUGH; 197 case CK_Broadwell: 198 setFeatureEnabledImpl(Features, "rdseed", true); 199 setFeatureEnabledImpl(Features, "adx", true); 200 setFeatureEnabledImpl(Features, "prfchw", true); 201 LLVM_FALLTHROUGH; 202 case CK_Haswell: 203 setFeatureEnabledImpl(Features, "avx2", true); 204 setFeatureEnabledImpl(Features, "lzcnt", true); 205 setFeatureEnabledImpl(Features, "bmi", true); 206 setFeatureEnabledImpl(Features, "bmi2", true); 207 setFeatureEnabledImpl(Features, "fma", true); 208 setFeatureEnabledImpl(Features, "invpcid", true); 209 setFeatureEnabledImpl(Features, "movbe", true); 210 LLVM_FALLTHROUGH; 211 case CK_IvyBridge: 212 setFeatureEnabledImpl(Features, "rdrnd", true); 213 setFeatureEnabledImpl(Features, "f16c", true); 214 setFeatureEnabledImpl(Features, "fsgsbase", true); 215 LLVM_FALLTHROUGH; 216 case CK_SandyBridge: 217 setFeatureEnabledImpl(Features, "avx", true); 218 setFeatureEnabledImpl(Features, "xsave", true); 219 setFeatureEnabledImpl(Features, "xsaveopt", true); 220 LLVM_FALLTHROUGH; 221 case CK_Westmere: 222 setFeatureEnabledImpl(Features, "pclmul", true); 223 LLVM_FALLTHROUGH; 224 case CK_Nehalem: 225 setFeatureEnabledImpl(Features, "sse4.2", true); 226 LLVM_FALLTHROUGH; 227 case CK_Penryn: 228 setFeatureEnabledImpl(Features, "sse4.1", true); 229 LLVM_FALLTHROUGH; 230 case CK_Core2: 231 setFeatureEnabledImpl(Features, "ssse3", true); 232 setFeatureEnabledImpl(Features, "sahf", true); 233 LLVM_FALLTHROUGH; 234 case CK_Nocona: 235 setFeatureEnabledImpl(Features, "cx16", true); 236 LLVM_FALLTHROUGH; 237 case CK_Yonah: 238 case CK_Prescott: 239 setFeatureEnabledImpl(Features, "sse3", true); 240 LLVM_FALLTHROUGH; 241 case CK_PentiumM: 242 case CK_Pentium4: 243 case CK_x86_64: 244 setFeatureEnabledImpl(Features, "sse2", true); 245 LLVM_FALLTHROUGH; 246 case CK_Pentium3: 247 case CK_C3_2: 248 setFeatureEnabledImpl(Features, "sse", true); 249 LLVM_FALLTHROUGH; 250 case CK_Pentium2: 251 setFeatureEnabledImpl(Features, "fxsr", true); 252 LLVM_FALLTHROUGH; 253 case CK_PentiumMMX: 254 case CK_K6: 255 case CK_WinChipC6: 256 setFeatureEnabledImpl(Features, "mmx", true); 257 break; 258 259 case CK_Tremont: 260 setFeatureEnabledImpl(Features, "clwb", true); 261 setFeatureEnabledImpl(Features, "gfni", true); 262 LLVM_FALLTHROUGH; 263 case CK_GoldmontPlus: 264 setFeatureEnabledImpl(Features, "ptwrite", true); 265 setFeatureEnabledImpl(Features, "rdpid", true); 266 setFeatureEnabledImpl(Features, "sgx", true); 267 LLVM_FALLTHROUGH; 268 case CK_Goldmont: 269 setFeatureEnabledImpl(Features, "sha", true); 270 setFeatureEnabledImpl(Features, "rdseed", true); 271 setFeatureEnabledImpl(Features, "xsave", true); 272 setFeatureEnabledImpl(Features, "xsaveopt", true); 273 setFeatureEnabledImpl(Features, "xsavec", true); 274 setFeatureEnabledImpl(Features, "xsaves", true); 275 setFeatureEnabledImpl(Features, "clflushopt", true); 276 setFeatureEnabledImpl(Features, "fsgsbase", true); 277 setFeatureEnabledImpl(Features, "aes", true); 278 LLVM_FALLTHROUGH; 279 case CK_Silvermont: 280 setFeatureEnabledImpl(Features, "rdrnd", true); 281 setFeatureEnabledImpl(Features, "pclmul", true); 282 setFeatureEnabledImpl(Features, "sse4.2", true); 283 setFeatureEnabledImpl(Features, "prfchw", true); 284 LLVM_FALLTHROUGH; 285 case CK_Bonnell: 286 setFeatureEnabledImpl(Features, "movbe", true); 287 setFeatureEnabledImpl(Features, "ssse3", true); 288 setFeatureEnabledImpl(Features, "fxsr", true); 289 setFeatureEnabledImpl(Features, "cx16", true); 290 setFeatureEnabledImpl(Features, "sahf", true); 291 setFeatureEnabledImpl(Features, "mmx", true); 292 break; 293 294 case CK_KNM: 295 // TODO: Add avx5124fmaps/avx5124vnniw. 296 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 297 LLVM_FALLTHROUGH; 298 case CK_KNL: 299 setFeatureEnabledImpl(Features, "avx512f", true); 300 setFeatureEnabledImpl(Features, "avx512cd", true); 301 setFeatureEnabledImpl(Features, "avx512er", true); 302 setFeatureEnabledImpl(Features, "avx512pf", true); 303 setFeatureEnabledImpl(Features, "prfchw", true); 304 setFeatureEnabledImpl(Features, "prefetchwt1", true); 305 setFeatureEnabledImpl(Features, "fxsr", true); 306 setFeatureEnabledImpl(Features, "rdseed", true); 307 setFeatureEnabledImpl(Features, "adx", true); 308 setFeatureEnabledImpl(Features, "lzcnt", true); 309 setFeatureEnabledImpl(Features, "bmi", true); 310 setFeatureEnabledImpl(Features, "bmi2", true); 311 setFeatureEnabledImpl(Features, "fma", true); 312 setFeatureEnabledImpl(Features, "rdrnd", true); 313 setFeatureEnabledImpl(Features, "f16c", true); 314 setFeatureEnabledImpl(Features, "fsgsbase", true); 315 setFeatureEnabledImpl(Features, "aes", true); 316 setFeatureEnabledImpl(Features, "pclmul", true); 317 setFeatureEnabledImpl(Features, "cx16", true); 318 setFeatureEnabledImpl(Features, "xsaveopt", true); 319 setFeatureEnabledImpl(Features, "xsave", true); 320 setFeatureEnabledImpl(Features, "movbe", true); 321 setFeatureEnabledImpl(Features, "sahf", true); 322 setFeatureEnabledImpl(Features, "mmx", true); 323 break; 324 325 case CK_K6_2: 326 case CK_K6_3: 327 case CK_WinChip2: 328 case CK_C3: 329 setFeatureEnabledImpl(Features, "3dnow", true); 330 break; 331 332 case CK_AMDFAM10: 333 setFeatureEnabledImpl(Features, "sse4a", true); 334 setFeatureEnabledImpl(Features, "lzcnt", true); 335 setFeatureEnabledImpl(Features, "popcnt", true); 336 setFeatureEnabledImpl(Features, "sahf", true); 337 LLVM_FALLTHROUGH; 338 case CK_K8SSE3: 339 setFeatureEnabledImpl(Features, "sse3", true); 340 LLVM_FALLTHROUGH; 341 case CK_K8: 342 setFeatureEnabledImpl(Features, "sse2", true); 343 LLVM_FALLTHROUGH; 344 case CK_AthlonXP: 345 setFeatureEnabledImpl(Features, "sse", true); 346 setFeatureEnabledImpl(Features, "fxsr", true); 347 LLVM_FALLTHROUGH; 348 case CK_Athlon: 349 case CK_Geode: 350 setFeatureEnabledImpl(Features, "3dnowa", true); 351 break; 352 353 case CK_BTVER2: 354 setFeatureEnabledImpl(Features, "avx", true); 355 setFeatureEnabledImpl(Features, "aes", true); 356 setFeatureEnabledImpl(Features, "pclmul", true); 357 setFeatureEnabledImpl(Features, "bmi", true); 358 setFeatureEnabledImpl(Features, "f16c", true); 359 setFeatureEnabledImpl(Features, "xsaveopt", true); 360 setFeatureEnabledImpl(Features, "movbe", true); 361 LLVM_FALLTHROUGH; 362 case CK_BTVER1: 363 setFeatureEnabledImpl(Features, "ssse3", true); 364 setFeatureEnabledImpl(Features, "sse4a", true); 365 setFeatureEnabledImpl(Features, "lzcnt", true); 366 setFeatureEnabledImpl(Features, "popcnt", true); 367 setFeatureEnabledImpl(Features, "prfchw", true); 368 setFeatureEnabledImpl(Features, "cx16", true); 369 setFeatureEnabledImpl(Features, "fxsr", true); 370 setFeatureEnabledImpl(Features, "sahf", true); 371 setFeatureEnabledImpl(Features, "mmx", true); 372 break; 373 374 case CK_ZNVER2: 375 setFeatureEnabledImpl(Features, "clwb", true); 376 setFeatureEnabledImpl(Features, "rdpid", true); 377 setFeatureEnabledImpl(Features, "wbnoinvd", true); 378 LLVM_FALLTHROUGH; 379 case CK_ZNVER1: 380 setFeatureEnabledImpl(Features, "adx", true); 381 setFeatureEnabledImpl(Features, "aes", true); 382 setFeatureEnabledImpl(Features, "avx2", true); 383 setFeatureEnabledImpl(Features, "bmi", true); 384 setFeatureEnabledImpl(Features, "bmi2", true); 385 setFeatureEnabledImpl(Features, "clflushopt", true); 386 setFeatureEnabledImpl(Features, "clzero", true); 387 setFeatureEnabledImpl(Features, "cx16", true); 388 setFeatureEnabledImpl(Features, "f16c", true); 389 setFeatureEnabledImpl(Features, "fma", true); 390 setFeatureEnabledImpl(Features, "fsgsbase", true); 391 setFeatureEnabledImpl(Features, "fxsr", true); 392 setFeatureEnabledImpl(Features, "lzcnt", true); 393 setFeatureEnabledImpl(Features, "mmx", true); 394 setFeatureEnabledImpl(Features, "mwaitx", true); 395 setFeatureEnabledImpl(Features, "movbe", true); 396 setFeatureEnabledImpl(Features, "pclmul", true); 397 setFeatureEnabledImpl(Features, "popcnt", true); 398 setFeatureEnabledImpl(Features, "prfchw", true); 399 setFeatureEnabledImpl(Features, "rdrnd", true); 400 setFeatureEnabledImpl(Features, "rdseed", true); 401 setFeatureEnabledImpl(Features, "sahf", true); 402 setFeatureEnabledImpl(Features, "sha", true); 403 setFeatureEnabledImpl(Features, "sse4a", true); 404 setFeatureEnabledImpl(Features, "xsave", true); 405 setFeatureEnabledImpl(Features, "xsavec", true); 406 setFeatureEnabledImpl(Features, "xsaveopt", true); 407 setFeatureEnabledImpl(Features, "xsaves", true); 408 break; 409 410 case CK_BDVER4: 411 setFeatureEnabledImpl(Features, "avx2", true); 412 setFeatureEnabledImpl(Features, "bmi2", true); 413 setFeatureEnabledImpl(Features, "mwaitx", true); 414 LLVM_FALLTHROUGH; 415 case CK_BDVER3: 416 setFeatureEnabledImpl(Features, "fsgsbase", true); 417 setFeatureEnabledImpl(Features, "xsaveopt", true); 418 LLVM_FALLTHROUGH; 419 case CK_BDVER2: 420 setFeatureEnabledImpl(Features, "bmi", true); 421 setFeatureEnabledImpl(Features, "fma", true); 422 setFeatureEnabledImpl(Features, "f16c", true); 423 setFeatureEnabledImpl(Features, "tbm", true); 424 LLVM_FALLTHROUGH; 425 case CK_BDVER1: 426 // xop implies avx, sse4a and fma4. 427 setFeatureEnabledImpl(Features, "xop", true); 428 setFeatureEnabledImpl(Features, "lwp", true); 429 setFeatureEnabledImpl(Features, "lzcnt", true); 430 setFeatureEnabledImpl(Features, "aes", true); 431 setFeatureEnabledImpl(Features, "pclmul", true); 432 setFeatureEnabledImpl(Features, "prfchw", true); 433 setFeatureEnabledImpl(Features, "cx16", true); 434 setFeatureEnabledImpl(Features, "fxsr", true); 435 setFeatureEnabledImpl(Features, "xsave", true); 436 setFeatureEnabledImpl(Features, "sahf", true); 437 setFeatureEnabledImpl(Features, "mmx", true); 438 break; 439 } 440 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 441 return false; 442 443 // Can't do this earlier because we need to be able to explicitly enable 444 // or disable these features and the things that they depend upon. 445 446 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 447 auto I = Features.find("sse4.2"); 448 if (I != Features.end() && I->getValue() && 449 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 450 Features["popcnt"] = true; 451 452 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 453 I = Features.find("3dnow"); 454 if (I != Features.end() && I->getValue() && 455 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 456 Features["prfchw"] = true; 457 458 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 459 // then enable MMX. 460 I = Features.find("sse"); 461 if (I != Features.end() && I->getValue() && 462 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 463 Features["mmx"] = true; 464 465 return true; 466 } 467 468 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 469 X86SSEEnum Level, bool Enabled) { 470 if (Enabled) { 471 switch (Level) { 472 case AVX512F: 473 Features["avx512f"] = true; 474 Features["fma"] = true; 475 Features["f16c"] = true; 476 LLVM_FALLTHROUGH; 477 case AVX2: 478 Features["avx2"] = true; 479 LLVM_FALLTHROUGH; 480 case AVX: 481 Features["avx"] = true; 482 Features["xsave"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE42: 485 Features["sse4.2"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE41: 488 Features["sse4.1"] = true; 489 LLVM_FALLTHROUGH; 490 case SSSE3: 491 Features["ssse3"] = true; 492 LLVM_FALLTHROUGH; 493 case SSE3: 494 Features["sse3"] = true; 495 LLVM_FALLTHROUGH; 496 case SSE2: 497 Features["sse2"] = true; 498 LLVM_FALLTHROUGH; 499 case SSE1: 500 Features["sse"] = true; 501 LLVM_FALLTHROUGH; 502 case NoSSE: 503 break; 504 } 505 return; 506 } 507 508 switch (Level) { 509 case NoSSE: 510 case SSE1: 511 Features["sse"] = false; 512 LLVM_FALLTHROUGH; 513 case SSE2: 514 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 515 Features["sha"] = Features["gfni"] = false; 516 LLVM_FALLTHROUGH; 517 case SSE3: 518 Features["sse3"] = false; 519 setXOPLevel(Features, NoXOP, false); 520 LLVM_FALLTHROUGH; 521 case SSSE3: 522 Features["ssse3"] = false; 523 LLVM_FALLTHROUGH; 524 case SSE41: 525 Features["sse4.1"] = false; 526 LLVM_FALLTHROUGH; 527 case SSE42: 528 Features["sse4.2"] = false; 529 LLVM_FALLTHROUGH; 530 case AVX: 531 Features["fma"] = Features["avx"] = Features["f16c"] = false; 532 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 533 Features["vpclmulqdq"] = false; 534 setXOPLevel(Features, FMA4, false); 535 LLVM_FALLTHROUGH; 536 case AVX2: 537 Features["avx2"] = false; 538 LLVM_FALLTHROUGH; 539 case AVX512F: 540 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 541 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 542 Features["avx512vl"] = Features["avx512vbmi"] = false; 543 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 544 Features["avx512bitalg"] = Features["avx512vnni"] = false; 545 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 546 Features["avx512vp2intersect"] = false; 547 break; 548 } 549 } 550 551 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 552 MMX3DNowEnum Level, bool Enabled) { 553 if (Enabled) { 554 switch (Level) { 555 case AMD3DNowAthlon: 556 Features["3dnowa"] = true; 557 LLVM_FALLTHROUGH; 558 case AMD3DNow: 559 Features["3dnow"] = true; 560 LLVM_FALLTHROUGH; 561 case MMX: 562 Features["mmx"] = true; 563 LLVM_FALLTHROUGH; 564 case NoMMX3DNow: 565 break; 566 } 567 return; 568 } 569 570 switch (Level) { 571 case NoMMX3DNow: 572 case MMX: 573 Features["mmx"] = false; 574 LLVM_FALLTHROUGH; 575 case AMD3DNow: 576 Features["3dnow"] = false; 577 LLVM_FALLTHROUGH; 578 case AMD3DNowAthlon: 579 Features["3dnowa"] = false; 580 break; 581 } 582 } 583 584 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 585 bool Enabled) { 586 if (Enabled) { 587 switch (Level) { 588 case XOP: 589 Features["xop"] = true; 590 LLVM_FALLTHROUGH; 591 case FMA4: 592 Features["fma4"] = true; 593 setSSELevel(Features, AVX, true); 594 LLVM_FALLTHROUGH; 595 case SSE4A: 596 Features["sse4a"] = true; 597 setSSELevel(Features, SSE3, true); 598 LLVM_FALLTHROUGH; 599 case NoXOP: 600 break; 601 } 602 return; 603 } 604 605 switch (Level) { 606 case NoXOP: 607 case SSE4A: 608 Features["sse4a"] = false; 609 LLVM_FALLTHROUGH; 610 case FMA4: 611 Features["fma4"] = false; 612 LLVM_FALLTHROUGH; 613 case XOP: 614 Features["xop"] = false; 615 break; 616 } 617 } 618 619 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 620 StringRef Name, bool Enabled) { 621 // This is a bit of a hack to deal with the sse4 target feature when used 622 // as part of the target attribute. We handle sse4 correctly everywhere 623 // else. See below for more information on how we handle the sse4 options. 624 if (Name != "sse4") 625 Features[Name] = Enabled; 626 627 if (Name == "mmx") { 628 setMMXLevel(Features, MMX, Enabled); 629 } else if (Name == "sse") { 630 setSSELevel(Features, SSE1, Enabled); 631 } else if (Name == "sse2") { 632 setSSELevel(Features, SSE2, Enabled); 633 } else if (Name == "sse3") { 634 setSSELevel(Features, SSE3, Enabled); 635 } else if (Name == "ssse3") { 636 setSSELevel(Features, SSSE3, Enabled); 637 } else if (Name == "sse4.2") { 638 setSSELevel(Features, SSE42, Enabled); 639 } else if (Name == "sse4.1") { 640 setSSELevel(Features, SSE41, Enabled); 641 } else if (Name == "3dnow") { 642 setMMXLevel(Features, AMD3DNow, Enabled); 643 } else if (Name == "3dnowa") { 644 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 645 } else if (Name == "aes") { 646 if (Enabled) 647 setSSELevel(Features, SSE2, Enabled); 648 else 649 Features["vaes"] = false; 650 } else if (Name == "vaes") { 651 if (Enabled) { 652 setSSELevel(Features, AVX, Enabled); 653 Features["aes"] = true; 654 } 655 } else if (Name == "pclmul") { 656 if (Enabled) 657 setSSELevel(Features, SSE2, Enabled); 658 else 659 Features["vpclmulqdq"] = false; 660 } else if (Name == "vpclmulqdq") { 661 if (Enabled) { 662 setSSELevel(Features, AVX, Enabled); 663 Features["pclmul"] = true; 664 } 665 } else if (Name == "gfni") { 666 if (Enabled) 667 setSSELevel(Features, SSE2, Enabled); 668 } else if (Name == "avx") { 669 setSSELevel(Features, AVX, Enabled); 670 } else if (Name == "avx2") { 671 setSSELevel(Features, AVX2, Enabled); 672 } else if (Name == "avx512f") { 673 setSSELevel(Features, AVX512F, Enabled); 674 } else if (Name.startswith("avx512")) { 675 if (Enabled) 676 setSSELevel(Features, AVX512F, Enabled); 677 // Enable BWI instruction if certain features are being enabled. 678 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 679 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 680 Features["avx512bw"] = true; 681 // Also disable some features if BWI is being disabled. 682 if (Name == "avx512bw" && !Enabled) { 683 Features["avx512vbmi"] = false; 684 Features["avx512vbmi2"] = false; 685 Features["avx512bitalg"] = false; 686 Features["avx512bf16"] = false; 687 } 688 } else if (Name == "fma") { 689 if (Enabled) 690 setSSELevel(Features, AVX, Enabled); 691 else 692 setSSELevel(Features, AVX512F, Enabled); 693 } else if (Name == "fma4") { 694 setXOPLevel(Features, FMA4, Enabled); 695 } else if (Name == "xop") { 696 setXOPLevel(Features, XOP, Enabled); 697 } else if (Name == "sse4a") { 698 setXOPLevel(Features, SSE4A, Enabled); 699 } else if (Name == "f16c") { 700 if (Enabled) 701 setSSELevel(Features, AVX, Enabled); 702 else 703 setSSELevel(Features, AVX512F, Enabled); 704 } else if (Name == "sha") { 705 if (Enabled) 706 setSSELevel(Features, SSE2, Enabled); 707 } else if (Name == "sse4") { 708 // We can get here via the __target__ attribute since that's not controlled 709 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 710 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 711 // disabled. 712 if (Enabled) 713 setSSELevel(Features, SSE42, Enabled); 714 else 715 setSSELevel(Features, SSE41, Enabled); 716 } else if (Name == "xsave") { 717 if (!Enabled) 718 Features["xsaveopt"] = false; 719 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 720 if (Enabled) 721 Features["xsave"] = true; 722 } 723 } 724 725 /// handleTargetFeatures - Perform initialization based on the user 726 /// configured set of features. 727 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 728 DiagnosticsEngine &Diags) { 729 for (const auto &Feature : Features) { 730 if (Feature[0] != '+') 731 continue; 732 733 if (Feature == "+aes") { 734 HasAES = true; 735 } else if (Feature == "+vaes") { 736 HasVAES = true; 737 } else if (Feature == "+pclmul") { 738 HasPCLMUL = true; 739 } else if (Feature == "+vpclmulqdq") { 740 HasVPCLMULQDQ = true; 741 } else if (Feature == "+lzcnt") { 742 HasLZCNT = true; 743 } else if (Feature == "+rdrnd") { 744 HasRDRND = true; 745 } else if (Feature == "+fsgsbase") { 746 HasFSGSBASE = true; 747 } else if (Feature == "+bmi") { 748 HasBMI = true; 749 } else if (Feature == "+bmi2") { 750 HasBMI2 = true; 751 } else if (Feature == "+popcnt") { 752 HasPOPCNT = true; 753 } else if (Feature == "+rtm") { 754 HasRTM = true; 755 } else if (Feature == "+prfchw") { 756 HasPRFCHW = true; 757 } else if (Feature == "+rdseed") { 758 HasRDSEED = true; 759 } else if (Feature == "+adx") { 760 HasADX = true; 761 } else if (Feature == "+tbm") { 762 HasTBM = true; 763 } else if (Feature == "+lwp") { 764 HasLWP = true; 765 } else if (Feature == "+fma") { 766 HasFMA = true; 767 } else if (Feature == "+f16c") { 768 HasF16C = true; 769 } else if (Feature == "+gfni") { 770 HasGFNI = true; 771 } else if (Feature == "+avx512cd") { 772 HasAVX512CD = true; 773 } else if (Feature == "+avx512vpopcntdq") { 774 HasAVX512VPOPCNTDQ = true; 775 } else if (Feature == "+avx512vnni") { 776 HasAVX512VNNI = true; 777 } else if (Feature == "+avx512bf16") { 778 HasAVX512BF16 = true; 779 } else if (Feature == "+avx512er") { 780 HasAVX512ER = true; 781 } else if (Feature == "+avx512pf") { 782 HasAVX512PF = true; 783 } else if (Feature == "+avx512dq") { 784 HasAVX512DQ = true; 785 } else if (Feature == "+avx512bitalg") { 786 HasAVX512BITALG = true; 787 } else if (Feature == "+avx512bw") { 788 HasAVX512BW = true; 789 } else if (Feature == "+avx512vl") { 790 HasAVX512VL = true; 791 } else if (Feature == "+avx512vbmi") { 792 HasAVX512VBMI = true; 793 } else if (Feature == "+avx512vbmi2") { 794 HasAVX512VBMI2 = true; 795 } else if (Feature == "+avx512ifma") { 796 HasAVX512IFMA = true; 797 } else if (Feature == "+avx512vp2intersect") { 798 HasAVX512VP2INTERSECT = true; 799 } else if (Feature == "+sha") { 800 HasSHA = true; 801 } else if (Feature == "+shstk") { 802 HasSHSTK = true; 803 } else if (Feature == "+movbe") { 804 HasMOVBE = true; 805 } else if (Feature == "+sgx") { 806 HasSGX = true; 807 } else if (Feature == "+cx8") { 808 HasCX8 = true; 809 } else if (Feature == "+cx16") { 810 HasCX16 = true; 811 } else if (Feature == "+fxsr") { 812 HasFXSR = true; 813 } else if (Feature == "+xsave") { 814 HasXSAVE = true; 815 } else if (Feature == "+xsaveopt") { 816 HasXSAVEOPT = true; 817 } else if (Feature == "+xsavec") { 818 HasXSAVEC = true; 819 } else if (Feature == "+xsaves") { 820 HasXSAVES = true; 821 } else if (Feature == "+mwaitx") { 822 HasMWAITX = true; 823 } else if (Feature == "+pku") { 824 HasPKU = true; 825 } else if (Feature == "+clflushopt") { 826 HasCLFLUSHOPT = true; 827 } else if (Feature == "+clwb") { 828 HasCLWB = true; 829 } else if (Feature == "+wbnoinvd") { 830 HasWBNOINVD = true; 831 } else if (Feature == "+prefetchwt1") { 832 HasPREFETCHWT1 = true; 833 } else if (Feature == "+clzero") { 834 HasCLZERO = true; 835 } else if (Feature == "+cldemote") { 836 HasCLDEMOTE = true; 837 } else if (Feature == "+rdpid") { 838 HasRDPID = true; 839 } else if (Feature == "+retpoline-external-thunk") { 840 HasRetpolineExternalThunk = true; 841 } else if (Feature == "+sahf") { 842 HasLAHFSAHF = true; 843 } else if (Feature == "+waitpkg") { 844 HasWAITPKG = true; 845 } else if (Feature == "+movdiri") { 846 HasMOVDIRI = true; 847 } else if (Feature == "+movdir64b") { 848 HasMOVDIR64B = true; 849 } else if (Feature == "+pconfig") { 850 HasPCONFIG = true; 851 } else if (Feature == "+ptwrite") { 852 HasPTWRITE = true; 853 } else if (Feature == "+invpcid") { 854 HasINVPCID = true; 855 } else if (Feature == "+enqcmd") { 856 HasENQCMD = true; 857 } else if (Feature == "+serialize") { 858 HasSERIALIZE = true; 859 } else if (Feature == "+tsxldtrk") { 860 HasTSXLDTRK = true; 861 } 862 863 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 864 .Case("+avx512f", AVX512F) 865 .Case("+avx2", AVX2) 866 .Case("+avx", AVX) 867 .Case("+sse4.2", SSE42) 868 .Case("+sse4.1", SSE41) 869 .Case("+ssse3", SSSE3) 870 .Case("+sse3", SSE3) 871 .Case("+sse2", SSE2) 872 .Case("+sse", SSE1) 873 .Default(NoSSE); 874 SSELevel = std::max(SSELevel, Level); 875 876 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 877 .Case("+3dnowa", AMD3DNowAthlon) 878 .Case("+3dnow", AMD3DNow) 879 .Case("+mmx", MMX) 880 .Default(NoMMX3DNow); 881 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 882 883 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 884 .Case("+xop", XOP) 885 .Case("+fma4", FMA4) 886 .Case("+sse4a", SSE4A) 887 .Default(NoXOP); 888 XOPLevel = std::max(XOPLevel, XLevel); 889 } 890 891 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 892 // matches the selected sse level. 893 if ((FPMath == FP_SSE && SSELevel < SSE1) || 894 (FPMath == FP_387 && SSELevel >= SSE1)) { 895 Diags.Report(diag::err_target_unsupported_fpmath) 896 << (FPMath == FP_SSE ? "sse" : "387"); 897 return false; 898 } 899 900 SimdDefaultAlign = 901 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 902 return true; 903 } 904 905 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 906 /// definitions for this particular subtarget. 907 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 908 MacroBuilder &Builder) const { 909 // Inline assembly supports X86 flag outputs. 910 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 911 912 std::string CodeModel = getTargetOpts().CodeModel; 913 if (CodeModel == "default") 914 CodeModel = "small"; 915 Builder.defineMacro("__code_model_" + CodeModel + "__"); 916 917 // Target identification. 918 if (getTriple().getArch() == llvm::Triple::x86_64) { 919 Builder.defineMacro("__amd64__"); 920 Builder.defineMacro("__amd64"); 921 Builder.defineMacro("__x86_64"); 922 Builder.defineMacro("__x86_64__"); 923 if (getTriple().getArchName() == "x86_64h") { 924 Builder.defineMacro("__x86_64h"); 925 Builder.defineMacro("__x86_64h__"); 926 } 927 } else { 928 DefineStd(Builder, "i386", Opts); 929 } 930 931 Builder.defineMacro("__SEG_GS"); 932 Builder.defineMacro("__SEG_FS"); 933 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 934 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 935 936 // Subtarget options. 937 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 938 // truly should be based on -mtune options. 939 switch (CPU) { 940 case CK_Generic: 941 break; 942 case CK_i386: 943 // The rest are coming from the i386 define above. 944 Builder.defineMacro("__tune_i386__"); 945 break; 946 case CK_i486: 947 case CK_WinChipC6: 948 case CK_WinChip2: 949 case CK_C3: 950 defineCPUMacros(Builder, "i486"); 951 break; 952 case CK_PentiumMMX: 953 Builder.defineMacro("__pentium_mmx__"); 954 Builder.defineMacro("__tune_pentium_mmx__"); 955 LLVM_FALLTHROUGH; 956 case CK_i586: 957 case CK_Pentium: 958 defineCPUMacros(Builder, "i586"); 959 defineCPUMacros(Builder, "pentium"); 960 break; 961 case CK_Pentium3: 962 case CK_PentiumM: 963 Builder.defineMacro("__tune_pentium3__"); 964 LLVM_FALLTHROUGH; 965 case CK_Pentium2: 966 case CK_C3_2: 967 Builder.defineMacro("__tune_pentium2__"); 968 LLVM_FALLTHROUGH; 969 case CK_PentiumPro: 970 case CK_i686: 971 defineCPUMacros(Builder, "i686"); 972 defineCPUMacros(Builder, "pentiumpro"); 973 break; 974 case CK_Pentium4: 975 defineCPUMacros(Builder, "pentium4"); 976 break; 977 case CK_Yonah: 978 case CK_Prescott: 979 case CK_Nocona: 980 defineCPUMacros(Builder, "nocona"); 981 break; 982 case CK_Core2: 983 case CK_Penryn: 984 defineCPUMacros(Builder, "core2"); 985 break; 986 case CK_Bonnell: 987 defineCPUMacros(Builder, "atom"); 988 break; 989 case CK_Silvermont: 990 defineCPUMacros(Builder, "slm"); 991 break; 992 case CK_Goldmont: 993 defineCPUMacros(Builder, "goldmont"); 994 break; 995 case CK_GoldmontPlus: 996 defineCPUMacros(Builder, "goldmont_plus"); 997 break; 998 case CK_Tremont: 999 defineCPUMacros(Builder, "tremont"); 1000 break; 1001 case CK_Nehalem: 1002 case CK_Westmere: 1003 case CK_SandyBridge: 1004 case CK_IvyBridge: 1005 case CK_Haswell: 1006 case CK_Broadwell: 1007 case CK_SkylakeClient: 1008 case CK_SkylakeServer: 1009 case CK_Cascadelake: 1010 case CK_Cooperlake: 1011 case CK_Cannonlake: 1012 case CK_IcelakeClient: 1013 case CK_IcelakeServer: 1014 case CK_Tigerlake: 1015 // FIXME: Historically, we defined this legacy name, it would be nice to 1016 // remove it at some point. We've never exposed fine-grained names for 1017 // recent primary x86 CPUs, and we should keep it that way. 1018 defineCPUMacros(Builder, "corei7"); 1019 break; 1020 case CK_KNL: 1021 defineCPUMacros(Builder, "knl"); 1022 break; 1023 case CK_KNM: 1024 break; 1025 case CK_Lakemont: 1026 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1027 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1028 Builder.defineMacro("__tune_lakemont__"); 1029 break; 1030 case CK_K6_2: 1031 Builder.defineMacro("__k6_2__"); 1032 Builder.defineMacro("__tune_k6_2__"); 1033 LLVM_FALLTHROUGH; 1034 case CK_K6_3: 1035 if (CPU != CK_K6_2) { // In case of fallthrough 1036 // FIXME: GCC may be enabling these in cases where some other k6 1037 // architecture is specified but -m3dnow is explicitly provided. The 1038 // exact semantics need to be determined and emulated here. 1039 Builder.defineMacro("__k6_3__"); 1040 Builder.defineMacro("__tune_k6_3__"); 1041 } 1042 LLVM_FALLTHROUGH; 1043 case CK_K6: 1044 defineCPUMacros(Builder, "k6"); 1045 break; 1046 case CK_Athlon: 1047 case CK_AthlonXP: 1048 defineCPUMacros(Builder, "athlon"); 1049 if (SSELevel != NoSSE) { 1050 Builder.defineMacro("__athlon_sse__"); 1051 Builder.defineMacro("__tune_athlon_sse__"); 1052 } 1053 break; 1054 case CK_K8: 1055 case CK_K8SSE3: 1056 case CK_x86_64: 1057 defineCPUMacros(Builder, "k8"); 1058 break; 1059 case CK_AMDFAM10: 1060 defineCPUMacros(Builder, "amdfam10"); 1061 break; 1062 case CK_BTVER1: 1063 defineCPUMacros(Builder, "btver1"); 1064 break; 1065 case CK_BTVER2: 1066 defineCPUMacros(Builder, "btver2"); 1067 break; 1068 case CK_BDVER1: 1069 defineCPUMacros(Builder, "bdver1"); 1070 break; 1071 case CK_BDVER2: 1072 defineCPUMacros(Builder, "bdver2"); 1073 break; 1074 case CK_BDVER3: 1075 defineCPUMacros(Builder, "bdver3"); 1076 break; 1077 case CK_BDVER4: 1078 defineCPUMacros(Builder, "bdver4"); 1079 break; 1080 case CK_ZNVER1: 1081 defineCPUMacros(Builder, "znver1"); 1082 break; 1083 case CK_ZNVER2: 1084 defineCPUMacros(Builder, "znver2"); 1085 break; 1086 case CK_Geode: 1087 defineCPUMacros(Builder, "geode"); 1088 break; 1089 } 1090 1091 // Target properties. 1092 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1093 1094 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1095 // functions in glibc header files that use FP Stack inline asm which the 1096 // backend can't deal with (PR879). 1097 Builder.defineMacro("__NO_MATH_INLINES"); 1098 1099 if (HasAES) 1100 Builder.defineMacro("__AES__"); 1101 1102 if (HasVAES) 1103 Builder.defineMacro("__VAES__"); 1104 1105 if (HasPCLMUL) 1106 Builder.defineMacro("__PCLMUL__"); 1107 1108 if (HasVPCLMULQDQ) 1109 Builder.defineMacro("__VPCLMULQDQ__"); 1110 1111 if (HasLZCNT) 1112 Builder.defineMacro("__LZCNT__"); 1113 1114 if (HasRDRND) 1115 Builder.defineMacro("__RDRND__"); 1116 1117 if (HasFSGSBASE) 1118 Builder.defineMacro("__FSGSBASE__"); 1119 1120 if (HasBMI) 1121 Builder.defineMacro("__BMI__"); 1122 1123 if (HasBMI2) 1124 Builder.defineMacro("__BMI2__"); 1125 1126 if (HasPOPCNT) 1127 Builder.defineMacro("__POPCNT__"); 1128 1129 if (HasRTM) 1130 Builder.defineMacro("__RTM__"); 1131 1132 if (HasPRFCHW) 1133 Builder.defineMacro("__PRFCHW__"); 1134 1135 if (HasRDSEED) 1136 Builder.defineMacro("__RDSEED__"); 1137 1138 if (HasADX) 1139 Builder.defineMacro("__ADX__"); 1140 1141 if (HasTBM) 1142 Builder.defineMacro("__TBM__"); 1143 1144 if (HasLWP) 1145 Builder.defineMacro("__LWP__"); 1146 1147 if (HasMWAITX) 1148 Builder.defineMacro("__MWAITX__"); 1149 1150 if (HasMOVBE) 1151 Builder.defineMacro("__MOVBE__"); 1152 1153 switch (XOPLevel) { 1154 case XOP: 1155 Builder.defineMacro("__XOP__"); 1156 LLVM_FALLTHROUGH; 1157 case FMA4: 1158 Builder.defineMacro("__FMA4__"); 1159 LLVM_FALLTHROUGH; 1160 case SSE4A: 1161 Builder.defineMacro("__SSE4A__"); 1162 LLVM_FALLTHROUGH; 1163 case NoXOP: 1164 break; 1165 } 1166 1167 if (HasFMA) 1168 Builder.defineMacro("__FMA__"); 1169 1170 if (HasF16C) 1171 Builder.defineMacro("__F16C__"); 1172 1173 if (HasGFNI) 1174 Builder.defineMacro("__GFNI__"); 1175 1176 if (HasAVX512CD) 1177 Builder.defineMacro("__AVX512CD__"); 1178 if (HasAVX512VPOPCNTDQ) 1179 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1180 if (HasAVX512VNNI) 1181 Builder.defineMacro("__AVX512VNNI__"); 1182 if (HasAVX512BF16) 1183 Builder.defineMacro("__AVX512BF16__"); 1184 if (HasAVX512ER) 1185 Builder.defineMacro("__AVX512ER__"); 1186 if (HasAVX512PF) 1187 Builder.defineMacro("__AVX512PF__"); 1188 if (HasAVX512DQ) 1189 Builder.defineMacro("__AVX512DQ__"); 1190 if (HasAVX512BITALG) 1191 Builder.defineMacro("__AVX512BITALG__"); 1192 if (HasAVX512BW) 1193 Builder.defineMacro("__AVX512BW__"); 1194 if (HasAVX512VL) 1195 Builder.defineMacro("__AVX512VL__"); 1196 if (HasAVX512VBMI) 1197 Builder.defineMacro("__AVX512VBMI__"); 1198 if (HasAVX512VBMI2) 1199 Builder.defineMacro("__AVX512VBMI2__"); 1200 if (HasAVX512IFMA) 1201 Builder.defineMacro("__AVX512IFMA__"); 1202 if (HasAVX512VP2INTERSECT) 1203 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1204 if (HasSHA) 1205 Builder.defineMacro("__SHA__"); 1206 1207 if (HasFXSR) 1208 Builder.defineMacro("__FXSR__"); 1209 if (HasXSAVE) 1210 Builder.defineMacro("__XSAVE__"); 1211 if (HasXSAVEOPT) 1212 Builder.defineMacro("__XSAVEOPT__"); 1213 if (HasXSAVEC) 1214 Builder.defineMacro("__XSAVEC__"); 1215 if (HasXSAVES) 1216 Builder.defineMacro("__XSAVES__"); 1217 if (HasPKU) 1218 Builder.defineMacro("__PKU__"); 1219 if (HasCLFLUSHOPT) 1220 Builder.defineMacro("__CLFLUSHOPT__"); 1221 if (HasCLWB) 1222 Builder.defineMacro("__CLWB__"); 1223 if (HasWBNOINVD) 1224 Builder.defineMacro("__WBNOINVD__"); 1225 if (HasSHSTK) 1226 Builder.defineMacro("__SHSTK__"); 1227 if (HasSGX) 1228 Builder.defineMacro("__SGX__"); 1229 if (HasPREFETCHWT1) 1230 Builder.defineMacro("__PREFETCHWT1__"); 1231 if (HasCLZERO) 1232 Builder.defineMacro("__CLZERO__"); 1233 if (HasRDPID) 1234 Builder.defineMacro("__RDPID__"); 1235 if (HasCLDEMOTE) 1236 Builder.defineMacro("__CLDEMOTE__"); 1237 if (HasWAITPKG) 1238 Builder.defineMacro("__WAITPKG__"); 1239 if (HasMOVDIRI) 1240 Builder.defineMacro("__MOVDIRI__"); 1241 if (HasMOVDIR64B) 1242 Builder.defineMacro("__MOVDIR64B__"); 1243 if (HasPCONFIG) 1244 Builder.defineMacro("__PCONFIG__"); 1245 if (HasPTWRITE) 1246 Builder.defineMacro("__PTWRITE__"); 1247 if (HasINVPCID) 1248 Builder.defineMacro("__INVPCID__"); 1249 if (HasENQCMD) 1250 Builder.defineMacro("__ENQCMD__"); 1251 if (HasSERIALIZE) 1252 Builder.defineMacro("__SERIALIZE__"); 1253 if (HasTSXLDTRK) 1254 Builder.defineMacro("__TSXLDTRK__"); 1255 1256 // Each case falls through to the previous one here. 1257 switch (SSELevel) { 1258 case AVX512F: 1259 Builder.defineMacro("__AVX512F__"); 1260 LLVM_FALLTHROUGH; 1261 case AVX2: 1262 Builder.defineMacro("__AVX2__"); 1263 LLVM_FALLTHROUGH; 1264 case AVX: 1265 Builder.defineMacro("__AVX__"); 1266 LLVM_FALLTHROUGH; 1267 case SSE42: 1268 Builder.defineMacro("__SSE4_2__"); 1269 LLVM_FALLTHROUGH; 1270 case SSE41: 1271 Builder.defineMacro("__SSE4_1__"); 1272 LLVM_FALLTHROUGH; 1273 case SSSE3: 1274 Builder.defineMacro("__SSSE3__"); 1275 LLVM_FALLTHROUGH; 1276 case SSE3: 1277 Builder.defineMacro("__SSE3__"); 1278 LLVM_FALLTHROUGH; 1279 case SSE2: 1280 Builder.defineMacro("__SSE2__"); 1281 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1282 LLVM_FALLTHROUGH; 1283 case SSE1: 1284 Builder.defineMacro("__SSE__"); 1285 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1286 LLVM_FALLTHROUGH; 1287 case NoSSE: 1288 break; 1289 } 1290 1291 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1292 switch (SSELevel) { 1293 case AVX512F: 1294 case AVX2: 1295 case AVX: 1296 case SSE42: 1297 case SSE41: 1298 case SSSE3: 1299 case SSE3: 1300 case SSE2: 1301 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1302 break; 1303 case SSE1: 1304 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1305 break; 1306 default: 1307 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1308 break; 1309 } 1310 } 1311 1312 // Each case falls through to the previous one here. 1313 switch (MMX3DNowLevel) { 1314 case AMD3DNowAthlon: 1315 Builder.defineMacro("__3dNOW_A__"); 1316 LLVM_FALLTHROUGH; 1317 case AMD3DNow: 1318 Builder.defineMacro("__3dNOW__"); 1319 LLVM_FALLTHROUGH; 1320 case MMX: 1321 Builder.defineMacro("__MMX__"); 1322 LLVM_FALLTHROUGH; 1323 case NoMMX3DNow: 1324 break; 1325 } 1326 1327 if (CPU >= CK_i486 || CPU == CK_Generic) { 1328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1331 } 1332 if (HasCX8) 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1334 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1336 1337 if (HasFloat128) 1338 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1339 } 1340 1341 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1342 return llvm::StringSwitch<bool>(Name) 1343 .Case("3dnow", true) 1344 .Case("3dnowa", true) 1345 .Case("adx", true) 1346 .Case("aes", true) 1347 .Case("avx", true) 1348 .Case("avx2", true) 1349 .Case("avx512f", true) 1350 .Case("avx512cd", true) 1351 .Case("avx512vpopcntdq", true) 1352 .Case("avx512vnni", true) 1353 .Case("avx512bf16", true) 1354 .Case("avx512er", true) 1355 .Case("avx512pf", true) 1356 .Case("avx512dq", true) 1357 .Case("avx512bitalg", true) 1358 .Case("avx512bw", true) 1359 .Case("avx512vl", true) 1360 .Case("avx512vbmi", true) 1361 .Case("avx512vbmi2", true) 1362 .Case("avx512ifma", true) 1363 .Case("avx512vp2intersect", true) 1364 .Case("bmi", true) 1365 .Case("bmi2", true) 1366 .Case("cldemote", true) 1367 .Case("clflushopt", true) 1368 .Case("clwb", true) 1369 .Case("clzero", true) 1370 .Case("cx16", true) 1371 .Case("enqcmd", true) 1372 .Case("f16c", true) 1373 .Case("fma", true) 1374 .Case("fma4", true) 1375 .Case("fsgsbase", true) 1376 .Case("fxsr", true) 1377 .Case("gfni", true) 1378 .Case("invpcid", true) 1379 .Case("lwp", true) 1380 .Case("lzcnt", true) 1381 .Case("mmx", true) 1382 .Case("movbe", true) 1383 .Case("movdiri", true) 1384 .Case("movdir64b", true) 1385 .Case("mwaitx", true) 1386 .Case("pclmul", true) 1387 .Case("pconfig", true) 1388 .Case("pku", true) 1389 .Case("popcnt", true) 1390 .Case("prefetchwt1", true) 1391 .Case("prfchw", true) 1392 .Case("ptwrite", true) 1393 .Case("rdpid", true) 1394 .Case("rdrnd", true) 1395 .Case("rdseed", true) 1396 .Case("rtm", true) 1397 .Case("sahf", true) 1398 .Case("serialize", true) 1399 .Case("sgx", true) 1400 .Case("sha", true) 1401 .Case("shstk", true) 1402 .Case("sse", true) 1403 .Case("sse2", true) 1404 .Case("sse3", true) 1405 .Case("ssse3", true) 1406 .Case("sse4", true) 1407 .Case("sse4.1", true) 1408 .Case("sse4.2", true) 1409 .Case("sse4a", true) 1410 .Case("tbm", true) 1411 .Case("tsxldtrk", true) 1412 .Case("vaes", true) 1413 .Case("vpclmulqdq", true) 1414 .Case("wbnoinvd", true) 1415 .Case("waitpkg", true) 1416 .Case("x87", true) 1417 .Case("xop", true) 1418 .Case("xsave", true) 1419 .Case("xsavec", true) 1420 .Case("xsaves", true) 1421 .Case("xsaveopt", true) 1422 .Default(false); 1423 } 1424 1425 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1426 return llvm::StringSwitch<bool>(Feature) 1427 .Case("adx", HasADX) 1428 .Case("aes", HasAES) 1429 .Case("avx", SSELevel >= AVX) 1430 .Case("avx2", SSELevel >= AVX2) 1431 .Case("avx512f", SSELevel >= AVX512F) 1432 .Case("avx512cd", HasAVX512CD) 1433 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1434 .Case("avx512vnni", HasAVX512VNNI) 1435 .Case("avx512bf16", HasAVX512BF16) 1436 .Case("avx512er", HasAVX512ER) 1437 .Case("avx512pf", HasAVX512PF) 1438 .Case("avx512dq", HasAVX512DQ) 1439 .Case("avx512bitalg", HasAVX512BITALG) 1440 .Case("avx512bw", HasAVX512BW) 1441 .Case("avx512vl", HasAVX512VL) 1442 .Case("avx512vbmi", HasAVX512VBMI) 1443 .Case("avx512vbmi2", HasAVX512VBMI2) 1444 .Case("avx512ifma", HasAVX512IFMA) 1445 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1446 .Case("bmi", HasBMI) 1447 .Case("bmi2", HasBMI2) 1448 .Case("cldemote", HasCLDEMOTE) 1449 .Case("clflushopt", HasCLFLUSHOPT) 1450 .Case("clwb", HasCLWB) 1451 .Case("clzero", HasCLZERO) 1452 .Case("cx8", HasCX8) 1453 .Case("cx16", HasCX16) 1454 .Case("enqcmd", HasENQCMD) 1455 .Case("f16c", HasF16C) 1456 .Case("fma", HasFMA) 1457 .Case("fma4", XOPLevel >= FMA4) 1458 .Case("fsgsbase", HasFSGSBASE) 1459 .Case("fxsr", HasFXSR) 1460 .Case("gfni", HasGFNI) 1461 .Case("invpcid", HasINVPCID) 1462 .Case("lwp", HasLWP) 1463 .Case("lzcnt", HasLZCNT) 1464 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1465 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1466 .Case("mmx", MMX3DNowLevel >= MMX) 1467 .Case("movbe", HasMOVBE) 1468 .Case("movdiri", HasMOVDIRI) 1469 .Case("movdir64b", HasMOVDIR64B) 1470 .Case("mwaitx", HasMWAITX) 1471 .Case("pclmul", HasPCLMUL) 1472 .Case("pconfig", HasPCONFIG) 1473 .Case("pku", HasPKU) 1474 .Case("popcnt", HasPOPCNT) 1475 .Case("prefetchwt1", HasPREFETCHWT1) 1476 .Case("prfchw", HasPRFCHW) 1477 .Case("ptwrite", HasPTWRITE) 1478 .Case("rdpid", HasRDPID) 1479 .Case("rdrnd", HasRDRND) 1480 .Case("rdseed", HasRDSEED) 1481 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1482 .Case("rtm", HasRTM) 1483 .Case("sahf", HasLAHFSAHF) 1484 .Case("serialize", HasSERIALIZE) 1485 .Case("sgx", HasSGX) 1486 .Case("sha", HasSHA) 1487 .Case("shstk", HasSHSTK) 1488 .Case("sse", SSELevel >= SSE1) 1489 .Case("sse2", SSELevel >= SSE2) 1490 .Case("sse3", SSELevel >= SSE3) 1491 .Case("ssse3", SSELevel >= SSSE3) 1492 .Case("sse4.1", SSELevel >= SSE41) 1493 .Case("sse4.2", SSELevel >= SSE42) 1494 .Case("sse4a", XOPLevel >= SSE4A) 1495 .Case("tbm", HasTBM) 1496 .Case("tsxldtrk", HasTSXLDTRK) 1497 .Case("vaes", HasVAES) 1498 .Case("vpclmulqdq", HasVPCLMULQDQ) 1499 .Case("wbnoinvd", HasWBNOINVD) 1500 .Case("waitpkg", HasWAITPKG) 1501 .Case("x86", true) 1502 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1503 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1504 .Case("xop", XOPLevel >= XOP) 1505 .Case("xsave", HasXSAVE) 1506 .Case("xsavec", HasXSAVEC) 1507 .Case("xsaves", HasXSAVES) 1508 .Case("xsaveopt", HasXSAVEOPT) 1509 .Default(false); 1510 } 1511 1512 // We can't use a generic validation scheme for the features accepted here 1513 // versus subtarget features accepted in the target attribute because the 1514 // bitfield structure that's initialized in the runtime only supports the 1515 // below currently rather than the full range of subtarget features. (See 1516 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1517 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1518 return llvm::StringSwitch<bool>(FeatureStr) 1519 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1520 #include "llvm/Support/X86TargetParser.def" 1521 .Default(false); 1522 } 1523 1524 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1525 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1526 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1527 #include "llvm/Support/X86TargetParser.def" 1528 ; 1529 // Note, this function should only be used after ensuring the value is 1530 // correct, so it asserts if the value is out of range. 1531 } 1532 1533 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1534 enum class FeatPriority { 1535 #define FEATURE(FEAT) FEAT, 1536 #include "clang/Basic/X86Target.def" 1537 }; 1538 switch (Feat) { 1539 #define FEATURE(FEAT) \ 1540 case llvm::X86::FEAT: \ 1541 return static_cast<unsigned>(FeatPriority::FEAT); 1542 #include "clang/Basic/X86Target.def" 1543 default: 1544 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1545 } 1546 } 1547 1548 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1549 // Valid CPUs have a 'key feature' that compares just better than its key 1550 // feature. 1551 CPUKind Kind = getCPUKind(Name); 1552 if (Kind != CK_Generic) { 1553 switch (Kind) { 1554 default: 1555 llvm_unreachable( 1556 "CPU Type without a key feature used in 'target' attribute"); 1557 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1558 case CK_##ENUM: \ 1559 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1560 #include "clang/Basic/X86Target.def" 1561 } 1562 } 1563 1564 // Now we know we have a feature, so get its priority and shift it a few so 1565 // that we have sufficient room for the CPUs (above). 1566 return getFeaturePriority(getFeature(Name)) << 1; 1567 } 1568 1569 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1570 return llvm::StringSwitch<bool>(Name) 1571 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1572 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1573 #include "clang/Basic/X86Target.def" 1574 .Default(false); 1575 } 1576 1577 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1578 return llvm::StringSwitch<StringRef>(Name) 1579 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1580 #include "clang/Basic/X86Target.def" 1581 .Default(Name); 1582 } 1583 1584 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1585 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1586 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1587 #include "clang/Basic/X86Target.def" 1588 .Default(0); 1589 } 1590 1591 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1592 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1593 StringRef WholeList = 1594 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1595 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1596 #include "clang/Basic/X86Target.def" 1597 .Default(""); 1598 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1599 } 1600 1601 // We can't use a generic validation scheme for the cpus accepted here 1602 // versus subtarget cpus accepted in the target attribute because the 1603 // variables intitialized by the runtime only support the below currently 1604 // rather than the full range of cpus. 1605 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1606 return llvm::StringSwitch<bool>(FeatureStr) 1607 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1608 #define X86_CPU_TYPE_COMPAT_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1609 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1610 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1611 #include "llvm/Support/X86TargetParser.def" 1612 .Default(false); 1613 } 1614 1615 static unsigned matchAsmCCConstraint(const char *&Name) { 1616 auto RV = llvm::StringSwitch<unsigned>(Name) 1617 .Case("@cca", 4) 1618 .Case("@ccae", 5) 1619 .Case("@ccb", 4) 1620 .Case("@ccbe", 5) 1621 .Case("@ccc", 4) 1622 .Case("@cce", 4) 1623 .Case("@ccz", 4) 1624 .Case("@ccg", 4) 1625 .Case("@ccge", 5) 1626 .Case("@ccl", 4) 1627 .Case("@ccle", 5) 1628 .Case("@ccna", 5) 1629 .Case("@ccnae", 6) 1630 .Case("@ccnb", 5) 1631 .Case("@ccnbe", 6) 1632 .Case("@ccnc", 5) 1633 .Case("@ccne", 5) 1634 .Case("@ccnz", 5) 1635 .Case("@ccng", 5) 1636 .Case("@ccnge", 6) 1637 .Case("@ccnl", 5) 1638 .Case("@ccnle", 6) 1639 .Case("@ccno", 5) 1640 .Case("@ccnp", 5) 1641 .Case("@ccns", 5) 1642 .Case("@cco", 4) 1643 .Case("@ccp", 4) 1644 .Case("@ccs", 4) 1645 .Default(0); 1646 return RV; 1647 } 1648 1649 bool X86TargetInfo::validateAsmConstraint( 1650 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1651 switch (*Name) { 1652 default: 1653 return false; 1654 // Constant constraints. 1655 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1656 // instructions. 1657 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1658 // x86_64 instructions. 1659 case 's': 1660 Info.setRequiresImmediate(); 1661 return true; 1662 case 'I': 1663 Info.setRequiresImmediate(0, 31); 1664 return true; 1665 case 'J': 1666 Info.setRequiresImmediate(0, 63); 1667 return true; 1668 case 'K': 1669 Info.setRequiresImmediate(-128, 127); 1670 return true; 1671 case 'L': 1672 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1673 return true; 1674 case 'M': 1675 Info.setRequiresImmediate(0, 3); 1676 return true; 1677 case 'N': 1678 Info.setRequiresImmediate(0, 255); 1679 return true; 1680 case 'O': 1681 Info.setRequiresImmediate(0, 127); 1682 return true; 1683 // Register constraints. 1684 case 'Y': // 'Y' is the first character for several 2-character constraints. 1685 // Shift the pointer to the second character of the constraint. 1686 Name++; 1687 switch (*Name) { 1688 default: 1689 return false; 1690 case 'z': // First SSE register. 1691 case '2': 1692 case 't': // Any SSE register, when SSE2 is enabled. 1693 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1694 case 'm': // Any MMX register, when inter-unit moves enabled. 1695 case 'k': // AVX512 arch mask registers: k1-k7. 1696 Info.setAllowsRegister(); 1697 return true; 1698 } 1699 case 'f': // Any x87 floating point stack register. 1700 // Constraint 'f' cannot be used for output operands. 1701 if (Info.ConstraintStr[0] == '=') 1702 return false; 1703 Info.setAllowsRegister(); 1704 return true; 1705 case 'a': // eax. 1706 case 'b': // ebx. 1707 case 'c': // ecx. 1708 case 'd': // edx. 1709 case 'S': // esi. 1710 case 'D': // edi. 1711 case 'A': // edx:eax. 1712 case 't': // Top of floating point stack. 1713 case 'u': // Second from top of floating point stack. 1714 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1715 case 'y': // Any MMX register. 1716 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1717 case 'x': // Any SSE register. 1718 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1719 // for intermideate k reg operations). 1720 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1721 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1722 case 'l': // "Index" registers: any general register that can be used as an 1723 // index in a base+index memory access. 1724 Info.setAllowsRegister(); 1725 return true; 1726 // Floating point constant constraints. 1727 case 'C': // SSE floating point constant. 1728 case 'G': // x87 floating point constant. 1729 return true; 1730 case '@': 1731 // CC condition changes. 1732 if (auto Len = matchAsmCCConstraint(Name)) { 1733 Name += Len - 1; 1734 Info.setAllowsRegister(); 1735 return true; 1736 } 1737 return false; 1738 } 1739 } 1740 1741 // Below is based on the following information: 1742 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1743 // | Processor Name | Cache Line Size (Bytes) | Source | 1744 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1745 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1746 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1747 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1748 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1749 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1750 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1751 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1752 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1753 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1754 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1755 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1756 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1757 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1758 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1759 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1760 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1761 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1762 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1763 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1764 switch (CPU) { 1765 // i386 1766 case CK_i386: 1767 // i486 1768 case CK_i486: 1769 case CK_WinChipC6: 1770 case CK_WinChip2: 1771 case CK_C3: 1772 // Lakemont 1773 case CK_Lakemont: 1774 return 16; 1775 1776 // i586 1777 case CK_i586: 1778 case CK_Pentium: 1779 case CK_PentiumMMX: 1780 // i686 1781 case CK_PentiumPro: 1782 case CK_i686: 1783 case CK_Pentium2: 1784 case CK_Pentium3: 1785 case CK_PentiumM: 1786 case CK_C3_2: 1787 // K6 1788 case CK_K6: 1789 case CK_K6_2: 1790 case CK_K6_3: 1791 // Geode 1792 case CK_Geode: 1793 return 32; 1794 1795 // Netburst 1796 case CK_Pentium4: 1797 case CK_Prescott: 1798 case CK_Nocona: 1799 // Atom 1800 case CK_Bonnell: 1801 case CK_Silvermont: 1802 case CK_Goldmont: 1803 case CK_GoldmontPlus: 1804 case CK_Tremont: 1805 1806 case CK_Westmere: 1807 case CK_SandyBridge: 1808 case CK_IvyBridge: 1809 case CK_Haswell: 1810 case CK_Broadwell: 1811 case CK_SkylakeClient: 1812 case CK_SkylakeServer: 1813 case CK_Cascadelake: 1814 case CK_Nehalem: 1815 case CK_Cooperlake: 1816 case CK_Cannonlake: 1817 case CK_Tigerlake: 1818 case CK_IcelakeClient: 1819 case CK_IcelakeServer: 1820 case CK_KNL: 1821 case CK_KNM: 1822 // K7 1823 case CK_Athlon: 1824 case CK_AthlonXP: 1825 // K8 1826 case CK_K8: 1827 case CK_K8SSE3: 1828 case CK_AMDFAM10: 1829 // Bobcat 1830 case CK_BTVER1: 1831 case CK_BTVER2: 1832 // Bulldozer 1833 case CK_BDVER1: 1834 case CK_BDVER2: 1835 case CK_BDVER3: 1836 case CK_BDVER4: 1837 // Zen 1838 case CK_ZNVER1: 1839 case CK_ZNVER2: 1840 // Deprecated 1841 case CK_x86_64: 1842 case CK_Yonah: 1843 case CK_Penryn: 1844 case CK_Core2: 1845 return 64; 1846 1847 // The following currently have unknown cache line sizes (but they are probably all 64): 1848 // Core 1849 case CK_Generic: 1850 return None; 1851 } 1852 llvm_unreachable("Unknown CPU kind"); 1853 } 1854 1855 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1856 StringRef Constraint, 1857 unsigned Size) const { 1858 // Strip off constraint modifiers. 1859 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1860 Constraint = Constraint.substr(1); 1861 1862 return validateOperandSize(FeatureMap, Constraint, Size); 1863 } 1864 1865 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1866 StringRef Constraint, 1867 unsigned Size) const { 1868 return validateOperandSize(FeatureMap, Constraint, Size); 1869 } 1870 1871 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1872 StringRef Constraint, 1873 unsigned Size) const { 1874 switch (Constraint[0]) { 1875 default: 1876 break; 1877 case 'k': 1878 // Registers k0-k7 (AVX512) size limit is 64 bit. 1879 case 'y': 1880 return Size <= 64; 1881 case 'f': 1882 case 't': 1883 case 'u': 1884 return Size <= 128; 1885 case 'Y': 1886 // 'Y' is the first character for several 2-character constraints. 1887 switch (Constraint[1]) { 1888 default: 1889 return false; 1890 case 'm': 1891 // 'Ym' is synonymous with 'y'. 1892 case 'k': 1893 return Size <= 64; 1894 case 'z': 1895 // XMM0/YMM/ZMM0 1896 if (FeatureMap.lookup("avx512f")) 1897 // ZMM0 can be used if target supports AVX512F. 1898 return Size <= 512U; 1899 else if (FeatureMap.lookup("avx")) 1900 // YMM0 can be used if target supports AVX. 1901 return Size <= 256U; 1902 else if (FeatureMap.lookup("sse")) 1903 return Size <= 128U; 1904 return false; 1905 case 'i': 1906 case 't': 1907 case '2': 1908 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1909 if (SSELevel < SSE2) 1910 return false; 1911 break; 1912 } 1913 break; 1914 case 'v': 1915 case 'x': 1916 if (FeatureMap.lookup("avx512f")) 1917 // 512-bit zmm registers can be used if target supports AVX512F. 1918 return Size <= 512U; 1919 else if (FeatureMap.lookup("avx")) 1920 // 256-bit ymm registers can be used if target supports AVX. 1921 return Size <= 256U; 1922 return Size <= 128U; 1923 1924 } 1925 1926 return true; 1927 } 1928 1929 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1930 switch (*Constraint) { 1931 case '@': 1932 if (auto Len = matchAsmCCConstraint(Constraint)) { 1933 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1934 Constraint += Len - 1; 1935 return Converted; 1936 } 1937 return std::string(1, *Constraint); 1938 case 'a': 1939 return std::string("{ax}"); 1940 case 'b': 1941 return std::string("{bx}"); 1942 case 'c': 1943 return std::string("{cx}"); 1944 case 'd': 1945 return std::string("{dx}"); 1946 case 'S': 1947 return std::string("{si}"); 1948 case 'D': 1949 return std::string("{di}"); 1950 case 'p': // address 1951 return std::string("im"); 1952 case 't': // top of floating point stack. 1953 return std::string("{st}"); 1954 case 'u': // second from top of floating point stack. 1955 return std::string("{st(1)}"); // second from top of floating point stack. 1956 case 'Y': 1957 switch (Constraint[1]) { 1958 default: 1959 // Break from inner switch and fall through (copy single char), 1960 // continue parsing after copying the current constraint into 1961 // the return string. 1962 break; 1963 case 'k': 1964 case 'm': 1965 case 'i': 1966 case 't': 1967 case 'z': 1968 case '2': 1969 // "^" hints llvm that this is a 2 letter constraint. 1970 // "Constraint++" is used to promote the string iterator 1971 // to the next constraint. 1972 return std::string("^") + std::string(Constraint++, 2); 1973 } 1974 LLVM_FALLTHROUGH; 1975 default: 1976 return std::string(1, *Constraint); 1977 } 1978 } 1979 1980 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1981 // Perform any per-CPU checks necessary to determine if this CPU is 1982 // acceptable. 1983 switch (Kind) { 1984 case CK_Generic: 1985 // No processor selected! 1986 return false; 1987 #define PROC(ENUM, STRING, IS64BIT) \ 1988 case CK_##ENUM: \ 1989 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1990 #include "clang/Basic/X86Target.def" 1991 } 1992 llvm_unreachable("Unhandled CPU kind"); 1993 } 1994 1995 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1996 #define PROC(ENUM, STRING, IS64BIT) \ 1997 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1998 Values.emplace_back(STRING); 1999 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 2000 #define PROC_ALIAS(ENUM, ALIAS) \ 2001 if (checkCPUKind(CK_##ENUM)) \ 2002 Values.emplace_back(ALIAS); 2003 #include "clang/Basic/X86Target.def" 2004 } 2005 2006 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 2007 return llvm::StringSwitch<CPUKind>(CPU) 2008 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 2009 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 2010 #include "clang/Basic/X86Target.def" 2011 .Default(CK_Generic); 2012 } 2013 2014 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 2015 return llvm::makeArrayRef(GCCRegNames); 2016 } 2017 2018 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 2019 return llvm::makeArrayRef(AddlRegNames); 2020 } 2021 2022 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 2023 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 2024 Builtin::FirstTSBuiltin + 1); 2025 } 2026 2027 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 2028 return llvm::makeArrayRef(BuiltinInfoX86, 2029 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 2030 } 2031