1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+kl") { 280 HasKL = true; 281 } else if (Feature == "+widekl") { 282 HasWIDEKL = true; 283 } else if (Feature == "+retpoline-external-thunk") { 284 HasRetpolineExternalThunk = true; 285 } else if (Feature == "+sahf") { 286 HasLAHFSAHF = true; 287 } else if (Feature == "+waitpkg") { 288 HasWAITPKG = true; 289 } else if (Feature == "+movdiri") { 290 HasMOVDIRI = true; 291 } else if (Feature == "+movdir64b") { 292 HasMOVDIR64B = true; 293 } else if (Feature == "+pconfig") { 294 HasPCONFIG = true; 295 } else if (Feature == "+ptwrite") { 296 HasPTWRITE = true; 297 } else if (Feature == "+invpcid") { 298 HasINVPCID = true; 299 } else if (Feature == "+enqcmd") { 300 HasENQCMD = true; 301 } else if (Feature == "+hreset") { 302 HasHRESET = true; 303 } else if (Feature == "+amx-bf16") { 304 HasAMXBF16 = true; 305 } else if (Feature == "+amx-int8") { 306 HasAMXINT8 = true; 307 } else if (Feature == "+amx-tile") { 308 HasAMXTILE = true; 309 } else if (Feature == "+avxvnni") { 310 HasAVXVNNI = true; 311 } else if (Feature == "+serialize") { 312 HasSERIALIZE = true; 313 } else if (Feature == "+tsxldtrk") { 314 HasTSXLDTRK = true; 315 } else if (Feature == "+uintr") { 316 HasUINTR = true; 317 } 318 319 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 320 .Case("+avx512f", AVX512F) 321 .Case("+avx2", AVX2) 322 .Case("+avx", AVX) 323 .Case("+sse4.2", SSE42) 324 .Case("+sse4.1", SSE41) 325 .Case("+ssse3", SSSE3) 326 .Case("+sse3", SSE3) 327 .Case("+sse2", SSE2) 328 .Case("+sse", SSE1) 329 .Default(NoSSE); 330 SSELevel = std::max(SSELevel, Level); 331 332 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 333 .Case("+3dnowa", AMD3DNowAthlon) 334 .Case("+3dnow", AMD3DNow) 335 .Case("+mmx", MMX) 336 .Default(NoMMX3DNow); 337 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 338 339 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 340 .Case("+xop", XOP) 341 .Case("+fma4", FMA4) 342 .Case("+sse4a", SSE4A) 343 .Default(NoXOP); 344 XOPLevel = std::max(XOPLevel, XLevel); 345 } 346 347 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 348 // matches the selected sse level. 349 if ((FPMath == FP_SSE && SSELevel < SSE1) || 350 (FPMath == FP_387 && SSELevel >= SSE1)) { 351 Diags.Report(diag::err_target_unsupported_fpmath) 352 << (FPMath == FP_SSE ? "sse" : "387"); 353 return false; 354 } 355 356 SimdDefaultAlign = 357 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 358 return true; 359 } 360 361 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 362 /// definitions for this particular subtarget. 363 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 364 MacroBuilder &Builder) const { 365 // Inline assembly supports X86 flag outputs. 366 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 367 368 std::string CodeModel = getTargetOpts().CodeModel; 369 if (CodeModel == "default") 370 CodeModel = "small"; 371 Builder.defineMacro("__code_model_" + CodeModel + "__"); 372 373 // Target identification. 374 if (getTriple().getArch() == llvm::Triple::x86_64) { 375 Builder.defineMacro("__amd64__"); 376 Builder.defineMacro("__amd64"); 377 Builder.defineMacro("__x86_64"); 378 Builder.defineMacro("__x86_64__"); 379 if (getTriple().getArchName() == "x86_64h") { 380 Builder.defineMacro("__x86_64h"); 381 Builder.defineMacro("__x86_64h__"); 382 } 383 } else { 384 DefineStd(Builder, "i386", Opts); 385 } 386 387 Builder.defineMacro("__SEG_GS"); 388 Builder.defineMacro("__SEG_FS"); 389 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 390 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 391 392 // Subtarget options. 393 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 394 // truly should be based on -mtune options. 395 using namespace llvm::X86; 396 switch (CPU) { 397 case CK_None: 398 break; 399 case CK_i386: 400 // The rest are coming from the i386 define above. 401 Builder.defineMacro("__tune_i386__"); 402 break; 403 case CK_i486: 404 case CK_WinChipC6: 405 case CK_WinChip2: 406 case CK_C3: 407 defineCPUMacros(Builder, "i486"); 408 break; 409 case CK_PentiumMMX: 410 Builder.defineMacro("__pentium_mmx__"); 411 Builder.defineMacro("__tune_pentium_mmx__"); 412 LLVM_FALLTHROUGH; 413 case CK_i586: 414 case CK_Pentium: 415 defineCPUMacros(Builder, "i586"); 416 defineCPUMacros(Builder, "pentium"); 417 break; 418 case CK_Pentium3: 419 case CK_PentiumM: 420 Builder.defineMacro("__tune_pentium3__"); 421 LLVM_FALLTHROUGH; 422 case CK_Pentium2: 423 case CK_C3_2: 424 Builder.defineMacro("__tune_pentium2__"); 425 LLVM_FALLTHROUGH; 426 case CK_PentiumPro: 427 case CK_i686: 428 defineCPUMacros(Builder, "i686"); 429 defineCPUMacros(Builder, "pentiumpro"); 430 break; 431 case CK_Pentium4: 432 defineCPUMacros(Builder, "pentium4"); 433 break; 434 case CK_Yonah: 435 case CK_Prescott: 436 case CK_Nocona: 437 defineCPUMacros(Builder, "nocona"); 438 break; 439 case CK_Core2: 440 case CK_Penryn: 441 defineCPUMacros(Builder, "core2"); 442 break; 443 case CK_Bonnell: 444 defineCPUMacros(Builder, "atom"); 445 break; 446 case CK_Silvermont: 447 defineCPUMacros(Builder, "slm"); 448 break; 449 case CK_Goldmont: 450 defineCPUMacros(Builder, "goldmont"); 451 break; 452 case CK_GoldmontPlus: 453 defineCPUMacros(Builder, "goldmont_plus"); 454 break; 455 case CK_Tremont: 456 defineCPUMacros(Builder, "tremont"); 457 break; 458 case CK_Nehalem: 459 case CK_Westmere: 460 case CK_SandyBridge: 461 case CK_IvyBridge: 462 case CK_Haswell: 463 case CK_Broadwell: 464 case CK_SkylakeClient: 465 case CK_SkylakeServer: 466 case CK_Cascadelake: 467 case CK_Cooperlake: 468 case CK_Cannonlake: 469 case CK_IcelakeClient: 470 case CK_Rocketlake: 471 case CK_IcelakeServer: 472 case CK_Tigerlake: 473 case CK_SapphireRapids: 474 case CK_Alderlake: 475 // FIXME: Historically, we defined this legacy name, it would be nice to 476 // remove it at some point. We've never exposed fine-grained names for 477 // recent primary x86 CPUs, and we should keep it that way. 478 defineCPUMacros(Builder, "corei7"); 479 break; 480 case CK_KNL: 481 defineCPUMacros(Builder, "knl"); 482 break; 483 case CK_KNM: 484 break; 485 case CK_Lakemont: 486 defineCPUMacros(Builder, "i586", /*Tuning*/false); 487 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 488 Builder.defineMacro("__tune_lakemont__"); 489 break; 490 case CK_K6_2: 491 Builder.defineMacro("__k6_2__"); 492 Builder.defineMacro("__tune_k6_2__"); 493 LLVM_FALLTHROUGH; 494 case CK_K6_3: 495 if (CPU != CK_K6_2) { // In case of fallthrough 496 // FIXME: GCC may be enabling these in cases where some other k6 497 // architecture is specified but -m3dnow is explicitly provided. The 498 // exact semantics need to be determined and emulated here. 499 Builder.defineMacro("__k6_3__"); 500 Builder.defineMacro("__tune_k6_3__"); 501 } 502 LLVM_FALLTHROUGH; 503 case CK_K6: 504 defineCPUMacros(Builder, "k6"); 505 break; 506 case CK_Athlon: 507 case CK_AthlonXP: 508 defineCPUMacros(Builder, "athlon"); 509 if (SSELevel != NoSSE) { 510 Builder.defineMacro("__athlon_sse__"); 511 Builder.defineMacro("__tune_athlon_sse__"); 512 } 513 break; 514 case CK_K8: 515 case CK_K8SSE3: 516 case CK_x86_64: 517 defineCPUMacros(Builder, "k8"); 518 break; 519 case CK_x86_64_v2: 520 case CK_x86_64_v3: 521 case CK_x86_64_v4: 522 break; 523 case CK_AMDFAM10: 524 defineCPUMacros(Builder, "amdfam10"); 525 break; 526 case CK_BTVER1: 527 defineCPUMacros(Builder, "btver1"); 528 break; 529 case CK_BTVER2: 530 defineCPUMacros(Builder, "btver2"); 531 break; 532 case CK_BDVER1: 533 defineCPUMacros(Builder, "bdver1"); 534 break; 535 case CK_BDVER2: 536 defineCPUMacros(Builder, "bdver2"); 537 break; 538 case CK_BDVER3: 539 defineCPUMacros(Builder, "bdver3"); 540 break; 541 case CK_BDVER4: 542 defineCPUMacros(Builder, "bdver4"); 543 break; 544 case CK_ZNVER1: 545 defineCPUMacros(Builder, "znver1"); 546 break; 547 case CK_ZNVER2: 548 defineCPUMacros(Builder, "znver2"); 549 break; 550 case CK_ZNVER3: 551 defineCPUMacros(Builder, "znver3"); 552 break; 553 case CK_Geode: 554 defineCPUMacros(Builder, "geode"); 555 break; 556 } 557 558 // Target properties. 559 Builder.defineMacro("__REGISTER_PREFIX__", ""); 560 561 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 562 // functions in glibc header files that use FP Stack inline asm which the 563 // backend can't deal with (PR879). 564 Builder.defineMacro("__NO_MATH_INLINES"); 565 566 if (HasAES) 567 Builder.defineMacro("__AES__"); 568 569 if (HasVAES) 570 Builder.defineMacro("__VAES__"); 571 572 if (HasPCLMUL) 573 Builder.defineMacro("__PCLMUL__"); 574 575 if (HasVPCLMULQDQ) 576 Builder.defineMacro("__VPCLMULQDQ__"); 577 578 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 579 // the feature flag only applies to 64-bit mode. 580 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 581 Builder.defineMacro("__LAHF_SAHF__"); 582 583 if (HasLZCNT) 584 Builder.defineMacro("__LZCNT__"); 585 586 if (HasRDRND) 587 Builder.defineMacro("__RDRND__"); 588 589 if (HasFSGSBASE) 590 Builder.defineMacro("__FSGSBASE__"); 591 592 if (HasBMI) 593 Builder.defineMacro("__BMI__"); 594 595 if (HasBMI2) 596 Builder.defineMacro("__BMI2__"); 597 598 if (HasPOPCNT) 599 Builder.defineMacro("__POPCNT__"); 600 601 if (HasRTM) 602 Builder.defineMacro("__RTM__"); 603 604 if (HasPRFCHW) 605 Builder.defineMacro("__PRFCHW__"); 606 607 if (HasRDSEED) 608 Builder.defineMacro("__RDSEED__"); 609 610 if (HasADX) 611 Builder.defineMacro("__ADX__"); 612 613 if (HasTBM) 614 Builder.defineMacro("__TBM__"); 615 616 if (HasLWP) 617 Builder.defineMacro("__LWP__"); 618 619 if (HasMWAITX) 620 Builder.defineMacro("__MWAITX__"); 621 622 if (HasMOVBE) 623 Builder.defineMacro("__MOVBE__"); 624 625 switch (XOPLevel) { 626 case XOP: 627 Builder.defineMacro("__XOP__"); 628 LLVM_FALLTHROUGH; 629 case FMA4: 630 Builder.defineMacro("__FMA4__"); 631 LLVM_FALLTHROUGH; 632 case SSE4A: 633 Builder.defineMacro("__SSE4A__"); 634 LLVM_FALLTHROUGH; 635 case NoXOP: 636 break; 637 } 638 639 if (HasFMA) 640 Builder.defineMacro("__FMA__"); 641 642 if (HasF16C) 643 Builder.defineMacro("__F16C__"); 644 645 if (HasGFNI) 646 Builder.defineMacro("__GFNI__"); 647 648 if (HasAVX512CD) 649 Builder.defineMacro("__AVX512CD__"); 650 if (HasAVX512VPOPCNTDQ) 651 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 652 if (HasAVX512VNNI) 653 Builder.defineMacro("__AVX512VNNI__"); 654 if (HasAVX512BF16) 655 Builder.defineMacro("__AVX512BF16__"); 656 if (HasAVX512ER) 657 Builder.defineMacro("__AVX512ER__"); 658 if (HasAVX512PF) 659 Builder.defineMacro("__AVX512PF__"); 660 if (HasAVX512DQ) 661 Builder.defineMacro("__AVX512DQ__"); 662 if (HasAVX512BITALG) 663 Builder.defineMacro("__AVX512BITALG__"); 664 if (HasAVX512BW) 665 Builder.defineMacro("__AVX512BW__"); 666 if (HasAVX512VL) 667 Builder.defineMacro("__AVX512VL__"); 668 if (HasAVX512VBMI) 669 Builder.defineMacro("__AVX512VBMI__"); 670 if (HasAVX512VBMI2) 671 Builder.defineMacro("__AVX512VBMI2__"); 672 if (HasAVX512IFMA) 673 Builder.defineMacro("__AVX512IFMA__"); 674 if (HasAVX512VP2INTERSECT) 675 Builder.defineMacro("__AVX512VP2INTERSECT__"); 676 if (HasSHA) 677 Builder.defineMacro("__SHA__"); 678 679 if (HasFXSR) 680 Builder.defineMacro("__FXSR__"); 681 if (HasXSAVE) 682 Builder.defineMacro("__XSAVE__"); 683 if (HasXSAVEOPT) 684 Builder.defineMacro("__XSAVEOPT__"); 685 if (HasXSAVEC) 686 Builder.defineMacro("__XSAVEC__"); 687 if (HasXSAVES) 688 Builder.defineMacro("__XSAVES__"); 689 if (HasPKU) 690 Builder.defineMacro("__PKU__"); 691 if (HasCLFLUSHOPT) 692 Builder.defineMacro("__CLFLUSHOPT__"); 693 if (HasCLWB) 694 Builder.defineMacro("__CLWB__"); 695 if (HasWBNOINVD) 696 Builder.defineMacro("__WBNOINVD__"); 697 if (HasSHSTK) 698 Builder.defineMacro("__SHSTK__"); 699 if (HasSGX) 700 Builder.defineMacro("__SGX__"); 701 if (HasPREFETCHWT1) 702 Builder.defineMacro("__PREFETCHWT1__"); 703 if (HasCLZERO) 704 Builder.defineMacro("__CLZERO__"); 705 if (HasKL) 706 Builder.defineMacro("__KL__"); 707 if (HasWIDEKL) 708 Builder.defineMacro("__WIDEKL__"); 709 if (HasRDPID) 710 Builder.defineMacro("__RDPID__"); 711 if (HasCLDEMOTE) 712 Builder.defineMacro("__CLDEMOTE__"); 713 if (HasWAITPKG) 714 Builder.defineMacro("__WAITPKG__"); 715 if (HasMOVDIRI) 716 Builder.defineMacro("__MOVDIRI__"); 717 if (HasMOVDIR64B) 718 Builder.defineMacro("__MOVDIR64B__"); 719 if (HasPCONFIG) 720 Builder.defineMacro("__PCONFIG__"); 721 if (HasPTWRITE) 722 Builder.defineMacro("__PTWRITE__"); 723 if (HasINVPCID) 724 Builder.defineMacro("__INVPCID__"); 725 if (HasENQCMD) 726 Builder.defineMacro("__ENQCMD__"); 727 if (HasHRESET) 728 Builder.defineMacro("__HRESET__"); 729 if (HasAMXTILE) 730 Builder.defineMacro("__AMXTILE__"); 731 if (HasAMXINT8) 732 Builder.defineMacro("__AMXINT8__"); 733 if (HasAMXBF16) 734 Builder.defineMacro("__AMXBF16__"); 735 if (HasAVXVNNI) 736 Builder.defineMacro("__AVXVNNI__"); 737 if (HasSERIALIZE) 738 Builder.defineMacro("__SERIALIZE__"); 739 if (HasTSXLDTRK) 740 Builder.defineMacro("__TSXLDTRK__"); 741 if (HasUINTR) 742 Builder.defineMacro("__UINTR__"); 743 744 // Each case falls through to the previous one here. 745 switch (SSELevel) { 746 case AVX512F: 747 Builder.defineMacro("__AVX512F__"); 748 LLVM_FALLTHROUGH; 749 case AVX2: 750 Builder.defineMacro("__AVX2__"); 751 LLVM_FALLTHROUGH; 752 case AVX: 753 Builder.defineMacro("__AVX__"); 754 LLVM_FALLTHROUGH; 755 case SSE42: 756 Builder.defineMacro("__SSE4_2__"); 757 LLVM_FALLTHROUGH; 758 case SSE41: 759 Builder.defineMacro("__SSE4_1__"); 760 LLVM_FALLTHROUGH; 761 case SSSE3: 762 Builder.defineMacro("__SSSE3__"); 763 LLVM_FALLTHROUGH; 764 case SSE3: 765 Builder.defineMacro("__SSE3__"); 766 LLVM_FALLTHROUGH; 767 case SSE2: 768 Builder.defineMacro("__SSE2__"); 769 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 770 LLVM_FALLTHROUGH; 771 case SSE1: 772 Builder.defineMacro("__SSE__"); 773 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 774 LLVM_FALLTHROUGH; 775 case NoSSE: 776 break; 777 } 778 779 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 780 switch (SSELevel) { 781 case AVX512F: 782 case AVX2: 783 case AVX: 784 case SSE42: 785 case SSE41: 786 case SSSE3: 787 case SSE3: 788 case SSE2: 789 Builder.defineMacro("_M_IX86_FP", Twine(2)); 790 break; 791 case SSE1: 792 Builder.defineMacro("_M_IX86_FP", Twine(1)); 793 break; 794 default: 795 Builder.defineMacro("_M_IX86_FP", Twine(0)); 796 break; 797 } 798 } 799 800 // Each case falls through to the previous one here. 801 switch (MMX3DNowLevel) { 802 case AMD3DNowAthlon: 803 Builder.defineMacro("__3dNOW_A__"); 804 LLVM_FALLTHROUGH; 805 case AMD3DNow: 806 Builder.defineMacro("__3dNOW__"); 807 LLVM_FALLTHROUGH; 808 case MMX: 809 Builder.defineMacro("__MMX__"); 810 LLVM_FALLTHROUGH; 811 case NoMMX3DNow: 812 break; 813 } 814 815 if (CPU >= CK_i486 || CPU == CK_None) { 816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 817 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 818 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 819 } 820 if (HasCX8) 821 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 822 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 823 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 824 825 if (HasFloat128) 826 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 827 } 828 829 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 830 return llvm::StringSwitch<bool>(Name) 831 .Case("3dnow", true) 832 .Case("3dnowa", true) 833 .Case("adx", true) 834 .Case("aes", true) 835 .Case("amx-bf16", true) 836 .Case("amx-int8", true) 837 .Case("amx-tile", true) 838 .Case("avx", true) 839 .Case("avx2", true) 840 .Case("avx512f", true) 841 .Case("avx512cd", true) 842 .Case("avx512vpopcntdq", true) 843 .Case("avx512vnni", true) 844 .Case("avx512bf16", true) 845 .Case("avx512er", true) 846 .Case("avx512pf", true) 847 .Case("avx512dq", true) 848 .Case("avx512bitalg", true) 849 .Case("avx512bw", true) 850 .Case("avx512vl", true) 851 .Case("avx512vbmi", true) 852 .Case("avx512vbmi2", true) 853 .Case("avx512ifma", true) 854 .Case("avx512vp2intersect", true) 855 .Case("avxvnni", true) 856 .Case("bmi", true) 857 .Case("bmi2", true) 858 .Case("cldemote", true) 859 .Case("clflushopt", true) 860 .Case("clwb", true) 861 .Case("clzero", true) 862 .Case("cx16", true) 863 .Case("enqcmd", true) 864 .Case("f16c", true) 865 .Case("fma", true) 866 .Case("fma4", true) 867 .Case("fsgsbase", true) 868 .Case("fxsr", true) 869 .Case("gfni", true) 870 .Case("hreset", true) 871 .Case("invpcid", true) 872 .Case("kl", true) 873 .Case("widekl", true) 874 .Case("lwp", true) 875 .Case("lzcnt", true) 876 .Case("mmx", true) 877 .Case("movbe", true) 878 .Case("movdiri", true) 879 .Case("movdir64b", true) 880 .Case("mwaitx", true) 881 .Case("pclmul", true) 882 .Case("pconfig", true) 883 .Case("pku", true) 884 .Case("popcnt", true) 885 .Case("prefetchwt1", true) 886 .Case("prfchw", true) 887 .Case("ptwrite", true) 888 .Case("rdpid", true) 889 .Case("rdrnd", true) 890 .Case("rdseed", true) 891 .Case("rtm", true) 892 .Case("sahf", true) 893 .Case("serialize", true) 894 .Case("sgx", true) 895 .Case("sha", true) 896 .Case("shstk", true) 897 .Case("sse", true) 898 .Case("sse2", true) 899 .Case("sse3", true) 900 .Case("ssse3", true) 901 .Case("sse4", true) 902 .Case("sse4.1", true) 903 .Case("sse4.2", true) 904 .Case("sse4a", true) 905 .Case("tbm", true) 906 .Case("tsxldtrk", true) 907 .Case("uintr", true) 908 .Case("vaes", true) 909 .Case("vpclmulqdq", true) 910 .Case("wbnoinvd", true) 911 .Case("waitpkg", true) 912 .Case("x87", true) 913 .Case("xop", true) 914 .Case("xsave", true) 915 .Case("xsavec", true) 916 .Case("xsaves", true) 917 .Case("xsaveopt", true) 918 .Default(false); 919 } 920 921 bool X86TargetInfo::hasFeature(StringRef Feature) const { 922 return llvm::StringSwitch<bool>(Feature) 923 .Case("adx", HasADX) 924 .Case("aes", HasAES) 925 .Case("amx-bf16", HasAMXBF16) 926 .Case("amx-int8", HasAMXINT8) 927 .Case("amx-tile", HasAMXTILE) 928 .Case("avxvnni", HasAVXVNNI) 929 .Case("avx", SSELevel >= AVX) 930 .Case("avx2", SSELevel >= AVX2) 931 .Case("avx512f", SSELevel >= AVX512F) 932 .Case("avx512cd", HasAVX512CD) 933 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 934 .Case("avx512vnni", HasAVX512VNNI) 935 .Case("avx512bf16", HasAVX512BF16) 936 .Case("avx512er", HasAVX512ER) 937 .Case("avx512pf", HasAVX512PF) 938 .Case("avx512dq", HasAVX512DQ) 939 .Case("avx512bitalg", HasAVX512BITALG) 940 .Case("avx512bw", HasAVX512BW) 941 .Case("avx512vl", HasAVX512VL) 942 .Case("avx512vbmi", HasAVX512VBMI) 943 .Case("avx512vbmi2", HasAVX512VBMI2) 944 .Case("avx512ifma", HasAVX512IFMA) 945 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 946 .Case("bmi", HasBMI) 947 .Case("bmi2", HasBMI2) 948 .Case("cldemote", HasCLDEMOTE) 949 .Case("clflushopt", HasCLFLUSHOPT) 950 .Case("clwb", HasCLWB) 951 .Case("clzero", HasCLZERO) 952 .Case("cx8", HasCX8) 953 .Case("cx16", HasCX16) 954 .Case("enqcmd", HasENQCMD) 955 .Case("f16c", HasF16C) 956 .Case("fma", HasFMA) 957 .Case("fma4", XOPLevel >= FMA4) 958 .Case("fsgsbase", HasFSGSBASE) 959 .Case("fxsr", HasFXSR) 960 .Case("gfni", HasGFNI) 961 .Case("hreset", HasHRESET) 962 .Case("invpcid", HasINVPCID) 963 .Case("kl", HasKL) 964 .Case("widekl", HasWIDEKL) 965 .Case("lwp", HasLWP) 966 .Case("lzcnt", HasLZCNT) 967 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 968 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 969 .Case("mmx", MMX3DNowLevel >= MMX) 970 .Case("movbe", HasMOVBE) 971 .Case("movdiri", HasMOVDIRI) 972 .Case("movdir64b", HasMOVDIR64B) 973 .Case("mwaitx", HasMWAITX) 974 .Case("pclmul", HasPCLMUL) 975 .Case("pconfig", HasPCONFIG) 976 .Case("pku", HasPKU) 977 .Case("popcnt", HasPOPCNT) 978 .Case("prefetchwt1", HasPREFETCHWT1) 979 .Case("prfchw", HasPRFCHW) 980 .Case("ptwrite", HasPTWRITE) 981 .Case("rdpid", HasRDPID) 982 .Case("rdrnd", HasRDRND) 983 .Case("rdseed", HasRDSEED) 984 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 985 .Case("rtm", HasRTM) 986 .Case("sahf", HasLAHFSAHF) 987 .Case("serialize", HasSERIALIZE) 988 .Case("sgx", HasSGX) 989 .Case("sha", HasSHA) 990 .Case("shstk", HasSHSTK) 991 .Case("sse", SSELevel >= SSE1) 992 .Case("sse2", SSELevel >= SSE2) 993 .Case("sse3", SSELevel >= SSE3) 994 .Case("ssse3", SSELevel >= SSSE3) 995 .Case("sse4.1", SSELevel >= SSE41) 996 .Case("sse4.2", SSELevel >= SSE42) 997 .Case("sse4a", XOPLevel >= SSE4A) 998 .Case("tbm", HasTBM) 999 .Case("tsxldtrk", HasTSXLDTRK) 1000 .Case("uintr", HasUINTR) 1001 .Case("vaes", HasVAES) 1002 .Case("vpclmulqdq", HasVPCLMULQDQ) 1003 .Case("wbnoinvd", HasWBNOINVD) 1004 .Case("waitpkg", HasWAITPKG) 1005 .Case("x86", true) 1006 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1007 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1008 .Case("xop", XOPLevel >= XOP) 1009 .Case("xsave", HasXSAVE) 1010 .Case("xsavec", HasXSAVEC) 1011 .Case("xsaves", HasXSAVES) 1012 .Case("xsaveopt", HasXSAVEOPT) 1013 .Default(false); 1014 } 1015 1016 // We can't use a generic validation scheme for the features accepted here 1017 // versus subtarget features accepted in the target attribute because the 1018 // bitfield structure that's initialized in the runtime only supports the 1019 // below currently rather than the full range of subtarget features. (See 1020 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1021 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1022 return llvm::StringSwitch<bool>(FeatureStr) 1023 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 1024 #include "llvm/Support/X86TargetParser.def" 1025 .Default(false); 1026 } 1027 1028 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1029 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1030 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 1031 #include "llvm/Support/X86TargetParser.def" 1032 ; 1033 // Note, this function should only be used after ensuring the value is 1034 // correct, so it asserts if the value is out of range. 1035 } 1036 1037 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1038 enum class FeatPriority { 1039 #define FEATURE(FEAT) FEAT, 1040 #include "clang/Basic/X86Target.def" 1041 }; 1042 switch (Feat) { 1043 #define FEATURE(FEAT) \ 1044 case llvm::X86::FEAT: \ 1045 return static_cast<unsigned>(FeatPriority::FEAT); 1046 #include "clang/Basic/X86Target.def" 1047 default: 1048 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1049 } 1050 } 1051 1052 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1053 // Valid CPUs have a 'key feature' that compares just better than its key 1054 // feature. 1055 using namespace llvm::X86; 1056 CPUKind Kind = parseArchX86(Name); 1057 if (Kind != CK_None) { 1058 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1059 return (getFeaturePriority(KeyFeature) << 1) + 1; 1060 } 1061 1062 // Now we know we have a feature, so get its priority and shift it a few so 1063 // that we have sufficient room for the CPUs (above). 1064 return getFeaturePriority(getFeature(Name)) << 1; 1065 } 1066 1067 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1068 return llvm::StringSwitch<bool>(Name) 1069 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1070 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1071 #include "clang/Basic/X86Target.def" 1072 .Default(false); 1073 } 1074 1075 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1076 return llvm::StringSwitch<StringRef>(Name) 1077 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1078 #include "clang/Basic/X86Target.def" 1079 .Default(Name); 1080 } 1081 1082 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1083 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1084 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1085 #include "clang/Basic/X86Target.def" 1086 .Default(0); 1087 } 1088 1089 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1090 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1091 StringRef WholeList = 1092 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1093 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1094 #include "clang/Basic/X86Target.def" 1095 .Default(""); 1096 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1097 } 1098 1099 // We can't use a generic validation scheme for the cpus accepted here 1100 // versus subtarget cpus accepted in the target attribute because the 1101 // variables intitialized by the runtime only support the below currently 1102 // rather than the full range of cpus. 1103 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1104 return llvm::StringSwitch<bool>(FeatureStr) 1105 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1106 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1107 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1108 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1109 #include "llvm/Support/X86TargetParser.def" 1110 .Default(false); 1111 } 1112 1113 static unsigned matchAsmCCConstraint(const char *&Name) { 1114 auto RV = llvm::StringSwitch<unsigned>(Name) 1115 .Case("@cca", 4) 1116 .Case("@ccae", 5) 1117 .Case("@ccb", 4) 1118 .Case("@ccbe", 5) 1119 .Case("@ccc", 4) 1120 .Case("@cce", 4) 1121 .Case("@ccz", 4) 1122 .Case("@ccg", 4) 1123 .Case("@ccge", 5) 1124 .Case("@ccl", 4) 1125 .Case("@ccle", 5) 1126 .Case("@ccna", 5) 1127 .Case("@ccnae", 6) 1128 .Case("@ccnb", 5) 1129 .Case("@ccnbe", 6) 1130 .Case("@ccnc", 5) 1131 .Case("@ccne", 5) 1132 .Case("@ccnz", 5) 1133 .Case("@ccng", 5) 1134 .Case("@ccnge", 6) 1135 .Case("@ccnl", 5) 1136 .Case("@ccnle", 6) 1137 .Case("@ccno", 5) 1138 .Case("@ccnp", 5) 1139 .Case("@ccns", 5) 1140 .Case("@cco", 4) 1141 .Case("@ccp", 4) 1142 .Case("@ccs", 4) 1143 .Default(0); 1144 return RV; 1145 } 1146 1147 bool X86TargetInfo::validateAsmConstraint( 1148 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1149 switch (*Name) { 1150 default: 1151 return false; 1152 // Constant constraints. 1153 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1154 // instructions. 1155 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1156 // x86_64 instructions. 1157 case 's': 1158 Info.setRequiresImmediate(); 1159 return true; 1160 case 'I': 1161 Info.setRequiresImmediate(0, 31); 1162 return true; 1163 case 'J': 1164 Info.setRequiresImmediate(0, 63); 1165 return true; 1166 case 'K': 1167 Info.setRequiresImmediate(-128, 127); 1168 return true; 1169 case 'L': 1170 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1171 return true; 1172 case 'M': 1173 Info.setRequiresImmediate(0, 3); 1174 return true; 1175 case 'N': 1176 Info.setRequiresImmediate(0, 255); 1177 return true; 1178 case 'O': 1179 Info.setRequiresImmediate(0, 127); 1180 return true; 1181 // Register constraints. 1182 case 'Y': // 'Y' is the first character for several 2-character constraints. 1183 // Shift the pointer to the second character of the constraint. 1184 Name++; 1185 switch (*Name) { 1186 default: 1187 return false; 1188 case 'z': // First SSE register. 1189 case '2': 1190 case 't': // Any SSE register, when SSE2 is enabled. 1191 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1192 case 'm': // Any MMX register, when inter-unit moves enabled. 1193 case 'k': // AVX512 arch mask registers: k1-k7. 1194 Info.setAllowsRegister(); 1195 return true; 1196 } 1197 case 'f': // Any x87 floating point stack register. 1198 // Constraint 'f' cannot be used for output operands. 1199 if (Info.ConstraintStr[0] == '=') 1200 return false; 1201 Info.setAllowsRegister(); 1202 return true; 1203 case 'a': // eax. 1204 case 'b': // ebx. 1205 case 'c': // ecx. 1206 case 'd': // edx. 1207 case 'S': // esi. 1208 case 'D': // edi. 1209 case 'A': // edx:eax. 1210 case 't': // Top of floating point stack. 1211 case 'u': // Second from top of floating point stack. 1212 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1213 case 'y': // Any MMX register. 1214 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1215 case 'x': // Any SSE register. 1216 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1217 // for intermideate k reg operations). 1218 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1219 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1220 case 'l': // "Index" registers: any general register that can be used as an 1221 // index in a base+index memory access. 1222 Info.setAllowsRegister(); 1223 return true; 1224 // Floating point constant constraints. 1225 case 'C': // SSE floating point constant. 1226 case 'G': // x87 floating point constant. 1227 return true; 1228 case '@': 1229 // CC condition changes. 1230 if (auto Len = matchAsmCCConstraint(Name)) { 1231 Name += Len - 1; 1232 Info.setAllowsRegister(); 1233 return true; 1234 } 1235 return false; 1236 } 1237 } 1238 1239 // Below is based on the following information: 1240 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1241 // | Processor Name | Cache Line Size (Bytes) | Source | 1242 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1243 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1244 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1245 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1246 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1247 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1248 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1249 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1250 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1251 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1252 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1253 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1254 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1255 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1256 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1257 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1258 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1259 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1260 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1261 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1262 using namespace llvm::X86; 1263 switch (CPU) { 1264 // i386 1265 case CK_i386: 1266 // i486 1267 case CK_i486: 1268 case CK_WinChipC6: 1269 case CK_WinChip2: 1270 case CK_C3: 1271 // Lakemont 1272 case CK_Lakemont: 1273 return 16; 1274 1275 // i586 1276 case CK_i586: 1277 case CK_Pentium: 1278 case CK_PentiumMMX: 1279 // i686 1280 case CK_PentiumPro: 1281 case CK_i686: 1282 case CK_Pentium2: 1283 case CK_Pentium3: 1284 case CK_PentiumM: 1285 case CK_C3_2: 1286 // K6 1287 case CK_K6: 1288 case CK_K6_2: 1289 case CK_K6_3: 1290 // Geode 1291 case CK_Geode: 1292 return 32; 1293 1294 // Netburst 1295 case CK_Pentium4: 1296 case CK_Prescott: 1297 case CK_Nocona: 1298 // Atom 1299 case CK_Bonnell: 1300 case CK_Silvermont: 1301 case CK_Goldmont: 1302 case CK_GoldmontPlus: 1303 case CK_Tremont: 1304 1305 case CK_Westmere: 1306 case CK_SandyBridge: 1307 case CK_IvyBridge: 1308 case CK_Haswell: 1309 case CK_Broadwell: 1310 case CK_SkylakeClient: 1311 case CK_SkylakeServer: 1312 case CK_Cascadelake: 1313 case CK_Nehalem: 1314 case CK_Cooperlake: 1315 case CK_Cannonlake: 1316 case CK_Tigerlake: 1317 case CK_SapphireRapids: 1318 case CK_IcelakeClient: 1319 case CK_Rocketlake: 1320 case CK_IcelakeServer: 1321 case CK_Alderlake: 1322 case CK_KNL: 1323 case CK_KNM: 1324 // K7 1325 case CK_Athlon: 1326 case CK_AthlonXP: 1327 // K8 1328 case CK_K8: 1329 case CK_K8SSE3: 1330 case CK_AMDFAM10: 1331 // Bobcat 1332 case CK_BTVER1: 1333 case CK_BTVER2: 1334 // Bulldozer 1335 case CK_BDVER1: 1336 case CK_BDVER2: 1337 case CK_BDVER3: 1338 case CK_BDVER4: 1339 // Zen 1340 case CK_ZNVER1: 1341 case CK_ZNVER2: 1342 case CK_ZNVER3: 1343 // Deprecated 1344 case CK_x86_64: 1345 case CK_x86_64_v2: 1346 case CK_x86_64_v3: 1347 case CK_x86_64_v4: 1348 case CK_Yonah: 1349 case CK_Penryn: 1350 case CK_Core2: 1351 return 64; 1352 1353 // The following currently have unknown cache line sizes (but they are probably all 64): 1354 // Core 1355 case CK_None: 1356 return None; 1357 } 1358 llvm_unreachable("Unknown CPU kind"); 1359 } 1360 1361 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1362 StringRef Constraint, 1363 unsigned Size) const { 1364 // Strip off constraint modifiers. 1365 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1366 Constraint = Constraint.substr(1); 1367 1368 return validateOperandSize(FeatureMap, Constraint, Size); 1369 } 1370 1371 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1372 StringRef Constraint, 1373 unsigned Size) const { 1374 return validateOperandSize(FeatureMap, Constraint, Size); 1375 } 1376 1377 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1378 StringRef Constraint, 1379 unsigned Size) const { 1380 switch (Constraint[0]) { 1381 default: 1382 break; 1383 case 'k': 1384 // Registers k0-k7 (AVX512) size limit is 64 bit. 1385 case 'y': 1386 return Size <= 64; 1387 case 'f': 1388 case 't': 1389 case 'u': 1390 return Size <= 128; 1391 case 'Y': 1392 // 'Y' is the first character for several 2-character constraints. 1393 switch (Constraint[1]) { 1394 default: 1395 return false; 1396 case 'm': 1397 // 'Ym' is synonymous with 'y'. 1398 case 'k': 1399 return Size <= 64; 1400 case 'z': 1401 // XMM0/YMM/ZMM0 1402 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1403 // ZMM0 can be used if target supports AVX512F. 1404 return Size <= 512U; 1405 else if (hasFeatureEnabled(FeatureMap, "avx")) 1406 // YMM0 can be used if target supports AVX. 1407 return Size <= 256U; 1408 else if (hasFeatureEnabled(FeatureMap, "sse")) 1409 return Size <= 128U; 1410 return false; 1411 case 'i': 1412 case 't': 1413 case '2': 1414 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1415 if (SSELevel < SSE2) 1416 return false; 1417 break; 1418 } 1419 break; 1420 case 'v': 1421 case 'x': 1422 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1423 // 512-bit zmm registers can be used if target supports AVX512F. 1424 return Size <= 512U; 1425 else if (hasFeatureEnabled(FeatureMap, "avx")) 1426 // 256-bit ymm registers can be used if target supports AVX. 1427 return Size <= 256U; 1428 return Size <= 128U; 1429 1430 } 1431 1432 return true; 1433 } 1434 1435 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1436 switch (*Constraint) { 1437 case '@': 1438 if (auto Len = matchAsmCCConstraint(Constraint)) { 1439 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1440 Constraint += Len - 1; 1441 return Converted; 1442 } 1443 return std::string(1, *Constraint); 1444 case 'a': 1445 return std::string("{ax}"); 1446 case 'b': 1447 return std::string("{bx}"); 1448 case 'c': 1449 return std::string("{cx}"); 1450 case 'd': 1451 return std::string("{dx}"); 1452 case 'S': 1453 return std::string("{si}"); 1454 case 'D': 1455 return std::string("{di}"); 1456 case 'p': // address 1457 return std::string("im"); 1458 case 't': // top of floating point stack. 1459 return std::string("{st}"); 1460 case 'u': // second from top of floating point stack. 1461 return std::string("{st(1)}"); // second from top of floating point stack. 1462 case 'Y': 1463 switch (Constraint[1]) { 1464 default: 1465 // Break from inner switch and fall through (copy single char), 1466 // continue parsing after copying the current constraint into 1467 // the return string. 1468 break; 1469 case 'k': 1470 case 'm': 1471 case 'i': 1472 case 't': 1473 case 'z': 1474 case '2': 1475 // "^" hints llvm that this is a 2 letter constraint. 1476 // "Constraint++" is used to promote the string iterator 1477 // to the next constraint. 1478 return std::string("^") + std::string(Constraint++, 2); 1479 } 1480 LLVM_FALLTHROUGH; 1481 default: 1482 return std::string(1, *Constraint); 1483 } 1484 } 1485 1486 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1487 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1488 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1489 } 1490 1491 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1492 llvm::X86::fillValidTuneCPUList(Values); 1493 } 1494 1495 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1496 return llvm::makeArrayRef(GCCRegNames); 1497 } 1498 1499 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1500 return llvm::makeArrayRef(AddlRegNames); 1501 } 1502 1503 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1504 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1505 Builtin::FirstTSBuiltin + 1); 1506 } 1507 1508 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1509 return llvm::makeArrayRef(BuiltinInfoX86, 1510 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1511 } 1512