1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabledImpl(Features, "sse2", true); 112 113 const CPUKind Kind = getCPUKind(CPU); 114 115 // Enable X87 for all X86 processors but Lakemont. 116 if (Kind != CK_Lakemont) 117 setFeatureEnabledImpl(Features, "x87", true); 118 119 switch (Kind) { 120 case CK_Generic: 121 case CK_i386: 122 case CK_i486: 123 case CK_i586: 124 case CK_Pentium: 125 case CK_PentiumPro: 126 case CK_Lakemont: 127 break; 128 129 case CK_PentiumMMX: 130 case CK_Pentium2: 131 case CK_K6: 132 case CK_WinChipC6: 133 setFeatureEnabledImpl(Features, "mmx", true); 134 break; 135 136 case CK_IcelakeServer: 137 setFeatureEnabledImpl(Features, "pconfig", true); 138 setFeatureEnabledImpl(Features, "wbnoinvd", true); 139 LLVM_FALLTHROUGH; 140 case CK_IcelakeClient: 141 setFeatureEnabledImpl(Features, "vaes", true); 142 setFeatureEnabledImpl(Features, "gfni", true); 143 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 144 setFeatureEnabledImpl(Features, "avx512bitalg", true); 145 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 146 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 147 setFeatureEnabledImpl(Features, "rdpid", true); 148 LLVM_FALLTHROUGH; 149 case CK_Cannonlake: 150 setFeatureEnabledImpl(Features, "avx512ifma", true); 151 setFeatureEnabledImpl(Features, "avx512vbmi", true); 152 setFeatureEnabledImpl(Features, "sha", true); 153 LLVM_FALLTHROUGH; 154 case CK_Cascadelake: 155 //Cannonlake has no VNNI feature inside while Icelake has 156 if (Kind != CK_Cannonlake) 157 // CLK inherits all SKX features plus AVX512_VNNI 158 setFeatureEnabledImpl(Features, "avx512vnni", true); 159 LLVM_FALLTHROUGH; 160 case CK_SkylakeServer: 161 setFeatureEnabledImpl(Features, "avx512f", true); 162 setFeatureEnabledImpl(Features, "avx512cd", true); 163 setFeatureEnabledImpl(Features, "avx512dq", true); 164 setFeatureEnabledImpl(Features, "avx512bw", true); 165 setFeatureEnabledImpl(Features, "avx512vl", true); 166 setFeatureEnabledImpl(Features, "pku", true); 167 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 168 setFeatureEnabledImpl(Features, "clwb", true); 169 LLVM_FALLTHROUGH; 170 case CK_SkylakeClient: 171 setFeatureEnabledImpl(Features, "xsavec", true); 172 setFeatureEnabledImpl(Features, "xsaves", true); 173 setFeatureEnabledImpl(Features, "mpx", true); 174 if (Kind != CK_SkylakeServer 175 && Kind != CK_Cascadelake) 176 // SKX/CLX inherits all SKL features, except SGX 177 setFeatureEnabledImpl(Features, "sgx", true); 178 setFeatureEnabledImpl(Features, "clflushopt", true); 179 setFeatureEnabledImpl(Features, "aes", true); 180 LLVM_FALLTHROUGH; 181 case CK_Broadwell: 182 setFeatureEnabledImpl(Features, "rdseed", true); 183 setFeatureEnabledImpl(Features, "adx", true); 184 setFeatureEnabledImpl(Features, "prfchw", true); 185 LLVM_FALLTHROUGH; 186 case CK_Haswell: 187 setFeatureEnabledImpl(Features, "avx2", true); 188 setFeatureEnabledImpl(Features, "lzcnt", true); 189 setFeatureEnabledImpl(Features, "bmi", true); 190 setFeatureEnabledImpl(Features, "bmi2", true); 191 setFeatureEnabledImpl(Features, "fma", true); 192 setFeatureEnabledImpl(Features, "invpcid", true); 193 setFeatureEnabledImpl(Features, "movbe", true); 194 LLVM_FALLTHROUGH; 195 case CK_IvyBridge: 196 setFeatureEnabledImpl(Features, "rdrnd", true); 197 setFeatureEnabledImpl(Features, "f16c", true); 198 setFeatureEnabledImpl(Features, "fsgsbase", true); 199 LLVM_FALLTHROUGH; 200 case CK_SandyBridge: 201 setFeatureEnabledImpl(Features, "avx", true); 202 setFeatureEnabledImpl(Features, "xsave", true); 203 setFeatureEnabledImpl(Features, "xsaveopt", true); 204 LLVM_FALLTHROUGH; 205 case CK_Westmere: 206 setFeatureEnabledImpl(Features, "pclmul", true); 207 LLVM_FALLTHROUGH; 208 case CK_Nehalem: 209 setFeatureEnabledImpl(Features, "sse4.2", true); 210 LLVM_FALLTHROUGH; 211 case CK_Penryn: 212 setFeatureEnabledImpl(Features, "sse4.1", true); 213 LLVM_FALLTHROUGH; 214 case CK_Core2: 215 setFeatureEnabledImpl(Features, "ssse3", true); 216 setFeatureEnabledImpl(Features, "sahf", true); 217 LLVM_FALLTHROUGH; 218 case CK_Yonah: 219 case CK_Prescott: 220 case CK_Nocona: 221 setFeatureEnabledImpl(Features, "sse3", true); 222 setFeatureEnabledImpl(Features, "cx16", true); 223 LLVM_FALLTHROUGH; 224 case CK_PentiumM: 225 case CK_Pentium4: 226 case CK_x86_64: 227 setFeatureEnabledImpl(Features, "sse2", true); 228 LLVM_FALLTHROUGH; 229 case CK_Pentium3: 230 case CK_C3_2: 231 setFeatureEnabledImpl(Features, "sse", true); 232 setFeatureEnabledImpl(Features, "fxsr", true); 233 break; 234 235 case CK_Tremont: 236 setFeatureEnabledImpl(Features, "cldemote", true); 237 setFeatureEnabledImpl(Features, "movdiri", true); 238 setFeatureEnabledImpl(Features, "movdir64b", true); 239 setFeatureEnabledImpl(Features, "gfni", true); 240 setFeatureEnabledImpl(Features, "waitpkg", true); 241 LLVM_FALLTHROUGH; 242 case CK_GoldmontPlus: 243 setFeatureEnabledImpl(Features, "ptwrite", true); 244 setFeatureEnabledImpl(Features, "rdpid", true); 245 setFeatureEnabledImpl(Features, "sgx", true); 246 LLVM_FALLTHROUGH; 247 case CK_Goldmont: 248 setFeatureEnabledImpl(Features, "sha", true); 249 setFeatureEnabledImpl(Features, "rdseed", true); 250 setFeatureEnabledImpl(Features, "xsave", true); 251 setFeatureEnabledImpl(Features, "xsaveopt", true); 252 setFeatureEnabledImpl(Features, "xsavec", true); 253 setFeatureEnabledImpl(Features, "xsaves", true); 254 setFeatureEnabledImpl(Features, "clflushopt", true); 255 setFeatureEnabledImpl(Features, "mpx", true); 256 setFeatureEnabledImpl(Features, "fsgsbase", true); 257 setFeatureEnabledImpl(Features, "aes", true); 258 LLVM_FALLTHROUGH; 259 case CK_Silvermont: 260 setFeatureEnabledImpl(Features, "rdrnd", true); 261 setFeatureEnabledImpl(Features, "pclmul", true); 262 setFeatureEnabledImpl(Features, "sse4.2", true); 263 setFeatureEnabledImpl(Features, "prfchw", true); 264 LLVM_FALLTHROUGH; 265 case CK_Bonnell: 266 setFeatureEnabledImpl(Features, "movbe", true); 267 setFeatureEnabledImpl(Features, "ssse3", true); 268 setFeatureEnabledImpl(Features, "fxsr", true); 269 setFeatureEnabledImpl(Features, "cx16", true); 270 setFeatureEnabledImpl(Features, "sahf", true); 271 break; 272 273 case CK_KNM: 274 // TODO: Add avx5124fmaps/avx5124vnniw. 275 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 276 LLVM_FALLTHROUGH; 277 case CK_KNL: 278 setFeatureEnabledImpl(Features, "avx512f", true); 279 setFeatureEnabledImpl(Features, "avx512cd", true); 280 setFeatureEnabledImpl(Features, "avx512er", true); 281 setFeatureEnabledImpl(Features, "avx512pf", true); 282 setFeatureEnabledImpl(Features, "prfchw", true); 283 setFeatureEnabledImpl(Features, "prefetchwt1", true); 284 setFeatureEnabledImpl(Features, "fxsr", true); 285 setFeatureEnabledImpl(Features, "rdseed", true); 286 setFeatureEnabledImpl(Features, "adx", true); 287 setFeatureEnabledImpl(Features, "lzcnt", true); 288 setFeatureEnabledImpl(Features, "bmi", true); 289 setFeatureEnabledImpl(Features, "bmi2", true); 290 setFeatureEnabledImpl(Features, "fma", true); 291 setFeatureEnabledImpl(Features, "rdrnd", true); 292 setFeatureEnabledImpl(Features, "f16c", true); 293 setFeatureEnabledImpl(Features, "fsgsbase", true); 294 setFeatureEnabledImpl(Features, "aes", true); 295 setFeatureEnabledImpl(Features, "pclmul", true); 296 setFeatureEnabledImpl(Features, "cx16", true); 297 setFeatureEnabledImpl(Features, "xsaveopt", true); 298 setFeatureEnabledImpl(Features, "xsave", true); 299 setFeatureEnabledImpl(Features, "movbe", true); 300 setFeatureEnabledImpl(Features, "sahf", true); 301 break; 302 303 case CK_K6_2: 304 case CK_K6_3: 305 case CK_WinChip2: 306 case CK_C3: 307 setFeatureEnabledImpl(Features, "3dnow", true); 308 break; 309 310 case CK_AMDFAM10: 311 setFeatureEnabledImpl(Features, "sse4a", true); 312 setFeatureEnabledImpl(Features, "lzcnt", true); 313 setFeatureEnabledImpl(Features, "popcnt", true); 314 setFeatureEnabledImpl(Features, "sahf", true); 315 LLVM_FALLTHROUGH; 316 case CK_K8SSE3: 317 setFeatureEnabledImpl(Features, "sse3", true); 318 LLVM_FALLTHROUGH; 319 case CK_K8: 320 setFeatureEnabledImpl(Features, "sse2", true); 321 LLVM_FALLTHROUGH; 322 case CK_AthlonXP: 323 setFeatureEnabledImpl(Features, "sse", true); 324 setFeatureEnabledImpl(Features, "fxsr", true); 325 LLVM_FALLTHROUGH; 326 case CK_Athlon: 327 case CK_Geode: 328 setFeatureEnabledImpl(Features, "3dnowa", true); 329 break; 330 331 case CK_BTVER2: 332 setFeatureEnabledImpl(Features, "avx", true); 333 setFeatureEnabledImpl(Features, "aes", true); 334 setFeatureEnabledImpl(Features, "pclmul", true); 335 setFeatureEnabledImpl(Features, "bmi", true); 336 setFeatureEnabledImpl(Features, "f16c", true); 337 setFeatureEnabledImpl(Features, "xsaveopt", true); 338 setFeatureEnabledImpl(Features, "movbe", true); 339 LLVM_FALLTHROUGH; 340 case CK_BTVER1: 341 setFeatureEnabledImpl(Features, "ssse3", true); 342 setFeatureEnabledImpl(Features, "sse4a", true); 343 setFeatureEnabledImpl(Features, "lzcnt", true); 344 setFeatureEnabledImpl(Features, "popcnt", true); 345 setFeatureEnabledImpl(Features, "prfchw", true); 346 setFeatureEnabledImpl(Features, "cx16", true); 347 setFeatureEnabledImpl(Features, "fxsr", true); 348 setFeatureEnabledImpl(Features, "sahf", true); 349 break; 350 351 case CK_ZNVER1: 352 setFeatureEnabledImpl(Features, "adx", true); 353 setFeatureEnabledImpl(Features, "aes", true); 354 setFeatureEnabledImpl(Features, "avx2", true); 355 setFeatureEnabledImpl(Features, "bmi", true); 356 setFeatureEnabledImpl(Features, "bmi2", true); 357 setFeatureEnabledImpl(Features, "clflushopt", true); 358 setFeatureEnabledImpl(Features, "clzero", true); 359 setFeatureEnabledImpl(Features, "cx16", true); 360 setFeatureEnabledImpl(Features, "f16c", true); 361 setFeatureEnabledImpl(Features, "fma", true); 362 setFeatureEnabledImpl(Features, "fsgsbase", true); 363 setFeatureEnabledImpl(Features, "fxsr", true); 364 setFeatureEnabledImpl(Features, "lzcnt", true); 365 setFeatureEnabledImpl(Features, "mwaitx", true); 366 setFeatureEnabledImpl(Features, "movbe", true); 367 setFeatureEnabledImpl(Features, "pclmul", true); 368 setFeatureEnabledImpl(Features, "popcnt", true); 369 setFeatureEnabledImpl(Features, "prfchw", true); 370 setFeatureEnabledImpl(Features, "rdrnd", true); 371 setFeatureEnabledImpl(Features, "rdseed", true); 372 setFeatureEnabledImpl(Features, "sahf", true); 373 setFeatureEnabledImpl(Features, "sha", true); 374 setFeatureEnabledImpl(Features, "sse4a", true); 375 setFeatureEnabledImpl(Features, "xsave", true); 376 setFeatureEnabledImpl(Features, "xsavec", true); 377 setFeatureEnabledImpl(Features, "xsaveopt", true); 378 setFeatureEnabledImpl(Features, "xsaves", true); 379 break; 380 381 case CK_BDVER4: 382 setFeatureEnabledImpl(Features, "avx2", true); 383 setFeatureEnabledImpl(Features, "bmi2", true); 384 setFeatureEnabledImpl(Features, "mwaitx", true); 385 LLVM_FALLTHROUGH; 386 case CK_BDVER3: 387 setFeatureEnabledImpl(Features, "fsgsbase", true); 388 setFeatureEnabledImpl(Features, "xsaveopt", true); 389 LLVM_FALLTHROUGH; 390 case CK_BDVER2: 391 setFeatureEnabledImpl(Features, "bmi", true); 392 setFeatureEnabledImpl(Features, "fma", true); 393 setFeatureEnabledImpl(Features, "f16c", true); 394 setFeatureEnabledImpl(Features, "tbm", true); 395 LLVM_FALLTHROUGH; 396 case CK_BDVER1: 397 // xop implies avx, sse4a and fma4. 398 setFeatureEnabledImpl(Features, "xop", true); 399 setFeatureEnabledImpl(Features, "lwp", true); 400 setFeatureEnabledImpl(Features, "lzcnt", true); 401 setFeatureEnabledImpl(Features, "aes", true); 402 setFeatureEnabledImpl(Features, "pclmul", true); 403 setFeatureEnabledImpl(Features, "prfchw", true); 404 setFeatureEnabledImpl(Features, "cx16", true); 405 setFeatureEnabledImpl(Features, "fxsr", true); 406 setFeatureEnabledImpl(Features, "xsave", true); 407 setFeatureEnabledImpl(Features, "sahf", true); 408 break; 409 } 410 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 411 return false; 412 413 // Can't do this earlier because we need to be able to explicitly enable 414 // or disable these features and the things that they depend upon. 415 416 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 417 auto I = Features.find("sse4.2"); 418 if (I != Features.end() && I->getValue() && 419 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 420 FeaturesVec.end()) 421 Features["popcnt"] = true; 422 423 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 424 I = Features.find("3dnow"); 425 if (I != Features.end() && I->getValue() && 426 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 427 FeaturesVec.end()) 428 Features["prfchw"] = true; 429 430 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 431 // then enable MMX. 432 I = Features.find("sse"); 433 if (I != Features.end() && I->getValue() && 434 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 435 FeaturesVec.end()) 436 Features["mmx"] = true; 437 438 return true; 439 } 440 441 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 442 X86SSEEnum Level, bool Enabled) { 443 if (Enabled) { 444 switch (Level) { 445 case AVX512F: 446 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 447 LLVM_FALLTHROUGH; 448 case AVX2: 449 Features["avx2"] = true; 450 LLVM_FALLTHROUGH; 451 case AVX: 452 Features["avx"] = true; 453 Features["xsave"] = true; 454 LLVM_FALLTHROUGH; 455 case SSE42: 456 Features["sse4.2"] = true; 457 LLVM_FALLTHROUGH; 458 case SSE41: 459 Features["sse4.1"] = true; 460 LLVM_FALLTHROUGH; 461 case SSSE3: 462 Features["ssse3"] = true; 463 LLVM_FALLTHROUGH; 464 case SSE3: 465 Features["sse3"] = true; 466 LLVM_FALLTHROUGH; 467 case SSE2: 468 Features["sse2"] = true; 469 LLVM_FALLTHROUGH; 470 case SSE1: 471 Features["sse"] = true; 472 LLVM_FALLTHROUGH; 473 case NoSSE: 474 break; 475 } 476 return; 477 } 478 479 switch (Level) { 480 case NoSSE: 481 case SSE1: 482 Features["sse"] = false; 483 LLVM_FALLTHROUGH; 484 case SSE2: 485 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 486 Features["gfni"] = false; 487 LLVM_FALLTHROUGH; 488 case SSE3: 489 Features["sse3"] = false; 490 setXOPLevel(Features, NoXOP, false); 491 LLVM_FALLTHROUGH; 492 case SSSE3: 493 Features["ssse3"] = false; 494 LLVM_FALLTHROUGH; 495 case SSE41: 496 Features["sse4.1"] = false; 497 LLVM_FALLTHROUGH; 498 case SSE42: 499 Features["sse4.2"] = false; 500 LLVM_FALLTHROUGH; 501 case AVX: 502 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 503 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 504 setXOPLevel(Features, FMA4, false); 505 LLVM_FALLTHROUGH; 506 case AVX2: 507 Features["avx2"] = false; 508 LLVM_FALLTHROUGH; 509 case AVX512F: 510 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 511 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 512 Features["avx512vl"] = Features["avx512vbmi"] = 513 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 514 Features["avx512bitalg"] = Features["avx512vnni"] = 515 Features["avx512vbmi2"] = false; 516 break; 517 } 518 } 519 520 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 521 MMX3DNowEnum Level, bool Enabled) { 522 if (Enabled) { 523 switch (Level) { 524 case AMD3DNowAthlon: 525 Features["3dnowa"] = true; 526 LLVM_FALLTHROUGH; 527 case AMD3DNow: 528 Features["3dnow"] = true; 529 LLVM_FALLTHROUGH; 530 case MMX: 531 Features["mmx"] = true; 532 LLVM_FALLTHROUGH; 533 case NoMMX3DNow: 534 break; 535 } 536 return; 537 } 538 539 switch (Level) { 540 case NoMMX3DNow: 541 case MMX: 542 Features["mmx"] = false; 543 LLVM_FALLTHROUGH; 544 case AMD3DNow: 545 Features["3dnow"] = false; 546 LLVM_FALLTHROUGH; 547 case AMD3DNowAthlon: 548 Features["3dnowa"] = false; 549 break; 550 } 551 } 552 553 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 554 bool Enabled) { 555 if (Enabled) { 556 switch (Level) { 557 case XOP: 558 Features["xop"] = true; 559 LLVM_FALLTHROUGH; 560 case FMA4: 561 Features["fma4"] = true; 562 setSSELevel(Features, AVX, true); 563 LLVM_FALLTHROUGH; 564 case SSE4A: 565 Features["sse4a"] = true; 566 setSSELevel(Features, SSE3, true); 567 LLVM_FALLTHROUGH; 568 case NoXOP: 569 break; 570 } 571 return; 572 } 573 574 switch (Level) { 575 case NoXOP: 576 case SSE4A: 577 Features["sse4a"] = false; 578 LLVM_FALLTHROUGH; 579 case FMA4: 580 Features["fma4"] = false; 581 LLVM_FALLTHROUGH; 582 case XOP: 583 Features["xop"] = false; 584 break; 585 } 586 } 587 588 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 589 StringRef Name, bool Enabled) { 590 // This is a bit of a hack to deal with the sse4 target feature when used 591 // as part of the target attribute. We handle sse4 correctly everywhere 592 // else. See below for more information on how we handle the sse4 options. 593 if (Name != "sse4") 594 Features[Name] = Enabled; 595 596 if (Name == "mmx") { 597 setMMXLevel(Features, MMX, Enabled); 598 } else if (Name == "sse") { 599 setSSELevel(Features, SSE1, Enabled); 600 } else if (Name == "sse2") { 601 setSSELevel(Features, SSE2, Enabled); 602 } else if (Name == "sse3") { 603 setSSELevel(Features, SSE3, Enabled); 604 } else if (Name == "ssse3") { 605 setSSELevel(Features, SSSE3, Enabled); 606 } else if (Name == "sse4.2") { 607 setSSELevel(Features, SSE42, Enabled); 608 } else if (Name == "sse4.1") { 609 setSSELevel(Features, SSE41, Enabled); 610 } else if (Name == "3dnow") { 611 setMMXLevel(Features, AMD3DNow, Enabled); 612 } else if (Name == "3dnowa") { 613 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 614 } else if (Name == "aes") { 615 if (Enabled) 616 setSSELevel(Features, SSE2, Enabled); 617 else 618 Features["vaes"] = false; 619 } else if (Name == "vaes") { 620 if (Enabled) { 621 setSSELevel(Features, AVX, Enabled); 622 Features["aes"] = true; 623 } 624 } else if (Name == "pclmul") { 625 if (Enabled) 626 setSSELevel(Features, SSE2, Enabled); 627 else 628 Features["vpclmulqdq"] = false; 629 } else if (Name == "vpclmulqdq") { 630 if (Enabled) { 631 setSSELevel(Features, AVX, Enabled); 632 Features["pclmul"] = true; 633 } 634 } else if (Name == "gfni") { 635 if (Enabled) 636 setSSELevel(Features, SSE2, Enabled); 637 } else if (Name == "avx") { 638 setSSELevel(Features, AVX, Enabled); 639 } else if (Name == "avx2") { 640 setSSELevel(Features, AVX2, Enabled); 641 } else if (Name == "avx512f") { 642 setSSELevel(Features, AVX512F, Enabled); 643 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 644 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 645 Name == "avx512vbmi" || Name == "avx512ifma" || 646 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 647 Name == "avx512vnni" || Name == "avx512vbmi2") { 648 if (Enabled) 649 setSSELevel(Features, AVX512F, Enabled); 650 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 651 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 652 Features["avx512bw"] = true; 653 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 654 if (Name == "avx512bw" && !Enabled) 655 Features["avx512vbmi"] = Features["avx512vbmi2"] = 656 Features["avx512bitalg"] = false; 657 } else if (Name == "fma") { 658 if (Enabled) 659 setSSELevel(Features, AVX, Enabled); 660 else 661 setSSELevel(Features, AVX512F, Enabled); 662 } else if (Name == "fma4") { 663 setXOPLevel(Features, FMA4, Enabled); 664 } else if (Name == "xop") { 665 setXOPLevel(Features, XOP, Enabled); 666 } else if (Name == "sse4a") { 667 setXOPLevel(Features, SSE4A, Enabled); 668 } else if (Name == "f16c") { 669 if (Enabled) 670 setSSELevel(Features, AVX, Enabled); 671 else 672 setSSELevel(Features, AVX512F, Enabled); 673 } else if (Name == "sha") { 674 if (Enabled) 675 setSSELevel(Features, SSE2, Enabled); 676 } else if (Name == "sse4") { 677 // We can get here via the __target__ attribute since that's not controlled 678 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 679 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 680 // disabled. 681 if (Enabled) 682 setSSELevel(Features, SSE42, Enabled); 683 else 684 setSSELevel(Features, SSE41, Enabled); 685 } else if (Name == "xsave") { 686 if (!Enabled) 687 Features["xsaveopt"] = false; 688 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 689 if (Enabled) 690 Features["xsave"] = true; 691 } 692 } 693 694 /// handleTargetFeatures - Perform initialization based on the user 695 /// configured set of features. 696 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 697 DiagnosticsEngine &Diags) { 698 for (const auto &Feature : Features) { 699 if (Feature[0] != '+') 700 continue; 701 702 if (Feature == "+aes") { 703 HasAES = true; 704 } else if (Feature == "+vaes") { 705 HasVAES = true; 706 } else if (Feature == "+pclmul") { 707 HasPCLMUL = true; 708 } else if (Feature == "+vpclmulqdq") { 709 HasVPCLMULQDQ = true; 710 } else if (Feature == "+lzcnt") { 711 HasLZCNT = true; 712 } else if (Feature == "+rdrnd") { 713 HasRDRND = true; 714 } else if (Feature == "+fsgsbase") { 715 HasFSGSBASE = true; 716 } else if (Feature == "+bmi") { 717 HasBMI = true; 718 } else if (Feature == "+bmi2") { 719 HasBMI2 = true; 720 } else if (Feature == "+popcnt") { 721 HasPOPCNT = true; 722 } else if (Feature == "+rtm") { 723 HasRTM = true; 724 } else if (Feature == "+prfchw") { 725 HasPRFCHW = true; 726 } else if (Feature == "+rdseed") { 727 HasRDSEED = true; 728 } else if (Feature == "+adx") { 729 HasADX = true; 730 } else if (Feature == "+tbm") { 731 HasTBM = true; 732 } else if (Feature == "+lwp") { 733 HasLWP = true; 734 } else if (Feature == "+fma") { 735 HasFMA = true; 736 } else if (Feature == "+f16c") { 737 HasF16C = true; 738 } else if (Feature == "+gfni") { 739 HasGFNI = true; 740 } else if (Feature == "+avx512cd") { 741 HasAVX512CD = true; 742 } else if (Feature == "+avx512vpopcntdq") { 743 HasAVX512VPOPCNTDQ = true; 744 } else if (Feature == "+avx512vnni") { 745 HasAVX512VNNI = true; 746 } else if (Feature == "+avx512er") { 747 HasAVX512ER = true; 748 } else if (Feature == "+avx512pf") { 749 HasAVX512PF = true; 750 } else if (Feature == "+avx512dq") { 751 HasAVX512DQ = true; 752 } else if (Feature == "+avx512bitalg") { 753 HasAVX512BITALG = true; 754 } else if (Feature == "+avx512bw") { 755 HasAVX512BW = true; 756 } else if (Feature == "+avx512vl") { 757 HasAVX512VL = true; 758 } else if (Feature == "+avx512vbmi") { 759 HasAVX512VBMI = true; 760 } else if (Feature == "+avx512vbmi2") { 761 HasAVX512VBMI2 = true; 762 } else if (Feature == "+avx512ifma") { 763 HasAVX512IFMA = true; 764 } else if (Feature == "+sha") { 765 HasSHA = true; 766 } else if (Feature == "+mpx") { 767 HasMPX = true; 768 } else if (Feature == "+shstk") { 769 HasSHSTK = true; 770 } else if (Feature == "+movbe") { 771 HasMOVBE = true; 772 } else if (Feature == "+sgx") { 773 HasSGX = true; 774 } else if (Feature == "+cx16") { 775 HasCX16 = true; 776 } else if (Feature == "+fxsr") { 777 HasFXSR = true; 778 } else if (Feature == "+xsave") { 779 HasXSAVE = true; 780 } else if (Feature == "+xsaveopt") { 781 HasXSAVEOPT = true; 782 } else if (Feature == "+xsavec") { 783 HasXSAVEC = true; 784 } else if (Feature == "+xsaves") { 785 HasXSAVES = true; 786 } else if (Feature == "+mwaitx") { 787 HasMWAITX = true; 788 } else if (Feature == "+pku") { 789 HasPKU = true; 790 } else if (Feature == "+clflushopt") { 791 HasCLFLUSHOPT = true; 792 } else if (Feature == "+clwb") { 793 HasCLWB = true; 794 } else if (Feature == "+wbnoinvd") { 795 HasWBNOINVD = true; 796 } else if (Feature == "+prefetchwt1") { 797 HasPREFETCHWT1 = true; 798 } else if (Feature == "+clzero") { 799 HasCLZERO = true; 800 } else if (Feature == "+cldemote") { 801 HasCLDEMOTE = true; 802 } else if (Feature == "+rdpid") { 803 HasRDPID = true; 804 } else if (Feature == "+retpoline-external-thunk") { 805 HasRetpolineExternalThunk = true; 806 } else if (Feature == "+sahf") { 807 HasLAHFSAHF = true; 808 } else if (Feature == "+waitpkg") { 809 HasWAITPKG = true; 810 } else if (Feature == "+movdiri") { 811 HasMOVDIRI = true; 812 } else if (Feature == "+movdir64b") { 813 HasMOVDIR64B = true; 814 } else if (Feature == "+pconfig") { 815 HasPCONFIG = true; 816 } else if (Feature == "+ptwrite") { 817 HasPTWRITE = true; 818 } else if (Feature == "+invpcid") { 819 HasINVPCID = true; 820 } 821 822 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 823 .Case("+avx512f", AVX512F) 824 .Case("+avx2", AVX2) 825 .Case("+avx", AVX) 826 .Case("+sse4.2", SSE42) 827 .Case("+sse4.1", SSE41) 828 .Case("+ssse3", SSSE3) 829 .Case("+sse3", SSE3) 830 .Case("+sse2", SSE2) 831 .Case("+sse", SSE1) 832 .Default(NoSSE); 833 SSELevel = std::max(SSELevel, Level); 834 835 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 836 .Case("+3dnowa", AMD3DNowAthlon) 837 .Case("+3dnow", AMD3DNow) 838 .Case("+mmx", MMX) 839 .Default(NoMMX3DNow); 840 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 841 842 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 843 .Case("+xop", XOP) 844 .Case("+fma4", FMA4) 845 .Case("+sse4a", SSE4A) 846 .Default(NoXOP); 847 XOPLevel = std::max(XOPLevel, XLevel); 848 } 849 850 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 851 // matches the selected sse level. 852 if ((FPMath == FP_SSE && SSELevel < SSE1) || 853 (FPMath == FP_387 && SSELevel >= SSE1)) { 854 Diags.Report(diag::err_target_unsupported_fpmath) 855 << (FPMath == FP_SSE ? "sse" : "387"); 856 return false; 857 } 858 859 SimdDefaultAlign = 860 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 861 return true; 862 } 863 864 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 865 /// definitions for this particular subtarget. 866 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 867 MacroBuilder &Builder) const { 868 std::string CodeModel = getTargetOpts().CodeModel; 869 if (CodeModel == "default") 870 CodeModel = "small"; 871 Builder.defineMacro("__code_model_" + CodeModel + "_"); 872 873 // Target identification. 874 if (getTriple().getArch() == llvm::Triple::x86_64) { 875 Builder.defineMacro("__amd64__"); 876 Builder.defineMacro("__amd64"); 877 Builder.defineMacro("__x86_64"); 878 Builder.defineMacro("__x86_64__"); 879 if (getTriple().getArchName() == "x86_64h") { 880 Builder.defineMacro("__x86_64h"); 881 Builder.defineMacro("__x86_64h__"); 882 } 883 } else { 884 DefineStd(Builder, "i386", Opts); 885 } 886 887 // Subtarget options. 888 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 889 // truly should be based on -mtune options. 890 switch (CPU) { 891 case CK_Generic: 892 break; 893 case CK_i386: 894 // The rest are coming from the i386 define above. 895 Builder.defineMacro("__tune_i386__"); 896 break; 897 case CK_i486: 898 case CK_WinChipC6: 899 case CK_WinChip2: 900 case CK_C3: 901 defineCPUMacros(Builder, "i486"); 902 break; 903 case CK_PentiumMMX: 904 Builder.defineMacro("__pentium_mmx__"); 905 Builder.defineMacro("__tune_pentium_mmx__"); 906 LLVM_FALLTHROUGH; 907 case CK_i586: 908 case CK_Pentium: 909 defineCPUMacros(Builder, "i586"); 910 defineCPUMacros(Builder, "pentium"); 911 break; 912 case CK_Pentium3: 913 case CK_PentiumM: 914 Builder.defineMacro("__tune_pentium3__"); 915 LLVM_FALLTHROUGH; 916 case CK_Pentium2: 917 case CK_C3_2: 918 Builder.defineMacro("__tune_pentium2__"); 919 LLVM_FALLTHROUGH; 920 case CK_PentiumPro: 921 defineCPUMacros(Builder, "i686"); 922 defineCPUMacros(Builder, "pentiumpro"); 923 break; 924 case CK_Pentium4: 925 defineCPUMacros(Builder, "pentium4"); 926 break; 927 case CK_Yonah: 928 case CK_Prescott: 929 case CK_Nocona: 930 defineCPUMacros(Builder, "nocona"); 931 break; 932 case CK_Core2: 933 case CK_Penryn: 934 defineCPUMacros(Builder, "core2"); 935 break; 936 case CK_Bonnell: 937 defineCPUMacros(Builder, "atom"); 938 break; 939 case CK_Silvermont: 940 defineCPUMacros(Builder, "slm"); 941 break; 942 case CK_Goldmont: 943 defineCPUMacros(Builder, "goldmont"); 944 break; 945 case CK_GoldmontPlus: 946 defineCPUMacros(Builder, "goldmont_plus"); 947 break; 948 case CK_Tremont: 949 defineCPUMacros(Builder, "tremont"); 950 break; 951 case CK_Nehalem: 952 case CK_Westmere: 953 case CK_SandyBridge: 954 case CK_IvyBridge: 955 case CK_Haswell: 956 case CK_Broadwell: 957 case CK_SkylakeClient: 958 case CK_SkylakeServer: 959 case CK_Cascadelake: 960 case CK_Cannonlake: 961 case CK_IcelakeClient: 962 case CK_IcelakeServer: 963 // FIXME: Historically, we defined this legacy name, it would be nice to 964 // remove it at some point. We've never exposed fine-grained names for 965 // recent primary x86 CPUs, and we should keep it that way. 966 defineCPUMacros(Builder, "corei7"); 967 break; 968 case CK_KNL: 969 defineCPUMacros(Builder, "knl"); 970 break; 971 case CK_KNM: 972 break; 973 case CK_Lakemont: 974 defineCPUMacros(Builder, "i586", /*Tuning*/false); 975 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 976 Builder.defineMacro("__tune_lakemont__"); 977 break; 978 case CK_K6_2: 979 Builder.defineMacro("__k6_2__"); 980 Builder.defineMacro("__tune_k6_2__"); 981 LLVM_FALLTHROUGH; 982 case CK_K6_3: 983 if (CPU != CK_K6_2) { // In case of fallthrough 984 // FIXME: GCC may be enabling these in cases where some other k6 985 // architecture is specified but -m3dnow is explicitly provided. The 986 // exact semantics need to be determined and emulated here. 987 Builder.defineMacro("__k6_3__"); 988 Builder.defineMacro("__tune_k6_3__"); 989 } 990 LLVM_FALLTHROUGH; 991 case CK_K6: 992 defineCPUMacros(Builder, "k6"); 993 break; 994 case CK_Athlon: 995 case CK_AthlonXP: 996 defineCPUMacros(Builder, "athlon"); 997 if (SSELevel != NoSSE) { 998 Builder.defineMacro("__athlon_sse__"); 999 Builder.defineMacro("__tune_athlon_sse__"); 1000 } 1001 break; 1002 case CK_K8: 1003 case CK_K8SSE3: 1004 case CK_x86_64: 1005 defineCPUMacros(Builder, "k8"); 1006 break; 1007 case CK_AMDFAM10: 1008 defineCPUMacros(Builder, "amdfam10"); 1009 break; 1010 case CK_BTVER1: 1011 defineCPUMacros(Builder, "btver1"); 1012 break; 1013 case CK_BTVER2: 1014 defineCPUMacros(Builder, "btver2"); 1015 break; 1016 case CK_BDVER1: 1017 defineCPUMacros(Builder, "bdver1"); 1018 break; 1019 case CK_BDVER2: 1020 defineCPUMacros(Builder, "bdver2"); 1021 break; 1022 case CK_BDVER3: 1023 defineCPUMacros(Builder, "bdver3"); 1024 break; 1025 case CK_BDVER4: 1026 defineCPUMacros(Builder, "bdver4"); 1027 break; 1028 case CK_ZNVER1: 1029 defineCPUMacros(Builder, "znver1"); 1030 break; 1031 case CK_Geode: 1032 defineCPUMacros(Builder, "geode"); 1033 break; 1034 } 1035 1036 // Target properties. 1037 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1038 1039 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1040 // functions in glibc header files that use FP Stack inline asm which the 1041 // backend can't deal with (PR879). 1042 Builder.defineMacro("__NO_MATH_INLINES"); 1043 1044 if (HasAES) 1045 Builder.defineMacro("__AES__"); 1046 1047 if (HasVAES) 1048 Builder.defineMacro("__VAES__"); 1049 1050 if (HasPCLMUL) 1051 Builder.defineMacro("__PCLMUL__"); 1052 1053 if (HasVPCLMULQDQ) 1054 Builder.defineMacro("__VPCLMULQDQ__"); 1055 1056 if (HasLZCNT) 1057 Builder.defineMacro("__LZCNT__"); 1058 1059 if (HasRDRND) 1060 Builder.defineMacro("__RDRND__"); 1061 1062 if (HasFSGSBASE) 1063 Builder.defineMacro("__FSGSBASE__"); 1064 1065 if (HasBMI) 1066 Builder.defineMacro("__BMI__"); 1067 1068 if (HasBMI2) 1069 Builder.defineMacro("__BMI2__"); 1070 1071 if (HasPOPCNT) 1072 Builder.defineMacro("__POPCNT__"); 1073 1074 if (HasRTM) 1075 Builder.defineMacro("__RTM__"); 1076 1077 if (HasPRFCHW) 1078 Builder.defineMacro("__PRFCHW__"); 1079 1080 if (HasRDSEED) 1081 Builder.defineMacro("__RDSEED__"); 1082 1083 if (HasADX) 1084 Builder.defineMacro("__ADX__"); 1085 1086 if (HasTBM) 1087 Builder.defineMacro("__TBM__"); 1088 1089 if (HasLWP) 1090 Builder.defineMacro("__LWP__"); 1091 1092 if (HasMWAITX) 1093 Builder.defineMacro("__MWAITX__"); 1094 1095 if (HasMOVBE) 1096 Builder.defineMacro("__MOVBE__"); 1097 1098 switch (XOPLevel) { 1099 case XOP: 1100 Builder.defineMacro("__XOP__"); 1101 LLVM_FALLTHROUGH; 1102 case FMA4: 1103 Builder.defineMacro("__FMA4__"); 1104 LLVM_FALLTHROUGH; 1105 case SSE4A: 1106 Builder.defineMacro("__SSE4A__"); 1107 LLVM_FALLTHROUGH; 1108 case NoXOP: 1109 break; 1110 } 1111 1112 if (HasFMA) 1113 Builder.defineMacro("__FMA__"); 1114 1115 if (HasF16C) 1116 Builder.defineMacro("__F16C__"); 1117 1118 if (HasGFNI) 1119 Builder.defineMacro("__GFNI__"); 1120 1121 if (HasAVX512CD) 1122 Builder.defineMacro("__AVX512CD__"); 1123 if (HasAVX512VPOPCNTDQ) 1124 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1125 if (HasAVX512VNNI) 1126 Builder.defineMacro("__AVX512VNNI__"); 1127 if (HasAVX512ER) 1128 Builder.defineMacro("__AVX512ER__"); 1129 if (HasAVX512PF) 1130 Builder.defineMacro("__AVX512PF__"); 1131 if (HasAVX512DQ) 1132 Builder.defineMacro("__AVX512DQ__"); 1133 if (HasAVX512BITALG) 1134 Builder.defineMacro("__AVX512BITALG__"); 1135 if (HasAVX512BW) 1136 Builder.defineMacro("__AVX512BW__"); 1137 if (HasAVX512VL) 1138 Builder.defineMacro("__AVX512VL__"); 1139 if (HasAVX512VBMI) 1140 Builder.defineMacro("__AVX512VBMI__"); 1141 if (HasAVX512VBMI2) 1142 Builder.defineMacro("__AVX512VBMI2__"); 1143 if (HasAVX512IFMA) 1144 Builder.defineMacro("__AVX512IFMA__"); 1145 1146 if (HasSHA) 1147 Builder.defineMacro("__SHA__"); 1148 1149 if (HasFXSR) 1150 Builder.defineMacro("__FXSR__"); 1151 if (HasXSAVE) 1152 Builder.defineMacro("__XSAVE__"); 1153 if (HasXSAVEOPT) 1154 Builder.defineMacro("__XSAVEOPT__"); 1155 if (HasXSAVEC) 1156 Builder.defineMacro("__XSAVEC__"); 1157 if (HasXSAVES) 1158 Builder.defineMacro("__XSAVES__"); 1159 if (HasPKU) 1160 Builder.defineMacro("__PKU__"); 1161 if (HasCLFLUSHOPT) 1162 Builder.defineMacro("__CLFLUSHOPT__"); 1163 if (HasCLWB) 1164 Builder.defineMacro("__CLWB__"); 1165 if (HasWBNOINVD) 1166 Builder.defineMacro("__WBNOINVD__"); 1167 if (HasMPX) 1168 Builder.defineMacro("__MPX__"); 1169 if (HasSHSTK) 1170 Builder.defineMacro("__SHSTK__"); 1171 if (HasSGX) 1172 Builder.defineMacro("__SGX__"); 1173 if (HasPREFETCHWT1) 1174 Builder.defineMacro("__PREFETCHWT1__"); 1175 if (HasCLZERO) 1176 Builder.defineMacro("__CLZERO__"); 1177 if (HasRDPID) 1178 Builder.defineMacro("__RDPID__"); 1179 if (HasCLDEMOTE) 1180 Builder.defineMacro("__CLDEMOTE__"); 1181 if (HasWAITPKG) 1182 Builder.defineMacro("__WAITPKG__"); 1183 if (HasMOVDIRI) 1184 Builder.defineMacro("__MOVDIRI__"); 1185 if (HasMOVDIR64B) 1186 Builder.defineMacro("__MOVDIR64B__"); 1187 if (HasPCONFIG) 1188 Builder.defineMacro("__PCONFIG__"); 1189 if (HasPTWRITE) 1190 Builder.defineMacro("__PTWRITE__"); 1191 if (HasINVPCID) 1192 Builder.defineMacro("__INVPCID__"); 1193 1194 // Each case falls through to the previous one here. 1195 switch (SSELevel) { 1196 case AVX512F: 1197 Builder.defineMacro("__AVX512F__"); 1198 LLVM_FALLTHROUGH; 1199 case AVX2: 1200 Builder.defineMacro("__AVX2__"); 1201 LLVM_FALLTHROUGH; 1202 case AVX: 1203 Builder.defineMacro("__AVX__"); 1204 LLVM_FALLTHROUGH; 1205 case SSE42: 1206 Builder.defineMacro("__SSE4_2__"); 1207 LLVM_FALLTHROUGH; 1208 case SSE41: 1209 Builder.defineMacro("__SSE4_1__"); 1210 LLVM_FALLTHROUGH; 1211 case SSSE3: 1212 Builder.defineMacro("__SSSE3__"); 1213 LLVM_FALLTHROUGH; 1214 case SSE3: 1215 Builder.defineMacro("__SSE3__"); 1216 LLVM_FALLTHROUGH; 1217 case SSE2: 1218 Builder.defineMacro("__SSE2__"); 1219 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1220 LLVM_FALLTHROUGH; 1221 case SSE1: 1222 Builder.defineMacro("__SSE__"); 1223 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1224 LLVM_FALLTHROUGH; 1225 case NoSSE: 1226 break; 1227 } 1228 1229 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1230 switch (SSELevel) { 1231 case AVX512F: 1232 case AVX2: 1233 case AVX: 1234 case SSE42: 1235 case SSE41: 1236 case SSSE3: 1237 case SSE3: 1238 case SSE2: 1239 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1240 break; 1241 case SSE1: 1242 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1243 break; 1244 default: 1245 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1246 break; 1247 } 1248 } 1249 1250 // Each case falls through to the previous one here. 1251 switch (MMX3DNowLevel) { 1252 case AMD3DNowAthlon: 1253 Builder.defineMacro("__3dNOW_A__"); 1254 LLVM_FALLTHROUGH; 1255 case AMD3DNow: 1256 Builder.defineMacro("__3dNOW__"); 1257 LLVM_FALLTHROUGH; 1258 case MMX: 1259 Builder.defineMacro("__MMX__"); 1260 LLVM_FALLTHROUGH; 1261 case NoMMX3DNow: 1262 break; 1263 } 1264 1265 if (CPU >= CK_i486) { 1266 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1267 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1269 } 1270 if (CPU >= CK_i586) 1271 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1272 if (HasCX16) 1273 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1274 1275 if (HasFloat128) 1276 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1277 } 1278 1279 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1280 return llvm::StringSwitch<bool>(Name) 1281 .Case("3dnow", true) 1282 .Case("3dnowa", true) 1283 .Case("adx", true) 1284 .Case("aes", true) 1285 .Case("avx", true) 1286 .Case("avx2", true) 1287 .Case("avx512f", true) 1288 .Case("avx512cd", true) 1289 .Case("avx512vpopcntdq", true) 1290 .Case("avx512vnni", true) 1291 .Case("avx512er", true) 1292 .Case("avx512pf", true) 1293 .Case("avx512dq", true) 1294 .Case("avx512bitalg", true) 1295 .Case("avx512bw", true) 1296 .Case("avx512vl", true) 1297 .Case("avx512vbmi", true) 1298 .Case("avx512vbmi2", true) 1299 .Case("avx512ifma", true) 1300 .Case("bmi", true) 1301 .Case("bmi2", true) 1302 .Case("cldemote", true) 1303 .Case("clflushopt", true) 1304 .Case("clwb", true) 1305 .Case("clzero", true) 1306 .Case("cx16", true) 1307 .Case("f16c", true) 1308 .Case("fma", true) 1309 .Case("fma4", true) 1310 .Case("fsgsbase", true) 1311 .Case("fxsr", true) 1312 .Case("gfni", true) 1313 .Case("invpcid", true) 1314 .Case("lwp", true) 1315 .Case("lzcnt", true) 1316 .Case("mmx", true) 1317 .Case("movbe", true) 1318 .Case("movdiri", true) 1319 .Case("movdir64b", true) 1320 .Case("mpx", true) 1321 .Case("mwaitx", true) 1322 .Case("pclmul", true) 1323 .Case("pconfig", true) 1324 .Case("pku", true) 1325 .Case("popcnt", true) 1326 .Case("prefetchwt1", true) 1327 .Case("prfchw", true) 1328 .Case("ptwrite", true) 1329 .Case("rdpid", true) 1330 .Case("rdrnd", true) 1331 .Case("rdseed", true) 1332 .Case("rtm", true) 1333 .Case("sahf", true) 1334 .Case("sgx", true) 1335 .Case("sha", true) 1336 .Case("shstk", true) 1337 .Case("sse", true) 1338 .Case("sse2", true) 1339 .Case("sse3", true) 1340 .Case("ssse3", true) 1341 .Case("sse4", true) 1342 .Case("sse4.1", true) 1343 .Case("sse4.2", true) 1344 .Case("sse4a", true) 1345 .Case("tbm", true) 1346 .Case("vaes", true) 1347 .Case("vpclmulqdq", true) 1348 .Case("wbnoinvd", true) 1349 .Case("waitpkg", true) 1350 .Case("x87", true) 1351 .Case("xop", true) 1352 .Case("xsave", true) 1353 .Case("xsavec", true) 1354 .Case("xsaves", true) 1355 .Case("xsaveopt", true) 1356 .Default(false); 1357 } 1358 1359 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1360 return llvm::StringSwitch<bool>(Feature) 1361 .Case("adx", HasADX) 1362 .Case("aes", HasAES) 1363 .Case("avx", SSELevel >= AVX) 1364 .Case("avx2", SSELevel >= AVX2) 1365 .Case("avx512f", SSELevel >= AVX512F) 1366 .Case("avx512cd", HasAVX512CD) 1367 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1368 .Case("avx512vnni", HasAVX512VNNI) 1369 .Case("avx512er", HasAVX512ER) 1370 .Case("avx512pf", HasAVX512PF) 1371 .Case("avx512dq", HasAVX512DQ) 1372 .Case("avx512bitalg", HasAVX512BITALG) 1373 .Case("avx512bw", HasAVX512BW) 1374 .Case("avx512vl", HasAVX512VL) 1375 .Case("avx512vbmi", HasAVX512VBMI) 1376 .Case("avx512vbmi2", HasAVX512VBMI2) 1377 .Case("avx512ifma", HasAVX512IFMA) 1378 .Case("bmi", HasBMI) 1379 .Case("bmi2", HasBMI2) 1380 .Case("cldemote", HasCLDEMOTE) 1381 .Case("clflushopt", HasCLFLUSHOPT) 1382 .Case("clwb", HasCLWB) 1383 .Case("clzero", HasCLZERO) 1384 .Case("cx16", HasCX16) 1385 .Case("f16c", HasF16C) 1386 .Case("fma", HasFMA) 1387 .Case("fma4", XOPLevel >= FMA4) 1388 .Case("fsgsbase", HasFSGSBASE) 1389 .Case("fxsr", HasFXSR) 1390 .Case("gfni", HasGFNI) 1391 .Case("invpcid", HasINVPCID) 1392 .Case("lwp", HasLWP) 1393 .Case("lzcnt", HasLZCNT) 1394 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1395 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1396 .Case("mmx", MMX3DNowLevel >= MMX) 1397 .Case("movbe", HasMOVBE) 1398 .Case("movdiri", HasMOVDIRI) 1399 .Case("movdir64b", HasMOVDIR64B) 1400 .Case("mpx", HasMPX) 1401 .Case("mwaitx", HasMWAITX) 1402 .Case("pclmul", HasPCLMUL) 1403 .Case("pconfig", HasPCONFIG) 1404 .Case("pku", HasPKU) 1405 .Case("popcnt", HasPOPCNT) 1406 .Case("prefetchwt1", HasPREFETCHWT1) 1407 .Case("prfchw", HasPRFCHW) 1408 .Case("ptwrite", HasPTWRITE) 1409 .Case("rdpid", HasRDPID) 1410 .Case("rdrnd", HasRDRND) 1411 .Case("rdseed", HasRDSEED) 1412 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1413 .Case("rtm", HasRTM) 1414 .Case("sahf", HasLAHFSAHF) 1415 .Case("sgx", HasSGX) 1416 .Case("sha", HasSHA) 1417 .Case("shstk", HasSHSTK) 1418 .Case("sse", SSELevel >= SSE1) 1419 .Case("sse2", SSELevel >= SSE2) 1420 .Case("sse3", SSELevel >= SSE3) 1421 .Case("ssse3", SSELevel >= SSSE3) 1422 .Case("sse4.1", SSELevel >= SSE41) 1423 .Case("sse4.2", SSELevel >= SSE42) 1424 .Case("sse4a", XOPLevel >= SSE4A) 1425 .Case("tbm", HasTBM) 1426 .Case("vaes", HasVAES) 1427 .Case("vpclmulqdq", HasVPCLMULQDQ) 1428 .Case("wbnoinvd", HasWBNOINVD) 1429 .Case("waitpkg", HasWAITPKG) 1430 .Case("x86", true) 1431 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1432 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1433 .Case("xop", XOPLevel >= XOP) 1434 .Case("xsave", HasXSAVE) 1435 .Case("xsavec", HasXSAVEC) 1436 .Case("xsaves", HasXSAVES) 1437 .Case("xsaveopt", HasXSAVEOPT) 1438 .Default(false); 1439 } 1440 1441 // We can't use a generic validation scheme for the features accepted here 1442 // versus subtarget features accepted in the target attribute because the 1443 // bitfield structure that's initialized in the runtime only supports the 1444 // below currently rather than the full range of subtarget features. (See 1445 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1446 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1447 return llvm::StringSwitch<bool>(FeatureStr) 1448 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1449 #include "llvm/Support/X86TargetParser.def" 1450 .Default(false); 1451 } 1452 1453 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1454 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1455 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1456 #include "llvm/Support/X86TargetParser.def" 1457 ; 1458 // Note, this function should only be used after ensuring the value is 1459 // correct, so it asserts if the value is out of range. 1460 } 1461 1462 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1463 enum class FeatPriority { 1464 #define FEATURE(FEAT) FEAT, 1465 #include "clang/Basic/X86Target.def" 1466 }; 1467 switch (Feat) { 1468 #define FEATURE(FEAT) \ 1469 case llvm::X86::FEAT: \ 1470 return static_cast<unsigned>(FeatPriority::FEAT); 1471 #include "clang/Basic/X86Target.def" 1472 default: 1473 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1474 } 1475 } 1476 1477 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1478 // Valid CPUs have a 'key feature' that compares just better than its key 1479 // feature. 1480 CPUKind Kind = getCPUKind(Name); 1481 if (Kind != CK_Generic) { 1482 switch (Kind) { 1483 default: 1484 llvm_unreachable( 1485 "CPU Type without a key feature used in 'target' attribute"); 1486 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1487 case CK_##ENUM: \ 1488 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1489 #include "clang/Basic/X86Target.def" 1490 } 1491 } 1492 1493 // Now we know we have a feature, so get its priority and shift it a few so 1494 // that we have sufficient room for the CPUs (above). 1495 return getFeaturePriority(getFeature(Name)) << 1; 1496 } 1497 1498 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1499 return llvm::StringSwitch<bool>(Name) 1500 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1501 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1502 #include "clang/Basic/X86Target.def" 1503 .Default(false); 1504 } 1505 1506 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1507 return llvm::StringSwitch<StringRef>(Name) 1508 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1509 #include "clang/Basic/X86Target.def" 1510 .Default(Name); 1511 } 1512 1513 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1514 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1515 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1516 #include "clang/Basic/X86Target.def" 1517 .Default(0); 1518 } 1519 1520 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1521 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1522 StringRef WholeList = 1523 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1524 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1525 #include "clang/Basic/X86Target.def" 1526 .Default(""); 1527 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1528 } 1529 1530 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1531 switch (Kind) { 1532 case CK_Generic: 1533 return ""; 1534 #define PROC(ENUM, STRING, IS64BIT) \ 1535 case CK_##ENUM: \ 1536 return STRING; 1537 #include "clang/Basic/X86Target.def" 1538 } 1539 llvm_unreachable("Invalid CPUKind"); 1540 } 1541 1542 // We can't use a generic validation scheme for the cpus accepted here 1543 // versus subtarget cpus accepted in the target attribute because the 1544 // variables intitialized by the runtime only support the below currently 1545 // rather than the full range of cpus. 1546 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1547 return llvm::StringSwitch<bool>(FeatureStr) 1548 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1549 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1550 .Cases(STR, ALIAS, true) 1551 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1552 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1553 #include "llvm/Support/X86TargetParser.def" 1554 .Default(false); 1555 } 1556 1557 bool X86TargetInfo::validateAsmConstraint( 1558 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1559 switch (*Name) { 1560 default: 1561 return false; 1562 // Constant constraints. 1563 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1564 // instructions. 1565 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1566 // x86_64 instructions. 1567 case 's': 1568 Info.setRequiresImmediate(); 1569 return true; 1570 case 'I': 1571 Info.setRequiresImmediate(0, 31); 1572 return true; 1573 case 'J': 1574 Info.setRequiresImmediate(0, 63); 1575 return true; 1576 case 'K': 1577 Info.setRequiresImmediate(-128, 127); 1578 return true; 1579 case 'L': 1580 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1581 return true; 1582 case 'M': 1583 Info.setRequiresImmediate(0, 3); 1584 return true; 1585 case 'N': 1586 Info.setRequiresImmediate(0, 255); 1587 return true; 1588 case 'O': 1589 Info.setRequiresImmediate(0, 127); 1590 return true; 1591 // Register constraints. 1592 case 'Y': // 'Y' is the first character for several 2-character constraints. 1593 // Shift the pointer to the second character of the constraint. 1594 Name++; 1595 switch (*Name) { 1596 default: 1597 return false; 1598 case 'z': 1599 case '0': // First SSE register. 1600 case '2': 1601 case 't': // Any SSE register, when SSE2 is enabled. 1602 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1603 case 'm': // Any MMX register, when inter-unit moves enabled. 1604 case 'k': // AVX512 arch mask registers: k1-k7. 1605 Info.setAllowsRegister(); 1606 return true; 1607 } 1608 case 'f': // Any x87 floating point stack register. 1609 // Constraint 'f' cannot be used for output operands. 1610 if (Info.ConstraintStr[0] == '=') 1611 return false; 1612 Info.setAllowsRegister(); 1613 return true; 1614 case 'a': // eax. 1615 case 'b': // ebx. 1616 case 'c': // ecx. 1617 case 'd': // edx. 1618 case 'S': // esi. 1619 case 'D': // edi. 1620 case 'A': // edx:eax. 1621 case 't': // Top of floating point stack. 1622 case 'u': // Second from top of floating point stack. 1623 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1624 case 'y': // Any MMX register. 1625 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1626 case 'x': // Any SSE register. 1627 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1628 // for intermideate k reg operations). 1629 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1630 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1631 case 'l': // "Index" registers: any general register that can be used as an 1632 // index in a base+index memory access. 1633 Info.setAllowsRegister(); 1634 return true; 1635 // Floating point constant constraints. 1636 case 'C': // SSE floating point constant. 1637 case 'G': // x87 floating point constant. 1638 return true; 1639 } 1640 } 1641 1642 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1643 unsigned Size) const { 1644 // Strip off constraint modifiers. 1645 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1646 Constraint = Constraint.substr(1); 1647 1648 return validateOperandSize(Constraint, Size); 1649 } 1650 1651 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1652 unsigned Size) const { 1653 return validateOperandSize(Constraint, Size); 1654 } 1655 1656 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1657 unsigned Size) const { 1658 switch (Constraint[0]) { 1659 default: 1660 break; 1661 case 'k': 1662 // Registers k0-k7 (AVX512) size limit is 64 bit. 1663 case 'y': 1664 return Size <= 64; 1665 case 'f': 1666 case 't': 1667 case 'u': 1668 return Size <= 128; 1669 case 'Y': 1670 // 'Y' is the first character for several 2-character constraints. 1671 switch (Constraint[1]) { 1672 default: 1673 return false; 1674 case 'm': 1675 // 'Ym' is synonymous with 'y'. 1676 case 'k': 1677 return Size <= 64; 1678 case 'z': 1679 case '0': 1680 // XMM0 1681 if (SSELevel >= SSE1) 1682 return Size <= 128U; 1683 return false; 1684 case 'i': 1685 case 't': 1686 case '2': 1687 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1688 if (SSELevel < SSE2) 1689 return false; 1690 break; 1691 } 1692 LLVM_FALLTHROUGH; 1693 case 'v': 1694 case 'x': 1695 if (SSELevel >= AVX512F) 1696 // 512-bit zmm registers can be used if target supports AVX512F. 1697 return Size <= 512U; 1698 else if (SSELevel >= AVX) 1699 // 256-bit ymm registers can be used if target supports AVX. 1700 return Size <= 256U; 1701 return Size <= 128U; 1702 1703 } 1704 1705 return true; 1706 } 1707 1708 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1709 switch (*Constraint) { 1710 case 'a': 1711 return std::string("{ax}"); 1712 case 'b': 1713 return std::string("{bx}"); 1714 case 'c': 1715 return std::string("{cx}"); 1716 case 'd': 1717 return std::string("{dx}"); 1718 case 'S': 1719 return std::string("{si}"); 1720 case 'D': 1721 return std::string("{di}"); 1722 case 'p': // address 1723 return std::string("im"); 1724 case 't': // top of floating point stack. 1725 return std::string("{st}"); 1726 case 'u': // second from top of floating point stack. 1727 return std::string("{st(1)}"); // second from top of floating point stack. 1728 case 'Y': 1729 switch (Constraint[1]) { 1730 default: 1731 // Break from inner switch and fall through (copy single char), 1732 // continue parsing after copying the current constraint into 1733 // the return string. 1734 break; 1735 case 'k': 1736 case 'm': 1737 case 'i': 1738 case 't': 1739 case 'z': 1740 case '0': 1741 case '2': 1742 // "^" hints llvm that this is a 2 letter constraint. 1743 // "Constraint++" is used to promote the string iterator 1744 // to the next constraint. 1745 return std::string("^") + std::string(Constraint++, 2); 1746 } 1747 LLVM_FALLTHROUGH; 1748 default: 1749 return std::string(1, *Constraint); 1750 } 1751 } 1752 1753 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1754 // Perform any per-CPU checks necessary to determine if this CPU is 1755 // acceptable. 1756 switch (Kind) { 1757 case CK_Generic: 1758 // No processor selected! 1759 return false; 1760 #define PROC(ENUM, STRING, IS64BIT) \ 1761 case CK_##ENUM: \ 1762 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1763 #include "clang/Basic/X86Target.def" 1764 } 1765 llvm_unreachable("Unhandled CPU kind"); 1766 } 1767 1768 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1769 #define PROC(ENUM, STRING, IS64BIT) \ 1770 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1771 Values.emplace_back(STRING); 1772 // Go through CPUKind checking to ensure that the alias is de-aliased and 1773 // 64 bit-ness is checked. 1774 #define PROC_ALIAS(ENUM, ALIAS) \ 1775 if (checkCPUKind(getCPUKind(ALIAS))) \ 1776 Values.emplace_back(ALIAS); 1777 #include "clang/Basic/X86Target.def" 1778 } 1779 1780 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1781 return llvm::StringSwitch<CPUKind>(CPU) 1782 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1783 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1784 #include "clang/Basic/X86Target.def" 1785 .Default(CK_Generic); 1786 } 1787 1788 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1789 return llvm::makeArrayRef(GCCRegNames); 1790 } 1791 1792 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1793 return llvm::makeArrayRef(AddlRegNames); 1794 } 1795 1796 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1797 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1798 Builtin::FirstTSBuiltin + 1); 1799 } 1800 1801 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1802 return llvm::makeArrayRef(BuiltinInfoX86, 1803 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1804 } 1805