1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabledImpl(Features, "sse2", true); 112 113 const CPUKind Kind = getCPUKind(CPU); 114 115 // Enable X87 for all X86 processors but Lakemont. 116 if (Kind != CK_Lakemont) 117 setFeatureEnabledImpl(Features, "x87", true); 118 119 switch (Kind) { 120 case CK_Generic: 121 case CK_i386: 122 case CK_i486: 123 case CK_i586: 124 case CK_Pentium: 125 case CK_PentiumPro: 126 case CK_Lakemont: 127 break; 128 129 case CK_PentiumMMX: 130 case CK_Pentium2: 131 case CK_K6: 132 case CK_WinChipC6: 133 setFeatureEnabledImpl(Features, "mmx", true); 134 break; 135 136 case CK_IcelakeServer: 137 setFeatureEnabledImpl(Features, "pconfig", true); 138 setFeatureEnabledImpl(Features, "wbnoinvd", true); 139 LLVM_FALLTHROUGH; 140 case CK_IcelakeClient: 141 setFeatureEnabledImpl(Features, "vaes", true); 142 setFeatureEnabledImpl(Features, "gfni", true); 143 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 144 setFeatureEnabledImpl(Features, "avx512bitalg", true); 145 setFeatureEnabledImpl(Features, "avx512vnni", true); 146 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 147 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 148 setFeatureEnabledImpl(Features, "rdpid", true); 149 LLVM_FALLTHROUGH; 150 case CK_Cannonlake: 151 setFeatureEnabledImpl(Features, "avx512ifma", true); 152 setFeatureEnabledImpl(Features, "avx512vbmi", true); 153 setFeatureEnabledImpl(Features, "sha", true); 154 LLVM_FALLTHROUGH; 155 case CK_SkylakeServer: 156 setFeatureEnabledImpl(Features, "avx512f", true); 157 setFeatureEnabledImpl(Features, "avx512cd", true); 158 setFeatureEnabledImpl(Features, "avx512dq", true); 159 setFeatureEnabledImpl(Features, "avx512bw", true); 160 setFeatureEnabledImpl(Features, "avx512vl", true); 161 setFeatureEnabledImpl(Features, "pku", true); 162 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 163 setFeatureEnabledImpl(Features, "clwb", true); 164 LLVM_FALLTHROUGH; 165 case CK_SkylakeClient: 166 setFeatureEnabledImpl(Features, "xsavec", true); 167 setFeatureEnabledImpl(Features, "xsaves", true); 168 setFeatureEnabledImpl(Features, "mpx", true); 169 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 170 setFeatureEnabledImpl(Features, "sgx", true); 171 setFeatureEnabledImpl(Features, "clflushopt", true); 172 setFeatureEnabledImpl(Features, "rtm", true); 173 LLVM_FALLTHROUGH; 174 case CK_Broadwell: 175 setFeatureEnabledImpl(Features, "rdseed", true); 176 setFeatureEnabledImpl(Features, "adx", true); 177 setFeatureEnabledImpl(Features, "prfchw", true); 178 LLVM_FALLTHROUGH; 179 case CK_Haswell: 180 setFeatureEnabledImpl(Features, "avx2", true); 181 setFeatureEnabledImpl(Features, "lzcnt", true); 182 setFeatureEnabledImpl(Features, "bmi", true); 183 setFeatureEnabledImpl(Features, "bmi2", true); 184 setFeatureEnabledImpl(Features, "fma", true); 185 setFeatureEnabledImpl(Features, "invpcid", true); 186 setFeatureEnabledImpl(Features, "movbe", true); 187 LLVM_FALLTHROUGH; 188 case CK_IvyBridge: 189 setFeatureEnabledImpl(Features, "rdrnd", true); 190 setFeatureEnabledImpl(Features, "f16c", true); 191 setFeatureEnabledImpl(Features, "fsgsbase", true); 192 LLVM_FALLTHROUGH; 193 case CK_SandyBridge: 194 setFeatureEnabledImpl(Features, "avx", true); 195 setFeatureEnabledImpl(Features, "xsave", true); 196 setFeatureEnabledImpl(Features, "xsaveopt", true); 197 LLVM_FALLTHROUGH; 198 case CK_Westmere: 199 setFeatureEnabledImpl(Features, "aes", true); 200 setFeatureEnabledImpl(Features, "pclmul", true); 201 LLVM_FALLTHROUGH; 202 case CK_Nehalem: 203 setFeatureEnabledImpl(Features, "sse4.2", true); 204 LLVM_FALLTHROUGH; 205 case CK_Penryn: 206 setFeatureEnabledImpl(Features, "sse4.1", true); 207 LLVM_FALLTHROUGH; 208 case CK_Core2: 209 setFeatureEnabledImpl(Features, "ssse3", true); 210 setFeatureEnabledImpl(Features, "sahf", true); 211 LLVM_FALLTHROUGH; 212 case CK_Yonah: 213 case CK_Prescott: 214 case CK_Nocona: 215 setFeatureEnabledImpl(Features, "sse3", true); 216 setFeatureEnabledImpl(Features, "cx16", true); 217 LLVM_FALLTHROUGH; 218 case CK_PentiumM: 219 case CK_Pentium4: 220 case CK_x86_64: 221 setFeatureEnabledImpl(Features, "sse2", true); 222 LLVM_FALLTHROUGH; 223 case CK_Pentium3: 224 case CK_C3_2: 225 setFeatureEnabledImpl(Features, "sse", true); 226 setFeatureEnabledImpl(Features, "fxsr", true); 227 break; 228 229 case CK_Tremont: 230 setFeatureEnabledImpl(Features, "cldemote", true); 231 setFeatureEnabledImpl(Features, "movdiri", true); 232 setFeatureEnabledImpl(Features, "movdir64b", true); 233 setFeatureEnabledImpl(Features, "gfni", true); 234 setFeatureEnabledImpl(Features, "waitpkg", true); 235 LLVM_FALLTHROUGH; 236 case CK_GoldmontPlus: 237 setFeatureEnabledImpl(Features, "ptwrite", true); 238 setFeatureEnabledImpl(Features, "rdpid", true); 239 setFeatureEnabledImpl(Features, "sgx", true); 240 LLVM_FALLTHROUGH; 241 case CK_Goldmont: 242 setFeatureEnabledImpl(Features, "sha", true); 243 setFeatureEnabledImpl(Features, "rdseed", true); 244 setFeatureEnabledImpl(Features, "xsave", true); 245 setFeatureEnabledImpl(Features, "xsaveopt", true); 246 setFeatureEnabledImpl(Features, "xsavec", true); 247 setFeatureEnabledImpl(Features, "xsaves", true); 248 setFeatureEnabledImpl(Features, "clflushopt", true); 249 setFeatureEnabledImpl(Features, "mpx", true); 250 setFeatureEnabledImpl(Features, "fsgsbase", true); 251 LLVM_FALLTHROUGH; 252 case CK_Silvermont: 253 setFeatureEnabledImpl(Features, "rdrnd", true); 254 setFeatureEnabledImpl(Features, "aes", true); 255 setFeatureEnabledImpl(Features, "pclmul", true); 256 setFeatureEnabledImpl(Features, "sse4.2", true); 257 setFeatureEnabledImpl(Features, "prfchw", true); 258 LLVM_FALLTHROUGH; 259 case CK_Bonnell: 260 setFeatureEnabledImpl(Features, "movbe", true); 261 setFeatureEnabledImpl(Features, "ssse3", true); 262 setFeatureEnabledImpl(Features, "fxsr", true); 263 setFeatureEnabledImpl(Features, "cx16", true); 264 setFeatureEnabledImpl(Features, "sahf", true); 265 break; 266 267 case CK_KNM: 268 // TODO: Add avx5124fmaps/avx5124vnniw. 269 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 270 LLVM_FALLTHROUGH; 271 case CK_KNL: 272 setFeatureEnabledImpl(Features, "avx512f", true); 273 setFeatureEnabledImpl(Features, "avx512cd", true); 274 setFeatureEnabledImpl(Features, "avx512er", true); 275 setFeatureEnabledImpl(Features, "avx512pf", true); 276 setFeatureEnabledImpl(Features, "prfchw", true); 277 setFeatureEnabledImpl(Features, "prefetchwt1", true); 278 setFeatureEnabledImpl(Features, "fxsr", true); 279 setFeatureEnabledImpl(Features, "rdseed", true); 280 setFeatureEnabledImpl(Features, "adx", true); 281 setFeatureEnabledImpl(Features, "lzcnt", true); 282 setFeatureEnabledImpl(Features, "bmi", true); 283 setFeatureEnabledImpl(Features, "bmi2", true); 284 setFeatureEnabledImpl(Features, "rtm", true); 285 setFeatureEnabledImpl(Features, "fma", true); 286 setFeatureEnabledImpl(Features, "rdrnd", true); 287 setFeatureEnabledImpl(Features, "f16c", true); 288 setFeatureEnabledImpl(Features, "fsgsbase", true); 289 setFeatureEnabledImpl(Features, "aes", true); 290 setFeatureEnabledImpl(Features, "pclmul", true); 291 setFeatureEnabledImpl(Features, "cx16", true); 292 setFeatureEnabledImpl(Features, "xsaveopt", true); 293 setFeatureEnabledImpl(Features, "xsave", true); 294 setFeatureEnabledImpl(Features, "movbe", true); 295 setFeatureEnabledImpl(Features, "sahf", true); 296 break; 297 298 case CK_K6_2: 299 case CK_K6_3: 300 case CK_WinChip2: 301 case CK_C3: 302 setFeatureEnabledImpl(Features, "3dnow", true); 303 break; 304 305 case CK_AMDFAM10: 306 setFeatureEnabledImpl(Features, "sse4a", true); 307 setFeatureEnabledImpl(Features, "lzcnt", true); 308 setFeatureEnabledImpl(Features, "popcnt", true); 309 setFeatureEnabledImpl(Features, "sahf", true); 310 LLVM_FALLTHROUGH; 311 case CK_K8SSE3: 312 setFeatureEnabledImpl(Features, "sse3", true); 313 LLVM_FALLTHROUGH; 314 case CK_K8: 315 setFeatureEnabledImpl(Features, "sse2", true); 316 LLVM_FALLTHROUGH; 317 case CK_AthlonXP: 318 setFeatureEnabledImpl(Features, "sse", true); 319 setFeatureEnabledImpl(Features, "fxsr", true); 320 LLVM_FALLTHROUGH; 321 case CK_Athlon: 322 case CK_Geode: 323 setFeatureEnabledImpl(Features, "3dnowa", true); 324 break; 325 326 case CK_BTVER2: 327 setFeatureEnabledImpl(Features, "avx", true); 328 setFeatureEnabledImpl(Features, "aes", true); 329 setFeatureEnabledImpl(Features, "pclmul", true); 330 setFeatureEnabledImpl(Features, "bmi", true); 331 setFeatureEnabledImpl(Features, "f16c", true); 332 setFeatureEnabledImpl(Features, "xsaveopt", true); 333 setFeatureEnabledImpl(Features, "movbe", true); 334 LLVM_FALLTHROUGH; 335 case CK_BTVER1: 336 setFeatureEnabledImpl(Features, "ssse3", true); 337 setFeatureEnabledImpl(Features, "sse4a", true); 338 setFeatureEnabledImpl(Features, "lzcnt", true); 339 setFeatureEnabledImpl(Features, "popcnt", true); 340 setFeatureEnabledImpl(Features, "prfchw", true); 341 setFeatureEnabledImpl(Features, "cx16", true); 342 setFeatureEnabledImpl(Features, "fxsr", true); 343 setFeatureEnabledImpl(Features, "sahf", true); 344 break; 345 346 case CK_ZNVER1: 347 setFeatureEnabledImpl(Features, "adx", true); 348 setFeatureEnabledImpl(Features, "aes", true); 349 setFeatureEnabledImpl(Features, "avx2", true); 350 setFeatureEnabledImpl(Features, "bmi", true); 351 setFeatureEnabledImpl(Features, "bmi2", true); 352 setFeatureEnabledImpl(Features, "clflushopt", true); 353 setFeatureEnabledImpl(Features, "clzero", true); 354 setFeatureEnabledImpl(Features, "cx16", true); 355 setFeatureEnabledImpl(Features, "f16c", true); 356 setFeatureEnabledImpl(Features, "fma", true); 357 setFeatureEnabledImpl(Features, "fsgsbase", true); 358 setFeatureEnabledImpl(Features, "fxsr", true); 359 setFeatureEnabledImpl(Features, "lzcnt", true); 360 setFeatureEnabledImpl(Features, "mwaitx", true); 361 setFeatureEnabledImpl(Features, "movbe", true); 362 setFeatureEnabledImpl(Features, "pclmul", true); 363 setFeatureEnabledImpl(Features, "popcnt", true); 364 setFeatureEnabledImpl(Features, "prfchw", true); 365 setFeatureEnabledImpl(Features, "rdrnd", true); 366 setFeatureEnabledImpl(Features, "rdseed", true); 367 setFeatureEnabledImpl(Features, "sahf", true); 368 setFeatureEnabledImpl(Features, "sha", true); 369 setFeatureEnabledImpl(Features, "sse4a", true); 370 setFeatureEnabledImpl(Features, "xsave", true); 371 setFeatureEnabledImpl(Features, "xsavec", true); 372 setFeatureEnabledImpl(Features, "xsaveopt", true); 373 setFeatureEnabledImpl(Features, "xsaves", true); 374 break; 375 376 case CK_BDVER4: 377 setFeatureEnabledImpl(Features, "avx2", true); 378 setFeatureEnabledImpl(Features, "bmi2", true); 379 setFeatureEnabledImpl(Features, "mwaitx", true); 380 LLVM_FALLTHROUGH; 381 case CK_BDVER3: 382 setFeatureEnabledImpl(Features, "fsgsbase", true); 383 setFeatureEnabledImpl(Features, "xsaveopt", true); 384 LLVM_FALLTHROUGH; 385 case CK_BDVER2: 386 setFeatureEnabledImpl(Features, "bmi", true); 387 setFeatureEnabledImpl(Features, "fma", true); 388 setFeatureEnabledImpl(Features, "f16c", true); 389 setFeatureEnabledImpl(Features, "tbm", true); 390 LLVM_FALLTHROUGH; 391 case CK_BDVER1: 392 // xop implies avx, sse4a and fma4. 393 setFeatureEnabledImpl(Features, "xop", true); 394 setFeatureEnabledImpl(Features, "lwp", true); 395 setFeatureEnabledImpl(Features, "lzcnt", true); 396 setFeatureEnabledImpl(Features, "aes", true); 397 setFeatureEnabledImpl(Features, "pclmul", true); 398 setFeatureEnabledImpl(Features, "prfchw", true); 399 setFeatureEnabledImpl(Features, "cx16", true); 400 setFeatureEnabledImpl(Features, "fxsr", true); 401 setFeatureEnabledImpl(Features, "xsave", true); 402 setFeatureEnabledImpl(Features, "sahf", true); 403 break; 404 } 405 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 406 return false; 407 408 // Can't do this earlier because we need to be able to explicitly enable 409 // or disable these features and the things that they depend upon. 410 411 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 412 auto I = Features.find("sse4.2"); 413 if (I != Features.end() && I->getValue() && 414 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 415 FeaturesVec.end()) 416 Features["popcnt"] = true; 417 418 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 419 I = Features.find("3dnow"); 420 if (I != Features.end() && I->getValue() && 421 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 422 FeaturesVec.end()) 423 Features["prfchw"] = true; 424 425 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 426 // then enable MMX. 427 I = Features.find("sse"); 428 if (I != Features.end() && I->getValue() && 429 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 430 FeaturesVec.end()) 431 Features["mmx"] = true; 432 433 return true; 434 } 435 436 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 437 X86SSEEnum Level, bool Enabled) { 438 if (Enabled) { 439 switch (Level) { 440 case AVX512F: 441 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 442 LLVM_FALLTHROUGH; 443 case AVX2: 444 Features["avx2"] = true; 445 LLVM_FALLTHROUGH; 446 case AVX: 447 Features["avx"] = true; 448 Features["xsave"] = true; 449 LLVM_FALLTHROUGH; 450 case SSE42: 451 Features["sse4.2"] = true; 452 LLVM_FALLTHROUGH; 453 case SSE41: 454 Features["sse4.1"] = true; 455 LLVM_FALLTHROUGH; 456 case SSSE3: 457 Features["ssse3"] = true; 458 LLVM_FALLTHROUGH; 459 case SSE3: 460 Features["sse3"] = true; 461 LLVM_FALLTHROUGH; 462 case SSE2: 463 Features["sse2"] = true; 464 LLVM_FALLTHROUGH; 465 case SSE1: 466 Features["sse"] = true; 467 LLVM_FALLTHROUGH; 468 case NoSSE: 469 break; 470 } 471 return; 472 } 473 474 switch (Level) { 475 case NoSSE: 476 case SSE1: 477 Features["sse"] = false; 478 LLVM_FALLTHROUGH; 479 case SSE2: 480 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 481 Features["gfni"] = false; 482 LLVM_FALLTHROUGH; 483 case SSE3: 484 Features["sse3"] = false; 485 setXOPLevel(Features, NoXOP, false); 486 LLVM_FALLTHROUGH; 487 case SSSE3: 488 Features["ssse3"] = false; 489 LLVM_FALLTHROUGH; 490 case SSE41: 491 Features["sse4.1"] = false; 492 LLVM_FALLTHROUGH; 493 case SSE42: 494 Features["sse4.2"] = false; 495 LLVM_FALLTHROUGH; 496 case AVX: 497 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 498 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 499 setXOPLevel(Features, FMA4, false); 500 LLVM_FALLTHROUGH; 501 case AVX2: 502 Features["avx2"] = false; 503 LLVM_FALLTHROUGH; 504 case AVX512F: 505 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 506 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 507 Features["avx512vl"] = Features["avx512vbmi"] = 508 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 509 Features["avx512bitalg"] = Features["avx512vnni"] = 510 Features["avx512vbmi2"] = false; 511 break; 512 } 513 } 514 515 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 516 MMX3DNowEnum Level, bool Enabled) { 517 if (Enabled) { 518 switch (Level) { 519 case AMD3DNowAthlon: 520 Features["3dnowa"] = true; 521 LLVM_FALLTHROUGH; 522 case AMD3DNow: 523 Features["3dnow"] = true; 524 LLVM_FALLTHROUGH; 525 case MMX: 526 Features["mmx"] = true; 527 LLVM_FALLTHROUGH; 528 case NoMMX3DNow: 529 break; 530 } 531 return; 532 } 533 534 switch (Level) { 535 case NoMMX3DNow: 536 case MMX: 537 Features["mmx"] = false; 538 LLVM_FALLTHROUGH; 539 case AMD3DNow: 540 Features["3dnow"] = false; 541 LLVM_FALLTHROUGH; 542 case AMD3DNowAthlon: 543 Features["3dnowa"] = false; 544 break; 545 } 546 } 547 548 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 549 bool Enabled) { 550 if (Enabled) { 551 switch (Level) { 552 case XOP: 553 Features["xop"] = true; 554 LLVM_FALLTHROUGH; 555 case FMA4: 556 Features["fma4"] = true; 557 setSSELevel(Features, AVX, true); 558 LLVM_FALLTHROUGH; 559 case SSE4A: 560 Features["sse4a"] = true; 561 setSSELevel(Features, SSE3, true); 562 LLVM_FALLTHROUGH; 563 case NoXOP: 564 break; 565 } 566 return; 567 } 568 569 switch (Level) { 570 case NoXOP: 571 case SSE4A: 572 Features["sse4a"] = false; 573 LLVM_FALLTHROUGH; 574 case FMA4: 575 Features["fma4"] = false; 576 LLVM_FALLTHROUGH; 577 case XOP: 578 Features["xop"] = false; 579 break; 580 } 581 } 582 583 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 584 StringRef Name, bool Enabled) { 585 // This is a bit of a hack to deal with the sse4 target feature when used 586 // as part of the target attribute. We handle sse4 correctly everywhere 587 // else. See below for more information on how we handle the sse4 options. 588 if (Name != "sse4") 589 Features[Name] = Enabled; 590 591 if (Name == "mmx") { 592 setMMXLevel(Features, MMX, Enabled); 593 } else if (Name == "sse") { 594 setSSELevel(Features, SSE1, Enabled); 595 } else if (Name == "sse2") { 596 setSSELevel(Features, SSE2, Enabled); 597 } else if (Name == "sse3") { 598 setSSELevel(Features, SSE3, Enabled); 599 } else if (Name == "ssse3") { 600 setSSELevel(Features, SSSE3, Enabled); 601 } else if (Name == "sse4.2") { 602 setSSELevel(Features, SSE42, Enabled); 603 } else if (Name == "sse4.1") { 604 setSSELevel(Features, SSE41, Enabled); 605 } else if (Name == "3dnow") { 606 setMMXLevel(Features, AMD3DNow, Enabled); 607 } else if (Name == "3dnowa") { 608 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 609 } else if (Name == "aes") { 610 if (Enabled) 611 setSSELevel(Features, SSE2, Enabled); 612 else 613 Features["vaes"] = false; 614 } else if (Name == "vaes") { 615 if (Enabled) { 616 setSSELevel(Features, AVX, Enabled); 617 Features["aes"] = true; 618 } 619 } else if (Name == "pclmul") { 620 if (Enabled) 621 setSSELevel(Features, SSE2, Enabled); 622 else 623 Features["vpclmulqdq"] = false; 624 } else if (Name == "vpclmulqdq") { 625 if (Enabled) { 626 setSSELevel(Features, AVX, Enabled); 627 Features["pclmul"] = true; 628 } 629 } else if (Name == "gfni") { 630 if (Enabled) 631 setSSELevel(Features, SSE2, Enabled); 632 } else if (Name == "avx") { 633 setSSELevel(Features, AVX, Enabled); 634 } else if (Name == "avx2") { 635 setSSELevel(Features, AVX2, Enabled); 636 } else if (Name == "avx512f") { 637 setSSELevel(Features, AVX512F, Enabled); 638 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 639 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 640 Name == "avx512vbmi" || Name == "avx512ifma" || 641 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 642 Name == "avx512vnni" || Name == "avx512vbmi2") { 643 if (Enabled) 644 setSSELevel(Features, AVX512F, Enabled); 645 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 646 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 647 Features["avx512bw"] = true; 648 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 649 if (Name == "avx512bw" && !Enabled) 650 Features["avx512vbmi"] = Features["avx512vbmi2"] = 651 Features["avx512bitalg"] = false; 652 } else if (Name == "fma") { 653 if (Enabled) 654 setSSELevel(Features, AVX, Enabled); 655 else 656 setSSELevel(Features, AVX512F, Enabled); 657 } else if (Name == "fma4") { 658 setXOPLevel(Features, FMA4, Enabled); 659 } else if (Name == "xop") { 660 setXOPLevel(Features, XOP, Enabled); 661 } else if (Name == "sse4a") { 662 setXOPLevel(Features, SSE4A, Enabled); 663 } else if (Name == "f16c") { 664 if (Enabled) 665 setSSELevel(Features, AVX, Enabled); 666 else 667 setSSELevel(Features, AVX512F, Enabled); 668 } else if (Name == "sha") { 669 if (Enabled) 670 setSSELevel(Features, SSE2, Enabled); 671 } else if (Name == "sse4") { 672 // We can get here via the __target__ attribute since that's not controlled 673 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 674 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 675 // disabled. 676 if (Enabled) 677 setSSELevel(Features, SSE42, Enabled); 678 else 679 setSSELevel(Features, SSE41, Enabled); 680 } else if (Name == "xsave") { 681 if (!Enabled) 682 Features["xsaveopt"] = false; 683 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 684 if (Enabled) 685 Features["xsave"] = true; 686 } 687 } 688 689 /// handleTargetFeatures - Perform initialization based on the user 690 /// configured set of features. 691 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 692 DiagnosticsEngine &Diags) { 693 for (const auto &Feature : Features) { 694 if (Feature[0] != '+') 695 continue; 696 697 if (Feature == "+aes") { 698 HasAES = true; 699 } else if (Feature == "+vaes") { 700 HasVAES = true; 701 } else if (Feature == "+pclmul") { 702 HasPCLMUL = true; 703 } else if (Feature == "+vpclmulqdq") { 704 HasVPCLMULQDQ = true; 705 } else if (Feature == "+lzcnt") { 706 HasLZCNT = true; 707 } else if (Feature == "+rdrnd") { 708 HasRDRND = true; 709 } else if (Feature == "+fsgsbase") { 710 HasFSGSBASE = true; 711 } else if (Feature == "+bmi") { 712 HasBMI = true; 713 } else if (Feature == "+bmi2") { 714 HasBMI2 = true; 715 } else if (Feature == "+popcnt") { 716 HasPOPCNT = true; 717 } else if (Feature == "+rtm") { 718 HasRTM = true; 719 } else if (Feature == "+prfchw") { 720 HasPRFCHW = true; 721 } else if (Feature == "+rdseed") { 722 HasRDSEED = true; 723 } else if (Feature == "+adx") { 724 HasADX = true; 725 } else if (Feature == "+tbm") { 726 HasTBM = true; 727 } else if (Feature == "+lwp") { 728 HasLWP = true; 729 } else if (Feature == "+fma") { 730 HasFMA = true; 731 } else if (Feature == "+f16c") { 732 HasF16C = true; 733 } else if (Feature == "+gfni") { 734 HasGFNI = true; 735 } else if (Feature == "+avx512cd") { 736 HasAVX512CD = true; 737 } else if (Feature == "+avx512vpopcntdq") { 738 HasAVX512VPOPCNTDQ = true; 739 } else if (Feature == "+avx512vnni") { 740 HasAVX512VNNI = true; 741 } else if (Feature == "+avx512er") { 742 HasAVX512ER = true; 743 } else if (Feature == "+avx512pf") { 744 HasAVX512PF = true; 745 } else if (Feature == "+avx512dq") { 746 HasAVX512DQ = true; 747 } else if (Feature == "+avx512bitalg") { 748 HasAVX512BITALG = true; 749 } else if (Feature == "+avx512bw") { 750 HasAVX512BW = true; 751 } else if (Feature == "+avx512vl") { 752 HasAVX512VL = true; 753 } else if (Feature == "+avx512vbmi") { 754 HasAVX512VBMI = true; 755 } else if (Feature == "+avx512vbmi2") { 756 HasAVX512VBMI2 = true; 757 } else if (Feature == "+avx512ifma") { 758 HasAVX512IFMA = true; 759 } else if (Feature == "+sha") { 760 HasSHA = true; 761 } else if (Feature == "+mpx") { 762 HasMPX = true; 763 } else if (Feature == "+shstk") { 764 HasSHSTK = true; 765 } else if (Feature == "+movbe") { 766 HasMOVBE = true; 767 } else if (Feature == "+sgx") { 768 HasSGX = true; 769 } else if (Feature == "+cx16") { 770 HasCX16 = true; 771 } else if (Feature == "+fxsr") { 772 HasFXSR = true; 773 } else if (Feature == "+xsave") { 774 HasXSAVE = true; 775 } else if (Feature == "+xsaveopt") { 776 HasXSAVEOPT = true; 777 } else if (Feature == "+xsavec") { 778 HasXSAVEC = true; 779 } else if (Feature == "+xsaves") { 780 HasXSAVES = true; 781 } else if (Feature == "+mwaitx") { 782 HasMWAITX = true; 783 } else if (Feature == "+pku") { 784 HasPKU = true; 785 } else if (Feature == "+clflushopt") { 786 HasCLFLUSHOPT = true; 787 } else if (Feature == "+clwb") { 788 HasCLWB = true; 789 } else if (Feature == "+wbnoinvd") { 790 HasWBNOINVD = true; 791 } else if (Feature == "+prefetchwt1") { 792 HasPREFETCHWT1 = true; 793 } else if (Feature == "+clzero") { 794 HasCLZERO = true; 795 } else if (Feature == "+cldemote") { 796 HasCLDEMOTE = true; 797 } else if (Feature == "+rdpid") { 798 HasRDPID = true; 799 } else if (Feature == "+retpoline") { 800 HasRetpoline = true; 801 } else if (Feature == "+retpoline-external-thunk") { 802 HasRetpolineExternalThunk = true; 803 } else if (Feature == "+sahf") { 804 HasLAHFSAHF = true; 805 } else if (Feature == "+waitpkg") { 806 HasWAITPKG = true; 807 } else if (Feature == "+movdiri") { 808 HasMOVDIRI = true; 809 } else if (Feature == "+movdir64b") { 810 HasMOVDIR64B = true; 811 } else if (Feature == "+pconfig") { 812 HasPCONFIG = true; 813 } else if (Feature == "+ptwrite") { 814 HasPTWRITE = true; 815 } else if (Feature == "+invpcid") { 816 HasINVPCID = true; 817 } 818 819 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 820 .Case("+avx512f", AVX512F) 821 .Case("+avx2", AVX2) 822 .Case("+avx", AVX) 823 .Case("+sse4.2", SSE42) 824 .Case("+sse4.1", SSE41) 825 .Case("+ssse3", SSSE3) 826 .Case("+sse3", SSE3) 827 .Case("+sse2", SSE2) 828 .Case("+sse", SSE1) 829 .Default(NoSSE); 830 SSELevel = std::max(SSELevel, Level); 831 832 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 833 .Case("+3dnowa", AMD3DNowAthlon) 834 .Case("+3dnow", AMD3DNow) 835 .Case("+mmx", MMX) 836 .Default(NoMMX3DNow); 837 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 838 839 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 840 .Case("+xop", XOP) 841 .Case("+fma4", FMA4) 842 .Case("+sse4a", SSE4A) 843 .Default(NoXOP); 844 XOPLevel = std::max(XOPLevel, XLevel); 845 } 846 847 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 848 // matches the selected sse level. 849 if ((FPMath == FP_SSE && SSELevel < SSE1) || 850 (FPMath == FP_387 && SSELevel >= SSE1)) { 851 Diags.Report(diag::err_target_unsupported_fpmath) 852 << (FPMath == FP_SSE ? "sse" : "387"); 853 return false; 854 } 855 856 SimdDefaultAlign = 857 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 858 return true; 859 } 860 861 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 862 /// definitions for this particular subtarget. 863 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 864 MacroBuilder &Builder) const { 865 // Target identification. 866 if (getTriple().getArch() == llvm::Triple::x86_64) { 867 Builder.defineMacro("__amd64__"); 868 Builder.defineMacro("__amd64"); 869 Builder.defineMacro("__x86_64"); 870 Builder.defineMacro("__x86_64__"); 871 if (getTriple().getArchName() == "x86_64h") { 872 Builder.defineMacro("__x86_64h"); 873 Builder.defineMacro("__x86_64h__"); 874 } 875 } else { 876 DefineStd(Builder, "i386", Opts); 877 } 878 879 // Subtarget options. 880 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 881 // truly should be based on -mtune options. 882 switch (CPU) { 883 case CK_Generic: 884 break; 885 case CK_i386: 886 // The rest are coming from the i386 define above. 887 Builder.defineMacro("__tune_i386__"); 888 break; 889 case CK_i486: 890 case CK_WinChipC6: 891 case CK_WinChip2: 892 case CK_C3: 893 defineCPUMacros(Builder, "i486"); 894 break; 895 case CK_PentiumMMX: 896 Builder.defineMacro("__pentium_mmx__"); 897 Builder.defineMacro("__tune_pentium_mmx__"); 898 LLVM_FALLTHROUGH; 899 case CK_i586: 900 case CK_Pentium: 901 defineCPUMacros(Builder, "i586"); 902 defineCPUMacros(Builder, "pentium"); 903 break; 904 case CK_Pentium3: 905 case CK_PentiumM: 906 Builder.defineMacro("__tune_pentium3__"); 907 LLVM_FALLTHROUGH; 908 case CK_Pentium2: 909 case CK_C3_2: 910 Builder.defineMacro("__tune_pentium2__"); 911 LLVM_FALLTHROUGH; 912 case CK_PentiumPro: 913 defineCPUMacros(Builder, "i686"); 914 defineCPUMacros(Builder, "pentiumpro"); 915 break; 916 case CK_Pentium4: 917 defineCPUMacros(Builder, "pentium4"); 918 break; 919 case CK_Yonah: 920 case CK_Prescott: 921 case CK_Nocona: 922 defineCPUMacros(Builder, "nocona"); 923 break; 924 case CK_Core2: 925 case CK_Penryn: 926 defineCPUMacros(Builder, "core2"); 927 break; 928 case CK_Bonnell: 929 defineCPUMacros(Builder, "atom"); 930 break; 931 case CK_Silvermont: 932 defineCPUMacros(Builder, "slm"); 933 break; 934 case CK_Goldmont: 935 defineCPUMacros(Builder, "goldmont"); 936 break; 937 case CK_GoldmontPlus: 938 defineCPUMacros(Builder, "goldmont_plus"); 939 break; 940 case CK_Tremont: 941 defineCPUMacros(Builder, "tremont"); 942 break; 943 case CK_Nehalem: 944 case CK_Westmere: 945 case CK_SandyBridge: 946 case CK_IvyBridge: 947 case CK_Haswell: 948 case CK_Broadwell: 949 case CK_SkylakeClient: 950 case CK_SkylakeServer: 951 case CK_Cannonlake: 952 case CK_IcelakeClient: 953 case CK_IcelakeServer: 954 // FIXME: Historically, we defined this legacy name, it would be nice to 955 // remove it at some point. We've never exposed fine-grained names for 956 // recent primary x86 CPUs, and we should keep it that way. 957 defineCPUMacros(Builder, "corei7"); 958 break; 959 case CK_KNL: 960 defineCPUMacros(Builder, "knl"); 961 break; 962 case CK_KNM: 963 break; 964 case CK_Lakemont: 965 defineCPUMacros(Builder, "i586", /*Tuning*/false); 966 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 967 Builder.defineMacro("__tune_lakemont__"); 968 break; 969 case CK_K6_2: 970 Builder.defineMacro("__k6_2__"); 971 Builder.defineMacro("__tune_k6_2__"); 972 LLVM_FALLTHROUGH; 973 case CK_K6_3: 974 if (CPU != CK_K6_2) { // In case of fallthrough 975 // FIXME: GCC may be enabling these in cases where some other k6 976 // architecture is specified but -m3dnow is explicitly provided. The 977 // exact semantics need to be determined and emulated here. 978 Builder.defineMacro("__k6_3__"); 979 Builder.defineMacro("__tune_k6_3__"); 980 } 981 LLVM_FALLTHROUGH; 982 case CK_K6: 983 defineCPUMacros(Builder, "k6"); 984 break; 985 case CK_Athlon: 986 case CK_AthlonXP: 987 defineCPUMacros(Builder, "athlon"); 988 if (SSELevel != NoSSE) { 989 Builder.defineMacro("__athlon_sse__"); 990 Builder.defineMacro("__tune_athlon_sse__"); 991 } 992 break; 993 case CK_K8: 994 case CK_K8SSE3: 995 case CK_x86_64: 996 defineCPUMacros(Builder, "k8"); 997 break; 998 case CK_AMDFAM10: 999 defineCPUMacros(Builder, "amdfam10"); 1000 break; 1001 case CK_BTVER1: 1002 defineCPUMacros(Builder, "btver1"); 1003 break; 1004 case CK_BTVER2: 1005 defineCPUMacros(Builder, "btver2"); 1006 break; 1007 case CK_BDVER1: 1008 defineCPUMacros(Builder, "bdver1"); 1009 break; 1010 case CK_BDVER2: 1011 defineCPUMacros(Builder, "bdver2"); 1012 break; 1013 case CK_BDVER3: 1014 defineCPUMacros(Builder, "bdver3"); 1015 break; 1016 case CK_BDVER4: 1017 defineCPUMacros(Builder, "bdver4"); 1018 break; 1019 case CK_ZNVER1: 1020 defineCPUMacros(Builder, "znver1"); 1021 break; 1022 case CK_Geode: 1023 defineCPUMacros(Builder, "geode"); 1024 break; 1025 } 1026 1027 // Target properties. 1028 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1029 1030 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1031 // functions in glibc header files that use FP Stack inline asm which the 1032 // backend can't deal with (PR879). 1033 Builder.defineMacro("__NO_MATH_INLINES"); 1034 1035 if (HasAES) 1036 Builder.defineMacro("__AES__"); 1037 1038 if (HasVAES) 1039 Builder.defineMacro("__VAES__"); 1040 1041 if (HasPCLMUL) 1042 Builder.defineMacro("__PCLMUL__"); 1043 1044 if (HasVPCLMULQDQ) 1045 Builder.defineMacro("__VPCLMULQDQ__"); 1046 1047 if (HasLZCNT) 1048 Builder.defineMacro("__LZCNT__"); 1049 1050 if (HasRDRND) 1051 Builder.defineMacro("__RDRND__"); 1052 1053 if (HasFSGSBASE) 1054 Builder.defineMacro("__FSGSBASE__"); 1055 1056 if (HasBMI) 1057 Builder.defineMacro("__BMI__"); 1058 1059 if (HasBMI2) 1060 Builder.defineMacro("__BMI2__"); 1061 1062 if (HasPOPCNT) 1063 Builder.defineMacro("__POPCNT__"); 1064 1065 if (HasRTM) 1066 Builder.defineMacro("__RTM__"); 1067 1068 if (HasPRFCHW) 1069 Builder.defineMacro("__PRFCHW__"); 1070 1071 if (HasRDSEED) 1072 Builder.defineMacro("__RDSEED__"); 1073 1074 if (HasADX) 1075 Builder.defineMacro("__ADX__"); 1076 1077 if (HasTBM) 1078 Builder.defineMacro("__TBM__"); 1079 1080 if (HasLWP) 1081 Builder.defineMacro("__LWP__"); 1082 1083 if (HasMWAITX) 1084 Builder.defineMacro("__MWAITX__"); 1085 1086 switch (XOPLevel) { 1087 case XOP: 1088 Builder.defineMacro("__XOP__"); 1089 LLVM_FALLTHROUGH; 1090 case FMA4: 1091 Builder.defineMacro("__FMA4__"); 1092 LLVM_FALLTHROUGH; 1093 case SSE4A: 1094 Builder.defineMacro("__SSE4A__"); 1095 LLVM_FALLTHROUGH; 1096 case NoXOP: 1097 break; 1098 } 1099 1100 if (HasFMA) 1101 Builder.defineMacro("__FMA__"); 1102 1103 if (HasF16C) 1104 Builder.defineMacro("__F16C__"); 1105 1106 if (HasGFNI) 1107 Builder.defineMacro("__GFNI__"); 1108 1109 if (HasAVX512CD) 1110 Builder.defineMacro("__AVX512CD__"); 1111 if (HasAVX512VPOPCNTDQ) 1112 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1113 if (HasAVX512VNNI) 1114 Builder.defineMacro("__AVX512VNNI__"); 1115 if (HasAVX512ER) 1116 Builder.defineMacro("__AVX512ER__"); 1117 if (HasAVX512PF) 1118 Builder.defineMacro("__AVX512PF__"); 1119 if (HasAVX512DQ) 1120 Builder.defineMacro("__AVX512DQ__"); 1121 if (HasAVX512BITALG) 1122 Builder.defineMacro("__AVX512BITALG__"); 1123 if (HasAVX512BW) 1124 Builder.defineMacro("__AVX512BW__"); 1125 if (HasAVX512VL) 1126 Builder.defineMacro("__AVX512VL__"); 1127 if (HasAVX512VBMI) 1128 Builder.defineMacro("__AVX512VBMI__"); 1129 if (HasAVX512VBMI2) 1130 Builder.defineMacro("__AVX512VBMI2__"); 1131 if (HasAVX512IFMA) 1132 Builder.defineMacro("__AVX512IFMA__"); 1133 1134 if (HasSHA) 1135 Builder.defineMacro("__SHA__"); 1136 1137 if (HasFXSR) 1138 Builder.defineMacro("__FXSR__"); 1139 if (HasXSAVE) 1140 Builder.defineMacro("__XSAVE__"); 1141 if (HasXSAVEOPT) 1142 Builder.defineMacro("__XSAVEOPT__"); 1143 if (HasXSAVEC) 1144 Builder.defineMacro("__XSAVEC__"); 1145 if (HasXSAVES) 1146 Builder.defineMacro("__XSAVES__"); 1147 if (HasPKU) 1148 Builder.defineMacro("__PKU__"); 1149 if (HasCLFLUSHOPT) 1150 Builder.defineMacro("__CLFLUSHOPT__"); 1151 if (HasCLWB) 1152 Builder.defineMacro("__CLWB__"); 1153 if (HasWBNOINVD) 1154 Builder.defineMacro("__WBNOINVD__"); 1155 if (HasMPX) 1156 Builder.defineMacro("__MPX__"); 1157 if (HasSHSTK) 1158 Builder.defineMacro("__SHSTK__"); 1159 if (HasSGX) 1160 Builder.defineMacro("__SGX__"); 1161 if (HasPREFETCHWT1) 1162 Builder.defineMacro("__PREFETCHWT1__"); 1163 if (HasCLZERO) 1164 Builder.defineMacro("__CLZERO__"); 1165 if (HasRDPID) 1166 Builder.defineMacro("__RDPID__"); 1167 if (HasCLDEMOTE) 1168 Builder.defineMacro("__CLDEMOTE__"); 1169 if (HasWAITPKG) 1170 Builder.defineMacro("__WAITPKG__"); 1171 if (HasMOVDIRI) 1172 Builder.defineMacro("__MOVDIRI__"); 1173 if (HasMOVDIR64B) 1174 Builder.defineMacro("__MOVDIR64B__"); 1175 if (HasPCONFIG) 1176 Builder.defineMacro("__PCONFIG__"); 1177 if (HasPTWRITE) 1178 Builder.defineMacro("__PTWRITE__"); 1179 if (HasINVPCID) 1180 Builder.defineMacro("__INVPCID__"); 1181 1182 // Each case falls through to the previous one here. 1183 switch (SSELevel) { 1184 case AVX512F: 1185 Builder.defineMacro("__AVX512F__"); 1186 LLVM_FALLTHROUGH; 1187 case AVX2: 1188 Builder.defineMacro("__AVX2__"); 1189 LLVM_FALLTHROUGH; 1190 case AVX: 1191 Builder.defineMacro("__AVX__"); 1192 LLVM_FALLTHROUGH; 1193 case SSE42: 1194 Builder.defineMacro("__SSE4_2__"); 1195 LLVM_FALLTHROUGH; 1196 case SSE41: 1197 Builder.defineMacro("__SSE4_1__"); 1198 LLVM_FALLTHROUGH; 1199 case SSSE3: 1200 Builder.defineMacro("__SSSE3__"); 1201 LLVM_FALLTHROUGH; 1202 case SSE3: 1203 Builder.defineMacro("__SSE3__"); 1204 LLVM_FALLTHROUGH; 1205 case SSE2: 1206 Builder.defineMacro("__SSE2__"); 1207 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1208 LLVM_FALLTHROUGH; 1209 case SSE1: 1210 Builder.defineMacro("__SSE__"); 1211 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1212 LLVM_FALLTHROUGH; 1213 case NoSSE: 1214 break; 1215 } 1216 1217 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1218 switch (SSELevel) { 1219 case AVX512F: 1220 case AVX2: 1221 case AVX: 1222 case SSE42: 1223 case SSE41: 1224 case SSSE3: 1225 case SSE3: 1226 case SSE2: 1227 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1228 break; 1229 case SSE1: 1230 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1231 break; 1232 default: 1233 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1234 break; 1235 } 1236 } 1237 1238 // Each case falls through to the previous one here. 1239 switch (MMX3DNowLevel) { 1240 case AMD3DNowAthlon: 1241 Builder.defineMacro("__3dNOW_A__"); 1242 LLVM_FALLTHROUGH; 1243 case AMD3DNow: 1244 Builder.defineMacro("__3dNOW__"); 1245 LLVM_FALLTHROUGH; 1246 case MMX: 1247 Builder.defineMacro("__MMX__"); 1248 LLVM_FALLTHROUGH; 1249 case NoMMX3DNow: 1250 break; 1251 } 1252 1253 if (CPU >= CK_i486) { 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1257 } 1258 if (CPU >= CK_i586) 1259 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1260 if (HasCX16) 1261 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1262 1263 if (HasFloat128) 1264 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1265 } 1266 1267 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1268 return llvm::StringSwitch<bool>(Name) 1269 .Case("3dnow", true) 1270 .Case("3dnowa", true) 1271 .Case("adx", true) 1272 .Case("aes", true) 1273 .Case("avx", true) 1274 .Case("avx2", true) 1275 .Case("avx512f", true) 1276 .Case("avx512cd", true) 1277 .Case("avx512vpopcntdq", true) 1278 .Case("avx512vnni", true) 1279 .Case("avx512er", true) 1280 .Case("avx512pf", true) 1281 .Case("avx512dq", true) 1282 .Case("avx512bitalg", true) 1283 .Case("avx512bw", true) 1284 .Case("avx512vl", true) 1285 .Case("avx512vbmi", true) 1286 .Case("avx512vbmi2", true) 1287 .Case("avx512ifma", true) 1288 .Case("bmi", true) 1289 .Case("bmi2", true) 1290 .Case("cldemote", true) 1291 .Case("clflushopt", true) 1292 .Case("clwb", true) 1293 .Case("clzero", true) 1294 .Case("cx16", true) 1295 .Case("f16c", true) 1296 .Case("fma", true) 1297 .Case("fma4", true) 1298 .Case("fsgsbase", true) 1299 .Case("fxsr", true) 1300 .Case("gfni", true) 1301 .Case("invpcid", true) 1302 .Case("lwp", true) 1303 .Case("lzcnt", true) 1304 .Case("mmx", true) 1305 .Case("movbe", true) 1306 .Case("movdiri", true) 1307 .Case("movdir64b", true) 1308 .Case("mpx", true) 1309 .Case("mwaitx", true) 1310 .Case("pclmul", true) 1311 .Case("pconfig", true) 1312 .Case("pku", true) 1313 .Case("popcnt", true) 1314 .Case("prefetchwt1", true) 1315 .Case("prfchw", true) 1316 .Case("ptwrite", true) 1317 .Case("rdpid", true) 1318 .Case("rdrnd", true) 1319 .Case("rdseed", true) 1320 .Case("rtm", true) 1321 .Case("sahf", true) 1322 .Case("sgx", true) 1323 .Case("sha", true) 1324 .Case("shstk", true) 1325 .Case("sse", true) 1326 .Case("sse2", true) 1327 .Case("sse3", true) 1328 .Case("ssse3", true) 1329 .Case("sse4", true) 1330 .Case("sse4.1", true) 1331 .Case("sse4.2", true) 1332 .Case("sse4a", true) 1333 .Case("tbm", true) 1334 .Case("vaes", true) 1335 .Case("vpclmulqdq", true) 1336 .Case("wbnoinvd", true) 1337 .Case("waitpkg", true) 1338 .Case("x87", true) 1339 .Case("xop", true) 1340 .Case("xsave", true) 1341 .Case("xsavec", true) 1342 .Case("xsaves", true) 1343 .Case("xsaveopt", true) 1344 .Default(false); 1345 } 1346 1347 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1348 return llvm::StringSwitch<bool>(Feature) 1349 .Case("adx", HasADX) 1350 .Case("aes", HasAES) 1351 .Case("avx", SSELevel >= AVX) 1352 .Case("avx2", SSELevel >= AVX2) 1353 .Case("avx512f", SSELevel >= AVX512F) 1354 .Case("avx512cd", HasAVX512CD) 1355 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1356 .Case("avx512vnni", HasAVX512VNNI) 1357 .Case("avx512er", HasAVX512ER) 1358 .Case("avx512pf", HasAVX512PF) 1359 .Case("avx512dq", HasAVX512DQ) 1360 .Case("avx512bitalg", HasAVX512BITALG) 1361 .Case("avx512bw", HasAVX512BW) 1362 .Case("avx512vl", HasAVX512VL) 1363 .Case("avx512vbmi", HasAVX512VBMI) 1364 .Case("avx512vbmi2", HasAVX512VBMI2) 1365 .Case("avx512ifma", HasAVX512IFMA) 1366 .Case("bmi", HasBMI) 1367 .Case("bmi2", HasBMI2) 1368 .Case("cldemote", HasCLDEMOTE) 1369 .Case("clflushopt", HasCLFLUSHOPT) 1370 .Case("clwb", HasCLWB) 1371 .Case("clzero", HasCLZERO) 1372 .Case("cx16", HasCX16) 1373 .Case("f16c", HasF16C) 1374 .Case("fma", HasFMA) 1375 .Case("fma4", XOPLevel >= FMA4) 1376 .Case("fsgsbase", HasFSGSBASE) 1377 .Case("fxsr", HasFXSR) 1378 .Case("gfni", HasGFNI) 1379 .Case("invpcid", HasINVPCID) 1380 .Case("lwp", HasLWP) 1381 .Case("lzcnt", HasLZCNT) 1382 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1383 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1384 .Case("mmx", MMX3DNowLevel >= MMX) 1385 .Case("movbe", HasMOVBE) 1386 .Case("movdiri", HasMOVDIRI) 1387 .Case("movdir64b", HasMOVDIR64B) 1388 .Case("mpx", HasMPX) 1389 .Case("mwaitx", HasMWAITX) 1390 .Case("pclmul", HasPCLMUL) 1391 .Case("pconfig", HasPCONFIG) 1392 .Case("pku", HasPKU) 1393 .Case("popcnt", HasPOPCNT) 1394 .Case("prefetchwt1", HasPREFETCHWT1) 1395 .Case("prfchw", HasPRFCHW) 1396 .Case("ptwrite", HasPTWRITE) 1397 .Case("rdpid", HasRDPID) 1398 .Case("rdrnd", HasRDRND) 1399 .Case("rdseed", HasRDSEED) 1400 .Case("retpoline", HasRetpoline) 1401 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1402 .Case("rtm", HasRTM) 1403 .Case("sahf", HasLAHFSAHF) 1404 .Case("sgx", HasSGX) 1405 .Case("sha", HasSHA) 1406 .Case("shstk", HasSHSTK) 1407 .Case("sse", SSELevel >= SSE1) 1408 .Case("sse2", SSELevel >= SSE2) 1409 .Case("sse3", SSELevel >= SSE3) 1410 .Case("ssse3", SSELevel >= SSSE3) 1411 .Case("sse4.1", SSELevel >= SSE41) 1412 .Case("sse4.2", SSELevel >= SSE42) 1413 .Case("sse4a", XOPLevel >= SSE4A) 1414 .Case("tbm", HasTBM) 1415 .Case("vaes", HasVAES) 1416 .Case("vpclmulqdq", HasVPCLMULQDQ) 1417 .Case("wbnoinvd", HasWBNOINVD) 1418 .Case("waitpkg", HasWAITPKG) 1419 .Case("x86", true) 1420 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1421 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1422 .Case("xop", XOPLevel >= XOP) 1423 .Case("xsave", HasXSAVE) 1424 .Case("xsavec", HasXSAVEC) 1425 .Case("xsaves", HasXSAVES) 1426 .Case("xsaveopt", HasXSAVEOPT) 1427 .Default(false); 1428 } 1429 1430 // We can't use a generic validation scheme for the features accepted here 1431 // versus subtarget features accepted in the target attribute because the 1432 // bitfield structure that's initialized in the runtime only supports the 1433 // below currently rather than the full range of subtarget features. (See 1434 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1435 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1436 return llvm::StringSwitch<bool>(FeatureStr) 1437 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1438 #include "llvm/Support/X86TargetParser.def" 1439 .Default(false); 1440 } 1441 1442 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1443 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1444 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1445 #include "llvm/Support/X86TargetParser.def" 1446 ; 1447 // Note, this function should only be used after ensuring the value is 1448 // correct, so it asserts if the value is out of range. 1449 } 1450 1451 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1452 enum class FeatPriority { 1453 #define FEATURE(FEAT) FEAT, 1454 #include "clang/Basic/X86Target.def" 1455 }; 1456 switch (Feat) { 1457 #define FEATURE(FEAT) \ 1458 case llvm::X86::FEAT: \ 1459 return static_cast<unsigned>(FeatPriority::FEAT); 1460 #include "clang/Basic/X86Target.def" 1461 default: 1462 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1463 } 1464 } 1465 1466 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1467 // Valid CPUs have a 'key feature' that compares just better than its key 1468 // feature. 1469 CPUKind Kind = getCPUKind(Name); 1470 if (Kind != CK_Generic) { 1471 switch (Kind) { 1472 default: 1473 llvm_unreachable( 1474 "CPU Type without a key feature used in 'target' attribute"); 1475 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1476 case CK_##ENUM: \ 1477 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1478 #include "clang/Basic/X86Target.def" 1479 } 1480 } 1481 1482 // Now we know we have a feature, so get its priority and shift it a few so 1483 // that we have sufficient room for the CPUs (above). 1484 return getFeaturePriority(getFeature(Name)) << 1; 1485 } 1486 1487 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1488 return llvm::StringSwitch<bool>(Name) 1489 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1490 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1491 #include "clang/Basic/X86Target.def" 1492 .Default(false); 1493 } 1494 1495 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1496 return llvm::StringSwitch<StringRef>(Name) 1497 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1498 #include "clang/Basic/X86Target.def" 1499 .Default(Name); 1500 } 1501 1502 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1503 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1504 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1505 #include "clang/Basic/X86Target.def" 1506 .Default(0); 1507 } 1508 1509 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1510 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1511 StringRef WholeList = 1512 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1513 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1514 #include "clang/Basic/X86Target.def" 1515 .Default(""); 1516 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1517 } 1518 1519 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1520 switch (Kind) { 1521 case CK_Generic: 1522 return ""; 1523 #define PROC(ENUM, STRING, IS64BIT) \ 1524 case CK_##ENUM: \ 1525 return STRING; 1526 #include "clang/Basic/X86Target.def" 1527 } 1528 llvm_unreachable("Invalid CPUKind"); 1529 } 1530 1531 // We can't use a generic validation scheme for the cpus accepted here 1532 // versus subtarget cpus accepted in the target attribute because the 1533 // variables intitialized by the runtime only support the below currently 1534 // rather than the full range of cpus. 1535 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1536 return llvm::StringSwitch<bool>(FeatureStr) 1537 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1538 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1539 .Cases(STR, ALIAS, true) 1540 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1541 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1542 #include "llvm/Support/X86TargetParser.def" 1543 .Default(false); 1544 } 1545 1546 bool X86TargetInfo::validateAsmConstraint( 1547 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1548 switch (*Name) { 1549 default: 1550 return false; 1551 // Constant constraints. 1552 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1553 // instructions. 1554 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1555 // x86_64 instructions. 1556 case 's': 1557 Info.setRequiresImmediate(); 1558 return true; 1559 case 'I': 1560 Info.setRequiresImmediate(0, 31); 1561 return true; 1562 case 'J': 1563 Info.setRequiresImmediate(0, 63); 1564 return true; 1565 case 'K': 1566 Info.setRequiresImmediate(-128, 127); 1567 return true; 1568 case 'L': 1569 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1570 return true; 1571 case 'M': 1572 Info.setRequiresImmediate(0, 3); 1573 return true; 1574 case 'N': 1575 Info.setRequiresImmediate(0, 255); 1576 return true; 1577 case 'O': 1578 Info.setRequiresImmediate(0, 127); 1579 return true; 1580 // Register constraints. 1581 case 'Y': // 'Y' is the first character for several 2-character constraints. 1582 // Shift the pointer to the second character of the constraint. 1583 Name++; 1584 switch (*Name) { 1585 default: 1586 return false; 1587 case 'z': 1588 case '0': // First SSE register. 1589 case '2': 1590 case 't': // Any SSE register, when SSE2 is enabled. 1591 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1592 case 'm': // Any MMX register, when inter-unit moves enabled. 1593 case 'k': // AVX512 arch mask registers: k1-k7. 1594 Info.setAllowsRegister(); 1595 return true; 1596 } 1597 case 'f': // Any x87 floating point stack register. 1598 // Constraint 'f' cannot be used for output operands. 1599 if (Info.ConstraintStr[0] == '=') 1600 return false; 1601 Info.setAllowsRegister(); 1602 return true; 1603 case 'a': // eax. 1604 case 'b': // ebx. 1605 case 'c': // ecx. 1606 case 'd': // edx. 1607 case 'S': // esi. 1608 case 'D': // edi. 1609 case 'A': // edx:eax. 1610 case 't': // Top of floating point stack. 1611 case 'u': // Second from top of floating point stack. 1612 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1613 case 'y': // Any MMX register. 1614 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1615 case 'x': // Any SSE register. 1616 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1617 // for intermideate k reg operations). 1618 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1619 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1620 case 'l': // "Index" registers: any general register that can be used as an 1621 // index in a base+index memory access. 1622 Info.setAllowsRegister(); 1623 return true; 1624 // Floating point constant constraints. 1625 case 'C': // SSE floating point constant. 1626 case 'G': // x87 floating point constant. 1627 return true; 1628 } 1629 } 1630 1631 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1632 unsigned Size) const { 1633 // Strip off constraint modifiers. 1634 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1635 Constraint = Constraint.substr(1); 1636 1637 return validateOperandSize(Constraint, Size); 1638 } 1639 1640 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1641 unsigned Size) const { 1642 return validateOperandSize(Constraint, Size); 1643 } 1644 1645 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1646 unsigned Size) const { 1647 switch (Constraint[0]) { 1648 default: 1649 break; 1650 case 'k': 1651 // Registers k0-k7 (AVX512) size limit is 64 bit. 1652 case 'y': 1653 return Size <= 64; 1654 case 'f': 1655 case 't': 1656 case 'u': 1657 return Size <= 128; 1658 case 'Y': 1659 // 'Y' is the first character for several 2-character constraints. 1660 switch (Constraint[1]) { 1661 default: 1662 return false; 1663 case 'm': 1664 // 'Ym' is synonymous with 'y'. 1665 case 'k': 1666 return Size <= 64; 1667 case 'z': 1668 case '0': 1669 // XMM0 1670 if (SSELevel >= SSE1) 1671 return Size <= 128U; 1672 return false; 1673 case 'i': 1674 case 't': 1675 case '2': 1676 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1677 if (SSELevel < SSE2) 1678 return false; 1679 break; 1680 } 1681 case 'v': 1682 case 'x': 1683 if (SSELevel >= AVX512F) 1684 // 512-bit zmm registers can be used if target supports AVX512F. 1685 return Size <= 512U; 1686 else if (SSELevel >= AVX) 1687 // 256-bit ymm registers can be used if target supports AVX. 1688 return Size <= 256U; 1689 return Size <= 128U; 1690 1691 } 1692 1693 return true; 1694 } 1695 1696 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1697 switch (*Constraint) { 1698 case 'a': 1699 return std::string("{ax}"); 1700 case 'b': 1701 return std::string("{bx}"); 1702 case 'c': 1703 return std::string("{cx}"); 1704 case 'd': 1705 return std::string("{dx}"); 1706 case 'S': 1707 return std::string("{si}"); 1708 case 'D': 1709 return std::string("{di}"); 1710 case 'p': // address 1711 return std::string("im"); 1712 case 't': // top of floating point stack. 1713 return std::string("{st}"); 1714 case 'u': // second from top of floating point stack. 1715 return std::string("{st(1)}"); // second from top of floating point stack. 1716 case 'Y': 1717 switch (Constraint[1]) { 1718 default: 1719 // Break from inner switch and fall through (copy single char), 1720 // continue parsing after copying the current constraint into 1721 // the return string. 1722 break; 1723 case 'k': 1724 case 'm': 1725 case 'i': 1726 case 't': 1727 case 'z': 1728 case '0': 1729 case '2': 1730 // "^" hints llvm that this is a 2 letter constraint. 1731 // "Constraint++" is used to promote the string iterator 1732 // to the next constraint. 1733 return std::string("^") + std::string(Constraint++, 2); 1734 } 1735 LLVM_FALLTHROUGH; 1736 default: 1737 return std::string(1, *Constraint); 1738 } 1739 } 1740 1741 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1742 // Perform any per-CPU checks necessary to determine if this CPU is 1743 // acceptable. 1744 switch (Kind) { 1745 case CK_Generic: 1746 // No processor selected! 1747 return false; 1748 #define PROC(ENUM, STRING, IS64BIT) \ 1749 case CK_##ENUM: \ 1750 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1751 #include "clang/Basic/X86Target.def" 1752 } 1753 llvm_unreachable("Unhandled CPU kind"); 1754 } 1755 1756 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1757 #define PROC(ENUM, STRING, IS64BIT) \ 1758 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1759 Values.emplace_back(STRING); 1760 // Go through CPUKind checking to ensure that the alias is de-aliased and 1761 // 64 bit-ness is checked. 1762 #define PROC_ALIAS(ENUM, ALIAS) \ 1763 if (checkCPUKind(getCPUKind(ALIAS))) \ 1764 Values.emplace_back(ALIAS); 1765 #include "clang/Basic/X86Target.def" 1766 } 1767 1768 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1769 return llvm::StringSwitch<CPUKind>(CPU) 1770 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1771 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1772 #include "clang/Basic/X86Target.def" 1773 .Default(CK_Generic); 1774 } 1775 1776 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1777 return llvm::makeArrayRef(GCCRegNames); 1778 } 1779 1780 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1781 return llvm::makeArrayRef(AddlRegNames); 1782 } 1783 1784 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1785 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1786 Builtin::FirstTSBuiltin + 1); 1787 } 1788 1789 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1790 return llvm::makeArrayRef(BuiltinInfoX86, 1791 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1792 } 1793