1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/TargetParser.h" 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::checkCFProtectionReturnSupported( 106 DiagnosticsEngine &Diags) const { 107 if (HasSHSTK) 108 return true; 109 110 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=return" 111 << "-mshstk"; 112 return false; 113 } 114 115 bool X86TargetInfo::checkCFProtectionBranchSupported( 116 DiagnosticsEngine &Diags) const { 117 if (HasIBT) 118 return true; 119 120 Diags.Report(diag::err_opt_not_valid_without_opt) << "cf-protection=branch" 121 << "-mibt"; 122 return false; 123 } 124 125 bool X86TargetInfo::initFeatureMap( 126 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 127 const std::vector<std::string> &FeaturesVec) const { 128 // FIXME: This *really* should not be here. 129 // X86_64 always has SSE2. 130 if (getTriple().getArch() == llvm::Triple::x86_64) 131 setFeatureEnabledImpl(Features, "sse2", true); 132 133 const CPUKind Kind = getCPUKind(CPU); 134 135 // Enable X87 for all X86 processors but Lakemont. 136 if (Kind != CK_Lakemont) 137 setFeatureEnabledImpl(Features, "x87", true); 138 139 switch (Kind) { 140 case CK_Generic: 141 case CK_i386: 142 case CK_i486: 143 case CK_i586: 144 case CK_Pentium: 145 case CK_PentiumPro: 146 case CK_Lakemont: 147 break; 148 149 case CK_PentiumMMX: 150 case CK_Pentium2: 151 case CK_K6: 152 case CK_WinChipC6: 153 setFeatureEnabledImpl(Features, "mmx", true); 154 break; 155 156 case CK_IcelakeServer: 157 setFeatureEnabledImpl(Features, "pconfig", true); 158 setFeatureEnabledImpl(Features, "wbnoinvd", true); 159 LLVM_FALLTHROUGH; 160 case CK_IcelakeClient: 161 setFeatureEnabledImpl(Features, "vaes", true); 162 setFeatureEnabledImpl(Features, "gfni", true); 163 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 164 setFeatureEnabledImpl(Features, "avx512bitalg", true); 165 setFeatureEnabledImpl(Features, "avx512vnni", true); 166 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 167 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 168 setFeatureEnabledImpl(Features, "rdpid", true); 169 LLVM_FALLTHROUGH; 170 case CK_Cannonlake: 171 setFeatureEnabledImpl(Features, "avx512ifma", true); 172 setFeatureEnabledImpl(Features, "avx512vbmi", true); 173 setFeatureEnabledImpl(Features, "sha", true); 174 LLVM_FALLTHROUGH; 175 case CK_SkylakeServer: 176 setFeatureEnabledImpl(Features, "avx512f", true); 177 setFeatureEnabledImpl(Features, "avx512cd", true); 178 setFeatureEnabledImpl(Features, "avx512dq", true); 179 setFeatureEnabledImpl(Features, "avx512bw", true); 180 setFeatureEnabledImpl(Features, "avx512vl", true); 181 setFeatureEnabledImpl(Features, "pku", true); 182 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 183 setFeatureEnabledImpl(Features, "clwb", true); 184 LLVM_FALLTHROUGH; 185 case CK_SkylakeClient: 186 setFeatureEnabledImpl(Features, "xsavec", true); 187 setFeatureEnabledImpl(Features, "xsaves", true); 188 setFeatureEnabledImpl(Features, "mpx", true); 189 if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX 190 setFeatureEnabledImpl(Features, "sgx", true); 191 setFeatureEnabledImpl(Features, "clflushopt", true); 192 setFeatureEnabledImpl(Features, "rtm", true); 193 LLVM_FALLTHROUGH; 194 case CK_Broadwell: 195 setFeatureEnabledImpl(Features, "rdseed", true); 196 setFeatureEnabledImpl(Features, "adx", true); 197 setFeatureEnabledImpl(Features, "prfchw", true); 198 LLVM_FALLTHROUGH; 199 case CK_Haswell: 200 setFeatureEnabledImpl(Features, "avx2", true); 201 setFeatureEnabledImpl(Features, "lzcnt", true); 202 setFeatureEnabledImpl(Features, "bmi", true); 203 setFeatureEnabledImpl(Features, "bmi2", true); 204 setFeatureEnabledImpl(Features, "fma", true); 205 setFeatureEnabledImpl(Features, "movbe", true); 206 LLVM_FALLTHROUGH; 207 case CK_IvyBridge: 208 setFeatureEnabledImpl(Features, "rdrnd", true); 209 setFeatureEnabledImpl(Features, "f16c", true); 210 setFeatureEnabledImpl(Features, "fsgsbase", true); 211 LLVM_FALLTHROUGH; 212 case CK_SandyBridge: 213 setFeatureEnabledImpl(Features, "avx", true); 214 setFeatureEnabledImpl(Features, "xsave", true); 215 setFeatureEnabledImpl(Features, "xsaveopt", true); 216 LLVM_FALLTHROUGH; 217 case CK_Westmere: 218 setFeatureEnabledImpl(Features, "aes", true); 219 setFeatureEnabledImpl(Features, "pclmul", true); 220 LLVM_FALLTHROUGH; 221 case CK_Nehalem: 222 setFeatureEnabledImpl(Features, "sse4.2", true); 223 LLVM_FALLTHROUGH; 224 case CK_Penryn: 225 setFeatureEnabledImpl(Features, "sse4.1", true); 226 LLVM_FALLTHROUGH; 227 case CK_Core2: 228 setFeatureEnabledImpl(Features, "ssse3", true); 229 setFeatureEnabledImpl(Features, "sahf", true); 230 LLVM_FALLTHROUGH; 231 case CK_Yonah: 232 case CK_Prescott: 233 case CK_Nocona: 234 setFeatureEnabledImpl(Features, "sse3", true); 235 setFeatureEnabledImpl(Features, "cx16", true); 236 LLVM_FALLTHROUGH; 237 case CK_PentiumM: 238 case CK_Pentium4: 239 case CK_x86_64: 240 setFeatureEnabledImpl(Features, "sse2", true); 241 LLVM_FALLTHROUGH; 242 case CK_Pentium3: 243 case CK_C3_2: 244 setFeatureEnabledImpl(Features, "sse", true); 245 setFeatureEnabledImpl(Features, "fxsr", true); 246 break; 247 248 case CK_Tremont: 249 setFeatureEnabledImpl(Features, "cldemote", true); 250 setFeatureEnabledImpl(Features, "movdiri", true); 251 setFeatureEnabledImpl(Features, "movdir64b", true); 252 setFeatureEnabledImpl(Features, "gfni", true); 253 setFeatureEnabledImpl(Features, "waitpkg", true); 254 LLVM_FALLTHROUGH; 255 case CK_GoldmontPlus: 256 setFeatureEnabledImpl(Features, "ptwrite", true); 257 setFeatureEnabledImpl(Features, "rdpid", true); 258 setFeatureEnabledImpl(Features, "sgx", true); 259 LLVM_FALLTHROUGH; 260 case CK_Goldmont: 261 setFeatureEnabledImpl(Features, "sha", true); 262 setFeatureEnabledImpl(Features, "rdseed", true); 263 setFeatureEnabledImpl(Features, "xsave", true); 264 setFeatureEnabledImpl(Features, "xsaveopt", true); 265 setFeatureEnabledImpl(Features, "xsavec", true); 266 setFeatureEnabledImpl(Features, "xsaves", true); 267 setFeatureEnabledImpl(Features, "clflushopt", true); 268 setFeatureEnabledImpl(Features, "mpx", true); 269 setFeatureEnabledImpl(Features, "fsgsbase", true); 270 LLVM_FALLTHROUGH; 271 case CK_Silvermont: 272 setFeatureEnabledImpl(Features, "rdrnd", true); 273 setFeatureEnabledImpl(Features, "aes", true); 274 setFeatureEnabledImpl(Features, "pclmul", true); 275 setFeatureEnabledImpl(Features, "sse4.2", true); 276 setFeatureEnabledImpl(Features, "prfchw", true); 277 LLVM_FALLTHROUGH; 278 case CK_Bonnell: 279 setFeatureEnabledImpl(Features, "movbe", true); 280 setFeatureEnabledImpl(Features, "ssse3", true); 281 setFeatureEnabledImpl(Features, "fxsr", true); 282 setFeatureEnabledImpl(Features, "cx16", true); 283 setFeatureEnabledImpl(Features, "sahf", true); 284 break; 285 286 case CK_KNM: 287 // TODO: Add avx5124fmaps/avx5124vnniw. 288 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 289 LLVM_FALLTHROUGH; 290 case CK_KNL: 291 setFeatureEnabledImpl(Features, "avx512f", true); 292 setFeatureEnabledImpl(Features, "avx512cd", true); 293 setFeatureEnabledImpl(Features, "avx512er", true); 294 setFeatureEnabledImpl(Features, "avx512pf", true); 295 setFeatureEnabledImpl(Features, "prfchw", true); 296 setFeatureEnabledImpl(Features, "prefetchwt1", true); 297 setFeatureEnabledImpl(Features, "fxsr", true); 298 setFeatureEnabledImpl(Features, "rdseed", true); 299 setFeatureEnabledImpl(Features, "adx", true); 300 setFeatureEnabledImpl(Features, "lzcnt", true); 301 setFeatureEnabledImpl(Features, "bmi", true); 302 setFeatureEnabledImpl(Features, "bmi2", true); 303 setFeatureEnabledImpl(Features, "rtm", true); 304 setFeatureEnabledImpl(Features, "fma", true); 305 setFeatureEnabledImpl(Features, "rdrnd", true); 306 setFeatureEnabledImpl(Features, "f16c", true); 307 setFeatureEnabledImpl(Features, "fsgsbase", true); 308 setFeatureEnabledImpl(Features, "aes", true); 309 setFeatureEnabledImpl(Features, "pclmul", true); 310 setFeatureEnabledImpl(Features, "cx16", true); 311 setFeatureEnabledImpl(Features, "xsaveopt", true); 312 setFeatureEnabledImpl(Features, "xsave", true); 313 setFeatureEnabledImpl(Features, "movbe", true); 314 setFeatureEnabledImpl(Features, "sahf", true); 315 break; 316 317 case CK_K6_2: 318 case CK_K6_3: 319 case CK_WinChip2: 320 case CK_C3: 321 setFeatureEnabledImpl(Features, "3dnow", true); 322 break; 323 324 case CK_AMDFAM10: 325 setFeatureEnabledImpl(Features, "sse4a", true); 326 setFeatureEnabledImpl(Features, "lzcnt", true); 327 setFeatureEnabledImpl(Features, "popcnt", true); 328 setFeatureEnabledImpl(Features, "sahf", true); 329 LLVM_FALLTHROUGH; 330 case CK_K8SSE3: 331 setFeatureEnabledImpl(Features, "sse3", true); 332 LLVM_FALLTHROUGH; 333 case CK_K8: 334 setFeatureEnabledImpl(Features, "sse2", true); 335 LLVM_FALLTHROUGH; 336 case CK_AthlonXP: 337 setFeatureEnabledImpl(Features, "sse", true); 338 setFeatureEnabledImpl(Features, "fxsr", true); 339 LLVM_FALLTHROUGH; 340 case CK_Athlon: 341 case CK_Geode: 342 setFeatureEnabledImpl(Features, "3dnowa", true); 343 break; 344 345 case CK_BTVER2: 346 setFeatureEnabledImpl(Features, "avx", true); 347 setFeatureEnabledImpl(Features, "aes", true); 348 setFeatureEnabledImpl(Features, "pclmul", true); 349 setFeatureEnabledImpl(Features, "bmi", true); 350 setFeatureEnabledImpl(Features, "f16c", true); 351 setFeatureEnabledImpl(Features, "xsaveopt", true); 352 setFeatureEnabledImpl(Features, "movbe", true); 353 LLVM_FALLTHROUGH; 354 case CK_BTVER1: 355 setFeatureEnabledImpl(Features, "ssse3", true); 356 setFeatureEnabledImpl(Features, "sse4a", true); 357 setFeatureEnabledImpl(Features, "lzcnt", true); 358 setFeatureEnabledImpl(Features, "popcnt", true); 359 setFeatureEnabledImpl(Features, "prfchw", true); 360 setFeatureEnabledImpl(Features, "cx16", true); 361 setFeatureEnabledImpl(Features, "fxsr", true); 362 setFeatureEnabledImpl(Features, "sahf", true); 363 break; 364 365 case CK_ZNVER1: 366 setFeatureEnabledImpl(Features, "adx", true); 367 setFeatureEnabledImpl(Features, "aes", true); 368 setFeatureEnabledImpl(Features, "avx2", true); 369 setFeatureEnabledImpl(Features, "bmi", true); 370 setFeatureEnabledImpl(Features, "bmi2", true); 371 setFeatureEnabledImpl(Features, "clflushopt", true); 372 setFeatureEnabledImpl(Features, "clzero", true); 373 setFeatureEnabledImpl(Features, "cx16", true); 374 setFeatureEnabledImpl(Features, "f16c", true); 375 setFeatureEnabledImpl(Features, "fma", true); 376 setFeatureEnabledImpl(Features, "fsgsbase", true); 377 setFeatureEnabledImpl(Features, "fxsr", true); 378 setFeatureEnabledImpl(Features, "lzcnt", true); 379 setFeatureEnabledImpl(Features, "mwaitx", true); 380 setFeatureEnabledImpl(Features, "movbe", true); 381 setFeatureEnabledImpl(Features, "pclmul", true); 382 setFeatureEnabledImpl(Features, "popcnt", true); 383 setFeatureEnabledImpl(Features, "prfchw", true); 384 setFeatureEnabledImpl(Features, "rdrnd", true); 385 setFeatureEnabledImpl(Features, "rdseed", true); 386 setFeatureEnabledImpl(Features, "sahf", true); 387 setFeatureEnabledImpl(Features, "sha", true); 388 setFeatureEnabledImpl(Features, "sse4a", true); 389 setFeatureEnabledImpl(Features, "xsave", true); 390 setFeatureEnabledImpl(Features, "xsavec", true); 391 setFeatureEnabledImpl(Features, "xsaveopt", true); 392 setFeatureEnabledImpl(Features, "xsaves", true); 393 break; 394 395 case CK_BDVER4: 396 setFeatureEnabledImpl(Features, "avx2", true); 397 setFeatureEnabledImpl(Features, "bmi2", true); 398 setFeatureEnabledImpl(Features, "mwaitx", true); 399 LLVM_FALLTHROUGH; 400 case CK_BDVER3: 401 setFeatureEnabledImpl(Features, "fsgsbase", true); 402 setFeatureEnabledImpl(Features, "xsaveopt", true); 403 LLVM_FALLTHROUGH; 404 case CK_BDVER2: 405 setFeatureEnabledImpl(Features, "bmi", true); 406 setFeatureEnabledImpl(Features, "fma", true); 407 setFeatureEnabledImpl(Features, "f16c", true); 408 setFeatureEnabledImpl(Features, "tbm", true); 409 LLVM_FALLTHROUGH; 410 case CK_BDVER1: 411 // xop implies avx, sse4a and fma4. 412 setFeatureEnabledImpl(Features, "xop", true); 413 setFeatureEnabledImpl(Features, "lwp", true); 414 setFeatureEnabledImpl(Features, "lzcnt", true); 415 setFeatureEnabledImpl(Features, "aes", true); 416 setFeatureEnabledImpl(Features, "pclmul", true); 417 setFeatureEnabledImpl(Features, "prfchw", true); 418 setFeatureEnabledImpl(Features, "cx16", true); 419 setFeatureEnabledImpl(Features, "fxsr", true); 420 setFeatureEnabledImpl(Features, "xsave", true); 421 setFeatureEnabledImpl(Features, "sahf", true); 422 break; 423 } 424 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 425 return false; 426 427 // Can't do this earlier because we need to be able to explicitly enable 428 // or disable these features and the things that they depend upon. 429 430 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 431 auto I = Features.find("sse4.2"); 432 if (I != Features.end() && I->getValue() && 433 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 434 FeaturesVec.end()) 435 Features["popcnt"] = true; 436 437 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 438 I = Features.find("3dnow"); 439 if (I != Features.end() && I->getValue() && 440 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 441 FeaturesVec.end()) 442 Features["prfchw"] = true; 443 444 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 445 // then enable MMX. 446 I = Features.find("sse"); 447 if (I != Features.end() && I->getValue() && 448 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 449 FeaturesVec.end()) 450 Features["mmx"] = true; 451 452 return true; 453 } 454 455 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 456 X86SSEEnum Level, bool Enabled) { 457 if (Enabled) { 458 switch (Level) { 459 case AVX512F: 460 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 461 LLVM_FALLTHROUGH; 462 case AVX2: 463 Features["avx2"] = true; 464 LLVM_FALLTHROUGH; 465 case AVX: 466 Features["avx"] = true; 467 Features["xsave"] = true; 468 LLVM_FALLTHROUGH; 469 case SSE42: 470 Features["sse4.2"] = true; 471 LLVM_FALLTHROUGH; 472 case SSE41: 473 Features["sse4.1"] = true; 474 LLVM_FALLTHROUGH; 475 case SSSE3: 476 Features["ssse3"] = true; 477 LLVM_FALLTHROUGH; 478 case SSE3: 479 Features["sse3"] = true; 480 LLVM_FALLTHROUGH; 481 case SSE2: 482 Features["sse2"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE1: 485 Features["sse"] = true; 486 LLVM_FALLTHROUGH; 487 case NoSSE: 488 break; 489 } 490 return; 491 } 492 493 switch (Level) { 494 case NoSSE: 495 case SSE1: 496 Features["sse"] = false; 497 LLVM_FALLTHROUGH; 498 case SSE2: 499 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 500 Features["gfni"] = false; 501 LLVM_FALLTHROUGH; 502 case SSE3: 503 Features["sse3"] = false; 504 setXOPLevel(Features, NoXOP, false); 505 LLVM_FALLTHROUGH; 506 case SSSE3: 507 Features["ssse3"] = false; 508 LLVM_FALLTHROUGH; 509 case SSE41: 510 Features["sse4.1"] = false; 511 LLVM_FALLTHROUGH; 512 case SSE42: 513 Features["sse4.2"] = false; 514 LLVM_FALLTHROUGH; 515 case AVX: 516 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 517 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 518 setXOPLevel(Features, FMA4, false); 519 LLVM_FALLTHROUGH; 520 case AVX2: 521 Features["avx2"] = false; 522 LLVM_FALLTHROUGH; 523 case AVX512F: 524 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 525 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 526 Features["avx512vl"] = Features["avx512vbmi"] = 527 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 528 Features["avx512bitalg"] = Features["avx512vnni"] = 529 Features["avx512vbmi2"] = false; 530 break; 531 } 532 } 533 534 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 535 MMX3DNowEnum Level, bool Enabled) { 536 if (Enabled) { 537 switch (Level) { 538 case AMD3DNowAthlon: 539 Features["3dnowa"] = true; 540 LLVM_FALLTHROUGH; 541 case AMD3DNow: 542 Features["3dnow"] = true; 543 LLVM_FALLTHROUGH; 544 case MMX: 545 Features["mmx"] = true; 546 LLVM_FALLTHROUGH; 547 case NoMMX3DNow: 548 break; 549 } 550 return; 551 } 552 553 switch (Level) { 554 case NoMMX3DNow: 555 case MMX: 556 Features["mmx"] = false; 557 LLVM_FALLTHROUGH; 558 case AMD3DNow: 559 Features["3dnow"] = false; 560 LLVM_FALLTHROUGH; 561 case AMD3DNowAthlon: 562 Features["3dnowa"] = false; 563 break; 564 } 565 } 566 567 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 568 bool Enabled) { 569 if (Enabled) { 570 switch (Level) { 571 case XOP: 572 Features["xop"] = true; 573 LLVM_FALLTHROUGH; 574 case FMA4: 575 Features["fma4"] = true; 576 setSSELevel(Features, AVX, true); 577 LLVM_FALLTHROUGH; 578 case SSE4A: 579 Features["sse4a"] = true; 580 setSSELevel(Features, SSE3, true); 581 LLVM_FALLTHROUGH; 582 case NoXOP: 583 break; 584 } 585 return; 586 } 587 588 switch (Level) { 589 case NoXOP: 590 case SSE4A: 591 Features["sse4a"] = false; 592 LLVM_FALLTHROUGH; 593 case FMA4: 594 Features["fma4"] = false; 595 LLVM_FALLTHROUGH; 596 case XOP: 597 Features["xop"] = false; 598 break; 599 } 600 } 601 602 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 603 StringRef Name, bool Enabled) { 604 // This is a bit of a hack to deal with the sse4 target feature when used 605 // as part of the target attribute. We handle sse4 correctly everywhere 606 // else. See below for more information on how we handle the sse4 options. 607 if (Name != "sse4") 608 Features[Name] = Enabled; 609 610 if (Name == "mmx") { 611 setMMXLevel(Features, MMX, Enabled); 612 } else if (Name == "sse") { 613 setSSELevel(Features, SSE1, Enabled); 614 } else if (Name == "sse2") { 615 setSSELevel(Features, SSE2, Enabled); 616 } else if (Name == "sse3") { 617 setSSELevel(Features, SSE3, Enabled); 618 } else if (Name == "ssse3") { 619 setSSELevel(Features, SSSE3, Enabled); 620 } else if (Name == "sse4.2") { 621 setSSELevel(Features, SSE42, Enabled); 622 } else if (Name == "sse4.1") { 623 setSSELevel(Features, SSE41, Enabled); 624 } else if (Name == "3dnow") { 625 setMMXLevel(Features, AMD3DNow, Enabled); 626 } else if (Name == "3dnowa") { 627 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 628 } else if (Name == "aes") { 629 if (Enabled) 630 setSSELevel(Features, SSE2, Enabled); 631 else 632 Features["vaes"] = false; 633 } else if (Name == "vaes") { 634 if (Enabled) { 635 setSSELevel(Features, AVX, Enabled); 636 Features["aes"] = true; 637 } 638 } else if (Name == "pclmul") { 639 if (Enabled) 640 setSSELevel(Features, SSE2, Enabled); 641 else 642 Features["vpclmulqdq"] = false; 643 } else if (Name == "vpclmulqdq") { 644 if (Enabled) { 645 setSSELevel(Features, AVX, Enabled); 646 Features["pclmul"] = true; 647 } 648 } else if (Name == "gfni") { 649 if (Enabled) 650 setSSELevel(Features, SSE2, Enabled); 651 } else if (Name == "avx") { 652 setSSELevel(Features, AVX, Enabled); 653 } else if (Name == "avx2") { 654 setSSELevel(Features, AVX2, Enabled); 655 } else if (Name == "avx512f") { 656 setSSELevel(Features, AVX512F, Enabled); 657 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 658 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 659 Name == "avx512vbmi" || Name == "avx512ifma" || 660 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 661 Name == "avx512vnni" || Name == "avx512vbmi2") { 662 if (Enabled) 663 setSSELevel(Features, AVX512F, Enabled); 664 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 665 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 666 Features["avx512bw"] = true; 667 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 668 if (Name == "avx512bw" && !Enabled) 669 Features["avx512vbmi"] = Features["avx512vbmi2"] = 670 Features["avx512bitalg"] = false; 671 } else if (Name == "fma") { 672 if (Enabled) 673 setSSELevel(Features, AVX, Enabled); 674 else 675 setSSELevel(Features, AVX512F, Enabled); 676 } else if (Name == "fma4") { 677 setXOPLevel(Features, FMA4, Enabled); 678 } else if (Name == "xop") { 679 setXOPLevel(Features, XOP, Enabled); 680 } else if (Name == "sse4a") { 681 setXOPLevel(Features, SSE4A, Enabled); 682 } else if (Name == "f16c") { 683 if (Enabled) 684 setSSELevel(Features, AVX, Enabled); 685 else 686 setSSELevel(Features, AVX512F, Enabled); 687 } else if (Name == "sha") { 688 if (Enabled) 689 setSSELevel(Features, SSE2, Enabled); 690 } else if (Name == "sse4") { 691 // We can get here via the __target__ attribute since that's not controlled 692 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 693 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 694 // disabled. 695 if (Enabled) 696 setSSELevel(Features, SSE42, Enabled); 697 else 698 setSSELevel(Features, SSE41, Enabled); 699 } else if (Name == "xsave") { 700 if (!Enabled) 701 Features["xsaveopt"] = false; 702 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 703 if (Enabled) 704 Features["xsave"] = true; 705 } 706 } 707 708 /// handleTargetFeatures - Perform initialization based on the user 709 /// configured set of features. 710 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 711 DiagnosticsEngine &Diags) { 712 for (const auto &Feature : Features) { 713 if (Feature[0] != '+') 714 continue; 715 716 if (Feature == "+aes") { 717 HasAES = true; 718 } else if (Feature == "+vaes") { 719 HasVAES = true; 720 } else if (Feature == "+pclmul") { 721 HasPCLMUL = true; 722 } else if (Feature == "+vpclmulqdq") { 723 HasVPCLMULQDQ = true; 724 } else if (Feature == "+lzcnt") { 725 HasLZCNT = true; 726 } else if (Feature == "+rdrnd") { 727 HasRDRND = true; 728 } else if (Feature == "+fsgsbase") { 729 HasFSGSBASE = true; 730 } else if (Feature == "+bmi") { 731 HasBMI = true; 732 } else if (Feature == "+bmi2") { 733 HasBMI2 = true; 734 } else if (Feature == "+popcnt") { 735 HasPOPCNT = true; 736 } else if (Feature == "+rtm") { 737 HasRTM = true; 738 } else if (Feature == "+prfchw") { 739 HasPRFCHW = true; 740 } else if (Feature == "+rdseed") { 741 HasRDSEED = true; 742 } else if (Feature == "+adx") { 743 HasADX = true; 744 } else if (Feature == "+tbm") { 745 HasTBM = true; 746 } else if (Feature == "+lwp") { 747 HasLWP = true; 748 } else if (Feature == "+fma") { 749 HasFMA = true; 750 } else if (Feature == "+f16c") { 751 HasF16C = true; 752 } else if (Feature == "+gfni") { 753 HasGFNI = true; 754 } else if (Feature == "+avx512cd") { 755 HasAVX512CD = true; 756 } else if (Feature == "+avx512vpopcntdq") { 757 HasAVX512VPOPCNTDQ = true; 758 } else if (Feature == "+avx512vnni") { 759 HasAVX512VNNI = true; 760 } else if (Feature == "+avx512er") { 761 HasAVX512ER = true; 762 } else if (Feature == "+avx512pf") { 763 HasAVX512PF = true; 764 } else if (Feature == "+avx512dq") { 765 HasAVX512DQ = true; 766 } else if (Feature == "+avx512bitalg") { 767 HasAVX512BITALG = true; 768 } else if (Feature == "+avx512bw") { 769 HasAVX512BW = true; 770 } else if (Feature == "+avx512vl") { 771 HasAVX512VL = true; 772 } else if (Feature == "+avx512vbmi") { 773 HasAVX512VBMI = true; 774 } else if (Feature == "+avx512vbmi2") { 775 HasAVX512VBMI2 = true; 776 } else if (Feature == "+avx512ifma") { 777 HasAVX512IFMA = true; 778 } else if (Feature == "+sha") { 779 HasSHA = true; 780 } else if (Feature == "+mpx") { 781 HasMPX = true; 782 } else if (Feature == "+shstk") { 783 HasSHSTK = true; 784 } else if (Feature == "+ibt") { 785 HasIBT = true; 786 } else if (Feature == "+movbe") { 787 HasMOVBE = true; 788 } else if (Feature == "+sgx") { 789 HasSGX = true; 790 } else if (Feature == "+cx16") { 791 HasCX16 = true; 792 } else if (Feature == "+fxsr") { 793 HasFXSR = true; 794 } else if (Feature == "+xsave") { 795 HasXSAVE = true; 796 } else if (Feature == "+xsaveopt") { 797 HasXSAVEOPT = true; 798 } else if (Feature == "+xsavec") { 799 HasXSAVEC = true; 800 } else if (Feature == "+xsaves") { 801 HasXSAVES = true; 802 } else if (Feature == "+mwaitx") { 803 HasMWAITX = true; 804 } else if (Feature == "+pku") { 805 HasPKU = true; 806 } else if (Feature == "+clflushopt") { 807 HasCLFLUSHOPT = true; 808 } else if (Feature == "+clwb") { 809 HasCLWB = true; 810 } else if (Feature == "+wbnoinvd") { 811 HasWBNOINVD = true; 812 } else if (Feature == "+prefetchwt1") { 813 HasPREFETCHWT1 = true; 814 } else if (Feature == "+clzero") { 815 HasCLZERO = true; 816 } else if (Feature == "+cldemote") { 817 HasCLDEMOTE = true; 818 } else if (Feature == "+rdpid") { 819 HasRDPID = true; 820 } else if (Feature == "+retpoline") { 821 HasRetpoline = true; 822 } else if (Feature == "+retpoline-external-thunk") { 823 HasRetpolineExternalThunk = true; 824 } else if (Feature == "+sahf") { 825 HasLAHFSAHF = true; 826 } else if (Feature == "+waitpkg") { 827 HasWAITPKG = true; 828 } else if (Feature == "+movdiri") { 829 HasMOVDIRI = true; 830 } else if (Feature == "+movdir64b") { 831 HasMOVDIR64B = true; 832 } else if (Feature == "+pconfig") { 833 HasPCONFIG = true; 834 } else if (Feature == "+ptwrite") { 835 HasPTWRITE = true; 836 } 837 838 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 839 .Case("+avx512f", AVX512F) 840 .Case("+avx2", AVX2) 841 .Case("+avx", AVX) 842 .Case("+sse4.2", SSE42) 843 .Case("+sse4.1", SSE41) 844 .Case("+ssse3", SSSE3) 845 .Case("+sse3", SSE3) 846 .Case("+sse2", SSE2) 847 .Case("+sse", SSE1) 848 .Default(NoSSE); 849 SSELevel = std::max(SSELevel, Level); 850 851 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 852 .Case("+3dnowa", AMD3DNowAthlon) 853 .Case("+3dnow", AMD3DNow) 854 .Case("+mmx", MMX) 855 .Default(NoMMX3DNow); 856 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 857 858 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 859 .Case("+xop", XOP) 860 .Case("+fma4", FMA4) 861 .Case("+sse4a", SSE4A) 862 .Default(NoXOP); 863 XOPLevel = std::max(XOPLevel, XLevel); 864 } 865 866 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 867 // matches the selected sse level. 868 if ((FPMath == FP_SSE && SSELevel < SSE1) || 869 (FPMath == FP_387 && SSELevel >= SSE1)) { 870 Diags.Report(diag::err_target_unsupported_fpmath) 871 << (FPMath == FP_SSE ? "sse" : "387"); 872 return false; 873 } 874 875 SimdDefaultAlign = 876 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 877 return true; 878 } 879 880 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 881 /// definitions for this particular subtarget. 882 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 883 MacroBuilder &Builder) const { 884 // Target identification. 885 if (getTriple().getArch() == llvm::Triple::x86_64) { 886 Builder.defineMacro("__amd64__"); 887 Builder.defineMacro("__amd64"); 888 Builder.defineMacro("__x86_64"); 889 Builder.defineMacro("__x86_64__"); 890 if (getTriple().getArchName() == "x86_64h") { 891 Builder.defineMacro("__x86_64h"); 892 Builder.defineMacro("__x86_64h__"); 893 } 894 } else { 895 DefineStd(Builder, "i386", Opts); 896 } 897 898 // Subtarget options. 899 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 900 // truly should be based on -mtune options. 901 switch (CPU) { 902 case CK_Generic: 903 break; 904 case CK_i386: 905 // The rest are coming from the i386 define above. 906 Builder.defineMacro("__tune_i386__"); 907 break; 908 case CK_i486: 909 case CK_WinChipC6: 910 case CK_WinChip2: 911 case CK_C3: 912 defineCPUMacros(Builder, "i486"); 913 break; 914 case CK_PentiumMMX: 915 Builder.defineMacro("__pentium_mmx__"); 916 Builder.defineMacro("__tune_pentium_mmx__"); 917 LLVM_FALLTHROUGH; 918 case CK_i586: 919 case CK_Pentium: 920 defineCPUMacros(Builder, "i586"); 921 defineCPUMacros(Builder, "pentium"); 922 break; 923 case CK_Pentium3: 924 case CK_PentiumM: 925 Builder.defineMacro("__tune_pentium3__"); 926 LLVM_FALLTHROUGH; 927 case CK_Pentium2: 928 case CK_C3_2: 929 Builder.defineMacro("__tune_pentium2__"); 930 LLVM_FALLTHROUGH; 931 case CK_PentiumPro: 932 defineCPUMacros(Builder, "i686"); 933 defineCPUMacros(Builder, "pentiumpro"); 934 break; 935 case CK_Pentium4: 936 defineCPUMacros(Builder, "pentium4"); 937 break; 938 case CK_Yonah: 939 case CK_Prescott: 940 case CK_Nocona: 941 defineCPUMacros(Builder, "nocona"); 942 break; 943 case CK_Core2: 944 case CK_Penryn: 945 defineCPUMacros(Builder, "core2"); 946 break; 947 case CK_Bonnell: 948 defineCPUMacros(Builder, "atom"); 949 break; 950 case CK_Silvermont: 951 defineCPUMacros(Builder, "slm"); 952 break; 953 case CK_Goldmont: 954 defineCPUMacros(Builder, "goldmont"); 955 break; 956 case CK_GoldmontPlus: 957 defineCPUMacros(Builder, "goldmont_plus"); 958 break; 959 case CK_Tremont: 960 defineCPUMacros(Builder, "tremont"); 961 break; 962 case CK_Nehalem: 963 case CK_Westmere: 964 case CK_SandyBridge: 965 case CK_IvyBridge: 966 case CK_Haswell: 967 case CK_Broadwell: 968 case CK_SkylakeClient: 969 case CK_SkylakeServer: 970 case CK_Cannonlake: 971 case CK_IcelakeClient: 972 case CK_IcelakeServer: 973 // FIXME: Historically, we defined this legacy name, it would be nice to 974 // remove it at some point. We've never exposed fine-grained names for 975 // recent primary x86 CPUs, and we should keep it that way. 976 defineCPUMacros(Builder, "corei7"); 977 break; 978 case CK_KNL: 979 defineCPUMacros(Builder, "knl"); 980 break; 981 case CK_KNM: 982 break; 983 case CK_Lakemont: 984 defineCPUMacros(Builder, "i586", /*Tuning*/false); 985 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 986 Builder.defineMacro("__tune_lakemont__"); 987 break; 988 case CK_K6_2: 989 Builder.defineMacro("__k6_2__"); 990 Builder.defineMacro("__tune_k6_2__"); 991 LLVM_FALLTHROUGH; 992 case CK_K6_3: 993 if (CPU != CK_K6_2) { // In case of fallthrough 994 // FIXME: GCC may be enabling these in cases where some other k6 995 // architecture is specified but -m3dnow is explicitly provided. The 996 // exact semantics need to be determined and emulated here. 997 Builder.defineMacro("__k6_3__"); 998 Builder.defineMacro("__tune_k6_3__"); 999 } 1000 LLVM_FALLTHROUGH; 1001 case CK_K6: 1002 defineCPUMacros(Builder, "k6"); 1003 break; 1004 case CK_Athlon: 1005 case CK_AthlonXP: 1006 defineCPUMacros(Builder, "athlon"); 1007 if (SSELevel != NoSSE) { 1008 Builder.defineMacro("__athlon_sse__"); 1009 Builder.defineMacro("__tune_athlon_sse__"); 1010 } 1011 break; 1012 case CK_K8: 1013 case CK_K8SSE3: 1014 case CK_x86_64: 1015 defineCPUMacros(Builder, "k8"); 1016 break; 1017 case CK_AMDFAM10: 1018 defineCPUMacros(Builder, "amdfam10"); 1019 break; 1020 case CK_BTVER1: 1021 defineCPUMacros(Builder, "btver1"); 1022 break; 1023 case CK_BTVER2: 1024 defineCPUMacros(Builder, "btver2"); 1025 break; 1026 case CK_BDVER1: 1027 defineCPUMacros(Builder, "bdver1"); 1028 break; 1029 case CK_BDVER2: 1030 defineCPUMacros(Builder, "bdver2"); 1031 break; 1032 case CK_BDVER3: 1033 defineCPUMacros(Builder, "bdver3"); 1034 break; 1035 case CK_BDVER4: 1036 defineCPUMacros(Builder, "bdver4"); 1037 break; 1038 case CK_ZNVER1: 1039 defineCPUMacros(Builder, "znver1"); 1040 break; 1041 case CK_Geode: 1042 defineCPUMacros(Builder, "geode"); 1043 break; 1044 } 1045 1046 // Target properties. 1047 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1048 1049 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1050 // functions in glibc header files that use FP Stack inline asm which the 1051 // backend can't deal with (PR879). 1052 Builder.defineMacro("__NO_MATH_INLINES"); 1053 1054 if (HasAES) 1055 Builder.defineMacro("__AES__"); 1056 1057 if (HasVAES) 1058 Builder.defineMacro("__VAES__"); 1059 1060 if (HasPCLMUL) 1061 Builder.defineMacro("__PCLMUL__"); 1062 1063 if (HasVPCLMULQDQ) 1064 Builder.defineMacro("__VPCLMULQDQ__"); 1065 1066 if (HasLZCNT) 1067 Builder.defineMacro("__LZCNT__"); 1068 1069 if (HasRDRND) 1070 Builder.defineMacro("__RDRND__"); 1071 1072 if (HasFSGSBASE) 1073 Builder.defineMacro("__FSGSBASE__"); 1074 1075 if (HasBMI) 1076 Builder.defineMacro("__BMI__"); 1077 1078 if (HasBMI2) 1079 Builder.defineMacro("__BMI2__"); 1080 1081 if (HasPOPCNT) 1082 Builder.defineMacro("__POPCNT__"); 1083 1084 if (HasRTM) 1085 Builder.defineMacro("__RTM__"); 1086 1087 if (HasPRFCHW) 1088 Builder.defineMacro("__PRFCHW__"); 1089 1090 if (HasRDSEED) 1091 Builder.defineMacro("__RDSEED__"); 1092 1093 if (HasADX) 1094 Builder.defineMacro("__ADX__"); 1095 1096 if (HasTBM) 1097 Builder.defineMacro("__TBM__"); 1098 1099 if (HasLWP) 1100 Builder.defineMacro("__LWP__"); 1101 1102 if (HasMWAITX) 1103 Builder.defineMacro("__MWAITX__"); 1104 1105 switch (XOPLevel) { 1106 case XOP: 1107 Builder.defineMacro("__XOP__"); 1108 LLVM_FALLTHROUGH; 1109 case FMA4: 1110 Builder.defineMacro("__FMA4__"); 1111 LLVM_FALLTHROUGH; 1112 case SSE4A: 1113 Builder.defineMacro("__SSE4A__"); 1114 LLVM_FALLTHROUGH; 1115 case NoXOP: 1116 break; 1117 } 1118 1119 if (HasFMA) 1120 Builder.defineMacro("__FMA__"); 1121 1122 if (HasF16C) 1123 Builder.defineMacro("__F16C__"); 1124 1125 if (HasGFNI) 1126 Builder.defineMacro("__GFNI__"); 1127 1128 if (HasAVX512CD) 1129 Builder.defineMacro("__AVX512CD__"); 1130 if (HasAVX512VPOPCNTDQ) 1131 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1132 if (HasAVX512VNNI) 1133 Builder.defineMacro("__AVX512VNNI__"); 1134 if (HasAVX512ER) 1135 Builder.defineMacro("__AVX512ER__"); 1136 if (HasAVX512PF) 1137 Builder.defineMacro("__AVX512PF__"); 1138 if (HasAVX512DQ) 1139 Builder.defineMacro("__AVX512DQ__"); 1140 if (HasAVX512BITALG) 1141 Builder.defineMacro("__AVX512BITALG__"); 1142 if (HasAVX512BW) 1143 Builder.defineMacro("__AVX512BW__"); 1144 if (HasAVX512VL) 1145 Builder.defineMacro("__AVX512VL__"); 1146 if (HasAVX512VBMI) 1147 Builder.defineMacro("__AVX512VBMI__"); 1148 if (HasAVX512VBMI2) 1149 Builder.defineMacro("__AVX512VBMI2__"); 1150 if (HasAVX512IFMA) 1151 Builder.defineMacro("__AVX512IFMA__"); 1152 1153 if (HasSHA) 1154 Builder.defineMacro("__SHA__"); 1155 1156 if (HasFXSR) 1157 Builder.defineMacro("__FXSR__"); 1158 if (HasXSAVE) 1159 Builder.defineMacro("__XSAVE__"); 1160 if (HasXSAVEOPT) 1161 Builder.defineMacro("__XSAVEOPT__"); 1162 if (HasXSAVEC) 1163 Builder.defineMacro("__XSAVEC__"); 1164 if (HasXSAVES) 1165 Builder.defineMacro("__XSAVES__"); 1166 if (HasPKU) 1167 Builder.defineMacro("__PKU__"); 1168 if (HasCLFLUSHOPT) 1169 Builder.defineMacro("__CLFLUSHOPT__"); 1170 if (HasCLWB) 1171 Builder.defineMacro("__CLWB__"); 1172 if (HasWBNOINVD) 1173 Builder.defineMacro("__WBNOINVD__"); 1174 if (HasMPX) 1175 Builder.defineMacro("__MPX__"); 1176 if (HasSHSTK) 1177 Builder.defineMacro("__SHSTK__"); 1178 if (HasIBT) 1179 Builder.defineMacro("__IBT__"); 1180 if (HasSGX) 1181 Builder.defineMacro("__SGX__"); 1182 if (HasPREFETCHWT1) 1183 Builder.defineMacro("__PREFETCHWT1__"); 1184 if (HasCLZERO) 1185 Builder.defineMacro("__CLZERO__"); 1186 if (HasRDPID) 1187 Builder.defineMacro("__RDPID__"); 1188 if (HasCLDEMOTE) 1189 Builder.defineMacro("__CLDEMOTE__"); 1190 if (HasWAITPKG) 1191 Builder.defineMacro("__WAITPKG__"); 1192 if (HasMOVDIRI) 1193 Builder.defineMacro("__MOVDIRI__"); 1194 if (HasMOVDIR64B) 1195 Builder.defineMacro("__MOVDIR64B__"); 1196 if (HasPCONFIG) 1197 Builder.defineMacro("__PCONFIG__"); 1198 if (HasPTWRITE) 1199 Builder.defineMacro("__PTWRITE__"); 1200 1201 // Each case falls through to the previous one here. 1202 switch (SSELevel) { 1203 case AVX512F: 1204 Builder.defineMacro("__AVX512F__"); 1205 LLVM_FALLTHROUGH; 1206 case AVX2: 1207 Builder.defineMacro("__AVX2__"); 1208 LLVM_FALLTHROUGH; 1209 case AVX: 1210 Builder.defineMacro("__AVX__"); 1211 LLVM_FALLTHROUGH; 1212 case SSE42: 1213 Builder.defineMacro("__SSE4_2__"); 1214 LLVM_FALLTHROUGH; 1215 case SSE41: 1216 Builder.defineMacro("__SSE4_1__"); 1217 LLVM_FALLTHROUGH; 1218 case SSSE3: 1219 Builder.defineMacro("__SSSE3__"); 1220 LLVM_FALLTHROUGH; 1221 case SSE3: 1222 Builder.defineMacro("__SSE3__"); 1223 LLVM_FALLTHROUGH; 1224 case SSE2: 1225 Builder.defineMacro("__SSE2__"); 1226 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1227 LLVM_FALLTHROUGH; 1228 case SSE1: 1229 Builder.defineMacro("__SSE__"); 1230 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1231 LLVM_FALLTHROUGH; 1232 case NoSSE: 1233 break; 1234 } 1235 1236 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1237 switch (SSELevel) { 1238 case AVX512F: 1239 case AVX2: 1240 case AVX: 1241 case SSE42: 1242 case SSE41: 1243 case SSSE3: 1244 case SSE3: 1245 case SSE2: 1246 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1247 break; 1248 case SSE1: 1249 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1250 break; 1251 default: 1252 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1253 break; 1254 } 1255 } 1256 1257 // Each case falls through to the previous one here. 1258 switch (MMX3DNowLevel) { 1259 case AMD3DNowAthlon: 1260 Builder.defineMacro("__3dNOW_A__"); 1261 LLVM_FALLTHROUGH; 1262 case AMD3DNow: 1263 Builder.defineMacro("__3dNOW__"); 1264 LLVM_FALLTHROUGH; 1265 case MMX: 1266 Builder.defineMacro("__MMX__"); 1267 LLVM_FALLTHROUGH; 1268 case NoMMX3DNow: 1269 break; 1270 } 1271 1272 if (CPU >= CK_i486) { 1273 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1274 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1276 } 1277 if (CPU >= CK_i586) 1278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1279 if (HasCX16) 1280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1281 1282 if (HasFloat128) 1283 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1284 } 1285 1286 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1287 return llvm::StringSwitch<bool>(Name) 1288 .Case("3dnow", true) 1289 .Case("3dnowa", true) 1290 .Case("adx", true) 1291 .Case("aes", true) 1292 .Case("avx", true) 1293 .Case("avx2", true) 1294 .Case("avx512f", true) 1295 .Case("avx512cd", true) 1296 .Case("avx512vpopcntdq", true) 1297 .Case("avx512vnni", true) 1298 .Case("avx512er", true) 1299 .Case("avx512pf", true) 1300 .Case("avx512dq", true) 1301 .Case("avx512bitalg", true) 1302 .Case("avx512bw", true) 1303 .Case("avx512vl", true) 1304 .Case("avx512vbmi", true) 1305 .Case("avx512vbmi2", true) 1306 .Case("avx512ifma", true) 1307 .Case("bmi", true) 1308 .Case("bmi2", true) 1309 .Case("cldemote", true) 1310 .Case("clflushopt", true) 1311 .Case("clwb", true) 1312 .Case("clzero", true) 1313 .Case("cx16", true) 1314 .Case("f16c", true) 1315 .Case("fma", true) 1316 .Case("fma4", true) 1317 .Case("fsgsbase", true) 1318 .Case("fxsr", true) 1319 .Case("gfni", true) 1320 .Case("lwp", true) 1321 .Case("lzcnt", true) 1322 .Case("mmx", true) 1323 .Case("movbe", true) 1324 .Case("movdiri", true) 1325 .Case("movdir64b", true) 1326 .Case("mpx", true) 1327 .Case("mwaitx", true) 1328 .Case("pclmul", true) 1329 .Case("pconfig", true) 1330 .Case("pku", true) 1331 .Case("popcnt", true) 1332 .Case("prefetchwt1", true) 1333 .Case("prfchw", true) 1334 .Case("ptwrite", true) 1335 .Case("rdpid", true) 1336 .Case("rdrnd", true) 1337 .Case("rdseed", true) 1338 .Case("rtm", true) 1339 .Case("sahf", true) 1340 .Case("sgx", true) 1341 .Case("sha", true) 1342 .Case("shstk", true) 1343 .Case("sse", true) 1344 .Case("sse2", true) 1345 .Case("sse3", true) 1346 .Case("ssse3", true) 1347 .Case("sse4", true) 1348 .Case("sse4.1", true) 1349 .Case("sse4.2", true) 1350 .Case("sse4a", true) 1351 .Case("tbm", true) 1352 .Case("vaes", true) 1353 .Case("vpclmulqdq", true) 1354 .Case("wbnoinvd", true) 1355 .Case("waitpkg", true) 1356 .Case("x87", true) 1357 .Case("xop", true) 1358 .Case("xsave", true) 1359 .Case("xsavec", true) 1360 .Case("xsaves", true) 1361 .Case("xsaveopt", true) 1362 .Default(false); 1363 } 1364 1365 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1366 return llvm::StringSwitch<bool>(Feature) 1367 .Case("adx", HasADX) 1368 .Case("aes", HasAES) 1369 .Case("avx", SSELevel >= AVX) 1370 .Case("avx2", SSELevel >= AVX2) 1371 .Case("avx512f", SSELevel >= AVX512F) 1372 .Case("avx512cd", HasAVX512CD) 1373 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1374 .Case("avx512vnni", HasAVX512VNNI) 1375 .Case("avx512er", HasAVX512ER) 1376 .Case("avx512pf", HasAVX512PF) 1377 .Case("avx512dq", HasAVX512DQ) 1378 .Case("avx512bitalg", HasAVX512BITALG) 1379 .Case("avx512bw", HasAVX512BW) 1380 .Case("avx512vl", HasAVX512VL) 1381 .Case("avx512vbmi", HasAVX512VBMI) 1382 .Case("avx512vbmi2", HasAVX512VBMI2) 1383 .Case("avx512ifma", HasAVX512IFMA) 1384 .Case("bmi", HasBMI) 1385 .Case("bmi2", HasBMI2) 1386 .Case("cldemote", HasCLDEMOTE) 1387 .Case("clflushopt", HasCLFLUSHOPT) 1388 .Case("clwb", HasCLWB) 1389 .Case("clzero", HasCLZERO) 1390 .Case("cx16", HasCX16) 1391 .Case("f16c", HasF16C) 1392 .Case("fma", HasFMA) 1393 .Case("fma4", XOPLevel >= FMA4) 1394 .Case("fsgsbase", HasFSGSBASE) 1395 .Case("fxsr", HasFXSR) 1396 .Case("gfni", HasGFNI) 1397 .Case("ibt", HasIBT) 1398 .Case("lwp", HasLWP) 1399 .Case("lzcnt", HasLZCNT) 1400 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1401 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1402 .Case("mmx", MMX3DNowLevel >= MMX) 1403 .Case("movbe", HasMOVBE) 1404 .Case("movdiri", HasMOVDIRI) 1405 .Case("movdir64b", HasMOVDIR64B) 1406 .Case("mpx", HasMPX) 1407 .Case("mwaitx", HasMWAITX) 1408 .Case("pclmul", HasPCLMUL) 1409 .Case("pconfig", HasPCONFIG) 1410 .Case("pku", HasPKU) 1411 .Case("popcnt", HasPOPCNT) 1412 .Case("prefetchwt1", HasPREFETCHWT1) 1413 .Case("prfchw", HasPRFCHW) 1414 .Case("ptwrite", HasPTWRITE) 1415 .Case("rdpid", HasRDPID) 1416 .Case("rdrnd", HasRDRND) 1417 .Case("rdseed", HasRDSEED) 1418 .Case("retpoline", HasRetpoline) 1419 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1420 .Case("rtm", HasRTM) 1421 .Case("sahf", HasLAHFSAHF) 1422 .Case("sgx", HasSGX) 1423 .Case("sha", HasSHA) 1424 .Case("shstk", HasSHSTK) 1425 .Case("sse", SSELevel >= SSE1) 1426 .Case("sse2", SSELevel >= SSE2) 1427 .Case("sse3", SSELevel >= SSE3) 1428 .Case("ssse3", SSELevel >= SSSE3) 1429 .Case("sse4.1", SSELevel >= SSE41) 1430 .Case("sse4.2", SSELevel >= SSE42) 1431 .Case("sse4a", XOPLevel >= SSE4A) 1432 .Case("tbm", HasTBM) 1433 .Case("vaes", HasVAES) 1434 .Case("vpclmulqdq", HasVPCLMULQDQ) 1435 .Case("wbnoinvd", HasWBNOINVD) 1436 .Case("waitpkg", HasWAITPKG) 1437 .Case("x86", true) 1438 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1439 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1440 .Case("xop", XOPLevel >= XOP) 1441 .Case("xsave", HasXSAVE) 1442 .Case("xsavec", HasXSAVEC) 1443 .Case("xsaves", HasXSAVES) 1444 .Case("xsaveopt", HasXSAVEOPT) 1445 .Default(false); 1446 } 1447 1448 // We can't use a generic validation scheme for the features accepted here 1449 // versus subtarget features accepted in the target attribute because the 1450 // bitfield structure that's initialized in the runtime only supports the 1451 // below currently rather than the full range of subtarget features. (See 1452 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1453 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1454 return llvm::StringSwitch<bool>(FeatureStr) 1455 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1456 #include "llvm/Support/X86TargetParser.def" 1457 .Default(false); 1458 } 1459 1460 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1461 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1462 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1463 #include "llvm/Support/X86TargetParser.def" 1464 ; 1465 // Note, this function should only be used after ensuring the value is 1466 // correct, so it asserts if the value is out of range. 1467 } 1468 1469 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1470 enum class FeatPriority { 1471 #define FEATURE(FEAT) FEAT, 1472 #include "clang/Basic/X86Target.def" 1473 }; 1474 switch (Feat) { 1475 #define FEATURE(FEAT) \ 1476 case llvm::X86::FEAT: \ 1477 return static_cast<unsigned>(FeatPriority::FEAT); 1478 #include "clang/Basic/X86Target.def" 1479 default: 1480 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1481 } 1482 } 1483 1484 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1485 // Valid CPUs have a 'key feature' that compares just better than its key 1486 // feature. 1487 CPUKind Kind = getCPUKind(Name); 1488 if (Kind != CK_Generic) { 1489 switch (Kind) { 1490 default: 1491 llvm_unreachable( 1492 "CPU Type without a key feature used in 'target' attribute"); 1493 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1494 case CK_##ENUM: \ 1495 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1496 #include "clang/Basic/X86Target.def" 1497 } 1498 } 1499 1500 // Now we know we have a feature, so get its priority and shift it a few so 1501 // that we have sufficient room for the CPUs (above). 1502 return getFeaturePriority(getFeature(Name)) << 1; 1503 } 1504 1505 std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { 1506 switch (Kind) { 1507 case CK_Generic: 1508 return ""; 1509 #define PROC(ENUM, STRING, IS64BIT) \ 1510 case CK_##ENUM: \ 1511 return STRING; 1512 #include "clang/Basic/X86Target.def" 1513 } 1514 llvm_unreachable("Invalid CPUKind"); 1515 } 1516 1517 // We can't use a generic validation scheme for the cpus accepted here 1518 // versus subtarget cpus accepted in the target attribute because the 1519 // variables intitialized by the runtime only support the below currently 1520 // rather than the full range of cpus. 1521 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1522 return llvm::StringSwitch<bool>(FeatureStr) 1523 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1524 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1525 .Cases(STR, ALIAS, true) 1526 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1527 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1528 #include "llvm/Support/X86TargetParser.def" 1529 .Default(false); 1530 } 1531 1532 bool X86TargetInfo::validateAsmConstraint( 1533 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1534 switch (*Name) { 1535 default: 1536 return false; 1537 // Constant constraints. 1538 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1539 // instructions. 1540 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1541 // x86_64 instructions. 1542 case 's': 1543 Info.setRequiresImmediate(); 1544 return true; 1545 case 'I': 1546 Info.setRequiresImmediate(0, 31); 1547 return true; 1548 case 'J': 1549 Info.setRequiresImmediate(0, 63); 1550 return true; 1551 case 'K': 1552 Info.setRequiresImmediate(-128, 127); 1553 return true; 1554 case 'L': 1555 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1556 return true; 1557 case 'M': 1558 Info.setRequiresImmediate(0, 3); 1559 return true; 1560 case 'N': 1561 Info.setRequiresImmediate(0, 255); 1562 return true; 1563 case 'O': 1564 Info.setRequiresImmediate(0, 127); 1565 return true; 1566 // Register constraints. 1567 case 'Y': // 'Y' is the first character for several 2-character constraints. 1568 // Shift the pointer to the second character of the constraint. 1569 Name++; 1570 switch (*Name) { 1571 default: 1572 return false; 1573 case 'z': 1574 case '0': // First SSE register. 1575 case '2': 1576 case 't': // Any SSE register, when SSE2 is enabled. 1577 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1578 case 'm': // Any MMX register, when inter-unit moves enabled. 1579 case 'k': // AVX512 arch mask registers: k1-k7. 1580 Info.setAllowsRegister(); 1581 return true; 1582 } 1583 case 'f': // Any x87 floating point stack register. 1584 // Constraint 'f' cannot be used for output operands. 1585 if (Info.ConstraintStr[0] == '=') 1586 return false; 1587 Info.setAllowsRegister(); 1588 return true; 1589 case 'a': // eax. 1590 case 'b': // ebx. 1591 case 'c': // ecx. 1592 case 'd': // edx. 1593 case 'S': // esi. 1594 case 'D': // edi. 1595 case 'A': // edx:eax. 1596 case 't': // Top of floating point stack. 1597 case 'u': // Second from top of floating point stack. 1598 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1599 case 'y': // Any MMX register. 1600 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1601 case 'x': // Any SSE register. 1602 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1603 // for intermideate k reg operations). 1604 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1605 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1606 case 'l': // "Index" registers: any general register that can be used as an 1607 // index in a base+index memory access. 1608 Info.setAllowsRegister(); 1609 return true; 1610 // Floating point constant constraints. 1611 case 'C': // SSE floating point constant. 1612 case 'G': // x87 floating point constant. 1613 return true; 1614 } 1615 } 1616 1617 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1618 unsigned Size) const { 1619 // Strip off constraint modifiers. 1620 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1621 Constraint = Constraint.substr(1); 1622 1623 return validateOperandSize(Constraint, Size); 1624 } 1625 1626 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1627 unsigned Size) const { 1628 return validateOperandSize(Constraint, Size); 1629 } 1630 1631 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1632 unsigned Size) const { 1633 switch (Constraint[0]) { 1634 default: 1635 break; 1636 case 'k': 1637 // Registers k0-k7 (AVX512) size limit is 64 bit. 1638 case 'y': 1639 return Size <= 64; 1640 case 'f': 1641 case 't': 1642 case 'u': 1643 return Size <= 128; 1644 case 'Y': 1645 // 'Y' is the first character for several 2-character constraints. 1646 switch (Constraint[1]) { 1647 default: 1648 return false; 1649 case 'm': 1650 // 'Ym' is synonymous with 'y'. 1651 case 'k': 1652 return Size <= 64; 1653 case 'z': 1654 case '0': 1655 // XMM0 1656 if (SSELevel >= SSE1) 1657 return Size <= 128U; 1658 return false; 1659 case 'i': 1660 case 't': 1661 case '2': 1662 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1663 if (SSELevel < SSE2) 1664 return false; 1665 break; 1666 } 1667 case 'v': 1668 case 'x': 1669 if (SSELevel >= AVX512F) 1670 // 512-bit zmm registers can be used if target supports AVX512F. 1671 return Size <= 512U; 1672 else if (SSELevel >= AVX) 1673 // 256-bit ymm registers can be used if target supports AVX. 1674 return Size <= 256U; 1675 return Size <= 128U; 1676 1677 } 1678 1679 return true; 1680 } 1681 1682 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1683 switch (*Constraint) { 1684 case 'a': 1685 return std::string("{ax}"); 1686 case 'b': 1687 return std::string("{bx}"); 1688 case 'c': 1689 return std::string("{cx}"); 1690 case 'd': 1691 return std::string("{dx}"); 1692 case 'S': 1693 return std::string("{si}"); 1694 case 'D': 1695 return std::string("{di}"); 1696 case 'p': // address 1697 return std::string("im"); 1698 case 't': // top of floating point stack. 1699 return std::string("{st}"); 1700 case 'u': // second from top of floating point stack. 1701 return std::string("{st(1)}"); // second from top of floating point stack. 1702 case 'Y': 1703 switch (Constraint[1]) { 1704 default: 1705 // Break from inner switch and fall through (copy single char), 1706 // continue parsing after copying the current constraint into 1707 // the return string. 1708 break; 1709 case 'k': 1710 case 'm': 1711 case 'i': 1712 case 't': 1713 case 'z': 1714 case '0': 1715 case '2': 1716 // "^" hints llvm that this is a 2 letter constraint. 1717 // "Constraint++" is used to promote the string iterator 1718 // to the next constraint. 1719 return std::string("^") + std::string(Constraint++, 2); 1720 } 1721 LLVM_FALLTHROUGH; 1722 default: 1723 return std::string(1, *Constraint); 1724 } 1725 } 1726 1727 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1728 // Perform any per-CPU checks necessary to determine if this CPU is 1729 // acceptable. 1730 switch (Kind) { 1731 case CK_Generic: 1732 // No processor selected! 1733 return false; 1734 #define PROC(ENUM, STRING, IS64BIT) \ 1735 case CK_##ENUM: \ 1736 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1737 #include "clang/Basic/X86Target.def" 1738 } 1739 llvm_unreachable("Unhandled CPU kind"); 1740 } 1741 1742 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1743 #define PROC(ENUM, STRING, IS64BIT) \ 1744 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1745 Values.emplace_back(STRING); 1746 // Go through CPUKind checking to ensure that the alias is de-aliased and 1747 // 64 bit-ness is checked. 1748 #define PROC_ALIAS(ENUM, ALIAS) \ 1749 if (checkCPUKind(getCPUKind(ALIAS))) \ 1750 Values.emplace_back(ALIAS); 1751 #include "clang/Basic/X86Target.def" 1752 } 1753 1754 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1755 return llvm::StringSwitch<CPUKind>(CPU) 1756 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1757 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1758 #include "clang/Basic/X86Target.def" 1759 .Default(CK_Generic); 1760 } 1761 1762 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1763 return llvm::makeArrayRef(GCCRegNames); 1764 } 1765 1766 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1767 return llvm::makeArrayRef(AddlRegNames); 1768 } 1769 1770 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1771 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1772 Builtin::FirstTSBuiltin + 1); 1773 } 1774 1775 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1776 return llvm::makeArrayRef(BuiltinInfoX86, 1777 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1778 } 1779