1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+retpoline-external-thunk") { 280 HasRetpolineExternalThunk = true; 281 } else if (Feature == "+sahf") { 282 HasLAHFSAHF = true; 283 } else if (Feature == "+waitpkg") { 284 HasWAITPKG = true; 285 } else if (Feature == "+movdiri") { 286 HasMOVDIRI = true; 287 } else if (Feature == "+movdir64b") { 288 HasMOVDIR64B = true; 289 } else if (Feature == "+pconfig") { 290 HasPCONFIG = true; 291 } else if (Feature == "+ptwrite") { 292 HasPTWRITE = true; 293 } else if (Feature == "+invpcid") { 294 HasINVPCID = true; 295 } else if (Feature == "+enqcmd") { 296 HasENQCMD = true; 297 } else if (Feature == "+amx-bf16") { 298 HasAMXBF16 = true; 299 } else if (Feature == "+amx-int8") { 300 HasAMXINT8 = true; 301 } else if (Feature == "+amx-tile") { 302 HasAMXTILE = true; 303 } else if (Feature == "+serialize") { 304 HasSERIALIZE = true; 305 } else if (Feature == "+tsxldtrk") { 306 HasTSXLDTRK = true; 307 } 308 309 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 310 .Case("+avx512f", AVX512F) 311 .Case("+avx2", AVX2) 312 .Case("+avx", AVX) 313 .Case("+sse4.2", SSE42) 314 .Case("+sse4.1", SSE41) 315 .Case("+ssse3", SSSE3) 316 .Case("+sse3", SSE3) 317 .Case("+sse2", SSE2) 318 .Case("+sse", SSE1) 319 .Default(NoSSE); 320 SSELevel = std::max(SSELevel, Level); 321 322 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 323 .Case("+3dnowa", AMD3DNowAthlon) 324 .Case("+3dnow", AMD3DNow) 325 .Case("+mmx", MMX) 326 .Default(NoMMX3DNow); 327 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 328 329 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 330 .Case("+xop", XOP) 331 .Case("+fma4", FMA4) 332 .Case("+sse4a", SSE4A) 333 .Default(NoXOP); 334 XOPLevel = std::max(XOPLevel, XLevel); 335 } 336 337 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 338 // matches the selected sse level. 339 if ((FPMath == FP_SSE && SSELevel < SSE1) || 340 (FPMath == FP_387 && SSELevel >= SSE1)) { 341 Diags.Report(diag::err_target_unsupported_fpmath) 342 << (FPMath == FP_SSE ? "sse" : "387"); 343 return false; 344 } 345 346 SimdDefaultAlign = 347 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 348 return true; 349 } 350 351 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 352 /// definitions for this particular subtarget. 353 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 354 MacroBuilder &Builder) const { 355 // Inline assembly supports X86 flag outputs. 356 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 357 358 std::string CodeModel = getTargetOpts().CodeModel; 359 if (CodeModel == "default") 360 CodeModel = "small"; 361 Builder.defineMacro("__code_model_" + CodeModel + "__"); 362 363 // Target identification. 364 if (getTriple().getArch() == llvm::Triple::x86_64) { 365 Builder.defineMacro("__amd64__"); 366 Builder.defineMacro("__amd64"); 367 Builder.defineMacro("__x86_64"); 368 Builder.defineMacro("__x86_64__"); 369 if (getTriple().getArchName() == "x86_64h") { 370 Builder.defineMacro("__x86_64h"); 371 Builder.defineMacro("__x86_64h__"); 372 } 373 } else { 374 DefineStd(Builder, "i386", Opts); 375 } 376 377 Builder.defineMacro("__SEG_GS"); 378 Builder.defineMacro("__SEG_FS"); 379 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 380 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 381 382 // Subtarget options. 383 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 384 // truly should be based on -mtune options. 385 using namespace llvm::X86; 386 switch (CPU) { 387 case CK_None: 388 break; 389 case CK_i386: 390 // The rest are coming from the i386 define above. 391 Builder.defineMacro("__tune_i386__"); 392 break; 393 case CK_i486: 394 case CK_WinChipC6: 395 case CK_WinChip2: 396 case CK_C3: 397 defineCPUMacros(Builder, "i486"); 398 break; 399 case CK_PentiumMMX: 400 Builder.defineMacro("__pentium_mmx__"); 401 Builder.defineMacro("__tune_pentium_mmx__"); 402 LLVM_FALLTHROUGH; 403 case CK_i586: 404 case CK_Pentium: 405 defineCPUMacros(Builder, "i586"); 406 defineCPUMacros(Builder, "pentium"); 407 break; 408 case CK_Pentium3: 409 case CK_PentiumM: 410 Builder.defineMacro("__tune_pentium3__"); 411 LLVM_FALLTHROUGH; 412 case CK_Pentium2: 413 case CK_C3_2: 414 Builder.defineMacro("__tune_pentium2__"); 415 LLVM_FALLTHROUGH; 416 case CK_PentiumPro: 417 case CK_i686: 418 defineCPUMacros(Builder, "i686"); 419 defineCPUMacros(Builder, "pentiumpro"); 420 break; 421 case CK_Pentium4: 422 defineCPUMacros(Builder, "pentium4"); 423 break; 424 case CK_Yonah: 425 case CK_Prescott: 426 case CK_Nocona: 427 defineCPUMacros(Builder, "nocona"); 428 break; 429 case CK_Core2: 430 case CK_Penryn: 431 defineCPUMacros(Builder, "core2"); 432 break; 433 case CK_Bonnell: 434 defineCPUMacros(Builder, "atom"); 435 break; 436 case CK_Silvermont: 437 defineCPUMacros(Builder, "slm"); 438 break; 439 case CK_Goldmont: 440 defineCPUMacros(Builder, "goldmont"); 441 break; 442 case CK_GoldmontPlus: 443 defineCPUMacros(Builder, "goldmont_plus"); 444 break; 445 case CK_Tremont: 446 defineCPUMacros(Builder, "tremont"); 447 break; 448 case CK_Nehalem: 449 case CK_Westmere: 450 case CK_SandyBridge: 451 case CK_IvyBridge: 452 case CK_Haswell: 453 case CK_Broadwell: 454 case CK_SkylakeClient: 455 case CK_SkylakeServer: 456 case CK_Cascadelake: 457 case CK_Cooperlake: 458 case CK_Cannonlake: 459 case CK_IcelakeClient: 460 case CK_IcelakeServer: 461 case CK_Tigerlake: 462 // FIXME: Historically, we defined this legacy name, it would be nice to 463 // remove it at some point. We've never exposed fine-grained names for 464 // recent primary x86 CPUs, and we should keep it that way. 465 defineCPUMacros(Builder, "corei7"); 466 break; 467 case CK_KNL: 468 defineCPUMacros(Builder, "knl"); 469 break; 470 case CK_KNM: 471 break; 472 case CK_Lakemont: 473 defineCPUMacros(Builder, "i586", /*Tuning*/false); 474 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 475 Builder.defineMacro("__tune_lakemont__"); 476 break; 477 case CK_K6_2: 478 Builder.defineMacro("__k6_2__"); 479 Builder.defineMacro("__tune_k6_2__"); 480 LLVM_FALLTHROUGH; 481 case CK_K6_3: 482 if (CPU != CK_K6_2) { // In case of fallthrough 483 // FIXME: GCC may be enabling these in cases where some other k6 484 // architecture is specified but -m3dnow is explicitly provided. The 485 // exact semantics need to be determined and emulated here. 486 Builder.defineMacro("__k6_3__"); 487 Builder.defineMacro("__tune_k6_3__"); 488 } 489 LLVM_FALLTHROUGH; 490 case CK_K6: 491 defineCPUMacros(Builder, "k6"); 492 break; 493 case CK_Athlon: 494 case CK_AthlonXP: 495 defineCPUMacros(Builder, "athlon"); 496 if (SSELevel != NoSSE) { 497 Builder.defineMacro("__athlon_sse__"); 498 Builder.defineMacro("__tune_athlon_sse__"); 499 } 500 break; 501 case CK_K8: 502 case CK_K8SSE3: 503 case CK_x86_64: 504 defineCPUMacros(Builder, "k8"); 505 break; 506 case CK_AMDFAM10: 507 defineCPUMacros(Builder, "amdfam10"); 508 break; 509 case CK_BTVER1: 510 defineCPUMacros(Builder, "btver1"); 511 break; 512 case CK_BTVER2: 513 defineCPUMacros(Builder, "btver2"); 514 break; 515 case CK_BDVER1: 516 defineCPUMacros(Builder, "bdver1"); 517 break; 518 case CK_BDVER2: 519 defineCPUMacros(Builder, "bdver2"); 520 break; 521 case CK_BDVER3: 522 defineCPUMacros(Builder, "bdver3"); 523 break; 524 case CK_BDVER4: 525 defineCPUMacros(Builder, "bdver4"); 526 break; 527 case CK_ZNVER1: 528 defineCPUMacros(Builder, "znver1"); 529 break; 530 case CK_ZNVER2: 531 defineCPUMacros(Builder, "znver2"); 532 break; 533 case CK_Geode: 534 defineCPUMacros(Builder, "geode"); 535 break; 536 } 537 538 // Target properties. 539 Builder.defineMacro("__REGISTER_PREFIX__", ""); 540 541 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 542 // functions in glibc header files that use FP Stack inline asm which the 543 // backend can't deal with (PR879). 544 Builder.defineMacro("__NO_MATH_INLINES"); 545 546 if (HasAES) 547 Builder.defineMacro("__AES__"); 548 549 if (HasVAES) 550 Builder.defineMacro("__VAES__"); 551 552 if (HasPCLMUL) 553 Builder.defineMacro("__PCLMUL__"); 554 555 if (HasVPCLMULQDQ) 556 Builder.defineMacro("__VPCLMULQDQ__"); 557 558 if (HasLZCNT) 559 Builder.defineMacro("__LZCNT__"); 560 561 if (HasRDRND) 562 Builder.defineMacro("__RDRND__"); 563 564 if (HasFSGSBASE) 565 Builder.defineMacro("__FSGSBASE__"); 566 567 if (HasBMI) 568 Builder.defineMacro("__BMI__"); 569 570 if (HasBMI2) 571 Builder.defineMacro("__BMI2__"); 572 573 if (HasPOPCNT) 574 Builder.defineMacro("__POPCNT__"); 575 576 if (HasRTM) 577 Builder.defineMacro("__RTM__"); 578 579 if (HasPRFCHW) 580 Builder.defineMacro("__PRFCHW__"); 581 582 if (HasRDSEED) 583 Builder.defineMacro("__RDSEED__"); 584 585 if (HasADX) 586 Builder.defineMacro("__ADX__"); 587 588 if (HasTBM) 589 Builder.defineMacro("__TBM__"); 590 591 if (HasLWP) 592 Builder.defineMacro("__LWP__"); 593 594 if (HasMWAITX) 595 Builder.defineMacro("__MWAITX__"); 596 597 if (HasMOVBE) 598 Builder.defineMacro("__MOVBE__"); 599 600 switch (XOPLevel) { 601 case XOP: 602 Builder.defineMacro("__XOP__"); 603 LLVM_FALLTHROUGH; 604 case FMA4: 605 Builder.defineMacro("__FMA4__"); 606 LLVM_FALLTHROUGH; 607 case SSE4A: 608 Builder.defineMacro("__SSE4A__"); 609 LLVM_FALLTHROUGH; 610 case NoXOP: 611 break; 612 } 613 614 if (HasFMA) 615 Builder.defineMacro("__FMA__"); 616 617 if (HasF16C) 618 Builder.defineMacro("__F16C__"); 619 620 if (HasGFNI) 621 Builder.defineMacro("__GFNI__"); 622 623 if (HasAVX512CD) 624 Builder.defineMacro("__AVX512CD__"); 625 if (HasAVX512VPOPCNTDQ) 626 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 627 if (HasAVX512VNNI) 628 Builder.defineMacro("__AVX512VNNI__"); 629 if (HasAVX512BF16) 630 Builder.defineMacro("__AVX512BF16__"); 631 if (HasAVX512ER) 632 Builder.defineMacro("__AVX512ER__"); 633 if (HasAVX512PF) 634 Builder.defineMacro("__AVX512PF__"); 635 if (HasAVX512DQ) 636 Builder.defineMacro("__AVX512DQ__"); 637 if (HasAVX512BITALG) 638 Builder.defineMacro("__AVX512BITALG__"); 639 if (HasAVX512BW) 640 Builder.defineMacro("__AVX512BW__"); 641 if (HasAVX512VL) 642 Builder.defineMacro("__AVX512VL__"); 643 if (HasAVX512VBMI) 644 Builder.defineMacro("__AVX512VBMI__"); 645 if (HasAVX512VBMI2) 646 Builder.defineMacro("__AVX512VBMI2__"); 647 if (HasAVX512IFMA) 648 Builder.defineMacro("__AVX512IFMA__"); 649 if (HasAVX512VP2INTERSECT) 650 Builder.defineMacro("__AVX512VP2INTERSECT__"); 651 if (HasSHA) 652 Builder.defineMacro("__SHA__"); 653 654 if (HasFXSR) 655 Builder.defineMacro("__FXSR__"); 656 if (HasXSAVE) 657 Builder.defineMacro("__XSAVE__"); 658 if (HasXSAVEOPT) 659 Builder.defineMacro("__XSAVEOPT__"); 660 if (HasXSAVEC) 661 Builder.defineMacro("__XSAVEC__"); 662 if (HasXSAVES) 663 Builder.defineMacro("__XSAVES__"); 664 if (HasPKU) 665 Builder.defineMacro("__PKU__"); 666 if (HasCLFLUSHOPT) 667 Builder.defineMacro("__CLFLUSHOPT__"); 668 if (HasCLWB) 669 Builder.defineMacro("__CLWB__"); 670 if (HasWBNOINVD) 671 Builder.defineMacro("__WBNOINVD__"); 672 if (HasSHSTK) 673 Builder.defineMacro("__SHSTK__"); 674 if (HasSGX) 675 Builder.defineMacro("__SGX__"); 676 if (HasPREFETCHWT1) 677 Builder.defineMacro("__PREFETCHWT1__"); 678 if (HasCLZERO) 679 Builder.defineMacro("__CLZERO__"); 680 if (HasRDPID) 681 Builder.defineMacro("__RDPID__"); 682 if (HasCLDEMOTE) 683 Builder.defineMacro("__CLDEMOTE__"); 684 if (HasWAITPKG) 685 Builder.defineMacro("__WAITPKG__"); 686 if (HasMOVDIRI) 687 Builder.defineMacro("__MOVDIRI__"); 688 if (HasMOVDIR64B) 689 Builder.defineMacro("__MOVDIR64B__"); 690 if (HasPCONFIG) 691 Builder.defineMacro("__PCONFIG__"); 692 if (HasPTWRITE) 693 Builder.defineMacro("__PTWRITE__"); 694 if (HasINVPCID) 695 Builder.defineMacro("__INVPCID__"); 696 if (HasENQCMD) 697 Builder.defineMacro("__ENQCMD__"); 698 if (HasAMXTILE) 699 Builder.defineMacro("__AMXTILE__"); 700 if (HasAMXINT8) 701 Builder.defineMacro("__AMXINT8__"); 702 if (HasAMXBF16) 703 Builder.defineMacro("__AMXBF16__"); 704 if (HasSERIALIZE) 705 Builder.defineMacro("__SERIALIZE__"); 706 if (HasTSXLDTRK) 707 Builder.defineMacro("__TSXLDTRK__"); 708 709 // Each case falls through to the previous one here. 710 switch (SSELevel) { 711 case AVX512F: 712 Builder.defineMacro("__AVX512F__"); 713 LLVM_FALLTHROUGH; 714 case AVX2: 715 Builder.defineMacro("__AVX2__"); 716 LLVM_FALLTHROUGH; 717 case AVX: 718 Builder.defineMacro("__AVX__"); 719 LLVM_FALLTHROUGH; 720 case SSE42: 721 Builder.defineMacro("__SSE4_2__"); 722 LLVM_FALLTHROUGH; 723 case SSE41: 724 Builder.defineMacro("__SSE4_1__"); 725 LLVM_FALLTHROUGH; 726 case SSSE3: 727 Builder.defineMacro("__SSSE3__"); 728 LLVM_FALLTHROUGH; 729 case SSE3: 730 Builder.defineMacro("__SSE3__"); 731 LLVM_FALLTHROUGH; 732 case SSE2: 733 Builder.defineMacro("__SSE2__"); 734 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 735 LLVM_FALLTHROUGH; 736 case SSE1: 737 Builder.defineMacro("__SSE__"); 738 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 739 LLVM_FALLTHROUGH; 740 case NoSSE: 741 break; 742 } 743 744 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 745 switch (SSELevel) { 746 case AVX512F: 747 case AVX2: 748 case AVX: 749 case SSE42: 750 case SSE41: 751 case SSSE3: 752 case SSE3: 753 case SSE2: 754 Builder.defineMacro("_M_IX86_FP", Twine(2)); 755 break; 756 case SSE1: 757 Builder.defineMacro("_M_IX86_FP", Twine(1)); 758 break; 759 default: 760 Builder.defineMacro("_M_IX86_FP", Twine(0)); 761 break; 762 } 763 } 764 765 // Each case falls through to the previous one here. 766 switch (MMX3DNowLevel) { 767 case AMD3DNowAthlon: 768 Builder.defineMacro("__3dNOW_A__"); 769 LLVM_FALLTHROUGH; 770 case AMD3DNow: 771 Builder.defineMacro("__3dNOW__"); 772 LLVM_FALLTHROUGH; 773 case MMX: 774 Builder.defineMacro("__MMX__"); 775 LLVM_FALLTHROUGH; 776 case NoMMX3DNow: 777 break; 778 } 779 780 if (CPU >= CK_i486 || CPU == CK_None) { 781 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 782 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 783 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 784 } 785 if (HasCX8) 786 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 787 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 788 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 789 790 if (HasFloat128) 791 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 792 } 793 794 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 795 return llvm::StringSwitch<bool>(Name) 796 .Case("3dnow", true) 797 .Case("3dnowa", true) 798 .Case("adx", true) 799 .Case("aes", true) 800 .Case("amx-bf16", true) 801 .Case("amx-int8", true) 802 .Case("amx-tile", true) 803 .Case("avx", true) 804 .Case("avx2", true) 805 .Case("avx512f", true) 806 .Case("avx512cd", true) 807 .Case("avx512vpopcntdq", true) 808 .Case("avx512vnni", true) 809 .Case("avx512bf16", true) 810 .Case("avx512er", true) 811 .Case("avx512pf", true) 812 .Case("avx512dq", true) 813 .Case("avx512bitalg", true) 814 .Case("avx512bw", true) 815 .Case("avx512vl", true) 816 .Case("avx512vbmi", true) 817 .Case("avx512vbmi2", true) 818 .Case("avx512ifma", true) 819 .Case("avx512vp2intersect", true) 820 .Case("bmi", true) 821 .Case("bmi2", true) 822 .Case("cldemote", true) 823 .Case("clflushopt", true) 824 .Case("clwb", true) 825 .Case("clzero", true) 826 .Case("cx16", true) 827 .Case("enqcmd", true) 828 .Case("f16c", true) 829 .Case("fma", true) 830 .Case("fma4", true) 831 .Case("fsgsbase", true) 832 .Case("fxsr", true) 833 .Case("gfni", true) 834 .Case("invpcid", true) 835 .Case("lwp", true) 836 .Case("lzcnt", true) 837 .Case("mmx", true) 838 .Case("movbe", true) 839 .Case("movdiri", true) 840 .Case("movdir64b", true) 841 .Case("mwaitx", true) 842 .Case("pclmul", true) 843 .Case("pconfig", true) 844 .Case("pku", true) 845 .Case("popcnt", true) 846 .Case("prefetchwt1", true) 847 .Case("prfchw", true) 848 .Case("ptwrite", true) 849 .Case("rdpid", true) 850 .Case("rdrnd", true) 851 .Case("rdseed", true) 852 .Case("rtm", true) 853 .Case("sahf", true) 854 .Case("serialize", true) 855 .Case("sgx", true) 856 .Case("sha", true) 857 .Case("shstk", true) 858 .Case("sse", true) 859 .Case("sse2", true) 860 .Case("sse3", true) 861 .Case("ssse3", true) 862 .Case("sse4", true) 863 .Case("sse4.1", true) 864 .Case("sse4.2", true) 865 .Case("sse4a", true) 866 .Case("tbm", true) 867 .Case("tsxldtrk", true) 868 .Case("vaes", true) 869 .Case("vpclmulqdq", true) 870 .Case("wbnoinvd", true) 871 .Case("waitpkg", true) 872 .Case("x87", true) 873 .Case("xop", true) 874 .Case("xsave", true) 875 .Case("xsavec", true) 876 .Case("xsaves", true) 877 .Case("xsaveopt", true) 878 .Default(false); 879 } 880 881 bool X86TargetInfo::hasFeature(StringRef Feature) const { 882 return llvm::StringSwitch<bool>(Feature) 883 .Case("adx", HasADX) 884 .Case("aes", HasAES) 885 .Case("amx-bf16", HasAMXBF16) 886 .Case("amx-int8", HasAMXINT8) 887 .Case("amx-tile", HasAMXTILE) 888 .Case("avx", SSELevel >= AVX) 889 .Case("avx2", SSELevel >= AVX2) 890 .Case("avx512f", SSELevel >= AVX512F) 891 .Case("avx512cd", HasAVX512CD) 892 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 893 .Case("avx512vnni", HasAVX512VNNI) 894 .Case("avx512bf16", HasAVX512BF16) 895 .Case("avx512er", HasAVX512ER) 896 .Case("avx512pf", HasAVX512PF) 897 .Case("avx512dq", HasAVX512DQ) 898 .Case("avx512bitalg", HasAVX512BITALG) 899 .Case("avx512bw", HasAVX512BW) 900 .Case("avx512vl", HasAVX512VL) 901 .Case("avx512vbmi", HasAVX512VBMI) 902 .Case("avx512vbmi2", HasAVX512VBMI2) 903 .Case("avx512ifma", HasAVX512IFMA) 904 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 905 .Case("bmi", HasBMI) 906 .Case("bmi2", HasBMI2) 907 .Case("cldemote", HasCLDEMOTE) 908 .Case("clflushopt", HasCLFLUSHOPT) 909 .Case("clwb", HasCLWB) 910 .Case("clzero", HasCLZERO) 911 .Case("cx8", HasCX8) 912 .Case("cx16", HasCX16) 913 .Case("enqcmd", HasENQCMD) 914 .Case("f16c", HasF16C) 915 .Case("fma", HasFMA) 916 .Case("fma4", XOPLevel >= FMA4) 917 .Case("fsgsbase", HasFSGSBASE) 918 .Case("fxsr", HasFXSR) 919 .Case("gfni", HasGFNI) 920 .Case("invpcid", HasINVPCID) 921 .Case("lwp", HasLWP) 922 .Case("lzcnt", HasLZCNT) 923 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 924 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 925 .Case("mmx", MMX3DNowLevel >= MMX) 926 .Case("movbe", HasMOVBE) 927 .Case("movdiri", HasMOVDIRI) 928 .Case("movdir64b", HasMOVDIR64B) 929 .Case("mwaitx", HasMWAITX) 930 .Case("pclmul", HasPCLMUL) 931 .Case("pconfig", HasPCONFIG) 932 .Case("pku", HasPKU) 933 .Case("popcnt", HasPOPCNT) 934 .Case("prefetchwt1", HasPREFETCHWT1) 935 .Case("prfchw", HasPRFCHW) 936 .Case("ptwrite", HasPTWRITE) 937 .Case("rdpid", HasRDPID) 938 .Case("rdrnd", HasRDRND) 939 .Case("rdseed", HasRDSEED) 940 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 941 .Case("rtm", HasRTM) 942 .Case("sahf", HasLAHFSAHF) 943 .Case("serialize", HasSERIALIZE) 944 .Case("sgx", HasSGX) 945 .Case("sha", HasSHA) 946 .Case("shstk", HasSHSTK) 947 .Case("sse", SSELevel >= SSE1) 948 .Case("sse2", SSELevel >= SSE2) 949 .Case("sse3", SSELevel >= SSE3) 950 .Case("ssse3", SSELevel >= SSSE3) 951 .Case("sse4.1", SSELevel >= SSE41) 952 .Case("sse4.2", SSELevel >= SSE42) 953 .Case("sse4a", XOPLevel >= SSE4A) 954 .Case("tbm", HasTBM) 955 .Case("tsxldtrk", HasTSXLDTRK) 956 .Case("vaes", HasVAES) 957 .Case("vpclmulqdq", HasVPCLMULQDQ) 958 .Case("wbnoinvd", HasWBNOINVD) 959 .Case("waitpkg", HasWAITPKG) 960 .Case("x86", true) 961 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 962 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 963 .Case("xop", XOPLevel >= XOP) 964 .Case("xsave", HasXSAVE) 965 .Case("xsavec", HasXSAVEC) 966 .Case("xsaves", HasXSAVES) 967 .Case("xsaveopt", HasXSAVEOPT) 968 .Default(false); 969 } 970 971 // We can't use a generic validation scheme for the features accepted here 972 // versus subtarget features accepted in the target attribute because the 973 // bitfield structure that's initialized in the runtime only supports the 974 // below currently rather than the full range of subtarget features. (See 975 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 976 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 977 return llvm::StringSwitch<bool>(FeatureStr) 978 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 979 #include "llvm/Support/X86TargetParser.def" 980 .Default(false); 981 } 982 983 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 984 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 985 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 986 #include "llvm/Support/X86TargetParser.def" 987 ; 988 // Note, this function should only be used after ensuring the value is 989 // correct, so it asserts if the value is out of range. 990 } 991 992 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 993 enum class FeatPriority { 994 #define FEATURE(FEAT) FEAT, 995 #include "clang/Basic/X86Target.def" 996 }; 997 switch (Feat) { 998 #define FEATURE(FEAT) \ 999 case llvm::X86::FEAT: \ 1000 return static_cast<unsigned>(FeatPriority::FEAT); 1001 #include "clang/Basic/X86Target.def" 1002 default: 1003 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1004 } 1005 } 1006 1007 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1008 // Valid CPUs have a 'key feature' that compares just better than its key 1009 // feature. 1010 using namespace llvm::X86; 1011 CPUKind Kind = parseArchX86(Name); 1012 if (Kind != CK_None) { 1013 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1014 return (getFeaturePriority(KeyFeature) << 1) + 1; 1015 } 1016 1017 // Now we know we have a feature, so get its priority and shift it a few so 1018 // that we have sufficient room for the CPUs (above). 1019 return getFeaturePriority(getFeature(Name)) << 1; 1020 } 1021 1022 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1023 return llvm::StringSwitch<bool>(Name) 1024 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1025 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1026 #include "clang/Basic/X86Target.def" 1027 .Default(false); 1028 } 1029 1030 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1031 return llvm::StringSwitch<StringRef>(Name) 1032 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1033 #include "clang/Basic/X86Target.def" 1034 .Default(Name); 1035 } 1036 1037 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1038 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1039 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1040 #include "clang/Basic/X86Target.def" 1041 .Default(0); 1042 } 1043 1044 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1045 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1046 StringRef WholeList = 1047 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1048 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1049 #include "clang/Basic/X86Target.def" 1050 .Default(""); 1051 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1052 } 1053 1054 // We can't use a generic validation scheme for the cpus accepted here 1055 // versus subtarget cpus accepted in the target attribute because the 1056 // variables intitialized by the runtime only support the below currently 1057 // rather than the full range of cpus. 1058 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1059 return llvm::StringSwitch<bool>(FeatureStr) 1060 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1061 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1062 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1063 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1064 #include "llvm/Support/X86TargetParser.def" 1065 .Default(false); 1066 } 1067 1068 static unsigned matchAsmCCConstraint(const char *&Name) { 1069 auto RV = llvm::StringSwitch<unsigned>(Name) 1070 .Case("@cca", 4) 1071 .Case("@ccae", 5) 1072 .Case("@ccb", 4) 1073 .Case("@ccbe", 5) 1074 .Case("@ccc", 4) 1075 .Case("@cce", 4) 1076 .Case("@ccz", 4) 1077 .Case("@ccg", 4) 1078 .Case("@ccge", 5) 1079 .Case("@ccl", 4) 1080 .Case("@ccle", 5) 1081 .Case("@ccna", 5) 1082 .Case("@ccnae", 6) 1083 .Case("@ccnb", 5) 1084 .Case("@ccnbe", 6) 1085 .Case("@ccnc", 5) 1086 .Case("@ccne", 5) 1087 .Case("@ccnz", 5) 1088 .Case("@ccng", 5) 1089 .Case("@ccnge", 6) 1090 .Case("@ccnl", 5) 1091 .Case("@ccnle", 6) 1092 .Case("@ccno", 5) 1093 .Case("@ccnp", 5) 1094 .Case("@ccns", 5) 1095 .Case("@cco", 4) 1096 .Case("@ccp", 4) 1097 .Case("@ccs", 4) 1098 .Default(0); 1099 return RV; 1100 } 1101 1102 bool X86TargetInfo::validateAsmConstraint( 1103 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1104 switch (*Name) { 1105 default: 1106 return false; 1107 // Constant constraints. 1108 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1109 // instructions. 1110 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1111 // x86_64 instructions. 1112 case 's': 1113 Info.setRequiresImmediate(); 1114 return true; 1115 case 'I': 1116 Info.setRequiresImmediate(0, 31); 1117 return true; 1118 case 'J': 1119 Info.setRequiresImmediate(0, 63); 1120 return true; 1121 case 'K': 1122 Info.setRequiresImmediate(-128, 127); 1123 return true; 1124 case 'L': 1125 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1126 return true; 1127 case 'M': 1128 Info.setRequiresImmediate(0, 3); 1129 return true; 1130 case 'N': 1131 Info.setRequiresImmediate(0, 255); 1132 return true; 1133 case 'O': 1134 Info.setRequiresImmediate(0, 127); 1135 return true; 1136 // Register constraints. 1137 case 'Y': // 'Y' is the first character for several 2-character constraints. 1138 // Shift the pointer to the second character of the constraint. 1139 Name++; 1140 switch (*Name) { 1141 default: 1142 return false; 1143 case 'z': // First SSE register. 1144 case '2': 1145 case 't': // Any SSE register, when SSE2 is enabled. 1146 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1147 case 'm': // Any MMX register, when inter-unit moves enabled. 1148 case 'k': // AVX512 arch mask registers: k1-k7. 1149 Info.setAllowsRegister(); 1150 return true; 1151 } 1152 case 'f': // Any x87 floating point stack register. 1153 // Constraint 'f' cannot be used for output operands. 1154 if (Info.ConstraintStr[0] == '=') 1155 return false; 1156 Info.setAllowsRegister(); 1157 return true; 1158 case 'a': // eax. 1159 case 'b': // ebx. 1160 case 'c': // ecx. 1161 case 'd': // edx. 1162 case 'S': // esi. 1163 case 'D': // edi. 1164 case 'A': // edx:eax. 1165 case 't': // Top of floating point stack. 1166 case 'u': // Second from top of floating point stack. 1167 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1168 case 'y': // Any MMX register. 1169 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1170 case 'x': // Any SSE register. 1171 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1172 // for intermideate k reg operations). 1173 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1174 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1175 case 'l': // "Index" registers: any general register that can be used as an 1176 // index in a base+index memory access. 1177 Info.setAllowsRegister(); 1178 return true; 1179 // Floating point constant constraints. 1180 case 'C': // SSE floating point constant. 1181 case 'G': // x87 floating point constant. 1182 return true; 1183 case '@': 1184 // CC condition changes. 1185 if (auto Len = matchAsmCCConstraint(Name)) { 1186 Name += Len - 1; 1187 Info.setAllowsRegister(); 1188 return true; 1189 } 1190 return false; 1191 } 1192 } 1193 1194 // Below is based on the following information: 1195 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1196 // | Processor Name | Cache Line Size (Bytes) | Source | 1197 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1198 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1199 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1200 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1201 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1202 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1203 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1204 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1205 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1206 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1207 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1208 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1209 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1210 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1211 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1212 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1213 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1214 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1215 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1216 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1217 using namespace llvm::X86; 1218 switch (CPU) { 1219 // i386 1220 case CK_i386: 1221 // i486 1222 case CK_i486: 1223 case CK_WinChipC6: 1224 case CK_WinChip2: 1225 case CK_C3: 1226 // Lakemont 1227 case CK_Lakemont: 1228 return 16; 1229 1230 // i586 1231 case CK_i586: 1232 case CK_Pentium: 1233 case CK_PentiumMMX: 1234 // i686 1235 case CK_PentiumPro: 1236 case CK_i686: 1237 case CK_Pentium2: 1238 case CK_Pentium3: 1239 case CK_PentiumM: 1240 case CK_C3_2: 1241 // K6 1242 case CK_K6: 1243 case CK_K6_2: 1244 case CK_K6_3: 1245 // Geode 1246 case CK_Geode: 1247 return 32; 1248 1249 // Netburst 1250 case CK_Pentium4: 1251 case CK_Prescott: 1252 case CK_Nocona: 1253 // Atom 1254 case CK_Bonnell: 1255 case CK_Silvermont: 1256 case CK_Goldmont: 1257 case CK_GoldmontPlus: 1258 case CK_Tremont: 1259 1260 case CK_Westmere: 1261 case CK_SandyBridge: 1262 case CK_IvyBridge: 1263 case CK_Haswell: 1264 case CK_Broadwell: 1265 case CK_SkylakeClient: 1266 case CK_SkylakeServer: 1267 case CK_Cascadelake: 1268 case CK_Nehalem: 1269 case CK_Cooperlake: 1270 case CK_Cannonlake: 1271 case CK_Tigerlake: 1272 case CK_IcelakeClient: 1273 case CK_IcelakeServer: 1274 case CK_KNL: 1275 case CK_KNM: 1276 // K7 1277 case CK_Athlon: 1278 case CK_AthlonXP: 1279 // K8 1280 case CK_K8: 1281 case CK_K8SSE3: 1282 case CK_AMDFAM10: 1283 // Bobcat 1284 case CK_BTVER1: 1285 case CK_BTVER2: 1286 // Bulldozer 1287 case CK_BDVER1: 1288 case CK_BDVER2: 1289 case CK_BDVER3: 1290 case CK_BDVER4: 1291 // Zen 1292 case CK_ZNVER1: 1293 case CK_ZNVER2: 1294 // Deprecated 1295 case CK_x86_64: 1296 case CK_Yonah: 1297 case CK_Penryn: 1298 case CK_Core2: 1299 return 64; 1300 1301 // The following currently have unknown cache line sizes (but they are probably all 64): 1302 // Core 1303 case CK_None: 1304 return None; 1305 } 1306 llvm_unreachable("Unknown CPU kind"); 1307 } 1308 1309 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1310 StringRef Constraint, 1311 unsigned Size) const { 1312 // Strip off constraint modifiers. 1313 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1314 Constraint = Constraint.substr(1); 1315 1316 return validateOperandSize(FeatureMap, Constraint, Size); 1317 } 1318 1319 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1320 StringRef Constraint, 1321 unsigned Size) const { 1322 return validateOperandSize(FeatureMap, Constraint, Size); 1323 } 1324 1325 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1326 StringRef Constraint, 1327 unsigned Size) const { 1328 switch (Constraint[0]) { 1329 default: 1330 break; 1331 case 'k': 1332 // Registers k0-k7 (AVX512) size limit is 64 bit. 1333 case 'y': 1334 return Size <= 64; 1335 case 'f': 1336 case 't': 1337 case 'u': 1338 return Size <= 128; 1339 case 'Y': 1340 // 'Y' is the first character for several 2-character constraints. 1341 switch (Constraint[1]) { 1342 default: 1343 return false; 1344 case 'm': 1345 // 'Ym' is synonymous with 'y'. 1346 case 'k': 1347 return Size <= 64; 1348 case 'z': 1349 // XMM0/YMM/ZMM0 1350 if (FeatureMap.lookup("avx512f")) 1351 // ZMM0 can be used if target supports AVX512F. 1352 return Size <= 512U; 1353 else if (FeatureMap.lookup("avx")) 1354 // YMM0 can be used if target supports AVX. 1355 return Size <= 256U; 1356 else if (FeatureMap.lookup("sse")) 1357 return Size <= 128U; 1358 return false; 1359 case 'i': 1360 case 't': 1361 case '2': 1362 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1363 if (SSELevel < SSE2) 1364 return false; 1365 break; 1366 } 1367 break; 1368 case 'v': 1369 case 'x': 1370 if (FeatureMap.lookup("avx512f")) 1371 // 512-bit zmm registers can be used if target supports AVX512F. 1372 return Size <= 512U; 1373 else if (FeatureMap.lookup("avx")) 1374 // 256-bit ymm registers can be used if target supports AVX. 1375 return Size <= 256U; 1376 return Size <= 128U; 1377 1378 } 1379 1380 return true; 1381 } 1382 1383 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1384 switch (*Constraint) { 1385 case '@': 1386 if (auto Len = matchAsmCCConstraint(Constraint)) { 1387 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1388 Constraint += Len - 1; 1389 return Converted; 1390 } 1391 return std::string(1, *Constraint); 1392 case 'a': 1393 return std::string("{ax}"); 1394 case 'b': 1395 return std::string("{bx}"); 1396 case 'c': 1397 return std::string("{cx}"); 1398 case 'd': 1399 return std::string("{dx}"); 1400 case 'S': 1401 return std::string("{si}"); 1402 case 'D': 1403 return std::string("{di}"); 1404 case 'p': // address 1405 return std::string("im"); 1406 case 't': // top of floating point stack. 1407 return std::string("{st}"); 1408 case 'u': // second from top of floating point stack. 1409 return std::string("{st(1)}"); // second from top of floating point stack. 1410 case 'Y': 1411 switch (Constraint[1]) { 1412 default: 1413 // Break from inner switch and fall through (copy single char), 1414 // continue parsing after copying the current constraint into 1415 // the return string. 1416 break; 1417 case 'k': 1418 case 'm': 1419 case 'i': 1420 case 't': 1421 case 'z': 1422 case '2': 1423 // "^" hints llvm that this is a 2 letter constraint. 1424 // "Constraint++" is used to promote the string iterator 1425 // to the next constraint. 1426 return std::string("^") + std::string(Constraint++, 2); 1427 } 1428 LLVM_FALLTHROUGH; 1429 default: 1430 return std::string(1, *Constraint); 1431 } 1432 } 1433 1434 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1435 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1436 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1437 } 1438 1439 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1440 return llvm::makeArrayRef(GCCRegNames); 1441 } 1442 1443 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1444 return llvm::makeArrayRef(AddlRegNames); 1445 } 1446 1447 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1448 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1449 Builtin::FirstTSBuiltin + 1); 1450 } 1451 1452 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1453 return llvm::makeArrayRef(BuiltinInfoX86, 1454 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1455 } 1456