1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_IcelakeServer: 142 setFeatureEnabledImpl(Features, "pconfig", true); 143 setFeatureEnabledImpl(Features, "wbnoinvd", true); 144 LLVM_FALLTHROUGH; 145 case CK_IcelakeClient: 146 setFeatureEnabledImpl(Features, "vaes", true); 147 setFeatureEnabledImpl(Features, "gfni", true); 148 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 149 setFeatureEnabledImpl(Features, "avx512bitalg", true); 150 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 151 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 152 setFeatureEnabledImpl(Features, "rdpid", true); 153 LLVM_FALLTHROUGH; 154 case CK_Cannonlake: 155 setFeatureEnabledImpl(Features, "avx512ifma", true); 156 setFeatureEnabledImpl(Features, "avx512vbmi", true); 157 setFeatureEnabledImpl(Features, "sha", true); 158 LLVM_FALLTHROUGH; 159 case CK_Cascadelake: 160 //Cannonlake has no VNNI feature inside while Icelake has 161 if (Kind != CK_Cannonlake) 162 // CLK inherits all SKX features plus AVX512_VNNI 163 setFeatureEnabledImpl(Features, "avx512vnni", true); 164 LLVM_FALLTHROUGH; 165 case CK_SkylakeServer: 166 setFeatureEnabledImpl(Features, "avx512f", true); 167 setFeatureEnabledImpl(Features, "avx512cd", true); 168 setFeatureEnabledImpl(Features, "avx512dq", true); 169 setFeatureEnabledImpl(Features, "avx512bw", true); 170 setFeatureEnabledImpl(Features, "avx512vl", true); 171 setFeatureEnabledImpl(Features, "pku", true); 172 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 173 setFeatureEnabledImpl(Features, "clwb", true); 174 LLVM_FALLTHROUGH; 175 case CK_SkylakeClient: 176 setFeatureEnabledImpl(Features, "xsavec", true); 177 setFeatureEnabledImpl(Features, "xsaves", true); 178 setFeatureEnabledImpl(Features, "mpx", true); 179 if (Kind != CK_SkylakeServer 180 && Kind != CK_Cascadelake) 181 // SKX/CLX inherits all SKL features, except SGX 182 setFeatureEnabledImpl(Features, "sgx", true); 183 setFeatureEnabledImpl(Features, "clflushopt", true); 184 setFeatureEnabledImpl(Features, "aes", true); 185 LLVM_FALLTHROUGH; 186 case CK_Broadwell: 187 setFeatureEnabledImpl(Features, "rdseed", true); 188 setFeatureEnabledImpl(Features, "adx", true); 189 setFeatureEnabledImpl(Features, "prfchw", true); 190 LLVM_FALLTHROUGH; 191 case CK_Haswell: 192 setFeatureEnabledImpl(Features, "avx2", true); 193 setFeatureEnabledImpl(Features, "lzcnt", true); 194 setFeatureEnabledImpl(Features, "bmi", true); 195 setFeatureEnabledImpl(Features, "bmi2", true); 196 setFeatureEnabledImpl(Features, "fma", true); 197 setFeatureEnabledImpl(Features, "invpcid", true); 198 setFeatureEnabledImpl(Features, "movbe", true); 199 LLVM_FALLTHROUGH; 200 case CK_IvyBridge: 201 setFeatureEnabledImpl(Features, "rdrnd", true); 202 setFeatureEnabledImpl(Features, "f16c", true); 203 setFeatureEnabledImpl(Features, "fsgsbase", true); 204 LLVM_FALLTHROUGH; 205 case CK_SandyBridge: 206 setFeatureEnabledImpl(Features, "avx", true); 207 setFeatureEnabledImpl(Features, "xsave", true); 208 setFeatureEnabledImpl(Features, "xsaveopt", true); 209 LLVM_FALLTHROUGH; 210 case CK_Westmere: 211 setFeatureEnabledImpl(Features, "pclmul", true); 212 LLVM_FALLTHROUGH; 213 case CK_Nehalem: 214 setFeatureEnabledImpl(Features, "sse4.2", true); 215 LLVM_FALLTHROUGH; 216 case CK_Penryn: 217 setFeatureEnabledImpl(Features, "sse4.1", true); 218 LLVM_FALLTHROUGH; 219 case CK_Core2: 220 setFeatureEnabledImpl(Features, "ssse3", true); 221 setFeatureEnabledImpl(Features, "sahf", true); 222 LLVM_FALLTHROUGH; 223 case CK_Nocona: 224 setFeatureEnabledImpl(Features, "cx16", true); 225 LLVM_FALLTHROUGH; 226 case CK_Yonah: 227 case CK_Prescott: 228 setFeatureEnabledImpl(Features, "sse3", true); 229 LLVM_FALLTHROUGH; 230 case CK_PentiumM: 231 case CK_Pentium4: 232 case CK_x86_64: 233 setFeatureEnabledImpl(Features, "sse2", true); 234 LLVM_FALLTHROUGH; 235 case CK_Pentium3: 236 case CK_C3_2: 237 setFeatureEnabledImpl(Features, "sse", true); 238 setFeatureEnabledImpl(Features, "fxsr", true); 239 break; 240 241 case CK_Tremont: 242 setFeatureEnabledImpl(Features, "cldemote", true); 243 setFeatureEnabledImpl(Features, "movdiri", true); 244 setFeatureEnabledImpl(Features, "movdir64b", true); 245 setFeatureEnabledImpl(Features, "gfni", true); 246 setFeatureEnabledImpl(Features, "waitpkg", true); 247 LLVM_FALLTHROUGH; 248 case CK_GoldmontPlus: 249 setFeatureEnabledImpl(Features, "ptwrite", true); 250 setFeatureEnabledImpl(Features, "rdpid", true); 251 setFeatureEnabledImpl(Features, "sgx", true); 252 LLVM_FALLTHROUGH; 253 case CK_Goldmont: 254 setFeatureEnabledImpl(Features, "sha", true); 255 setFeatureEnabledImpl(Features, "rdseed", true); 256 setFeatureEnabledImpl(Features, "xsave", true); 257 setFeatureEnabledImpl(Features, "xsaveopt", true); 258 setFeatureEnabledImpl(Features, "xsavec", true); 259 setFeatureEnabledImpl(Features, "xsaves", true); 260 setFeatureEnabledImpl(Features, "clflushopt", true); 261 setFeatureEnabledImpl(Features, "mpx", true); 262 setFeatureEnabledImpl(Features, "fsgsbase", true); 263 setFeatureEnabledImpl(Features, "aes", true); 264 LLVM_FALLTHROUGH; 265 case CK_Silvermont: 266 setFeatureEnabledImpl(Features, "rdrnd", true); 267 setFeatureEnabledImpl(Features, "pclmul", true); 268 setFeatureEnabledImpl(Features, "sse4.2", true); 269 setFeatureEnabledImpl(Features, "prfchw", true); 270 LLVM_FALLTHROUGH; 271 case CK_Bonnell: 272 setFeatureEnabledImpl(Features, "movbe", true); 273 setFeatureEnabledImpl(Features, "ssse3", true); 274 setFeatureEnabledImpl(Features, "fxsr", true); 275 setFeatureEnabledImpl(Features, "cx16", true); 276 setFeatureEnabledImpl(Features, "sahf", true); 277 break; 278 279 case CK_KNM: 280 // TODO: Add avx5124fmaps/avx5124vnniw. 281 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 282 LLVM_FALLTHROUGH; 283 case CK_KNL: 284 setFeatureEnabledImpl(Features, "avx512f", true); 285 setFeatureEnabledImpl(Features, "avx512cd", true); 286 setFeatureEnabledImpl(Features, "avx512er", true); 287 setFeatureEnabledImpl(Features, "avx512pf", true); 288 setFeatureEnabledImpl(Features, "prfchw", true); 289 setFeatureEnabledImpl(Features, "prefetchwt1", true); 290 setFeatureEnabledImpl(Features, "fxsr", true); 291 setFeatureEnabledImpl(Features, "rdseed", true); 292 setFeatureEnabledImpl(Features, "adx", true); 293 setFeatureEnabledImpl(Features, "lzcnt", true); 294 setFeatureEnabledImpl(Features, "bmi", true); 295 setFeatureEnabledImpl(Features, "bmi2", true); 296 setFeatureEnabledImpl(Features, "fma", true); 297 setFeatureEnabledImpl(Features, "rdrnd", true); 298 setFeatureEnabledImpl(Features, "f16c", true); 299 setFeatureEnabledImpl(Features, "fsgsbase", true); 300 setFeatureEnabledImpl(Features, "aes", true); 301 setFeatureEnabledImpl(Features, "pclmul", true); 302 setFeatureEnabledImpl(Features, "cx16", true); 303 setFeatureEnabledImpl(Features, "xsaveopt", true); 304 setFeatureEnabledImpl(Features, "xsave", true); 305 setFeatureEnabledImpl(Features, "movbe", true); 306 setFeatureEnabledImpl(Features, "sahf", true); 307 break; 308 309 case CK_K6_2: 310 case CK_K6_3: 311 case CK_WinChip2: 312 case CK_C3: 313 setFeatureEnabledImpl(Features, "3dnow", true); 314 break; 315 316 case CK_AMDFAM10: 317 setFeatureEnabledImpl(Features, "sse4a", true); 318 setFeatureEnabledImpl(Features, "lzcnt", true); 319 setFeatureEnabledImpl(Features, "popcnt", true); 320 setFeatureEnabledImpl(Features, "sahf", true); 321 LLVM_FALLTHROUGH; 322 case CK_K8SSE3: 323 setFeatureEnabledImpl(Features, "sse3", true); 324 LLVM_FALLTHROUGH; 325 case CK_K8: 326 setFeatureEnabledImpl(Features, "sse2", true); 327 LLVM_FALLTHROUGH; 328 case CK_AthlonXP: 329 setFeatureEnabledImpl(Features, "sse", true); 330 setFeatureEnabledImpl(Features, "fxsr", true); 331 LLVM_FALLTHROUGH; 332 case CK_Athlon: 333 case CK_Geode: 334 setFeatureEnabledImpl(Features, "3dnowa", true); 335 break; 336 337 case CK_BTVER2: 338 setFeatureEnabledImpl(Features, "avx", true); 339 setFeatureEnabledImpl(Features, "aes", true); 340 setFeatureEnabledImpl(Features, "pclmul", true); 341 setFeatureEnabledImpl(Features, "bmi", true); 342 setFeatureEnabledImpl(Features, "f16c", true); 343 setFeatureEnabledImpl(Features, "xsaveopt", true); 344 setFeatureEnabledImpl(Features, "movbe", true); 345 LLVM_FALLTHROUGH; 346 case CK_BTVER1: 347 setFeatureEnabledImpl(Features, "ssse3", true); 348 setFeatureEnabledImpl(Features, "sse4a", true); 349 setFeatureEnabledImpl(Features, "lzcnt", true); 350 setFeatureEnabledImpl(Features, "popcnt", true); 351 setFeatureEnabledImpl(Features, "prfchw", true); 352 setFeatureEnabledImpl(Features, "cx16", true); 353 setFeatureEnabledImpl(Features, "fxsr", true); 354 setFeatureEnabledImpl(Features, "sahf", true); 355 break; 356 357 case CK_ZNVER2: 358 setFeatureEnabledImpl(Features, "clwb", true); 359 setFeatureEnabledImpl(Features, "rdpid", true); 360 setFeatureEnabledImpl(Features, "wbnoinvd", true); 361 LLVM_FALLTHROUGH; 362 case CK_ZNVER1: 363 setFeatureEnabledImpl(Features, "adx", true); 364 setFeatureEnabledImpl(Features, "aes", true); 365 setFeatureEnabledImpl(Features, "avx2", true); 366 setFeatureEnabledImpl(Features, "bmi", true); 367 setFeatureEnabledImpl(Features, "bmi2", true); 368 setFeatureEnabledImpl(Features, "clflushopt", true); 369 setFeatureEnabledImpl(Features, "clzero", true); 370 setFeatureEnabledImpl(Features, "cx16", true); 371 setFeatureEnabledImpl(Features, "f16c", true); 372 setFeatureEnabledImpl(Features, "fma", true); 373 setFeatureEnabledImpl(Features, "fsgsbase", true); 374 setFeatureEnabledImpl(Features, "fxsr", true); 375 setFeatureEnabledImpl(Features, "lzcnt", true); 376 setFeatureEnabledImpl(Features, "mwaitx", true); 377 setFeatureEnabledImpl(Features, "movbe", true); 378 setFeatureEnabledImpl(Features, "pclmul", true); 379 setFeatureEnabledImpl(Features, "popcnt", true); 380 setFeatureEnabledImpl(Features, "prfchw", true); 381 setFeatureEnabledImpl(Features, "rdrnd", true); 382 setFeatureEnabledImpl(Features, "rdseed", true); 383 setFeatureEnabledImpl(Features, "sahf", true); 384 setFeatureEnabledImpl(Features, "sha", true); 385 setFeatureEnabledImpl(Features, "sse4a", true); 386 setFeatureEnabledImpl(Features, "xsave", true); 387 setFeatureEnabledImpl(Features, "xsavec", true); 388 setFeatureEnabledImpl(Features, "xsaveopt", true); 389 setFeatureEnabledImpl(Features, "xsaves", true); 390 break; 391 392 case CK_BDVER4: 393 setFeatureEnabledImpl(Features, "avx2", true); 394 setFeatureEnabledImpl(Features, "bmi2", true); 395 setFeatureEnabledImpl(Features, "mwaitx", true); 396 LLVM_FALLTHROUGH; 397 case CK_BDVER3: 398 setFeatureEnabledImpl(Features, "fsgsbase", true); 399 setFeatureEnabledImpl(Features, "xsaveopt", true); 400 LLVM_FALLTHROUGH; 401 case CK_BDVER2: 402 setFeatureEnabledImpl(Features, "bmi", true); 403 setFeatureEnabledImpl(Features, "fma", true); 404 setFeatureEnabledImpl(Features, "f16c", true); 405 setFeatureEnabledImpl(Features, "tbm", true); 406 LLVM_FALLTHROUGH; 407 case CK_BDVER1: 408 // xop implies avx, sse4a and fma4. 409 setFeatureEnabledImpl(Features, "xop", true); 410 setFeatureEnabledImpl(Features, "lwp", true); 411 setFeatureEnabledImpl(Features, "lzcnt", true); 412 setFeatureEnabledImpl(Features, "aes", true); 413 setFeatureEnabledImpl(Features, "pclmul", true); 414 setFeatureEnabledImpl(Features, "prfchw", true); 415 setFeatureEnabledImpl(Features, "cx16", true); 416 setFeatureEnabledImpl(Features, "fxsr", true); 417 setFeatureEnabledImpl(Features, "xsave", true); 418 setFeatureEnabledImpl(Features, "sahf", true); 419 break; 420 } 421 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 422 return false; 423 424 // Can't do this earlier because we need to be able to explicitly enable 425 // or disable these features and the things that they depend upon. 426 427 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 428 auto I = Features.find("sse4.2"); 429 if (I != Features.end() && I->getValue() && 430 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 431 Features["popcnt"] = true; 432 433 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 434 I = Features.find("3dnow"); 435 if (I != Features.end() && I->getValue() && 436 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 437 Features["prfchw"] = true; 438 439 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 440 // then enable MMX. 441 I = Features.find("sse"); 442 if (I != Features.end() && I->getValue() && 443 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 444 Features["mmx"] = true; 445 446 return true; 447 } 448 449 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 450 X86SSEEnum Level, bool Enabled) { 451 if (Enabled) { 452 switch (Level) { 453 case AVX512F: 454 Features["avx512f"] = true; 455 Features["fma"] = true; 456 Features["f16c"] = true; 457 LLVM_FALLTHROUGH; 458 case AVX2: 459 Features["avx2"] = true; 460 LLVM_FALLTHROUGH; 461 case AVX: 462 Features["avx"] = true; 463 Features["xsave"] = true; 464 LLVM_FALLTHROUGH; 465 case SSE42: 466 Features["sse4.2"] = true; 467 LLVM_FALLTHROUGH; 468 case SSE41: 469 Features["sse4.1"] = true; 470 LLVM_FALLTHROUGH; 471 case SSSE3: 472 Features["ssse3"] = true; 473 LLVM_FALLTHROUGH; 474 case SSE3: 475 Features["sse3"] = true; 476 LLVM_FALLTHROUGH; 477 case SSE2: 478 Features["sse2"] = true; 479 LLVM_FALLTHROUGH; 480 case SSE1: 481 Features["sse"] = true; 482 LLVM_FALLTHROUGH; 483 case NoSSE: 484 break; 485 } 486 return; 487 } 488 489 switch (Level) { 490 case NoSSE: 491 case SSE1: 492 Features["sse"] = false; 493 LLVM_FALLTHROUGH; 494 case SSE2: 495 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 496 Features["sha"] = Features["gfni"] = false; 497 LLVM_FALLTHROUGH; 498 case SSE3: 499 Features["sse3"] = false; 500 setXOPLevel(Features, NoXOP, false); 501 LLVM_FALLTHROUGH; 502 case SSSE3: 503 Features["ssse3"] = false; 504 LLVM_FALLTHROUGH; 505 case SSE41: 506 Features["sse4.1"] = false; 507 LLVM_FALLTHROUGH; 508 case SSE42: 509 Features["sse4.2"] = false; 510 LLVM_FALLTHROUGH; 511 case AVX: 512 Features["fma"] = Features["avx"] = Features["f16c"] = false; 513 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 514 Features["vpclmulqdq"] = false; 515 setXOPLevel(Features, FMA4, false); 516 LLVM_FALLTHROUGH; 517 case AVX2: 518 Features["avx2"] = false; 519 LLVM_FALLTHROUGH; 520 case AVX512F: 521 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 522 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 523 Features["avx512vl"] = Features["avx512vbmi"] = false; 524 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 525 Features["avx512bitalg"] = Features["avx512vnni"] = false; 526 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 527 break; 528 } 529 } 530 531 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 532 MMX3DNowEnum Level, bool Enabled) { 533 if (Enabled) { 534 switch (Level) { 535 case AMD3DNowAthlon: 536 Features["3dnowa"] = true; 537 LLVM_FALLTHROUGH; 538 case AMD3DNow: 539 Features["3dnow"] = true; 540 LLVM_FALLTHROUGH; 541 case MMX: 542 Features["mmx"] = true; 543 LLVM_FALLTHROUGH; 544 case NoMMX3DNow: 545 break; 546 } 547 return; 548 } 549 550 switch (Level) { 551 case NoMMX3DNow: 552 case MMX: 553 Features["mmx"] = false; 554 LLVM_FALLTHROUGH; 555 case AMD3DNow: 556 Features["3dnow"] = false; 557 LLVM_FALLTHROUGH; 558 case AMD3DNowAthlon: 559 Features["3dnowa"] = false; 560 break; 561 } 562 } 563 564 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 565 bool Enabled) { 566 if (Enabled) { 567 switch (Level) { 568 case XOP: 569 Features["xop"] = true; 570 LLVM_FALLTHROUGH; 571 case FMA4: 572 Features["fma4"] = true; 573 setSSELevel(Features, AVX, true); 574 LLVM_FALLTHROUGH; 575 case SSE4A: 576 Features["sse4a"] = true; 577 setSSELevel(Features, SSE3, true); 578 LLVM_FALLTHROUGH; 579 case NoXOP: 580 break; 581 } 582 return; 583 } 584 585 switch (Level) { 586 case NoXOP: 587 case SSE4A: 588 Features["sse4a"] = false; 589 LLVM_FALLTHROUGH; 590 case FMA4: 591 Features["fma4"] = false; 592 LLVM_FALLTHROUGH; 593 case XOP: 594 Features["xop"] = false; 595 break; 596 } 597 } 598 599 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 600 StringRef Name, bool Enabled) { 601 // This is a bit of a hack to deal with the sse4 target feature when used 602 // as part of the target attribute. We handle sse4 correctly everywhere 603 // else. See below for more information on how we handle the sse4 options. 604 if (Name != "sse4") 605 Features[Name] = Enabled; 606 607 if (Name == "mmx") { 608 setMMXLevel(Features, MMX, Enabled); 609 } else if (Name == "sse") { 610 setSSELevel(Features, SSE1, Enabled); 611 } else if (Name == "sse2") { 612 setSSELevel(Features, SSE2, Enabled); 613 } else if (Name == "sse3") { 614 setSSELevel(Features, SSE3, Enabled); 615 } else if (Name == "ssse3") { 616 setSSELevel(Features, SSSE3, Enabled); 617 } else if (Name == "sse4.2") { 618 setSSELevel(Features, SSE42, Enabled); 619 } else if (Name == "sse4.1") { 620 setSSELevel(Features, SSE41, Enabled); 621 } else if (Name == "3dnow") { 622 setMMXLevel(Features, AMD3DNow, Enabled); 623 } else if (Name == "3dnowa") { 624 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 625 } else if (Name == "aes") { 626 if (Enabled) 627 setSSELevel(Features, SSE2, Enabled); 628 else 629 Features["vaes"] = false; 630 } else if (Name == "vaes") { 631 if (Enabled) { 632 setSSELevel(Features, AVX, Enabled); 633 Features["aes"] = true; 634 } 635 } else if (Name == "pclmul") { 636 if (Enabled) 637 setSSELevel(Features, SSE2, Enabled); 638 else 639 Features["vpclmulqdq"] = false; 640 } else if (Name == "vpclmulqdq") { 641 if (Enabled) { 642 setSSELevel(Features, AVX, Enabled); 643 Features["pclmul"] = true; 644 } 645 } else if (Name == "gfni") { 646 if (Enabled) 647 setSSELevel(Features, SSE2, Enabled); 648 } else if (Name == "avx") { 649 setSSELevel(Features, AVX, Enabled); 650 } else if (Name == "avx2") { 651 setSSELevel(Features, AVX2, Enabled); 652 } else if (Name == "avx512f") { 653 setSSELevel(Features, AVX512F, Enabled); 654 } else if (Name.startswith("avx512")) { 655 if (Enabled) 656 setSSELevel(Features, AVX512F, Enabled); 657 // Enable BWI instruction if certain features are being enabled. 658 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 659 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 660 Features["avx512bw"] = true; 661 // Also disable some features if BWI is being disabled. 662 if (Name == "avx512bw" && !Enabled) { 663 Features["avx512vbmi"] = false; 664 Features["avx512vbmi2"] = false; 665 Features["avx512bitalg"] = false; 666 Features["avx512bf16"] = false; 667 } 668 } else if (Name == "fma") { 669 if (Enabled) 670 setSSELevel(Features, AVX, Enabled); 671 else 672 setSSELevel(Features, AVX512F, Enabled); 673 } else if (Name == "fma4") { 674 setXOPLevel(Features, FMA4, Enabled); 675 } else if (Name == "xop") { 676 setXOPLevel(Features, XOP, Enabled); 677 } else if (Name == "sse4a") { 678 setXOPLevel(Features, SSE4A, Enabled); 679 } else if (Name == "f16c") { 680 if (Enabled) 681 setSSELevel(Features, AVX, Enabled); 682 else 683 setSSELevel(Features, AVX512F, Enabled); 684 } else if (Name == "sha") { 685 if (Enabled) 686 setSSELevel(Features, SSE2, Enabled); 687 } else if (Name == "sse4") { 688 // We can get here via the __target__ attribute since that's not controlled 689 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 690 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 691 // disabled. 692 if (Enabled) 693 setSSELevel(Features, SSE42, Enabled); 694 else 695 setSSELevel(Features, SSE41, Enabled); 696 } else if (Name == "xsave") { 697 if (!Enabled) 698 Features["xsaveopt"] = false; 699 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 700 if (Enabled) 701 Features["xsave"] = true; 702 } 703 } 704 705 /// handleTargetFeatures - Perform initialization based on the user 706 /// configured set of features. 707 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 708 DiagnosticsEngine &Diags) { 709 for (const auto &Feature : Features) { 710 if (Feature[0] != '+') 711 continue; 712 713 if (Feature == "+aes") { 714 HasAES = true; 715 } else if (Feature == "+vaes") { 716 HasVAES = true; 717 } else if (Feature == "+pclmul") { 718 HasPCLMUL = true; 719 } else if (Feature == "+vpclmulqdq") { 720 HasVPCLMULQDQ = true; 721 } else if (Feature == "+lzcnt") { 722 HasLZCNT = true; 723 } else if (Feature == "+rdrnd") { 724 HasRDRND = true; 725 } else if (Feature == "+fsgsbase") { 726 HasFSGSBASE = true; 727 } else if (Feature == "+bmi") { 728 HasBMI = true; 729 } else if (Feature == "+bmi2") { 730 HasBMI2 = true; 731 } else if (Feature == "+popcnt") { 732 HasPOPCNT = true; 733 } else if (Feature == "+rtm") { 734 HasRTM = true; 735 } else if (Feature == "+prfchw") { 736 HasPRFCHW = true; 737 } else if (Feature == "+rdseed") { 738 HasRDSEED = true; 739 } else if (Feature == "+adx") { 740 HasADX = true; 741 } else if (Feature == "+tbm") { 742 HasTBM = true; 743 } else if (Feature == "+lwp") { 744 HasLWP = true; 745 } else if (Feature == "+fma") { 746 HasFMA = true; 747 } else if (Feature == "+f16c") { 748 HasF16C = true; 749 } else if (Feature == "+gfni") { 750 HasGFNI = true; 751 } else if (Feature == "+avx512cd") { 752 HasAVX512CD = true; 753 } else if (Feature == "+avx512vpopcntdq") { 754 HasAVX512VPOPCNTDQ = true; 755 } else if (Feature == "+avx512vnni") { 756 HasAVX512VNNI = true; 757 } else if (Feature == "+avx512bf16") { 758 HasAVX512BF16 = true; 759 } else if (Feature == "+avx512er") { 760 HasAVX512ER = true; 761 } else if (Feature == "+avx512pf") { 762 HasAVX512PF = true; 763 } else if (Feature == "+avx512dq") { 764 HasAVX512DQ = true; 765 } else if (Feature == "+avx512bitalg") { 766 HasAVX512BITALG = true; 767 } else if (Feature == "+avx512bw") { 768 HasAVX512BW = true; 769 } else if (Feature == "+avx512vl") { 770 HasAVX512VL = true; 771 } else if (Feature == "+avx512vbmi") { 772 HasAVX512VBMI = true; 773 } else if (Feature == "+avx512vbmi2") { 774 HasAVX512VBMI2 = true; 775 } else if (Feature == "+avx512ifma") { 776 HasAVX512IFMA = true; 777 } else if (Feature == "+sha") { 778 HasSHA = true; 779 } else if (Feature == "+mpx") { 780 HasMPX = true; 781 } else if (Feature == "+shstk") { 782 HasSHSTK = true; 783 } else if (Feature == "+movbe") { 784 HasMOVBE = true; 785 } else if (Feature == "+sgx") { 786 HasSGX = true; 787 } else if (Feature == "+cx8") { 788 HasCX8 = true; 789 } else if (Feature == "+cx16") { 790 HasCX16 = true; 791 } else if (Feature == "+fxsr") { 792 HasFXSR = true; 793 } else if (Feature == "+xsave") { 794 HasXSAVE = true; 795 } else if (Feature == "+xsaveopt") { 796 HasXSAVEOPT = true; 797 } else if (Feature == "+xsavec") { 798 HasXSAVEC = true; 799 } else if (Feature == "+xsaves") { 800 HasXSAVES = true; 801 } else if (Feature == "+mwaitx") { 802 HasMWAITX = true; 803 } else if (Feature == "+pku") { 804 HasPKU = true; 805 } else if (Feature == "+clflushopt") { 806 HasCLFLUSHOPT = true; 807 } else if (Feature == "+clwb") { 808 HasCLWB = true; 809 } else if (Feature == "+wbnoinvd") { 810 HasWBNOINVD = true; 811 } else if (Feature == "+prefetchwt1") { 812 HasPREFETCHWT1 = true; 813 } else if (Feature == "+clzero") { 814 HasCLZERO = true; 815 } else if (Feature == "+cldemote") { 816 HasCLDEMOTE = true; 817 } else if (Feature == "+rdpid") { 818 HasRDPID = true; 819 } else if (Feature == "+retpoline-external-thunk") { 820 HasRetpolineExternalThunk = true; 821 } else if (Feature == "+sahf") { 822 HasLAHFSAHF = true; 823 } else if (Feature == "+waitpkg") { 824 HasWAITPKG = true; 825 } else if (Feature == "+movdiri") { 826 HasMOVDIRI = true; 827 } else if (Feature == "+movdir64b") { 828 HasMOVDIR64B = true; 829 } else if (Feature == "+pconfig") { 830 HasPCONFIG = true; 831 } else if (Feature == "+ptwrite") { 832 HasPTWRITE = true; 833 } else if (Feature == "+invpcid") { 834 HasINVPCID = true; 835 } 836 837 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 838 .Case("+avx512f", AVX512F) 839 .Case("+avx2", AVX2) 840 .Case("+avx", AVX) 841 .Case("+sse4.2", SSE42) 842 .Case("+sse4.1", SSE41) 843 .Case("+ssse3", SSSE3) 844 .Case("+sse3", SSE3) 845 .Case("+sse2", SSE2) 846 .Case("+sse", SSE1) 847 .Default(NoSSE); 848 SSELevel = std::max(SSELevel, Level); 849 850 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 851 .Case("+3dnowa", AMD3DNowAthlon) 852 .Case("+3dnow", AMD3DNow) 853 .Case("+mmx", MMX) 854 .Default(NoMMX3DNow); 855 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 856 857 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 858 .Case("+xop", XOP) 859 .Case("+fma4", FMA4) 860 .Case("+sse4a", SSE4A) 861 .Default(NoXOP); 862 XOPLevel = std::max(XOPLevel, XLevel); 863 } 864 865 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 866 // matches the selected sse level. 867 if ((FPMath == FP_SSE && SSELevel < SSE1) || 868 (FPMath == FP_387 && SSELevel >= SSE1)) { 869 Diags.Report(diag::err_target_unsupported_fpmath) 870 << (FPMath == FP_SSE ? "sse" : "387"); 871 return false; 872 } 873 874 SimdDefaultAlign = 875 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 876 return true; 877 } 878 879 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 880 /// definitions for this particular subtarget. 881 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 882 MacroBuilder &Builder) const { 883 // Inline assembly supports X86 flag outputs. 884 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 885 886 std::string CodeModel = getTargetOpts().CodeModel; 887 if (CodeModel == "default") 888 CodeModel = "small"; 889 Builder.defineMacro("__code_model_" + CodeModel + "_"); 890 891 // Target identification. 892 if (getTriple().getArch() == llvm::Triple::x86_64) { 893 Builder.defineMacro("__amd64__"); 894 Builder.defineMacro("__amd64"); 895 Builder.defineMacro("__x86_64"); 896 Builder.defineMacro("__x86_64__"); 897 if (getTriple().getArchName() == "x86_64h") { 898 Builder.defineMacro("__x86_64h"); 899 Builder.defineMacro("__x86_64h__"); 900 } 901 } else { 902 DefineStd(Builder, "i386", Opts); 903 } 904 905 // Subtarget options. 906 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 907 // truly should be based on -mtune options. 908 switch (CPU) { 909 case CK_Generic: 910 break; 911 case CK_i386: 912 // The rest are coming from the i386 define above. 913 Builder.defineMacro("__tune_i386__"); 914 break; 915 case CK_i486: 916 case CK_WinChipC6: 917 case CK_WinChip2: 918 case CK_C3: 919 defineCPUMacros(Builder, "i486"); 920 break; 921 case CK_PentiumMMX: 922 Builder.defineMacro("__pentium_mmx__"); 923 Builder.defineMacro("__tune_pentium_mmx__"); 924 LLVM_FALLTHROUGH; 925 case CK_i586: 926 case CK_Pentium: 927 defineCPUMacros(Builder, "i586"); 928 defineCPUMacros(Builder, "pentium"); 929 break; 930 case CK_Pentium3: 931 case CK_PentiumM: 932 Builder.defineMacro("__tune_pentium3__"); 933 LLVM_FALLTHROUGH; 934 case CK_Pentium2: 935 case CK_C3_2: 936 Builder.defineMacro("__tune_pentium2__"); 937 LLVM_FALLTHROUGH; 938 case CK_PentiumPro: 939 case CK_i686: 940 defineCPUMacros(Builder, "i686"); 941 defineCPUMacros(Builder, "pentiumpro"); 942 break; 943 case CK_Pentium4: 944 defineCPUMacros(Builder, "pentium4"); 945 break; 946 case CK_Yonah: 947 case CK_Prescott: 948 case CK_Nocona: 949 defineCPUMacros(Builder, "nocona"); 950 break; 951 case CK_Core2: 952 case CK_Penryn: 953 defineCPUMacros(Builder, "core2"); 954 break; 955 case CK_Bonnell: 956 defineCPUMacros(Builder, "atom"); 957 break; 958 case CK_Silvermont: 959 defineCPUMacros(Builder, "slm"); 960 break; 961 case CK_Goldmont: 962 defineCPUMacros(Builder, "goldmont"); 963 break; 964 case CK_GoldmontPlus: 965 defineCPUMacros(Builder, "goldmont_plus"); 966 break; 967 case CK_Tremont: 968 defineCPUMacros(Builder, "tremont"); 969 break; 970 case CK_Nehalem: 971 case CK_Westmere: 972 case CK_SandyBridge: 973 case CK_IvyBridge: 974 case CK_Haswell: 975 case CK_Broadwell: 976 case CK_SkylakeClient: 977 case CK_SkylakeServer: 978 case CK_Cascadelake: 979 case CK_Cannonlake: 980 case CK_IcelakeClient: 981 case CK_IcelakeServer: 982 // FIXME: Historically, we defined this legacy name, it would be nice to 983 // remove it at some point. We've never exposed fine-grained names for 984 // recent primary x86 CPUs, and we should keep it that way. 985 defineCPUMacros(Builder, "corei7"); 986 break; 987 case CK_KNL: 988 defineCPUMacros(Builder, "knl"); 989 break; 990 case CK_KNM: 991 break; 992 case CK_Lakemont: 993 defineCPUMacros(Builder, "i586", /*Tuning*/false); 994 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 995 Builder.defineMacro("__tune_lakemont__"); 996 break; 997 case CK_K6_2: 998 Builder.defineMacro("__k6_2__"); 999 Builder.defineMacro("__tune_k6_2__"); 1000 LLVM_FALLTHROUGH; 1001 case CK_K6_3: 1002 if (CPU != CK_K6_2) { // In case of fallthrough 1003 // FIXME: GCC may be enabling these in cases where some other k6 1004 // architecture is specified but -m3dnow is explicitly provided. The 1005 // exact semantics need to be determined and emulated here. 1006 Builder.defineMacro("__k6_3__"); 1007 Builder.defineMacro("__tune_k6_3__"); 1008 } 1009 LLVM_FALLTHROUGH; 1010 case CK_K6: 1011 defineCPUMacros(Builder, "k6"); 1012 break; 1013 case CK_Athlon: 1014 case CK_AthlonXP: 1015 defineCPUMacros(Builder, "athlon"); 1016 if (SSELevel != NoSSE) { 1017 Builder.defineMacro("__athlon_sse__"); 1018 Builder.defineMacro("__tune_athlon_sse__"); 1019 } 1020 break; 1021 case CK_K8: 1022 case CK_K8SSE3: 1023 case CK_x86_64: 1024 defineCPUMacros(Builder, "k8"); 1025 break; 1026 case CK_AMDFAM10: 1027 defineCPUMacros(Builder, "amdfam10"); 1028 break; 1029 case CK_BTVER1: 1030 defineCPUMacros(Builder, "btver1"); 1031 break; 1032 case CK_BTVER2: 1033 defineCPUMacros(Builder, "btver2"); 1034 break; 1035 case CK_BDVER1: 1036 defineCPUMacros(Builder, "bdver1"); 1037 break; 1038 case CK_BDVER2: 1039 defineCPUMacros(Builder, "bdver2"); 1040 break; 1041 case CK_BDVER3: 1042 defineCPUMacros(Builder, "bdver3"); 1043 break; 1044 case CK_BDVER4: 1045 defineCPUMacros(Builder, "bdver4"); 1046 break; 1047 case CK_ZNVER1: 1048 defineCPUMacros(Builder, "znver1"); 1049 break; 1050 case CK_ZNVER2: 1051 defineCPUMacros(Builder, "znver2"); 1052 break; 1053 case CK_Geode: 1054 defineCPUMacros(Builder, "geode"); 1055 break; 1056 } 1057 1058 // Target properties. 1059 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1060 1061 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1062 // functions in glibc header files that use FP Stack inline asm which the 1063 // backend can't deal with (PR879). 1064 Builder.defineMacro("__NO_MATH_INLINES"); 1065 1066 if (HasAES) 1067 Builder.defineMacro("__AES__"); 1068 1069 if (HasVAES) 1070 Builder.defineMacro("__VAES__"); 1071 1072 if (HasPCLMUL) 1073 Builder.defineMacro("__PCLMUL__"); 1074 1075 if (HasVPCLMULQDQ) 1076 Builder.defineMacro("__VPCLMULQDQ__"); 1077 1078 if (HasLZCNT) 1079 Builder.defineMacro("__LZCNT__"); 1080 1081 if (HasRDRND) 1082 Builder.defineMacro("__RDRND__"); 1083 1084 if (HasFSGSBASE) 1085 Builder.defineMacro("__FSGSBASE__"); 1086 1087 if (HasBMI) 1088 Builder.defineMacro("__BMI__"); 1089 1090 if (HasBMI2) 1091 Builder.defineMacro("__BMI2__"); 1092 1093 if (HasPOPCNT) 1094 Builder.defineMacro("__POPCNT__"); 1095 1096 if (HasRTM) 1097 Builder.defineMacro("__RTM__"); 1098 1099 if (HasPRFCHW) 1100 Builder.defineMacro("__PRFCHW__"); 1101 1102 if (HasRDSEED) 1103 Builder.defineMacro("__RDSEED__"); 1104 1105 if (HasADX) 1106 Builder.defineMacro("__ADX__"); 1107 1108 if (HasTBM) 1109 Builder.defineMacro("__TBM__"); 1110 1111 if (HasLWP) 1112 Builder.defineMacro("__LWP__"); 1113 1114 if (HasMWAITX) 1115 Builder.defineMacro("__MWAITX__"); 1116 1117 if (HasMOVBE) 1118 Builder.defineMacro("__MOVBE__"); 1119 1120 switch (XOPLevel) { 1121 case XOP: 1122 Builder.defineMacro("__XOP__"); 1123 LLVM_FALLTHROUGH; 1124 case FMA4: 1125 Builder.defineMacro("__FMA4__"); 1126 LLVM_FALLTHROUGH; 1127 case SSE4A: 1128 Builder.defineMacro("__SSE4A__"); 1129 LLVM_FALLTHROUGH; 1130 case NoXOP: 1131 break; 1132 } 1133 1134 if (HasFMA) 1135 Builder.defineMacro("__FMA__"); 1136 1137 if (HasF16C) 1138 Builder.defineMacro("__F16C__"); 1139 1140 if (HasGFNI) 1141 Builder.defineMacro("__GFNI__"); 1142 1143 if (HasAVX512CD) 1144 Builder.defineMacro("__AVX512CD__"); 1145 if (HasAVX512VPOPCNTDQ) 1146 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1147 if (HasAVX512VNNI) 1148 Builder.defineMacro("__AVX512VNNI__"); 1149 if (HasAVX512BF16) 1150 Builder.defineMacro("__AVX512BF16__"); 1151 if (HasAVX512ER) 1152 Builder.defineMacro("__AVX512ER__"); 1153 if (HasAVX512PF) 1154 Builder.defineMacro("__AVX512PF__"); 1155 if (HasAVX512DQ) 1156 Builder.defineMacro("__AVX512DQ__"); 1157 if (HasAVX512BITALG) 1158 Builder.defineMacro("__AVX512BITALG__"); 1159 if (HasAVX512BW) 1160 Builder.defineMacro("__AVX512BW__"); 1161 if (HasAVX512VL) 1162 Builder.defineMacro("__AVX512VL__"); 1163 if (HasAVX512VBMI) 1164 Builder.defineMacro("__AVX512VBMI__"); 1165 if (HasAVX512VBMI2) 1166 Builder.defineMacro("__AVX512VBMI2__"); 1167 if (HasAVX512IFMA) 1168 Builder.defineMacro("__AVX512IFMA__"); 1169 1170 if (HasSHA) 1171 Builder.defineMacro("__SHA__"); 1172 1173 if (HasFXSR) 1174 Builder.defineMacro("__FXSR__"); 1175 if (HasXSAVE) 1176 Builder.defineMacro("__XSAVE__"); 1177 if (HasXSAVEOPT) 1178 Builder.defineMacro("__XSAVEOPT__"); 1179 if (HasXSAVEC) 1180 Builder.defineMacro("__XSAVEC__"); 1181 if (HasXSAVES) 1182 Builder.defineMacro("__XSAVES__"); 1183 if (HasPKU) 1184 Builder.defineMacro("__PKU__"); 1185 if (HasCLFLUSHOPT) 1186 Builder.defineMacro("__CLFLUSHOPT__"); 1187 if (HasCLWB) 1188 Builder.defineMacro("__CLWB__"); 1189 if (HasWBNOINVD) 1190 Builder.defineMacro("__WBNOINVD__"); 1191 if (HasMPX) 1192 Builder.defineMacro("__MPX__"); 1193 if (HasSHSTK) 1194 Builder.defineMacro("__SHSTK__"); 1195 if (HasSGX) 1196 Builder.defineMacro("__SGX__"); 1197 if (HasPREFETCHWT1) 1198 Builder.defineMacro("__PREFETCHWT1__"); 1199 if (HasCLZERO) 1200 Builder.defineMacro("__CLZERO__"); 1201 if (HasRDPID) 1202 Builder.defineMacro("__RDPID__"); 1203 if (HasCLDEMOTE) 1204 Builder.defineMacro("__CLDEMOTE__"); 1205 if (HasWAITPKG) 1206 Builder.defineMacro("__WAITPKG__"); 1207 if (HasMOVDIRI) 1208 Builder.defineMacro("__MOVDIRI__"); 1209 if (HasMOVDIR64B) 1210 Builder.defineMacro("__MOVDIR64B__"); 1211 if (HasPCONFIG) 1212 Builder.defineMacro("__PCONFIG__"); 1213 if (HasPTWRITE) 1214 Builder.defineMacro("__PTWRITE__"); 1215 if (HasINVPCID) 1216 Builder.defineMacro("__INVPCID__"); 1217 1218 // Each case falls through to the previous one here. 1219 switch (SSELevel) { 1220 case AVX512F: 1221 Builder.defineMacro("__AVX512F__"); 1222 LLVM_FALLTHROUGH; 1223 case AVX2: 1224 Builder.defineMacro("__AVX2__"); 1225 LLVM_FALLTHROUGH; 1226 case AVX: 1227 Builder.defineMacro("__AVX__"); 1228 LLVM_FALLTHROUGH; 1229 case SSE42: 1230 Builder.defineMacro("__SSE4_2__"); 1231 LLVM_FALLTHROUGH; 1232 case SSE41: 1233 Builder.defineMacro("__SSE4_1__"); 1234 LLVM_FALLTHROUGH; 1235 case SSSE3: 1236 Builder.defineMacro("__SSSE3__"); 1237 LLVM_FALLTHROUGH; 1238 case SSE3: 1239 Builder.defineMacro("__SSE3__"); 1240 LLVM_FALLTHROUGH; 1241 case SSE2: 1242 Builder.defineMacro("__SSE2__"); 1243 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1244 LLVM_FALLTHROUGH; 1245 case SSE1: 1246 Builder.defineMacro("__SSE__"); 1247 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1248 LLVM_FALLTHROUGH; 1249 case NoSSE: 1250 break; 1251 } 1252 1253 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1254 switch (SSELevel) { 1255 case AVX512F: 1256 case AVX2: 1257 case AVX: 1258 case SSE42: 1259 case SSE41: 1260 case SSSE3: 1261 case SSE3: 1262 case SSE2: 1263 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1264 break; 1265 case SSE1: 1266 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1267 break; 1268 default: 1269 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1270 break; 1271 } 1272 } 1273 1274 // Each case falls through to the previous one here. 1275 switch (MMX3DNowLevel) { 1276 case AMD3DNowAthlon: 1277 Builder.defineMacro("__3dNOW_A__"); 1278 LLVM_FALLTHROUGH; 1279 case AMD3DNow: 1280 Builder.defineMacro("__3dNOW__"); 1281 LLVM_FALLTHROUGH; 1282 case MMX: 1283 Builder.defineMacro("__MMX__"); 1284 LLVM_FALLTHROUGH; 1285 case NoMMX3DNow: 1286 break; 1287 } 1288 1289 if (CPU >= CK_i486 || CPU == CK_Generic) { 1290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1292 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1293 } 1294 if (HasCX8) 1295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1296 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1298 1299 if (HasFloat128) 1300 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1301 } 1302 1303 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1304 return llvm::StringSwitch<bool>(Name) 1305 .Case("3dnow", true) 1306 .Case("3dnowa", true) 1307 .Case("adx", true) 1308 .Case("aes", true) 1309 .Case("avx", true) 1310 .Case("avx2", true) 1311 .Case("avx512f", true) 1312 .Case("avx512cd", true) 1313 .Case("avx512vpopcntdq", true) 1314 .Case("avx512vnni", true) 1315 .Case("avx512bf16", true) 1316 .Case("avx512er", true) 1317 .Case("avx512pf", true) 1318 .Case("avx512dq", true) 1319 .Case("avx512bitalg", true) 1320 .Case("avx512bw", true) 1321 .Case("avx512vl", true) 1322 .Case("avx512vbmi", true) 1323 .Case("avx512vbmi2", true) 1324 .Case("avx512ifma", true) 1325 .Case("bmi", true) 1326 .Case("bmi2", true) 1327 .Case("cldemote", true) 1328 .Case("clflushopt", true) 1329 .Case("clwb", true) 1330 .Case("clzero", true) 1331 .Case("cx16", true) 1332 .Case("f16c", true) 1333 .Case("fma", true) 1334 .Case("fma4", true) 1335 .Case("fsgsbase", true) 1336 .Case("fxsr", true) 1337 .Case("gfni", true) 1338 .Case("invpcid", true) 1339 .Case("lwp", true) 1340 .Case("lzcnt", true) 1341 .Case("mmx", true) 1342 .Case("movbe", true) 1343 .Case("movdiri", true) 1344 .Case("movdir64b", true) 1345 .Case("mpx", true) 1346 .Case("mwaitx", true) 1347 .Case("pclmul", true) 1348 .Case("pconfig", true) 1349 .Case("pku", true) 1350 .Case("popcnt", true) 1351 .Case("prefetchwt1", true) 1352 .Case("prfchw", true) 1353 .Case("ptwrite", true) 1354 .Case("rdpid", true) 1355 .Case("rdrnd", true) 1356 .Case("rdseed", true) 1357 .Case("rtm", true) 1358 .Case("sahf", true) 1359 .Case("sgx", true) 1360 .Case("sha", true) 1361 .Case("shstk", true) 1362 .Case("sse", true) 1363 .Case("sse2", true) 1364 .Case("sse3", true) 1365 .Case("ssse3", true) 1366 .Case("sse4", true) 1367 .Case("sse4.1", true) 1368 .Case("sse4.2", true) 1369 .Case("sse4a", true) 1370 .Case("tbm", true) 1371 .Case("vaes", true) 1372 .Case("vpclmulqdq", true) 1373 .Case("wbnoinvd", true) 1374 .Case("waitpkg", true) 1375 .Case("x87", true) 1376 .Case("xop", true) 1377 .Case("xsave", true) 1378 .Case("xsavec", true) 1379 .Case("xsaves", true) 1380 .Case("xsaveopt", true) 1381 .Default(false); 1382 } 1383 1384 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1385 return llvm::StringSwitch<bool>(Feature) 1386 .Case("adx", HasADX) 1387 .Case("aes", HasAES) 1388 .Case("avx", SSELevel >= AVX) 1389 .Case("avx2", SSELevel >= AVX2) 1390 .Case("avx512f", SSELevel >= AVX512F) 1391 .Case("avx512cd", HasAVX512CD) 1392 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1393 .Case("avx512vnni", HasAVX512VNNI) 1394 .Case("avx512bf16", HasAVX512BF16) 1395 .Case("avx512er", HasAVX512ER) 1396 .Case("avx512pf", HasAVX512PF) 1397 .Case("avx512dq", HasAVX512DQ) 1398 .Case("avx512bitalg", HasAVX512BITALG) 1399 .Case("avx512bw", HasAVX512BW) 1400 .Case("avx512vl", HasAVX512VL) 1401 .Case("avx512vbmi", HasAVX512VBMI) 1402 .Case("avx512vbmi2", HasAVX512VBMI2) 1403 .Case("avx512ifma", HasAVX512IFMA) 1404 .Case("bmi", HasBMI) 1405 .Case("bmi2", HasBMI2) 1406 .Case("cldemote", HasCLDEMOTE) 1407 .Case("clflushopt", HasCLFLUSHOPT) 1408 .Case("clwb", HasCLWB) 1409 .Case("clzero", HasCLZERO) 1410 .Case("cx8", HasCX8) 1411 .Case("cx16", HasCX16) 1412 .Case("f16c", HasF16C) 1413 .Case("fma", HasFMA) 1414 .Case("fma4", XOPLevel >= FMA4) 1415 .Case("fsgsbase", HasFSGSBASE) 1416 .Case("fxsr", HasFXSR) 1417 .Case("gfni", HasGFNI) 1418 .Case("invpcid", HasINVPCID) 1419 .Case("lwp", HasLWP) 1420 .Case("lzcnt", HasLZCNT) 1421 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1422 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1423 .Case("mmx", MMX3DNowLevel >= MMX) 1424 .Case("movbe", HasMOVBE) 1425 .Case("movdiri", HasMOVDIRI) 1426 .Case("movdir64b", HasMOVDIR64B) 1427 .Case("mpx", HasMPX) 1428 .Case("mwaitx", HasMWAITX) 1429 .Case("pclmul", HasPCLMUL) 1430 .Case("pconfig", HasPCONFIG) 1431 .Case("pku", HasPKU) 1432 .Case("popcnt", HasPOPCNT) 1433 .Case("prefetchwt1", HasPREFETCHWT1) 1434 .Case("prfchw", HasPRFCHW) 1435 .Case("ptwrite", HasPTWRITE) 1436 .Case("rdpid", HasRDPID) 1437 .Case("rdrnd", HasRDRND) 1438 .Case("rdseed", HasRDSEED) 1439 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1440 .Case("rtm", HasRTM) 1441 .Case("sahf", HasLAHFSAHF) 1442 .Case("sgx", HasSGX) 1443 .Case("sha", HasSHA) 1444 .Case("shstk", HasSHSTK) 1445 .Case("sse", SSELevel >= SSE1) 1446 .Case("sse2", SSELevel >= SSE2) 1447 .Case("sse3", SSELevel >= SSE3) 1448 .Case("ssse3", SSELevel >= SSSE3) 1449 .Case("sse4.1", SSELevel >= SSE41) 1450 .Case("sse4.2", SSELevel >= SSE42) 1451 .Case("sse4a", XOPLevel >= SSE4A) 1452 .Case("tbm", HasTBM) 1453 .Case("vaes", HasVAES) 1454 .Case("vpclmulqdq", HasVPCLMULQDQ) 1455 .Case("wbnoinvd", HasWBNOINVD) 1456 .Case("waitpkg", HasWAITPKG) 1457 .Case("x86", true) 1458 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1459 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1460 .Case("xop", XOPLevel >= XOP) 1461 .Case("xsave", HasXSAVE) 1462 .Case("xsavec", HasXSAVEC) 1463 .Case("xsaves", HasXSAVES) 1464 .Case("xsaveopt", HasXSAVEOPT) 1465 .Default(false); 1466 } 1467 1468 // We can't use a generic validation scheme for the features accepted here 1469 // versus subtarget features accepted in the target attribute because the 1470 // bitfield structure that's initialized in the runtime only supports the 1471 // below currently rather than the full range of subtarget features. (See 1472 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1473 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1474 return llvm::StringSwitch<bool>(FeatureStr) 1475 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1476 #include "llvm/Support/X86TargetParser.def" 1477 .Default(false); 1478 } 1479 1480 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1481 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1482 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1483 #include "llvm/Support/X86TargetParser.def" 1484 ; 1485 // Note, this function should only be used after ensuring the value is 1486 // correct, so it asserts if the value is out of range. 1487 } 1488 1489 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1490 enum class FeatPriority { 1491 #define FEATURE(FEAT) FEAT, 1492 #include "clang/Basic/X86Target.def" 1493 }; 1494 switch (Feat) { 1495 #define FEATURE(FEAT) \ 1496 case llvm::X86::FEAT: \ 1497 return static_cast<unsigned>(FeatPriority::FEAT); 1498 #include "clang/Basic/X86Target.def" 1499 default: 1500 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1501 } 1502 } 1503 1504 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1505 // Valid CPUs have a 'key feature' that compares just better than its key 1506 // feature. 1507 CPUKind Kind = getCPUKind(Name); 1508 if (Kind != CK_Generic) { 1509 switch (Kind) { 1510 default: 1511 llvm_unreachable( 1512 "CPU Type without a key feature used in 'target' attribute"); 1513 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1514 case CK_##ENUM: \ 1515 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1516 #include "clang/Basic/X86Target.def" 1517 } 1518 } 1519 1520 // Now we know we have a feature, so get its priority and shift it a few so 1521 // that we have sufficient room for the CPUs (above). 1522 return getFeaturePriority(getFeature(Name)) << 1; 1523 } 1524 1525 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1526 return llvm::StringSwitch<bool>(Name) 1527 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1528 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1529 #include "clang/Basic/X86Target.def" 1530 .Default(false); 1531 } 1532 1533 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1534 return llvm::StringSwitch<StringRef>(Name) 1535 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1536 #include "clang/Basic/X86Target.def" 1537 .Default(Name); 1538 } 1539 1540 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1541 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1542 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1543 #include "clang/Basic/X86Target.def" 1544 .Default(0); 1545 } 1546 1547 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1548 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1549 StringRef WholeList = 1550 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1551 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1552 #include "clang/Basic/X86Target.def" 1553 .Default(""); 1554 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1555 } 1556 1557 // We can't use a generic validation scheme for the cpus accepted here 1558 // versus subtarget cpus accepted in the target attribute because the 1559 // variables intitialized by the runtime only support the below currently 1560 // rather than the full range of cpus. 1561 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1562 return llvm::StringSwitch<bool>(FeatureStr) 1563 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1564 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1565 .Cases(STR, ALIAS, true) 1566 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1567 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1568 #include "llvm/Support/X86TargetParser.def" 1569 .Default(false); 1570 } 1571 1572 static unsigned matchAsmCCConstraint(const char *&Name) { 1573 auto RV = llvm::StringSwitch<unsigned>(Name) 1574 .Case("@cca", 4) 1575 .Case("@ccae", 5) 1576 .Case("@ccb", 4) 1577 .Case("@ccbe", 5) 1578 .Case("@ccc", 4) 1579 .Case("@cce", 4) 1580 .Case("@ccz", 4) 1581 .Case("@ccg", 4) 1582 .Case("@ccge", 5) 1583 .Case("@ccl", 4) 1584 .Case("@ccle", 5) 1585 .Case("@ccna", 5) 1586 .Case("@ccnae", 6) 1587 .Case("@ccnb", 5) 1588 .Case("@ccnbe", 6) 1589 .Case("@ccnc", 5) 1590 .Case("@ccne", 5) 1591 .Case("@ccnz", 5) 1592 .Case("@ccng", 5) 1593 .Case("@ccnge", 6) 1594 .Case("@ccnl", 5) 1595 .Case("@ccnle", 6) 1596 .Case("@ccno", 5) 1597 .Case("@ccnp", 5) 1598 .Case("@ccns", 5) 1599 .Case("@cco", 4) 1600 .Case("@ccp", 4) 1601 .Case("@ccs", 4) 1602 .Default(0); 1603 return RV; 1604 } 1605 1606 bool X86TargetInfo::validateAsmConstraint( 1607 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1608 switch (*Name) { 1609 default: 1610 return false; 1611 // Constant constraints. 1612 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1613 // instructions. 1614 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1615 // x86_64 instructions. 1616 case 's': 1617 Info.setRequiresImmediate(); 1618 return true; 1619 case 'I': 1620 Info.setRequiresImmediate(0, 31); 1621 return true; 1622 case 'J': 1623 Info.setRequiresImmediate(0, 63); 1624 return true; 1625 case 'K': 1626 Info.setRequiresImmediate(-128, 127); 1627 return true; 1628 case 'L': 1629 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1630 return true; 1631 case 'M': 1632 Info.setRequiresImmediate(0, 3); 1633 return true; 1634 case 'N': 1635 Info.setRequiresImmediate(0, 255); 1636 return true; 1637 case 'O': 1638 Info.setRequiresImmediate(0, 127); 1639 return true; 1640 // Register constraints. 1641 case 'Y': // 'Y' is the first character for several 2-character constraints. 1642 // Shift the pointer to the second character of the constraint. 1643 Name++; 1644 switch (*Name) { 1645 default: 1646 return false; 1647 case 'z': 1648 case '0': // First SSE register. 1649 case '2': 1650 case 't': // Any SSE register, when SSE2 is enabled. 1651 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1652 case 'm': // Any MMX register, when inter-unit moves enabled. 1653 case 'k': // AVX512 arch mask registers: k1-k7. 1654 Info.setAllowsRegister(); 1655 return true; 1656 } 1657 case 'f': // Any x87 floating point stack register. 1658 // Constraint 'f' cannot be used for output operands. 1659 if (Info.ConstraintStr[0] == '=') 1660 return false; 1661 Info.setAllowsRegister(); 1662 return true; 1663 case 'a': // eax. 1664 case 'b': // ebx. 1665 case 'c': // ecx. 1666 case 'd': // edx. 1667 case 'S': // esi. 1668 case 'D': // edi. 1669 case 'A': // edx:eax. 1670 case 't': // Top of floating point stack. 1671 case 'u': // Second from top of floating point stack. 1672 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1673 case 'y': // Any MMX register. 1674 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1675 case 'x': // Any SSE register. 1676 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1677 // for intermideate k reg operations). 1678 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1679 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1680 case 'l': // "Index" registers: any general register that can be used as an 1681 // index in a base+index memory access. 1682 Info.setAllowsRegister(); 1683 return true; 1684 // Floating point constant constraints. 1685 case 'C': // SSE floating point constant. 1686 case 'G': // x87 floating point constant. 1687 return true; 1688 case '@': 1689 // CC condition changes. 1690 if (auto Len = matchAsmCCConstraint(Name)) { 1691 Name += Len - 1; 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 return false; 1696 } 1697 } 1698 1699 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1700 unsigned Size) const { 1701 // Strip off constraint modifiers. 1702 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1703 Constraint = Constraint.substr(1); 1704 1705 return validateOperandSize(Constraint, Size); 1706 } 1707 1708 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1709 unsigned Size) const { 1710 return validateOperandSize(Constraint, Size); 1711 } 1712 1713 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1714 unsigned Size) const { 1715 switch (Constraint[0]) { 1716 default: 1717 break; 1718 case 'k': 1719 // Registers k0-k7 (AVX512) size limit is 64 bit. 1720 case 'y': 1721 return Size <= 64; 1722 case 'f': 1723 case 't': 1724 case 'u': 1725 return Size <= 128; 1726 case 'Y': 1727 // 'Y' is the first character for several 2-character constraints. 1728 switch (Constraint[1]) { 1729 default: 1730 return false; 1731 case 'm': 1732 // 'Ym' is synonymous with 'y'. 1733 case 'k': 1734 return Size <= 64; 1735 case 'z': 1736 case '0': 1737 // XMM0 1738 if (SSELevel >= SSE1) 1739 return Size <= 128U; 1740 return false; 1741 case 'i': 1742 case 't': 1743 case '2': 1744 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1745 if (SSELevel < SSE2) 1746 return false; 1747 break; 1748 } 1749 LLVM_FALLTHROUGH; 1750 case 'v': 1751 case 'x': 1752 if (SSELevel >= AVX512F) 1753 // 512-bit zmm registers can be used if target supports AVX512F. 1754 return Size <= 512U; 1755 else if (SSELevel >= AVX) 1756 // 256-bit ymm registers can be used if target supports AVX. 1757 return Size <= 256U; 1758 return Size <= 128U; 1759 1760 } 1761 1762 return true; 1763 } 1764 1765 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1766 switch (*Constraint) { 1767 case '@': 1768 if (auto Len = matchAsmCCConstraint(Constraint)) { 1769 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1770 Constraint += Len - 1; 1771 return Converted; 1772 } 1773 return std::string(1, *Constraint); 1774 case 'a': 1775 return std::string("{ax}"); 1776 case 'b': 1777 return std::string("{bx}"); 1778 case 'c': 1779 return std::string("{cx}"); 1780 case 'd': 1781 return std::string("{dx}"); 1782 case 'S': 1783 return std::string("{si}"); 1784 case 'D': 1785 return std::string("{di}"); 1786 case 'p': // address 1787 return std::string("im"); 1788 case 't': // top of floating point stack. 1789 return std::string("{st}"); 1790 case 'u': // second from top of floating point stack. 1791 return std::string("{st(1)}"); // second from top of floating point stack. 1792 case 'Y': 1793 switch (Constraint[1]) { 1794 default: 1795 // Break from inner switch and fall through (copy single char), 1796 // continue parsing after copying the current constraint into 1797 // the return string. 1798 break; 1799 case 'k': 1800 case 'm': 1801 case 'i': 1802 case 't': 1803 case 'z': 1804 case '0': 1805 case '2': 1806 // "^" hints llvm that this is a 2 letter constraint. 1807 // "Constraint++" is used to promote the string iterator 1808 // to the next constraint. 1809 return std::string("^") + std::string(Constraint++, 2); 1810 } 1811 LLVM_FALLTHROUGH; 1812 default: 1813 return std::string(1, *Constraint); 1814 } 1815 } 1816 1817 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1818 // Perform any per-CPU checks necessary to determine if this CPU is 1819 // acceptable. 1820 switch (Kind) { 1821 case CK_Generic: 1822 // No processor selected! 1823 return false; 1824 #define PROC(ENUM, STRING, IS64BIT) \ 1825 case CK_##ENUM: \ 1826 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1827 #include "clang/Basic/X86Target.def" 1828 } 1829 llvm_unreachable("Unhandled CPU kind"); 1830 } 1831 1832 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1833 #define PROC(ENUM, STRING, IS64BIT) \ 1834 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1835 Values.emplace_back(STRING); 1836 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1837 #define PROC_ALIAS(ENUM, ALIAS) \ 1838 if (checkCPUKind(CK_##ENUM)) \ 1839 Values.emplace_back(ALIAS); 1840 #include "clang/Basic/X86Target.def" 1841 } 1842 1843 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1844 return llvm::StringSwitch<CPUKind>(CPU) 1845 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1846 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1847 #include "clang/Basic/X86Target.def" 1848 .Default(CK_Generic); 1849 } 1850 1851 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1852 return llvm::makeArrayRef(GCCRegNames); 1853 } 1854 1855 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1856 return llvm::makeArrayRef(AddlRegNames); 1857 } 1858 1859 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1860 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1861 Builtin::FirstTSBuiltin + 1); 1862 } 1863 1864 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1865 return llvm::makeArrayRef(BuiltinInfoX86, 1866 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1867 } 1868