1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_Cooperlake: 135 // CPX inherits all CLX features plus AVX512BF16 136 setFeatureEnabledImpl(Features, "avx512bf16", true); 137 LLVM_FALLTHROUGH; 138 case CK_Cascadelake: 139 // CLX inherits all SKX features plus AVX512VNNI 140 setFeatureEnabledImpl(Features, "avx512vnni", true); 141 LLVM_FALLTHROUGH; 142 case CK_SkylakeServer: 143 setFeatureEnabledImpl(Features, "avx512f", true); 144 setFeatureEnabledImpl(Features, "avx512cd", true); 145 setFeatureEnabledImpl(Features, "avx512dq", true); 146 setFeatureEnabledImpl(Features, "avx512bw", true); 147 setFeatureEnabledImpl(Features, "avx512vl", true); 148 setFeatureEnabledImpl(Features, "clwb", true); 149 setFeatureEnabledImpl(Features, "pku", true); 150 // SkylakeServer cores inherits all SKL features, except SGX 151 goto SkylakeCommon; 152 153 case CK_Tigerlake: 154 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 155 setFeatureEnabledImpl(Features, "movdiri", true); 156 setFeatureEnabledImpl(Features, "movdir64b", true); 157 setFeatureEnabledImpl(Features, "shstk", true); 158 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 159 goto IcelakeCommon; 160 161 case CK_IcelakeServer: 162 setFeatureEnabledImpl(Features, "pconfig", true); 163 setFeatureEnabledImpl(Features, "wbnoinvd", true); 164 LLVM_FALLTHROUGH; 165 case CK_IcelakeClient: 166 IcelakeCommon: 167 setFeatureEnabledImpl(Features, "vaes", true); 168 setFeatureEnabledImpl(Features, "gfni", true); 169 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 170 setFeatureEnabledImpl(Features, "avx512bitalg", true); 171 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 172 setFeatureEnabledImpl(Features, "avx512vnni", true); 173 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 174 setFeatureEnabledImpl(Features, "rdpid", true); 175 setFeatureEnabledImpl(Features, "clwb", true); 176 LLVM_FALLTHROUGH; 177 case CK_Cannonlake: 178 setFeatureEnabledImpl(Features, "avx512f", true); 179 setFeatureEnabledImpl(Features, "avx512cd", true); 180 setFeatureEnabledImpl(Features, "avx512dq", true); 181 setFeatureEnabledImpl(Features, "avx512bw", true); 182 setFeatureEnabledImpl(Features, "avx512vl", true); 183 setFeatureEnabledImpl(Features, "avx512ifma", true); 184 setFeatureEnabledImpl(Features, "avx512vbmi", true); 185 setFeatureEnabledImpl(Features, "pku", true); 186 setFeatureEnabledImpl(Features, "sha", true); 187 LLVM_FALLTHROUGH; 188 case CK_SkylakeClient: 189 setFeatureEnabledImpl(Features, "sgx", true); 190 // SkylakeServer cores inherits all SKL features, except SGX 191 SkylakeCommon: 192 setFeatureEnabledImpl(Features, "xsavec", true); 193 setFeatureEnabledImpl(Features, "xsaves", true); 194 setFeatureEnabledImpl(Features, "clflushopt", true); 195 setFeatureEnabledImpl(Features, "aes", true); 196 LLVM_FALLTHROUGH; 197 case CK_Broadwell: 198 setFeatureEnabledImpl(Features, "rdseed", true); 199 setFeatureEnabledImpl(Features, "adx", true); 200 setFeatureEnabledImpl(Features, "prfchw", true); 201 LLVM_FALLTHROUGH; 202 case CK_Haswell: 203 setFeatureEnabledImpl(Features, "avx2", true); 204 setFeatureEnabledImpl(Features, "lzcnt", true); 205 setFeatureEnabledImpl(Features, "bmi", true); 206 setFeatureEnabledImpl(Features, "bmi2", true); 207 setFeatureEnabledImpl(Features, "fma", true); 208 setFeatureEnabledImpl(Features, "invpcid", true); 209 setFeatureEnabledImpl(Features, "movbe", true); 210 LLVM_FALLTHROUGH; 211 case CK_IvyBridge: 212 setFeatureEnabledImpl(Features, "rdrnd", true); 213 setFeatureEnabledImpl(Features, "f16c", true); 214 setFeatureEnabledImpl(Features, "fsgsbase", true); 215 LLVM_FALLTHROUGH; 216 case CK_SandyBridge: 217 setFeatureEnabledImpl(Features, "avx", true); 218 setFeatureEnabledImpl(Features, "xsave", true); 219 setFeatureEnabledImpl(Features, "xsaveopt", true); 220 LLVM_FALLTHROUGH; 221 case CK_Westmere: 222 setFeatureEnabledImpl(Features, "pclmul", true); 223 LLVM_FALLTHROUGH; 224 case CK_Nehalem: 225 setFeatureEnabledImpl(Features, "sse4.2", true); 226 LLVM_FALLTHROUGH; 227 case CK_Penryn: 228 setFeatureEnabledImpl(Features, "sse4.1", true); 229 LLVM_FALLTHROUGH; 230 case CK_Core2: 231 setFeatureEnabledImpl(Features, "ssse3", true); 232 setFeatureEnabledImpl(Features, "sahf", true); 233 LLVM_FALLTHROUGH; 234 case CK_Nocona: 235 setFeatureEnabledImpl(Features, "cx16", true); 236 LLVM_FALLTHROUGH; 237 case CK_Yonah: 238 case CK_Prescott: 239 setFeatureEnabledImpl(Features, "sse3", true); 240 LLVM_FALLTHROUGH; 241 case CK_PentiumM: 242 case CK_Pentium4: 243 case CK_x86_64: 244 setFeatureEnabledImpl(Features, "sse2", true); 245 LLVM_FALLTHROUGH; 246 case CK_Pentium3: 247 case CK_C3_2: 248 setFeatureEnabledImpl(Features, "sse", true); 249 LLVM_FALLTHROUGH; 250 case CK_Pentium2: 251 setFeatureEnabledImpl(Features, "fxsr", true); 252 LLVM_FALLTHROUGH; 253 case CK_PentiumMMX: 254 case CK_K6: 255 case CK_WinChipC6: 256 setFeatureEnabledImpl(Features, "mmx", true); 257 break; 258 259 case CK_Tremont: 260 setFeatureEnabledImpl(Features, "cldemote", true); 261 setFeatureEnabledImpl(Features, "movdiri", true); 262 setFeatureEnabledImpl(Features, "movdir64b", true); 263 setFeatureEnabledImpl(Features, "gfni", true); 264 setFeatureEnabledImpl(Features, "waitpkg", true); 265 LLVM_FALLTHROUGH; 266 case CK_GoldmontPlus: 267 setFeatureEnabledImpl(Features, "ptwrite", true); 268 setFeatureEnabledImpl(Features, "rdpid", true); 269 setFeatureEnabledImpl(Features, "sgx", true); 270 LLVM_FALLTHROUGH; 271 case CK_Goldmont: 272 setFeatureEnabledImpl(Features, "sha", true); 273 setFeatureEnabledImpl(Features, "rdseed", true); 274 setFeatureEnabledImpl(Features, "xsave", true); 275 setFeatureEnabledImpl(Features, "xsaveopt", true); 276 setFeatureEnabledImpl(Features, "xsavec", true); 277 setFeatureEnabledImpl(Features, "xsaves", true); 278 setFeatureEnabledImpl(Features, "clflushopt", true); 279 setFeatureEnabledImpl(Features, "fsgsbase", true); 280 setFeatureEnabledImpl(Features, "aes", true); 281 LLVM_FALLTHROUGH; 282 case CK_Silvermont: 283 setFeatureEnabledImpl(Features, "rdrnd", true); 284 setFeatureEnabledImpl(Features, "pclmul", true); 285 setFeatureEnabledImpl(Features, "sse4.2", true); 286 setFeatureEnabledImpl(Features, "prfchw", true); 287 LLVM_FALLTHROUGH; 288 case CK_Bonnell: 289 setFeatureEnabledImpl(Features, "movbe", true); 290 setFeatureEnabledImpl(Features, "ssse3", true); 291 setFeatureEnabledImpl(Features, "fxsr", true); 292 setFeatureEnabledImpl(Features, "cx16", true); 293 setFeatureEnabledImpl(Features, "sahf", true); 294 setFeatureEnabledImpl(Features, "mmx", true); 295 break; 296 297 case CK_KNM: 298 // TODO: Add avx5124fmaps/avx5124vnniw. 299 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 300 LLVM_FALLTHROUGH; 301 case CK_KNL: 302 setFeatureEnabledImpl(Features, "avx512f", true); 303 setFeatureEnabledImpl(Features, "avx512cd", true); 304 setFeatureEnabledImpl(Features, "avx512er", true); 305 setFeatureEnabledImpl(Features, "avx512pf", true); 306 setFeatureEnabledImpl(Features, "prfchw", true); 307 setFeatureEnabledImpl(Features, "prefetchwt1", true); 308 setFeatureEnabledImpl(Features, "fxsr", true); 309 setFeatureEnabledImpl(Features, "rdseed", true); 310 setFeatureEnabledImpl(Features, "adx", true); 311 setFeatureEnabledImpl(Features, "lzcnt", true); 312 setFeatureEnabledImpl(Features, "bmi", true); 313 setFeatureEnabledImpl(Features, "bmi2", true); 314 setFeatureEnabledImpl(Features, "fma", true); 315 setFeatureEnabledImpl(Features, "rdrnd", true); 316 setFeatureEnabledImpl(Features, "f16c", true); 317 setFeatureEnabledImpl(Features, "fsgsbase", true); 318 setFeatureEnabledImpl(Features, "aes", true); 319 setFeatureEnabledImpl(Features, "pclmul", true); 320 setFeatureEnabledImpl(Features, "cx16", true); 321 setFeatureEnabledImpl(Features, "xsaveopt", true); 322 setFeatureEnabledImpl(Features, "xsave", true); 323 setFeatureEnabledImpl(Features, "movbe", true); 324 setFeatureEnabledImpl(Features, "sahf", true); 325 setFeatureEnabledImpl(Features, "mmx", true); 326 break; 327 328 case CK_K6_2: 329 case CK_K6_3: 330 case CK_WinChip2: 331 case CK_C3: 332 setFeatureEnabledImpl(Features, "3dnow", true); 333 break; 334 335 case CK_AMDFAM10: 336 setFeatureEnabledImpl(Features, "sse4a", true); 337 setFeatureEnabledImpl(Features, "lzcnt", true); 338 setFeatureEnabledImpl(Features, "popcnt", true); 339 setFeatureEnabledImpl(Features, "sahf", true); 340 LLVM_FALLTHROUGH; 341 case CK_K8SSE3: 342 setFeatureEnabledImpl(Features, "sse3", true); 343 LLVM_FALLTHROUGH; 344 case CK_K8: 345 setFeatureEnabledImpl(Features, "sse2", true); 346 LLVM_FALLTHROUGH; 347 case CK_AthlonXP: 348 setFeatureEnabledImpl(Features, "sse", true); 349 setFeatureEnabledImpl(Features, "fxsr", true); 350 LLVM_FALLTHROUGH; 351 case CK_Athlon: 352 case CK_Geode: 353 setFeatureEnabledImpl(Features, "3dnowa", true); 354 break; 355 356 case CK_BTVER2: 357 setFeatureEnabledImpl(Features, "avx", true); 358 setFeatureEnabledImpl(Features, "aes", true); 359 setFeatureEnabledImpl(Features, "pclmul", true); 360 setFeatureEnabledImpl(Features, "bmi", true); 361 setFeatureEnabledImpl(Features, "f16c", true); 362 setFeatureEnabledImpl(Features, "xsaveopt", true); 363 setFeatureEnabledImpl(Features, "movbe", true); 364 LLVM_FALLTHROUGH; 365 case CK_BTVER1: 366 setFeatureEnabledImpl(Features, "ssse3", true); 367 setFeatureEnabledImpl(Features, "sse4a", true); 368 setFeatureEnabledImpl(Features, "lzcnt", true); 369 setFeatureEnabledImpl(Features, "popcnt", true); 370 setFeatureEnabledImpl(Features, "prfchw", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "fxsr", true); 373 setFeatureEnabledImpl(Features, "sahf", true); 374 setFeatureEnabledImpl(Features, "mmx", true); 375 break; 376 377 case CK_ZNVER2: 378 setFeatureEnabledImpl(Features, "clwb", true); 379 setFeatureEnabledImpl(Features, "rdpid", true); 380 setFeatureEnabledImpl(Features, "wbnoinvd", true); 381 LLVM_FALLTHROUGH; 382 case CK_ZNVER1: 383 setFeatureEnabledImpl(Features, "adx", true); 384 setFeatureEnabledImpl(Features, "aes", true); 385 setFeatureEnabledImpl(Features, "avx2", true); 386 setFeatureEnabledImpl(Features, "bmi", true); 387 setFeatureEnabledImpl(Features, "bmi2", true); 388 setFeatureEnabledImpl(Features, "clflushopt", true); 389 setFeatureEnabledImpl(Features, "clzero", true); 390 setFeatureEnabledImpl(Features, "cx16", true); 391 setFeatureEnabledImpl(Features, "f16c", true); 392 setFeatureEnabledImpl(Features, "fma", true); 393 setFeatureEnabledImpl(Features, "fsgsbase", true); 394 setFeatureEnabledImpl(Features, "fxsr", true); 395 setFeatureEnabledImpl(Features, "lzcnt", true); 396 setFeatureEnabledImpl(Features, "mmx", true); 397 setFeatureEnabledImpl(Features, "mwaitx", true); 398 setFeatureEnabledImpl(Features, "movbe", true); 399 setFeatureEnabledImpl(Features, "pclmul", true); 400 setFeatureEnabledImpl(Features, "popcnt", true); 401 setFeatureEnabledImpl(Features, "prfchw", true); 402 setFeatureEnabledImpl(Features, "rdrnd", true); 403 setFeatureEnabledImpl(Features, "rdseed", true); 404 setFeatureEnabledImpl(Features, "sahf", true); 405 setFeatureEnabledImpl(Features, "sha", true); 406 setFeatureEnabledImpl(Features, "sse4a", true); 407 setFeatureEnabledImpl(Features, "xsave", true); 408 setFeatureEnabledImpl(Features, "xsavec", true); 409 setFeatureEnabledImpl(Features, "xsaveopt", true); 410 setFeatureEnabledImpl(Features, "xsaves", true); 411 break; 412 413 case CK_BDVER4: 414 setFeatureEnabledImpl(Features, "avx2", true); 415 setFeatureEnabledImpl(Features, "bmi2", true); 416 setFeatureEnabledImpl(Features, "mwaitx", true); 417 LLVM_FALLTHROUGH; 418 case CK_BDVER3: 419 setFeatureEnabledImpl(Features, "fsgsbase", true); 420 setFeatureEnabledImpl(Features, "xsaveopt", true); 421 LLVM_FALLTHROUGH; 422 case CK_BDVER2: 423 setFeatureEnabledImpl(Features, "bmi", true); 424 setFeatureEnabledImpl(Features, "fma", true); 425 setFeatureEnabledImpl(Features, "f16c", true); 426 setFeatureEnabledImpl(Features, "tbm", true); 427 LLVM_FALLTHROUGH; 428 case CK_BDVER1: 429 // xop implies avx, sse4a and fma4. 430 setFeatureEnabledImpl(Features, "xop", true); 431 setFeatureEnabledImpl(Features, "lwp", true); 432 setFeatureEnabledImpl(Features, "lzcnt", true); 433 setFeatureEnabledImpl(Features, "aes", true); 434 setFeatureEnabledImpl(Features, "pclmul", true); 435 setFeatureEnabledImpl(Features, "prfchw", true); 436 setFeatureEnabledImpl(Features, "cx16", true); 437 setFeatureEnabledImpl(Features, "fxsr", true); 438 setFeatureEnabledImpl(Features, "xsave", true); 439 setFeatureEnabledImpl(Features, "sahf", true); 440 setFeatureEnabledImpl(Features, "mmx", true); 441 break; 442 } 443 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 444 return false; 445 446 // Can't do this earlier because we need to be able to explicitly enable 447 // or disable these features and the things that they depend upon. 448 449 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 450 auto I = Features.find("sse4.2"); 451 if (I != Features.end() && I->getValue() && 452 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 453 Features["popcnt"] = true; 454 455 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 456 I = Features.find("3dnow"); 457 if (I != Features.end() && I->getValue() && 458 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 459 Features["prfchw"] = true; 460 461 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 462 // then enable MMX. 463 I = Features.find("sse"); 464 if (I != Features.end() && I->getValue() && 465 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 466 Features["mmx"] = true; 467 468 return true; 469 } 470 471 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 472 X86SSEEnum Level, bool Enabled) { 473 if (Enabled) { 474 switch (Level) { 475 case AVX512F: 476 Features["avx512f"] = true; 477 Features["fma"] = true; 478 Features["f16c"] = true; 479 LLVM_FALLTHROUGH; 480 case AVX2: 481 Features["avx2"] = true; 482 LLVM_FALLTHROUGH; 483 case AVX: 484 Features["avx"] = true; 485 Features["xsave"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE42: 488 Features["sse4.2"] = true; 489 LLVM_FALLTHROUGH; 490 case SSE41: 491 Features["sse4.1"] = true; 492 LLVM_FALLTHROUGH; 493 case SSSE3: 494 Features["ssse3"] = true; 495 LLVM_FALLTHROUGH; 496 case SSE3: 497 Features["sse3"] = true; 498 LLVM_FALLTHROUGH; 499 case SSE2: 500 Features["sse2"] = true; 501 LLVM_FALLTHROUGH; 502 case SSE1: 503 Features["sse"] = true; 504 LLVM_FALLTHROUGH; 505 case NoSSE: 506 break; 507 } 508 return; 509 } 510 511 switch (Level) { 512 case NoSSE: 513 case SSE1: 514 Features["sse"] = false; 515 LLVM_FALLTHROUGH; 516 case SSE2: 517 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 518 Features["sha"] = Features["gfni"] = false; 519 LLVM_FALLTHROUGH; 520 case SSE3: 521 Features["sse3"] = false; 522 setXOPLevel(Features, NoXOP, false); 523 LLVM_FALLTHROUGH; 524 case SSSE3: 525 Features["ssse3"] = false; 526 LLVM_FALLTHROUGH; 527 case SSE41: 528 Features["sse4.1"] = false; 529 LLVM_FALLTHROUGH; 530 case SSE42: 531 Features["sse4.2"] = false; 532 LLVM_FALLTHROUGH; 533 case AVX: 534 Features["fma"] = Features["avx"] = Features["f16c"] = false; 535 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 536 Features["vpclmulqdq"] = false; 537 setXOPLevel(Features, FMA4, false); 538 LLVM_FALLTHROUGH; 539 case AVX2: 540 Features["avx2"] = false; 541 LLVM_FALLTHROUGH; 542 case AVX512F: 543 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 544 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 545 Features["avx512vl"] = Features["avx512vbmi"] = false; 546 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 547 Features["avx512bitalg"] = Features["avx512vnni"] = false; 548 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 549 Features["avx512vp2intersect"] = false; 550 break; 551 } 552 } 553 554 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 555 MMX3DNowEnum Level, bool Enabled) { 556 if (Enabled) { 557 switch (Level) { 558 case AMD3DNowAthlon: 559 Features["3dnowa"] = true; 560 LLVM_FALLTHROUGH; 561 case AMD3DNow: 562 Features["3dnow"] = true; 563 LLVM_FALLTHROUGH; 564 case MMX: 565 Features["mmx"] = true; 566 LLVM_FALLTHROUGH; 567 case NoMMX3DNow: 568 break; 569 } 570 return; 571 } 572 573 switch (Level) { 574 case NoMMX3DNow: 575 case MMX: 576 Features["mmx"] = false; 577 LLVM_FALLTHROUGH; 578 case AMD3DNow: 579 Features["3dnow"] = false; 580 LLVM_FALLTHROUGH; 581 case AMD3DNowAthlon: 582 Features["3dnowa"] = false; 583 break; 584 } 585 } 586 587 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 588 bool Enabled) { 589 if (Enabled) { 590 switch (Level) { 591 case XOP: 592 Features["xop"] = true; 593 LLVM_FALLTHROUGH; 594 case FMA4: 595 Features["fma4"] = true; 596 setSSELevel(Features, AVX, true); 597 LLVM_FALLTHROUGH; 598 case SSE4A: 599 Features["sse4a"] = true; 600 setSSELevel(Features, SSE3, true); 601 LLVM_FALLTHROUGH; 602 case NoXOP: 603 break; 604 } 605 return; 606 } 607 608 switch (Level) { 609 case NoXOP: 610 case SSE4A: 611 Features["sse4a"] = false; 612 LLVM_FALLTHROUGH; 613 case FMA4: 614 Features["fma4"] = false; 615 LLVM_FALLTHROUGH; 616 case XOP: 617 Features["xop"] = false; 618 break; 619 } 620 } 621 622 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 623 StringRef Name, bool Enabled) { 624 // This is a bit of a hack to deal with the sse4 target feature when used 625 // as part of the target attribute. We handle sse4 correctly everywhere 626 // else. See below for more information on how we handle the sse4 options. 627 if (Name != "sse4") 628 Features[Name] = Enabled; 629 630 if (Name == "mmx") { 631 setMMXLevel(Features, MMX, Enabled); 632 } else if (Name == "sse") { 633 setSSELevel(Features, SSE1, Enabled); 634 } else if (Name == "sse2") { 635 setSSELevel(Features, SSE2, Enabled); 636 } else if (Name == "sse3") { 637 setSSELevel(Features, SSE3, Enabled); 638 } else if (Name == "ssse3") { 639 setSSELevel(Features, SSSE3, Enabled); 640 } else if (Name == "sse4.2") { 641 setSSELevel(Features, SSE42, Enabled); 642 } else if (Name == "sse4.1") { 643 setSSELevel(Features, SSE41, Enabled); 644 } else if (Name == "3dnow") { 645 setMMXLevel(Features, AMD3DNow, Enabled); 646 } else if (Name == "3dnowa") { 647 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 648 } else if (Name == "aes") { 649 if (Enabled) 650 setSSELevel(Features, SSE2, Enabled); 651 else 652 Features["vaes"] = false; 653 } else if (Name == "vaes") { 654 if (Enabled) { 655 setSSELevel(Features, AVX, Enabled); 656 Features["aes"] = true; 657 } 658 } else if (Name == "pclmul") { 659 if (Enabled) 660 setSSELevel(Features, SSE2, Enabled); 661 else 662 Features["vpclmulqdq"] = false; 663 } else if (Name == "vpclmulqdq") { 664 if (Enabled) { 665 setSSELevel(Features, AVX, Enabled); 666 Features["pclmul"] = true; 667 } 668 } else if (Name == "gfni") { 669 if (Enabled) 670 setSSELevel(Features, SSE2, Enabled); 671 } else if (Name == "avx") { 672 setSSELevel(Features, AVX, Enabled); 673 } else if (Name == "avx2") { 674 setSSELevel(Features, AVX2, Enabled); 675 } else if (Name == "avx512f") { 676 setSSELevel(Features, AVX512F, Enabled); 677 } else if (Name.startswith("avx512")) { 678 if (Enabled) 679 setSSELevel(Features, AVX512F, Enabled); 680 // Enable BWI instruction if certain features are being enabled. 681 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 682 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 683 Features["avx512bw"] = true; 684 // Also disable some features if BWI is being disabled. 685 if (Name == "avx512bw" && !Enabled) { 686 Features["avx512vbmi"] = false; 687 Features["avx512vbmi2"] = false; 688 Features["avx512bitalg"] = false; 689 Features["avx512bf16"] = false; 690 } 691 } else if (Name == "fma") { 692 if (Enabled) 693 setSSELevel(Features, AVX, Enabled); 694 else 695 setSSELevel(Features, AVX512F, Enabled); 696 } else if (Name == "fma4") { 697 setXOPLevel(Features, FMA4, Enabled); 698 } else if (Name == "xop") { 699 setXOPLevel(Features, XOP, Enabled); 700 } else if (Name == "sse4a") { 701 setXOPLevel(Features, SSE4A, Enabled); 702 } else if (Name == "f16c") { 703 if (Enabled) 704 setSSELevel(Features, AVX, Enabled); 705 else 706 setSSELevel(Features, AVX512F, Enabled); 707 } else if (Name == "sha") { 708 if (Enabled) 709 setSSELevel(Features, SSE2, Enabled); 710 } else if (Name == "sse4") { 711 // We can get here via the __target__ attribute since that's not controlled 712 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 713 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 714 // disabled. 715 if (Enabled) 716 setSSELevel(Features, SSE42, Enabled); 717 else 718 setSSELevel(Features, SSE41, Enabled); 719 } else if (Name == "xsave") { 720 if (!Enabled) 721 Features["xsaveopt"] = false; 722 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 723 if (Enabled) 724 Features["xsave"] = true; 725 } 726 } 727 728 /// handleTargetFeatures - Perform initialization based on the user 729 /// configured set of features. 730 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 731 DiagnosticsEngine &Diags) { 732 for (const auto &Feature : Features) { 733 if (Feature[0] != '+') 734 continue; 735 736 if (Feature == "+aes") { 737 HasAES = true; 738 } else if (Feature == "+vaes") { 739 HasVAES = true; 740 } else if (Feature == "+pclmul") { 741 HasPCLMUL = true; 742 } else if (Feature == "+vpclmulqdq") { 743 HasVPCLMULQDQ = true; 744 } else if (Feature == "+lzcnt") { 745 HasLZCNT = true; 746 } else if (Feature == "+rdrnd") { 747 HasRDRND = true; 748 } else if (Feature == "+fsgsbase") { 749 HasFSGSBASE = true; 750 } else if (Feature == "+bmi") { 751 HasBMI = true; 752 } else if (Feature == "+bmi2") { 753 HasBMI2 = true; 754 } else if (Feature == "+popcnt") { 755 HasPOPCNT = true; 756 } else if (Feature == "+rtm") { 757 HasRTM = true; 758 } else if (Feature == "+prfchw") { 759 HasPRFCHW = true; 760 } else if (Feature == "+rdseed") { 761 HasRDSEED = true; 762 } else if (Feature == "+adx") { 763 HasADX = true; 764 } else if (Feature == "+tbm") { 765 HasTBM = true; 766 } else if (Feature == "+lwp") { 767 HasLWP = true; 768 } else if (Feature == "+fma") { 769 HasFMA = true; 770 } else if (Feature == "+f16c") { 771 HasF16C = true; 772 } else if (Feature == "+gfni") { 773 HasGFNI = true; 774 } else if (Feature == "+avx512cd") { 775 HasAVX512CD = true; 776 } else if (Feature == "+avx512vpopcntdq") { 777 HasAVX512VPOPCNTDQ = true; 778 } else if (Feature == "+avx512vnni") { 779 HasAVX512VNNI = true; 780 } else if (Feature == "+avx512bf16") { 781 HasAVX512BF16 = true; 782 } else if (Feature == "+avx512er") { 783 HasAVX512ER = true; 784 } else if (Feature == "+avx512pf") { 785 HasAVX512PF = true; 786 } else if (Feature == "+avx512dq") { 787 HasAVX512DQ = true; 788 } else if (Feature == "+avx512bitalg") { 789 HasAVX512BITALG = true; 790 } else if (Feature == "+avx512bw") { 791 HasAVX512BW = true; 792 } else if (Feature == "+avx512vl") { 793 HasAVX512VL = true; 794 } else if (Feature == "+avx512vbmi") { 795 HasAVX512VBMI = true; 796 } else if (Feature == "+avx512vbmi2") { 797 HasAVX512VBMI2 = true; 798 } else if (Feature == "+avx512ifma") { 799 HasAVX512IFMA = true; 800 } else if (Feature == "+avx512vp2intersect") { 801 HasAVX512VP2INTERSECT = true; 802 } else if (Feature == "+sha") { 803 HasSHA = true; 804 } else if (Feature == "+shstk") { 805 HasSHSTK = true; 806 } else if (Feature == "+movbe") { 807 HasMOVBE = true; 808 } else if (Feature == "+sgx") { 809 HasSGX = true; 810 } else if (Feature == "+cx8") { 811 HasCX8 = true; 812 } else if (Feature == "+cx16") { 813 HasCX16 = true; 814 } else if (Feature == "+fxsr") { 815 HasFXSR = true; 816 } else if (Feature == "+xsave") { 817 HasXSAVE = true; 818 } else if (Feature == "+xsaveopt") { 819 HasXSAVEOPT = true; 820 } else if (Feature == "+xsavec") { 821 HasXSAVEC = true; 822 } else if (Feature == "+xsaves") { 823 HasXSAVES = true; 824 } else if (Feature == "+mwaitx") { 825 HasMWAITX = true; 826 } else if (Feature == "+pku") { 827 HasPKU = true; 828 } else if (Feature == "+clflushopt") { 829 HasCLFLUSHOPT = true; 830 } else if (Feature == "+clwb") { 831 HasCLWB = true; 832 } else if (Feature == "+wbnoinvd") { 833 HasWBNOINVD = true; 834 } else if (Feature == "+prefetchwt1") { 835 HasPREFETCHWT1 = true; 836 } else if (Feature == "+clzero") { 837 HasCLZERO = true; 838 } else if (Feature == "+cldemote") { 839 HasCLDEMOTE = true; 840 } else if (Feature == "+rdpid") { 841 HasRDPID = true; 842 } else if (Feature == "+retpoline-external-thunk") { 843 HasRetpolineExternalThunk = true; 844 } else if (Feature == "+sahf") { 845 HasLAHFSAHF = true; 846 } else if (Feature == "+waitpkg") { 847 HasWAITPKG = true; 848 } else if (Feature == "+movdiri") { 849 HasMOVDIRI = true; 850 } else if (Feature == "+movdir64b") { 851 HasMOVDIR64B = true; 852 } else if (Feature == "+pconfig") { 853 HasPCONFIG = true; 854 } else if (Feature == "+ptwrite") { 855 HasPTWRITE = true; 856 } else if (Feature == "+invpcid") { 857 HasINVPCID = true; 858 } else if (Feature == "+enqcmd") { 859 HasENQCMD = true; 860 } else if (Feature == "+serialize") { 861 HasSERIALIZE = true; 862 } else if (Feature == "+tsxldtrk") { 863 HasTSXLDTRK = true; 864 } 865 866 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 867 .Case("+avx512f", AVX512F) 868 .Case("+avx2", AVX2) 869 .Case("+avx", AVX) 870 .Case("+sse4.2", SSE42) 871 .Case("+sse4.1", SSE41) 872 .Case("+ssse3", SSSE3) 873 .Case("+sse3", SSE3) 874 .Case("+sse2", SSE2) 875 .Case("+sse", SSE1) 876 .Default(NoSSE); 877 SSELevel = std::max(SSELevel, Level); 878 879 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 880 .Case("+3dnowa", AMD3DNowAthlon) 881 .Case("+3dnow", AMD3DNow) 882 .Case("+mmx", MMX) 883 .Default(NoMMX3DNow); 884 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 885 886 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 887 .Case("+xop", XOP) 888 .Case("+fma4", FMA4) 889 .Case("+sse4a", SSE4A) 890 .Default(NoXOP); 891 XOPLevel = std::max(XOPLevel, XLevel); 892 } 893 894 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 895 // matches the selected sse level. 896 if ((FPMath == FP_SSE && SSELevel < SSE1) || 897 (FPMath == FP_387 && SSELevel >= SSE1)) { 898 Diags.Report(diag::err_target_unsupported_fpmath) 899 << (FPMath == FP_SSE ? "sse" : "387"); 900 return false; 901 } 902 903 SimdDefaultAlign = 904 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 905 return true; 906 } 907 908 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 909 /// definitions for this particular subtarget. 910 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 911 MacroBuilder &Builder) const { 912 // Inline assembly supports X86 flag outputs. 913 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 914 915 std::string CodeModel = getTargetOpts().CodeModel; 916 if (CodeModel == "default") 917 CodeModel = "small"; 918 Builder.defineMacro("__code_model_" + CodeModel + "__"); 919 920 // Target identification. 921 if (getTriple().getArch() == llvm::Triple::x86_64) { 922 Builder.defineMacro("__amd64__"); 923 Builder.defineMacro("__amd64"); 924 Builder.defineMacro("__x86_64"); 925 Builder.defineMacro("__x86_64__"); 926 if (getTriple().getArchName() == "x86_64h") { 927 Builder.defineMacro("__x86_64h"); 928 Builder.defineMacro("__x86_64h__"); 929 } 930 } else { 931 DefineStd(Builder, "i386", Opts); 932 } 933 934 Builder.defineMacro("__SEG_GS"); 935 Builder.defineMacro("__SEG_FS"); 936 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 937 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 938 939 // Subtarget options. 940 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 941 // truly should be based on -mtune options. 942 switch (CPU) { 943 case CK_Generic: 944 break; 945 case CK_i386: 946 // The rest are coming from the i386 define above. 947 Builder.defineMacro("__tune_i386__"); 948 break; 949 case CK_i486: 950 case CK_WinChipC6: 951 case CK_WinChip2: 952 case CK_C3: 953 defineCPUMacros(Builder, "i486"); 954 break; 955 case CK_PentiumMMX: 956 Builder.defineMacro("__pentium_mmx__"); 957 Builder.defineMacro("__tune_pentium_mmx__"); 958 LLVM_FALLTHROUGH; 959 case CK_i586: 960 case CK_Pentium: 961 defineCPUMacros(Builder, "i586"); 962 defineCPUMacros(Builder, "pentium"); 963 break; 964 case CK_Pentium3: 965 case CK_PentiumM: 966 Builder.defineMacro("__tune_pentium3__"); 967 LLVM_FALLTHROUGH; 968 case CK_Pentium2: 969 case CK_C3_2: 970 Builder.defineMacro("__tune_pentium2__"); 971 LLVM_FALLTHROUGH; 972 case CK_PentiumPro: 973 case CK_i686: 974 defineCPUMacros(Builder, "i686"); 975 defineCPUMacros(Builder, "pentiumpro"); 976 break; 977 case CK_Pentium4: 978 defineCPUMacros(Builder, "pentium4"); 979 break; 980 case CK_Yonah: 981 case CK_Prescott: 982 case CK_Nocona: 983 defineCPUMacros(Builder, "nocona"); 984 break; 985 case CK_Core2: 986 case CK_Penryn: 987 defineCPUMacros(Builder, "core2"); 988 break; 989 case CK_Bonnell: 990 defineCPUMacros(Builder, "atom"); 991 break; 992 case CK_Silvermont: 993 defineCPUMacros(Builder, "slm"); 994 break; 995 case CK_Goldmont: 996 defineCPUMacros(Builder, "goldmont"); 997 break; 998 case CK_GoldmontPlus: 999 defineCPUMacros(Builder, "goldmont_plus"); 1000 break; 1001 case CK_Tremont: 1002 defineCPUMacros(Builder, "tremont"); 1003 break; 1004 case CK_Nehalem: 1005 case CK_Westmere: 1006 case CK_SandyBridge: 1007 case CK_IvyBridge: 1008 case CK_Haswell: 1009 case CK_Broadwell: 1010 case CK_SkylakeClient: 1011 case CK_SkylakeServer: 1012 case CK_Cascadelake: 1013 case CK_Cooperlake: 1014 case CK_Cannonlake: 1015 case CK_IcelakeClient: 1016 case CK_IcelakeServer: 1017 case CK_Tigerlake: 1018 // FIXME: Historically, we defined this legacy name, it would be nice to 1019 // remove it at some point. We've never exposed fine-grained names for 1020 // recent primary x86 CPUs, and we should keep it that way. 1021 defineCPUMacros(Builder, "corei7"); 1022 break; 1023 case CK_KNL: 1024 defineCPUMacros(Builder, "knl"); 1025 break; 1026 case CK_KNM: 1027 break; 1028 case CK_Lakemont: 1029 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1030 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1031 Builder.defineMacro("__tune_lakemont__"); 1032 break; 1033 case CK_K6_2: 1034 Builder.defineMacro("__k6_2__"); 1035 Builder.defineMacro("__tune_k6_2__"); 1036 LLVM_FALLTHROUGH; 1037 case CK_K6_3: 1038 if (CPU != CK_K6_2) { // In case of fallthrough 1039 // FIXME: GCC may be enabling these in cases where some other k6 1040 // architecture is specified but -m3dnow is explicitly provided. The 1041 // exact semantics need to be determined and emulated here. 1042 Builder.defineMacro("__k6_3__"); 1043 Builder.defineMacro("__tune_k6_3__"); 1044 } 1045 LLVM_FALLTHROUGH; 1046 case CK_K6: 1047 defineCPUMacros(Builder, "k6"); 1048 break; 1049 case CK_Athlon: 1050 case CK_AthlonXP: 1051 defineCPUMacros(Builder, "athlon"); 1052 if (SSELevel != NoSSE) { 1053 Builder.defineMacro("__athlon_sse__"); 1054 Builder.defineMacro("__tune_athlon_sse__"); 1055 } 1056 break; 1057 case CK_K8: 1058 case CK_K8SSE3: 1059 case CK_x86_64: 1060 defineCPUMacros(Builder, "k8"); 1061 break; 1062 case CK_AMDFAM10: 1063 defineCPUMacros(Builder, "amdfam10"); 1064 break; 1065 case CK_BTVER1: 1066 defineCPUMacros(Builder, "btver1"); 1067 break; 1068 case CK_BTVER2: 1069 defineCPUMacros(Builder, "btver2"); 1070 break; 1071 case CK_BDVER1: 1072 defineCPUMacros(Builder, "bdver1"); 1073 break; 1074 case CK_BDVER2: 1075 defineCPUMacros(Builder, "bdver2"); 1076 break; 1077 case CK_BDVER3: 1078 defineCPUMacros(Builder, "bdver3"); 1079 break; 1080 case CK_BDVER4: 1081 defineCPUMacros(Builder, "bdver4"); 1082 break; 1083 case CK_ZNVER1: 1084 defineCPUMacros(Builder, "znver1"); 1085 break; 1086 case CK_ZNVER2: 1087 defineCPUMacros(Builder, "znver2"); 1088 break; 1089 case CK_Geode: 1090 defineCPUMacros(Builder, "geode"); 1091 break; 1092 } 1093 1094 // Target properties. 1095 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1096 1097 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1098 // functions in glibc header files that use FP Stack inline asm which the 1099 // backend can't deal with (PR879). 1100 Builder.defineMacro("__NO_MATH_INLINES"); 1101 1102 if (HasAES) 1103 Builder.defineMacro("__AES__"); 1104 1105 if (HasVAES) 1106 Builder.defineMacro("__VAES__"); 1107 1108 if (HasPCLMUL) 1109 Builder.defineMacro("__PCLMUL__"); 1110 1111 if (HasVPCLMULQDQ) 1112 Builder.defineMacro("__VPCLMULQDQ__"); 1113 1114 if (HasLZCNT) 1115 Builder.defineMacro("__LZCNT__"); 1116 1117 if (HasRDRND) 1118 Builder.defineMacro("__RDRND__"); 1119 1120 if (HasFSGSBASE) 1121 Builder.defineMacro("__FSGSBASE__"); 1122 1123 if (HasBMI) 1124 Builder.defineMacro("__BMI__"); 1125 1126 if (HasBMI2) 1127 Builder.defineMacro("__BMI2__"); 1128 1129 if (HasPOPCNT) 1130 Builder.defineMacro("__POPCNT__"); 1131 1132 if (HasRTM) 1133 Builder.defineMacro("__RTM__"); 1134 1135 if (HasPRFCHW) 1136 Builder.defineMacro("__PRFCHW__"); 1137 1138 if (HasRDSEED) 1139 Builder.defineMacro("__RDSEED__"); 1140 1141 if (HasADX) 1142 Builder.defineMacro("__ADX__"); 1143 1144 if (HasTBM) 1145 Builder.defineMacro("__TBM__"); 1146 1147 if (HasLWP) 1148 Builder.defineMacro("__LWP__"); 1149 1150 if (HasMWAITX) 1151 Builder.defineMacro("__MWAITX__"); 1152 1153 if (HasMOVBE) 1154 Builder.defineMacro("__MOVBE__"); 1155 1156 switch (XOPLevel) { 1157 case XOP: 1158 Builder.defineMacro("__XOP__"); 1159 LLVM_FALLTHROUGH; 1160 case FMA4: 1161 Builder.defineMacro("__FMA4__"); 1162 LLVM_FALLTHROUGH; 1163 case SSE4A: 1164 Builder.defineMacro("__SSE4A__"); 1165 LLVM_FALLTHROUGH; 1166 case NoXOP: 1167 break; 1168 } 1169 1170 if (HasFMA) 1171 Builder.defineMacro("__FMA__"); 1172 1173 if (HasF16C) 1174 Builder.defineMacro("__F16C__"); 1175 1176 if (HasGFNI) 1177 Builder.defineMacro("__GFNI__"); 1178 1179 if (HasAVX512CD) 1180 Builder.defineMacro("__AVX512CD__"); 1181 if (HasAVX512VPOPCNTDQ) 1182 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1183 if (HasAVX512VNNI) 1184 Builder.defineMacro("__AVX512VNNI__"); 1185 if (HasAVX512BF16) 1186 Builder.defineMacro("__AVX512BF16__"); 1187 if (HasAVX512ER) 1188 Builder.defineMacro("__AVX512ER__"); 1189 if (HasAVX512PF) 1190 Builder.defineMacro("__AVX512PF__"); 1191 if (HasAVX512DQ) 1192 Builder.defineMacro("__AVX512DQ__"); 1193 if (HasAVX512BITALG) 1194 Builder.defineMacro("__AVX512BITALG__"); 1195 if (HasAVX512BW) 1196 Builder.defineMacro("__AVX512BW__"); 1197 if (HasAVX512VL) 1198 Builder.defineMacro("__AVX512VL__"); 1199 if (HasAVX512VBMI) 1200 Builder.defineMacro("__AVX512VBMI__"); 1201 if (HasAVX512VBMI2) 1202 Builder.defineMacro("__AVX512VBMI2__"); 1203 if (HasAVX512IFMA) 1204 Builder.defineMacro("__AVX512IFMA__"); 1205 if (HasAVX512VP2INTERSECT) 1206 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1207 if (HasSHA) 1208 Builder.defineMacro("__SHA__"); 1209 1210 if (HasFXSR) 1211 Builder.defineMacro("__FXSR__"); 1212 if (HasXSAVE) 1213 Builder.defineMacro("__XSAVE__"); 1214 if (HasXSAVEOPT) 1215 Builder.defineMacro("__XSAVEOPT__"); 1216 if (HasXSAVEC) 1217 Builder.defineMacro("__XSAVEC__"); 1218 if (HasXSAVES) 1219 Builder.defineMacro("__XSAVES__"); 1220 if (HasPKU) 1221 Builder.defineMacro("__PKU__"); 1222 if (HasCLFLUSHOPT) 1223 Builder.defineMacro("__CLFLUSHOPT__"); 1224 if (HasCLWB) 1225 Builder.defineMacro("__CLWB__"); 1226 if (HasWBNOINVD) 1227 Builder.defineMacro("__WBNOINVD__"); 1228 if (HasSHSTK) 1229 Builder.defineMacro("__SHSTK__"); 1230 if (HasSGX) 1231 Builder.defineMacro("__SGX__"); 1232 if (HasPREFETCHWT1) 1233 Builder.defineMacro("__PREFETCHWT1__"); 1234 if (HasCLZERO) 1235 Builder.defineMacro("__CLZERO__"); 1236 if (HasRDPID) 1237 Builder.defineMacro("__RDPID__"); 1238 if (HasCLDEMOTE) 1239 Builder.defineMacro("__CLDEMOTE__"); 1240 if (HasWAITPKG) 1241 Builder.defineMacro("__WAITPKG__"); 1242 if (HasMOVDIRI) 1243 Builder.defineMacro("__MOVDIRI__"); 1244 if (HasMOVDIR64B) 1245 Builder.defineMacro("__MOVDIR64B__"); 1246 if (HasPCONFIG) 1247 Builder.defineMacro("__PCONFIG__"); 1248 if (HasPTWRITE) 1249 Builder.defineMacro("__PTWRITE__"); 1250 if (HasINVPCID) 1251 Builder.defineMacro("__INVPCID__"); 1252 if (HasENQCMD) 1253 Builder.defineMacro("__ENQCMD__"); 1254 if (HasSERIALIZE) 1255 Builder.defineMacro("__SERIALIZE__"); 1256 if (HasTSXLDTRK) 1257 Builder.defineMacro("__TSXLDTRK__"); 1258 1259 // Each case falls through to the previous one here. 1260 switch (SSELevel) { 1261 case AVX512F: 1262 Builder.defineMacro("__AVX512F__"); 1263 LLVM_FALLTHROUGH; 1264 case AVX2: 1265 Builder.defineMacro("__AVX2__"); 1266 LLVM_FALLTHROUGH; 1267 case AVX: 1268 Builder.defineMacro("__AVX__"); 1269 LLVM_FALLTHROUGH; 1270 case SSE42: 1271 Builder.defineMacro("__SSE4_2__"); 1272 LLVM_FALLTHROUGH; 1273 case SSE41: 1274 Builder.defineMacro("__SSE4_1__"); 1275 LLVM_FALLTHROUGH; 1276 case SSSE3: 1277 Builder.defineMacro("__SSSE3__"); 1278 LLVM_FALLTHROUGH; 1279 case SSE3: 1280 Builder.defineMacro("__SSE3__"); 1281 LLVM_FALLTHROUGH; 1282 case SSE2: 1283 Builder.defineMacro("__SSE2__"); 1284 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1285 LLVM_FALLTHROUGH; 1286 case SSE1: 1287 Builder.defineMacro("__SSE__"); 1288 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1289 LLVM_FALLTHROUGH; 1290 case NoSSE: 1291 break; 1292 } 1293 1294 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1295 switch (SSELevel) { 1296 case AVX512F: 1297 case AVX2: 1298 case AVX: 1299 case SSE42: 1300 case SSE41: 1301 case SSSE3: 1302 case SSE3: 1303 case SSE2: 1304 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1305 break; 1306 case SSE1: 1307 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1308 break; 1309 default: 1310 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1311 break; 1312 } 1313 } 1314 1315 // Each case falls through to the previous one here. 1316 switch (MMX3DNowLevel) { 1317 case AMD3DNowAthlon: 1318 Builder.defineMacro("__3dNOW_A__"); 1319 LLVM_FALLTHROUGH; 1320 case AMD3DNow: 1321 Builder.defineMacro("__3dNOW__"); 1322 LLVM_FALLTHROUGH; 1323 case MMX: 1324 Builder.defineMacro("__MMX__"); 1325 LLVM_FALLTHROUGH; 1326 case NoMMX3DNow: 1327 break; 1328 } 1329 1330 if (CPU >= CK_i486 || CPU == CK_Generic) { 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1334 } 1335 if (HasCX8) 1336 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1337 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1338 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1339 1340 if (HasFloat128) 1341 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1342 } 1343 1344 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1345 return llvm::StringSwitch<bool>(Name) 1346 .Case("3dnow", true) 1347 .Case("3dnowa", true) 1348 .Case("adx", true) 1349 .Case("aes", true) 1350 .Case("avx", true) 1351 .Case("avx2", true) 1352 .Case("avx512f", true) 1353 .Case("avx512cd", true) 1354 .Case("avx512vpopcntdq", true) 1355 .Case("avx512vnni", true) 1356 .Case("avx512bf16", true) 1357 .Case("avx512er", true) 1358 .Case("avx512pf", true) 1359 .Case("avx512dq", true) 1360 .Case("avx512bitalg", true) 1361 .Case("avx512bw", true) 1362 .Case("avx512vl", true) 1363 .Case("avx512vbmi", true) 1364 .Case("avx512vbmi2", true) 1365 .Case("avx512ifma", true) 1366 .Case("avx512vp2intersect", true) 1367 .Case("bmi", true) 1368 .Case("bmi2", true) 1369 .Case("cldemote", true) 1370 .Case("clflushopt", true) 1371 .Case("clwb", true) 1372 .Case("clzero", true) 1373 .Case("cx16", true) 1374 .Case("enqcmd", true) 1375 .Case("f16c", true) 1376 .Case("fma", true) 1377 .Case("fma4", true) 1378 .Case("fsgsbase", true) 1379 .Case("fxsr", true) 1380 .Case("gfni", true) 1381 .Case("invpcid", true) 1382 .Case("lwp", true) 1383 .Case("lzcnt", true) 1384 .Case("mmx", true) 1385 .Case("movbe", true) 1386 .Case("movdiri", true) 1387 .Case("movdir64b", true) 1388 .Case("mwaitx", true) 1389 .Case("pclmul", true) 1390 .Case("pconfig", true) 1391 .Case("pku", true) 1392 .Case("popcnt", true) 1393 .Case("prefetchwt1", true) 1394 .Case("prfchw", true) 1395 .Case("ptwrite", true) 1396 .Case("rdpid", true) 1397 .Case("rdrnd", true) 1398 .Case("rdseed", true) 1399 .Case("rtm", true) 1400 .Case("sahf", true) 1401 .Case("serialize", true) 1402 .Case("sgx", true) 1403 .Case("sha", true) 1404 .Case("shstk", true) 1405 .Case("sse", true) 1406 .Case("sse2", true) 1407 .Case("sse3", true) 1408 .Case("ssse3", true) 1409 .Case("sse4", true) 1410 .Case("sse4.1", true) 1411 .Case("sse4.2", true) 1412 .Case("sse4a", true) 1413 .Case("tbm", true) 1414 .Case("tsxldtrk", true) 1415 .Case("vaes", true) 1416 .Case("vpclmulqdq", true) 1417 .Case("wbnoinvd", true) 1418 .Case("waitpkg", true) 1419 .Case("x87", true) 1420 .Case("xop", true) 1421 .Case("xsave", true) 1422 .Case("xsavec", true) 1423 .Case("xsaves", true) 1424 .Case("xsaveopt", true) 1425 .Default(false); 1426 } 1427 1428 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1429 return llvm::StringSwitch<bool>(Feature) 1430 .Case("adx", HasADX) 1431 .Case("aes", HasAES) 1432 .Case("avx", SSELevel >= AVX) 1433 .Case("avx2", SSELevel >= AVX2) 1434 .Case("avx512f", SSELevel >= AVX512F) 1435 .Case("avx512cd", HasAVX512CD) 1436 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1437 .Case("avx512vnni", HasAVX512VNNI) 1438 .Case("avx512bf16", HasAVX512BF16) 1439 .Case("avx512er", HasAVX512ER) 1440 .Case("avx512pf", HasAVX512PF) 1441 .Case("avx512dq", HasAVX512DQ) 1442 .Case("avx512bitalg", HasAVX512BITALG) 1443 .Case("avx512bw", HasAVX512BW) 1444 .Case("avx512vl", HasAVX512VL) 1445 .Case("avx512vbmi", HasAVX512VBMI) 1446 .Case("avx512vbmi2", HasAVX512VBMI2) 1447 .Case("avx512ifma", HasAVX512IFMA) 1448 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1449 .Case("bmi", HasBMI) 1450 .Case("bmi2", HasBMI2) 1451 .Case("cldemote", HasCLDEMOTE) 1452 .Case("clflushopt", HasCLFLUSHOPT) 1453 .Case("clwb", HasCLWB) 1454 .Case("clzero", HasCLZERO) 1455 .Case("cx8", HasCX8) 1456 .Case("cx16", HasCX16) 1457 .Case("enqcmd", HasENQCMD) 1458 .Case("f16c", HasF16C) 1459 .Case("fma", HasFMA) 1460 .Case("fma4", XOPLevel >= FMA4) 1461 .Case("fsgsbase", HasFSGSBASE) 1462 .Case("fxsr", HasFXSR) 1463 .Case("gfni", HasGFNI) 1464 .Case("invpcid", HasINVPCID) 1465 .Case("lwp", HasLWP) 1466 .Case("lzcnt", HasLZCNT) 1467 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1468 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1469 .Case("mmx", MMX3DNowLevel >= MMX) 1470 .Case("movbe", HasMOVBE) 1471 .Case("movdiri", HasMOVDIRI) 1472 .Case("movdir64b", HasMOVDIR64B) 1473 .Case("mwaitx", HasMWAITX) 1474 .Case("pclmul", HasPCLMUL) 1475 .Case("pconfig", HasPCONFIG) 1476 .Case("pku", HasPKU) 1477 .Case("popcnt", HasPOPCNT) 1478 .Case("prefetchwt1", HasPREFETCHWT1) 1479 .Case("prfchw", HasPRFCHW) 1480 .Case("ptwrite", HasPTWRITE) 1481 .Case("rdpid", HasRDPID) 1482 .Case("rdrnd", HasRDRND) 1483 .Case("rdseed", HasRDSEED) 1484 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1485 .Case("rtm", HasRTM) 1486 .Case("sahf", HasLAHFSAHF) 1487 .Case("serialize", HasSERIALIZE) 1488 .Case("sgx", HasSGX) 1489 .Case("sha", HasSHA) 1490 .Case("shstk", HasSHSTK) 1491 .Case("sse", SSELevel >= SSE1) 1492 .Case("sse2", SSELevel >= SSE2) 1493 .Case("sse3", SSELevel >= SSE3) 1494 .Case("ssse3", SSELevel >= SSSE3) 1495 .Case("sse4.1", SSELevel >= SSE41) 1496 .Case("sse4.2", SSELevel >= SSE42) 1497 .Case("sse4a", XOPLevel >= SSE4A) 1498 .Case("tbm", HasTBM) 1499 .Case("tsxldtrk", HasTSXLDTRK) 1500 .Case("vaes", HasVAES) 1501 .Case("vpclmulqdq", HasVPCLMULQDQ) 1502 .Case("wbnoinvd", HasWBNOINVD) 1503 .Case("waitpkg", HasWAITPKG) 1504 .Case("x86", true) 1505 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1506 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1507 .Case("xop", XOPLevel >= XOP) 1508 .Case("xsave", HasXSAVE) 1509 .Case("xsavec", HasXSAVEC) 1510 .Case("xsaves", HasXSAVES) 1511 .Case("xsaveopt", HasXSAVEOPT) 1512 .Default(false); 1513 } 1514 1515 // We can't use a generic validation scheme for the features accepted here 1516 // versus subtarget features accepted in the target attribute because the 1517 // bitfield structure that's initialized in the runtime only supports the 1518 // below currently rather than the full range of subtarget features. (See 1519 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1520 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1521 return llvm::StringSwitch<bool>(FeatureStr) 1522 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1523 #include "llvm/Support/X86TargetParser.def" 1524 .Default(false); 1525 } 1526 1527 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1528 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1529 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1530 #include "llvm/Support/X86TargetParser.def" 1531 ; 1532 // Note, this function should only be used after ensuring the value is 1533 // correct, so it asserts if the value is out of range. 1534 } 1535 1536 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1537 enum class FeatPriority { 1538 #define FEATURE(FEAT) FEAT, 1539 #include "clang/Basic/X86Target.def" 1540 }; 1541 switch (Feat) { 1542 #define FEATURE(FEAT) \ 1543 case llvm::X86::FEAT: \ 1544 return static_cast<unsigned>(FeatPriority::FEAT); 1545 #include "clang/Basic/X86Target.def" 1546 default: 1547 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1548 } 1549 } 1550 1551 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1552 // Valid CPUs have a 'key feature' that compares just better than its key 1553 // feature. 1554 CPUKind Kind = getCPUKind(Name); 1555 if (Kind != CK_Generic) { 1556 switch (Kind) { 1557 default: 1558 llvm_unreachable( 1559 "CPU Type without a key feature used in 'target' attribute"); 1560 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1561 case CK_##ENUM: \ 1562 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1563 #include "clang/Basic/X86Target.def" 1564 } 1565 } 1566 1567 // Now we know we have a feature, so get its priority and shift it a few so 1568 // that we have sufficient room for the CPUs (above). 1569 return getFeaturePriority(getFeature(Name)) << 1; 1570 } 1571 1572 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1573 return llvm::StringSwitch<bool>(Name) 1574 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1575 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1576 #include "clang/Basic/X86Target.def" 1577 .Default(false); 1578 } 1579 1580 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1581 return llvm::StringSwitch<StringRef>(Name) 1582 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1583 #include "clang/Basic/X86Target.def" 1584 .Default(Name); 1585 } 1586 1587 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1588 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1589 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1590 #include "clang/Basic/X86Target.def" 1591 .Default(0); 1592 } 1593 1594 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1595 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1596 StringRef WholeList = 1597 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1598 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1599 #include "clang/Basic/X86Target.def" 1600 .Default(""); 1601 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1602 } 1603 1604 // We can't use a generic validation scheme for the cpus accepted here 1605 // versus subtarget cpus accepted in the target attribute because the 1606 // variables intitialized by the runtime only support the below currently 1607 // rather than the full range of cpus. 1608 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1609 return llvm::StringSwitch<bool>(FeatureStr) 1610 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1611 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1612 .Cases(STR, ALIAS, true) 1613 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1614 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1615 #include "llvm/Support/X86TargetParser.def" 1616 .Default(false); 1617 } 1618 1619 static unsigned matchAsmCCConstraint(const char *&Name) { 1620 auto RV = llvm::StringSwitch<unsigned>(Name) 1621 .Case("@cca", 4) 1622 .Case("@ccae", 5) 1623 .Case("@ccb", 4) 1624 .Case("@ccbe", 5) 1625 .Case("@ccc", 4) 1626 .Case("@cce", 4) 1627 .Case("@ccz", 4) 1628 .Case("@ccg", 4) 1629 .Case("@ccge", 5) 1630 .Case("@ccl", 4) 1631 .Case("@ccle", 5) 1632 .Case("@ccna", 5) 1633 .Case("@ccnae", 6) 1634 .Case("@ccnb", 5) 1635 .Case("@ccnbe", 6) 1636 .Case("@ccnc", 5) 1637 .Case("@ccne", 5) 1638 .Case("@ccnz", 5) 1639 .Case("@ccng", 5) 1640 .Case("@ccnge", 6) 1641 .Case("@ccnl", 5) 1642 .Case("@ccnle", 6) 1643 .Case("@ccno", 5) 1644 .Case("@ccnp", 5) 1645 .Case("@ccns", 5) 1646 .Case("@cco", 4) 1647 .Case("@ccp", 4) 1648 .Case("@ccs", 4) 1649 .Default(0); 1650 return RV; 1651 } 1652 1653 bool X86TargetInfo::validateAsmConstraint( 1654 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1655 switch (*Name) { 1656 default: 1657 return false; 1658 // Constant constraints. 1659 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1660 // instructions. 1661 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1662 // x86_64 instructions. 1663 case 's': 1664 Info.setRequiresImmediate(); 1665 return true; 1666 case 'I': 1667 Info.setRequiresImmediate(0, 31); 1668 return true; 1669 case 'J': 1670 Info.setRequiresImmediate(0, 63); 1671 return true; 1672 case 'K': 1673 Info.setRequiresImmediate(-128, 127); 1674 return true; 1675 case 'L': 1676 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1677 return true; 1678 case 'M': 1679 Info.setRequiresImmediate(0, 3); 1680 return true; 1681 case 'N': 1682 Info.setRequiresImmediate(0, 255); 1683 return true; 1684 case 'O': 1685 Info.setRequiresImmediate(0, 127); 1686 return true; 1687 // Register constraints. 1688 case 'Y': // 'Y' is the first character for several 2-character constraints. 1689 // Shift the pointer to the second character of the constraint. 1690 Name++; 1691 switch (*Name) { 1692 default: 1693 return false; 1694 case 'z': 1695 case '0': // First SSE register. 1696 case '2': 1697 case 't': // Any SSE register, when SSE2 is enabled. 1698 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1699 case 'm': // Any MMX register, when inter-unit moves enabled. 1700 case 'k': // AVX512 arch mask registers: k1-k7. 1701 Info.setAllowsRegister(); 1702 return true; 1703 } 1704 case 'f': // Any x87 floating point stack register. 1705 // Constraint 'f' cannot be used for output operands. 1706 if (Info.ConstraintStr[0] == '=') 1707 return false; 1708 Info.setAllowsRegister(); 1709 return true; 1710 case 'a': // eax. 1711 case 'b': // ebx. 1712 case 'c': // ecx. 1713 case 'd': // edx. 1714 case 'S': // esi. 1715 case 'D': // edi. 1716 case 'A': // edx:eax. 1717 case 't': // Top of floating point stack. 1718 case 'u': // Second from top of floating point stack. 1719 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1720 case 'y': // Any MMX register. 1721 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1722 case 'x': // Any SSE register. 1723 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1724 // for intermideate k reg operations). 1725 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1726 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1727 case 'l': // "Index" registers: any general register that can be used as an 1728 // index in a base+index memory access. 1729 Info.setAllowsRegister(); 1730 return true; 1731 // Floating point constant constraints. 1732 case 'C': // SSE floating point constant. 1733 case 'G': // x87 floating point constant. 1734 return true; 1735 case '@': 1736 // CC condition changes. 1737 if (auto Len = matchAsmCCConstraint(Name)) { 1738 Name += Len - 1; 1739 Info.setAllowsRegister(); 1740 return true; 1741 } 1742 return false; 1743 } 1744 } 1745 1746 // Below is based on the following information: 1747 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1748 // | Processor Name | Cache Line Size (Bytes) | Source | 1749 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1750 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1751 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1752 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1753 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1754 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1755 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1756 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1757 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1758 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1759 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1760 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1761 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1762 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1763 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1764 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1765 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1766 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1767 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1768 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1769 switch (CPU) { 1770 // i386 1771 case CK_i386: 1772 // i486 1773 case CK_i486: 1774 case CK_WinChipC6: 1775 case CK_WinChip2: 1776 case CK_C3: 1777 // Lakemont 1778 case CK_Lakemont: 1779 return 16; 1780 1781 // i586 1782 case CK_i586: 1783 case CK_Pentium: 1784 case CK_PentiumMMX: 1785 // i686 1786 case CK_PentiumPro: 1787 case CK_i686: 1788 case CK_Pentium2: 1789 case CK_Pentium3: 1790 case CK_PentiumM: 1791 case CK_C3_2: 1792 // K6 1793 case CK_K6: 1794 case CK_K6_2: 1795 case CK_K6_3: 1796 // Geode 1797 case CK_Geode: 1798 return 32; 1799 1800 // Netburst 1801 case CK_Pentium4: 1802 case CK_Prescott: 1803 case CK_Nocona: 1804 // Atom 1805 case CK_Bonnell: 1806 case CK_Silvermont: 1807 case CK_Goldmont: 1808 case CK_GoldmontPlus: 1809 case CK_Tremont: 1810 1811 case CK_Westmere: 1812 case CK_SandyBridge: 1813 case CK_IvyBridge: 1814 case CK_Haswell: 1815 case CK_Broadwell: 1816 case CK_SkylakeClient: 1817 case CK_SkylakeServer: 1818 case CK_Cascadelake: 1819 case CK_Nehalem: 1820 case CK_Cooperlake: 1821 case CK_Cannonlake: 1822 case CK_Tigerlake: 1823 case CK_IcelakeClient: 1824 case CK_IcelakeServer: 1825 case CK_KNL: 1826 case CK_KNM: 1827 // K7 1828 case CK_Athlon: 1829 case CK_AthlonXP: 1830 // K8 1831 case CK_K8: 1832 case CK_K8SSE3: 1833 case CK_AMDFAM10: 1834 // Bobcat 1835 case CK_BTVER1: 1836 case CK_BTVER2: 1837 // Bulldozer 1838 case CK_BDVER1: 1839 case CK_BDVER2: 1840 case CK_BDVER3: 1841 case CK_BDVER4: 1842 // Zen 1843 case CK_ZNVER1: 1844 case CK_ZNVER2: 1845 // Deprecated 1846 case CK_x86_64: 1847 case CK_Yonah: 1848 case CK_Penryn: 1849 case CK_Core2: 1850 return 64; 1851 1852 // The following currently have unknown cache line sizes (but they are probably all 64): 1853 // Core 1854 case CK_Generic: 1855 return None; 1856 } 1857 llvm_unreachable("Unknown CPU kind"); 1858 } 1859 1860 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1861 StringRef Constraint, 1862 unsigned Size) const { 1863 // Strip off constraint modifiers. 1864 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1865 Constraint = Constraint.substr(1); 1866 1867 return validateOperandSize(FeatureMap, Constraint, Size); 1868 } 1869 1870 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1871 StringRef Constraint, 1872 unsigned Size) const { 1873 return validateOperandSize(FeatureMap, Constraint, Size); 1874 } 1875 1876 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1877 StringRef Constraint, 1878 unsigned Size) const { 1879 switch (Constraint[0]) { 1880 default: 1881 break; 1882 case 'k': 1883 // Registers k0-k7 (AVX512) size limit is 64 bit. 1884 case 'y': 1885 return Size <= 64; 1886 case 'f': 1887 case 't': 1888 case 'u': 1889 return Size <= 128; 1890 case 'Y': 1891 // 'Y' is the first character for several 2-character constraints. 1892 switch (Constraint[1]) { 1893 default: 1894 return false; 1895 case 'm': 1896 // 'Ym' is synonymous with 'y'. 1897 case 'k': 1898 return Size <= 64; 1899 case 'z': 1900 case '0': 1901 // XMM0 1902 if (FeatureMap.lookup("sse")) 1903 return Size <= 128U; 1904 return false; 1905 case 'i': 1906 case 't': 1907 case '2': 1908 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1909 if (SSELevel < SSE2) 1910 return false; 1911 break; 1912 } 1913 LLVM_FALLTHROUGH; 1914 case 'v': 1915 case 'x': 1916 if (FeatureMap.lookup("avx512f")) 1917 // 512-bit zmm registers can be used if target supports AVX512F. 1918 return Size <= 512U; 1919 else if (FeatureMap.lookup("avx")) 1920 // 256-bit ymm registers can be used if target supports AVX. 1921 return Size <= 256U; 1922 return Size <= 128U; 1923 1924 } 1925 1926 return true; 1927 } 1928 1929 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1930 switch (*Constraint) { 1931 case '@': 1932 if (auto Len = matchAsmCCConstraint(Constraint)) { 1933 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1934 Constraint += Len - 1; 1935 return Converted; 1936 } 1937 return std::string(1, *Constraint); 1938 case 'a': 1939 return std::string("{ax}"); 1940 case 'b': 1941 return std::string("{bx}"); 1942 case 'c': 1943 return std::string("{cx}"); 1944 case 'd': 1945 return std::string("{dx}"); 1946 case 'S': 1947 return std::string("{si}"); 1948 case 'D': 1949 return std::string("{di}"); 1950 case 'p': // address 1951 return std::string("im"); 1952 case 't': // top of floating point stack. 1953 return std::string("{st}"); 1954 case 'u': // second from top of floating point stack. 1955 return std::string("{st(1)}"); // second from top of floating point stack. 1956 case 'Y': 1957 switch (Constraint[1]) { 1958 default: 1959 // Break from inner switch and fall through (copy single char), 1960 // continue parsing after copying the current constraint into 1961 // the return string. 1962 break; 1963 case 'k': 1964 case 'm': 1965 case 'i': 1966 case 't': 1967 case 'z': 1968 case '0': 1969 case '2': 1970 // "^" hints llvm that this is a 2 letter constraint. 1971 // "Constraint++" is used to promote the string iterator 1972 // to the next constraint. 1973 return std::string("^") + std::string(Constraint++, 2); 1974 } 1975 LLVM_FALLTHROUGH; 1976 default: 1977 return std::string(1, *Constraint); 1978 } 1979 } 1980 1981 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1982 // Perform any per-CPU checks necessary to determine if this CPU is 1983 // acceptable. 1984 switch (Kind) { 1985 case CK_Generic: 1986 // No processor selected! 1987 return false; 1988 #define PROC(ENUM, STRING, IS64BIT) \ 1989 case CK_##ENUM: \ 1990 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1991 #include "clang/Basic/X86Target.def" 1992 } 1993 llvm_unreachable("Unhandled CPU kind"); 1994 } 1995 1996 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1997 #define PROC(ENUM, STRING, IS64BIT) \ 1998 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1999 Values.emplace_back(STRING); 2000 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 2001 #define PROC_ALIAS(ENUM, ALIAS) \ 2002 if (checkCPUKind(CK_##ENUM)) \ 2003 Values.emplace_back(ALIAS); 2004 #include "clang/Basic/X86Target.def" 2005 } 2006 2007 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 2008 return llvm::StringSwitch<CPUKind>(CPU) 2009 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 2010 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 2011 #include "clang/Basic/X86Target.def" 2012 .Default(CK_Generic); 2013 } 2014 2015 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 2016 return llvm::makeArrayRef(GCCRegNames); 2017 } 2018 2019 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 2020 return llvm::makeArrayRef(AddlRegNames); 2021 } 2022 2023 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 2024 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 2025 Builtin::FirstTSBuiltin + 1); 2026 } 2027 2028 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 2029 return llvm::makeArrayRef(BuiltinInfoX86, 2030 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 2031 } 2032