1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 using namespace llvm::X86; 113 const enum CPUKind Kind = parseArchX86(CPU); 114 115 // Enable X87 for all X86 processors but Lakemont. 116 if (Kind != CK_Lakemont) 117 setFeatureEnabledImpl(Features, "x87", true); 118 119 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 120 // compatibility. 121 if (Kind >= CK_i586 || Kind == CK_None) 122 setFeatureEnabledImpl(Features, "cx8", true); 123 124 switch (Kind) { 125 case CK_None: 126 case CK_i386: 127 case CK_i486: 128 case CK_i586: 129 case CK_Pentium: 130 case CK_PentiumPro: 131 case CK_i686: 132 case CK_Lakemont: 133 break; 134 135 case CK_Cooperlake: 136 // CPX inherits all CLX features plus AVX512BF16 137 setFeatureEnabledImpl(Features, "avx512bf16", true); 138 LLVM_FALLTHROUGH; 139 case CK_Cascadelake: 140 // CLX inherits all SKX features plus AVX512VNNI 141 setFeatureEnabledImpl(Features, "avx512vnni", true); 142 LLVM_FALLTHROUGH; 143 case CK_SkylakeServer: 144 setFeatureEnabledImpl(Features, "avx512f", true); 145 setFeatureEnabledImpl(Features, "avx512cd", true); 146 setFeatureEnabledImpl(Features, "avx512dq", true); 147 setFeatureEnabledImpl(Features, "avx512bw", true); 148 setFeatureEnabledImpl(Features, "avx512vl", true); 149 setFeatureEnabledImpl(Features, "clwb", true); 150 setFeatureEnabledImpl(Features, "pku", true); 151 // SkylakeServer cores inherits all SKL features, except SGX 152 goto SkylakeCommon; 153 154 case CK_Tigerlake: 155 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 156 setFeatureEnabledImpl(Features, "movdiri", true); 157 setFeatureEnabledImpl(Features, "movdir64b", true); 158 setFeatureEnabledImpl(Features, "shstk", true); 159 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 160 goto IcelakeCommon; 161 162 case CK_IcelakeServer: 163 setFeatureEnabledImpl(Features, "pconfig", true); 164 setFeatureEnabledImpl(Features, "wbnoinvd", true); 165 LLVM_FALLTHROUGH; 166 case CK_IcelakeClient: 167 IcelakeCommon: 168 setFeatureEnabledImpl(Features, "vaes", true); 169 setFeatureEnabledImpl(Features, "gfni", true); 170 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 171 setFeatureEnabledImpl(Features, "avx512bitalg", true); 172 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 173 setFeatureEnabledImpl(Features, "avx512vnni", true); 174 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 175 setFeatureEnabledImpl(Features, "rdpid", true); 176 setFeatureEnabledImpl(Features, "clwb", true); 177 LLVM_FALLTHROUGH; 178 case CK_Cannonlake: 179 setFeatureEnabledImpl(Features, "avx512f", true); 180 setFeatureEnabledImpl(Features, "avx512cd", true); 181 setFeatureEnabledImpl(Features, "avx512dq", true); 182 setFeatureEnabledImpl(Features, "avx512bw", true); 183 setFeatureEnabledImpl(Features, "avx512vl", true); 184 setFeatureEnabledImpl(Features, "avx512ifma", true); 185 setFeatureEnabledImpl(Features, "avx512vbmi", true); 186 setFeatureEnabledImpl(Features, "pku", true); 187 setFeatureEnabledImpl(Features, "sha", true); 188 LLVM_FALLTHROUGH; 189 case CK_SkylakeClient: 190 setFeatureEnabledImpl(Features, "sgx", true); 191 // SkylakeServer cores inherits all SKL features, except SGX 192 SkylakeCommon: 193 setFeatureEnabledImpl(Features, "xsavec", true); 194 setFeatureEnabledImpl(Features, "xsaves", true); 195 setFeatureEnabledImpl(Features, "clflushopt", true); 196 setFeatureEnabledImpl(Features, "aes", true); 197 LLVM_FALLTHROUGH; 198 case CK_Broadwell: 199 setFeatureEnabledImpl(Features, "rdseed", true); 200 setFeatureEnabledImpl(Features, "adx", true); 201 setFeatureEnabledImpl(Features, "prfchw", true); 202 LLVM_FALLTHROUGH; 203 case CK_Haswell: 204 setFeatureEnabledImpl(Features, "avx2", true); 205 setFeatureEnabledImpl(Features, "lzcnt", true); 206 setFeatureEnabledImpl(Features, "bmi", true); 207 setFeatureEnabledImpl(Features, "bmi2", true); 208 setFeatureEnabledImpl(Features, "fma", true); 209 setFeatureEnabledImpl(Features, "invpcid", true); 210 setFeatureEnabledImpl(Features, "movbe", true); 211 LLVM_FALLTHROUGH; 212 case CK_IvyBridge: 213 setFeatureEnabledImpl(Features, "rdrnd", true); 214 setFeatureEnabledImpl(Features, "f16c", true); 215 setFeatureEnabledImpl(Features, "fsgsbase", true); 216 LLVM_FALLTHROUGH; 217 case CK_SandyBridge: 218 setFeatureEnabledImpl(Features, "avx", true); 219 setFeatureEnabledImpl(Features, "xsave", true); 220 setFeatureEnabledImpl(Features, "xsaveopt", true); 221 LLVM_FALLTHROUGH; 222 case CK_Westmere: 223 setFeatureEnabledImpl(Features, "pclmul", true); 224 LLVM_FALLTHROUGH; 225 case CK_Nehalem: 226 setFeatureEnabledImpl(Features, "sse4.2", true); 227 LLVM_FALLTHROUGH; 228 case CK_Penryn: 229 setFeatureEnabledImpl(Features, "sse4.1", true); 230 LLVM_FALLTHROUGH; 231 case CK_Core2: 232 setFeatureEnabledImpl(Features, "ssse3", true); 233 setFeatureEnabledImpl(Features, "sahf", true); 234 LLVM_FALLTHROUGH; 235 case CK_Nocona: 236 setFeatureEnabledImpl(Features, "cx16", true); 237 LLVM_FALLTHROUGH; 238 case CK_Yonah: 239 case CK_Prescott: 240 setFeatureEnabledImpl(Features, "sse3", true); 241 LLVM_FALLTHROUGH; 242 case CK_PentiumM: 243 case CK_Pentium4: 244 case CK_x86_64: 245 setFeatureEnabledImpl(Features, "sse2", true); 246 LLVM_FALLTHROUGH; 247 case CK_Pentium3: 248 case CK_C3_2: 249 setFeatureEnabledImpl(Features, "sse", true); 250 LLVM_FALLTHROUGH; 251 case CK_Pentium2: 252 setFeatureEnabledImpl(Features, "fxsr", true); 253 LLVM_FALLTHROUGH; 254 case CK_PentiumMMX: 255 case CK_K6: 256 case CK_WinChipC6: 257 setFeatureEnabledImpl(Features, "mmx", true); 258 break; 259 260 case CK_Tremont: 261 setFeatureEnabledImpl(Features, "clwb", true); 262 setFeatureEnabledImpl(Features, "gfni", true); 263 LLVM_FALLTHROUGH; 264 case CK_GoldmontPlus: 265 setFeatureEnabledImpl(Features, "ptwrite", true); 266 setFeatureEnabledImpl(Features, "rdpid", true); 267 setFeatureEnabledImpl(Features, "sgx", true); 268 LLVM_FALLTHROUGH; 269 case CK_Goldmont: 270 setFeatureEnabledImpl(Features, "sha", true); 271 setFeatureEnabledImpl(Features, "rdseed", true); 272 setFeatureEnabledImpl(Features, "xsave", true); 273 setFeatureEnabledImpl(Features, "xsaveopt", true); 274 setFeatureEnabledImpl(Features, "xsavec", true); 275 setFeatureEnabledImpl(Features, "xsaves", true); 276 setFeatureEnabledImpl(Features, "clflushopt", true); 277 setFeatureEnabledImpl(Features, "fsgsbase", true); 278 setFeatureEnabledImpl(Features, "aes", true); 279 LLVM_FALLTHROUGH; 280 case CK_Silvermont: 281 setFeatureEnabledImpl(Features, "rdrnd", true); 282 setFeatureEnabledImpl(Features, "pclmul", true); 283 setFeatureEnabledImpl(Features, "sse4.2", true); 284 setFeatureEnabledImpl(Features, "prfchw", true); 285 LLVM_FALLTHROUGH; 286 case CK_Bonnell: 287 setFeatureEnabledImpl(Features, "movbe", true); 288 setFeatureEnabledImpl(Features, "ssse3", true); 289 setFeatureEnabledImpl(Features, "fxsr", true); 290 setFeatureEnabledImpl(Features, "cx16", true); 291 setFeatureEnabledImpl(Features, "sahf", true); 292 setFeatureEnabledImpl(Features, "mmx", true); 293 break; 294 295 case CK_KNM: 296 // TODO: Add avx5124fmaps/avx5124vnniw. 297 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 298 LLVM_FALLTHROUGH; 299 case CK_KNL: 300 setFeatureEnabledImpl(Features, "avx512f", true); 301 setFeatureEnabledImpl(Features, "avx512cd", true); 302 setFeatureEnabledImpl(Features, "avx512er", true); 303 setFeatureEnabledImpl(Features, "avx512pf", true); 304 setFeatureEnabledImpl(Features, "prfchw", true); 305 setFeatureEnabledImpl(Features, "prefetchwt1", true); 306 setFeatureEnabledImpl(Features, "fxsr", true); 307 setFeatureEnabledImpl(Features, "rdseed", true); 308 setFeatureEnabledImpl(Features, "adx", true); 309 setFeatureEnabledImpl(Features, "lzcnt", true); 310 setFeatureEnabledImpl(Features, "bmi", true); 311 setFeatureEnabledImpl(Features, "bmi2", true); 312 setFeatureEnabledImpl(Features, "fma", true); 313 setFeatureEnabledImpl(Features, "rdrnd", true); 314 setFeatureEnabledImpl(Features, "f16c", true); 315 setFeatureEnabledImpl(Features, "fsgsbase", true); 316 setFeatureEnabledImpl(Features, "aes", true); 317 setFeatureEnabledImpl(Features, "pclmul", true); 318 setFeatureEnabledImpl(Features, "cx16", true); 319 setFeatureEnabledImpl(Features, "xsaveopt", true); 320 setFeatureEnabledImpl(Features, "xsave", true); 321 setFeatureEnabledImpl(Features, "movbe", true); 322 setFeatureEnabledImpl(Features, "sahf", true); 323 setFeatureEnabledImpl(Features, "mmx", true); 324 break; 325 326 case CK_K6_2: 327 case CK_K6_3: 328 case CK_WinChip2: 329 case CK_C3: 330 setFeatureEnabledImpl(Features, "3dnow", true); 331 break; 332 333 case CK_AMDFAM10: 334 setFeatureEnabledImpl(Features, "sse4a", true); 335 setFeatureEnabledImpl(Features, "lzcnt", true); 336 setFeatureEnabledImpl(Features, "popcnt", true); 337 setFeatureEnabledImpl(Features, "sahf", true); 338 LLVM_FALLTHROUGH; 339 case CK_K8SSE3: 340 setFeatureEnabledImpl(Features, "sse3", true); 341 LLVM_FALLTHROUGH; 342 case CK_K8: 343 setFeatureEnabledImpl(Features, "sse2", true); 344 LLVM_FALLTHROUGH; 345 case CK_AthlonXP: 346 setFeatureEnabledImpl(Features, "sse", true); 347 setFeatureEnabledImpl(Features, "fxsr", true); 348 LLVM_FALLTHROUGH; 349 case CK_Athlon: 350 case CK_Geode: 351 setFeatureEnabledImpl(Features, "3dnowa", true); 352 break; 353 354 case CK_BTVER2: 355 setFeatureEnabledImpl(Features, "avx", true); 356 setFeatureEnabledImpl(Features, "aes", true); 357 setFeatureEnabledImpl(Features, "pclmul", true); 358 setFeatureEnabledImpl(Features, "bmi", true); 359 setFeatureEnabledImpl(Features, "f16c", true); 360 setFeatureEnabledImpl(Features, "xsaveopt", true); 361 setFeatureEnabledImpl(Features, "movbe", true); 362 LLVM_FALLTHROUGH; 363 case CK_BTVER1: 364 setFeatureEnabledImpl(Features, "ssse3", true); 365 setFeatureEnabledImpl(Features, "sse4a", true); 366 setFeatureEnabledImpl(Features, "lzcnt", true); 367 setFeatureEnabledImpl(Features, "popcnt", true); 368 setFeatureEnabledImpl(Features, "prfchw", true); 369 setFeatureEnabledImpl(Features, "cx16", true); 370 setFeatureEnabledImpl(Features, "fxsr", true); 371 setFeatureEnabledImpl(Features, "sahf", true); 372 setFeatureEnabledImpl(Features, "mmx", true); 373 break; 374 375 case CK_ZNVER2: 376 setFeatureEnabledImpl(Features, "clwb", true); 377 setFeatureEnabledImpl(Features, "rdpid", true); 378 setFeatureEnabledImpl(Features, "wbnoinvd", true); 379 LLVM_FALLTHROUGH; 380 case CK_ZNVER1: 381 setFeatureEnabledImpl(Features, "adx", true); 382 setFeatureEnabledImpl(Features, "aes", true); 383 setFeatureEnabledImpl(Features, "avx2", true); 384 setFeatureEnabledImpl(Features, "bmi", true); 385 setFeatureEnabledImpl(Features, "bmi2", true); 386 setFeatureEnabledImpl(Features, "clflushopt", true); 387 setFeatureEnabledImpl(Features, "clzero", true); 388 setFeatureEnabledImpl(Features, "cx16", true); 389 setFeatureEnabledImpl(Features, "f16c", true); 390 setFeatureEnabledImpl(Features, "fma", true); 391 setFeatureEnabledImpl(Features, "fsgsbase", true); 392 setFeatureEnabledImpl(Features, "fxsr", true); 393 setFeatureEnabledImpl(Features, "lzcnt", true); 394 setFeatureEnabledImpl(Features, "mmx", true); 395 setFeatureEnabledImpl(Features, "mwaitx", true); 396 setFeatureEnabledImpl(Features, "movbe", true); 397 setFeatureEnabledImpl(Features, "pclmul", true); 398 setFeatureEnabledImpl(Features, "popcnt", true); 399 setFeatureEnabledImpl(Features, "prfchw", true); 400 setFeatureEnabledImpl(Features, "rdrnd", true); 401 setFeatureEnabledImpl(Features, "rdseed", true); 402 setFeatureEnabledImpl(Features, "sahf", true); 403 setFeatureEnabledImpl(Features, "sha", true); 404 setFeatureEnabledImpl(Features, "sse4a", true); 405 setFeatureEnabledImpl(Features, "xsave", true); 406 setFeatureEnabledImpl(Features, "xsavec", true); 407 setFeatureEnabledImpl(Features, "xsaveopt", true); 408 setFeatureEnabledImpl(Features, "xsaves", true); 409 break; 410 411 case CK_BDVER4: 412 setFeatureEnabledImpl(Features, "avx2", true); 413 setFeatureEnabledImpl(Features, "bmi2", true); 414 setFeatureEnabledImpl(Features, "mwaitx", true); 415 LLVM_FALLTHROUGH; 416 case CK_BDVER3: 417 setFeatureEnabledImpl(Features, "fsgsbase", true); 418 setFeatureEnabledImpl(Features, "xsaveopt", true); 419 LLVM_FALLTHROUGH; 420 case CK_BDVER2: 421 setFeatureEnabledImpl(Features, "bmi", true); 422 setFeatureEnabledImpl(Features, "fma", true); 423 setFeatureEnabledImpl(Features, "f16c", true); 424 setFeatureEnabledImpl(Features, "tbm", true); 425 LLVM_FALLTHROUGH; 426 case CK_BDVER1: 427 // xop implies avx, sse4a and fma4. 428 setFeatureEnabledImpl(Features, "xop", true); 429 setFeatureEnabledImpl(Features, "lwp", true); 430 setFeatureEnabledImpl(Features, "lzcnt", true); 431 setFeatureEnabledImpl(Features, "aes", true); 432 setFeatureEnabledImpl(Features, "pclmul", true); 433 setFeatureEnabledImpl(Features, "prfchw", true); 434 setFeatureEnabledImpl(Features, "cx16", true); 435 setFeatureEnabledImpl(Features, "fxsr", true); 436 setFeatureEnabledImpl(Features, "xsave", true); 437 setFeatureEnabledImpl(Features, "sahf", true); 438 setFeatureEnabledImpl(Features, "mmx", true); 439 break; 440 } 441 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 442 return false; 443 444 // Can't do this earlier because we need to be able to explicitly enable 445 // or disable these features and the things that they depend upon. 446 447 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 448 auto I = Features.find("sse4.2"); 449 if (I != Features.end() && I->getValue() && 450 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 451 Features["popcnt"] = true; 452 453 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 454 I = Features.find("3dnow"); 455 if (I != Features.end() && I->getValue() && 456 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 457 Features["prfchw"] = true; 458 459 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 460 // then enable MMX. 461 I = Features.find("sse"); 462 if (I != Features.end() && I->getValue() && 463 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 464 Features["mmx"] = true; 465 466 return true; 467 } 468 469 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 470 X86SSEEnum Level, bool Enabled) { 471 if (Enabled) { 472 switch (Level) { 473 case AVX512F: 474 Features["avx512f"] = true; 475 Features["fma"] = true; 476 Features["f16c"] = true; 477 LLVM_FALLTHROUGH; 478 case AVX2: 479 Features["avx2"] = true; 480 LLVM_FALLTHROUGH; 481 case AVX: 482 Features["avx"] = true; 483 Features["xsave"] = true; 484 LLVM_FALLTHROUGH; 485 case SSE42: 486 Features["sse4.2"] = true; 487 LLVM_FALLTHROUGH; 488 case SSE41: 489 Features["sse4.1"] = true; 490 LLVM_FALLTHROUGH; 491 case SSSE3: 492 Features["ssse3"] = true; 493 LLVM_FALLTHROUGH; 494 case SSE3: 495 Features["sse3"] = true; 496 LLVM_FALLTHROUGH; 497 case SSE2: 498 Features["sse2"] = true; 499 LLVM_FALLTHROUGH; 500 case SSE1: 501 Features["sse"] = true; 502 LLVM_FALLTHROUGH; 503 case NoSSE: 504 break; 505 } 506 return; 507 } 508 509 switch (Level) { 510 case NoSSE: 511 case SSE1: 512 Features["sse"] = false; 513 LLVM_FALLTHROUGH; 514 case SSE2: 515 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 516 Features["sha"] = Features["gfni"] = false; 517 LLVM_FALLTHROUGH; 518 case SSE3: 519 Features["sse3"] = false; 520 setXOPLevel(Features, NoXOP, false); 521 LLVM_FALLTHROUGH; 522 case SSSE3: 523 Features["ssse3"] = false; 524 LLVM_FALLTHROUGH; 525 case SSE41: 526 Features["sse4.1"] = false; 527 LLVM_FALLTHROUGH; 528 case SSE42: 529 Features["sse4.2"] = false; 530 LLVM_FALLTHROUGH; 531 case AVX: 532 Features["fma"] = Features["avx"] = Features["f16c"] = false; 533 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 534 Features["vpclmulqdq"] = false; 535 setXOPLevel(Features, FMA4, false); 536 LLVM_FALLTHROUGH; 537 case AVX2: 538 Features["avx2"] = false; 539 LLVM_FALLTHROUGH; 540 case AVX512F: 541 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 542 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 543 Features["avx512vl"] = Features["avx512vbmi"] = false; 544 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 545 Features["avx512bitalg"] = Features["avx512vnni"] = false; 546 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 547 Features["avx512vp2intersect"] = false; 548 break; 549 } 550 } 551 552 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 553 MMX3DNowEnum Level, bool Enabled) { 554 if (Enabled) { 555 switch (Level) { 556 case AMD3DNowAthlon: 557 Features["3dnowa"] = true; 558 LLVM_FALLTHROUGH; 559 case AMD3DNow: 560 Features["3dnow"] = true; 561 LLVM_FALLTHROUGH; 562 case MMX: 563 Features["mmx"] = true; 564 LLVM_FALLTHROUGH; 565 case NoMMX3DNow: 566 break; 567 } 568 return; 569 } 570 571 switch (Level) { 572 case NoMMX3DNow: 573 case MMX: 574 Features["mmx"] = false; 575 LLVM_FALLTHROUGH; 576 case AMD3DNow: 577 Features["3dnow"] = false; 578 LLVM_FALLTHROUGH; 579 case AMD3DNowAthlon: 580 Features["3dnowa"] = false; 581 break; 582 } 583 } 584 585 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 586 bool Enabled) { 587 if (Enabled) { 588 switch (Level) { 589 case XOP: 590 Features["xop"] = true; 591 LLVM_FALLTHROUGH; 592 case FMA4: 593 Features["fma4"] = true; 594 setSSELevel(Features, AVX, true); 595 LLVM_FALLTHROUGH; 596 case SSE4A: 597 Features["sse4a"] = true; 598 setSSELevel(Features, SSE3, true); 599 LLVM_FALLTHROUGH; 600 case NoXOP: 601 break; 602 } 603 return; 604 } 605 606 switch (Level) { 607 case NoXOP: 608 case SSE4A: 609 Features["sse4a"] = false; 610 LLVM_FALLTHROUGH; 611 case FMA4: 612 Features["fma4"] = false; 613 LLVM_FALLTHROUGH; 614 case XOP: 615 Features["xop"] = false; 616 break; 617 } 618 } 619 620 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 621 StringRef Name, bool Enabled) { 622 // This is a bit of a hack to deal with the sse4 target feature when used 623 // as part of the target attribute. We handle sse4 correctly everywhere 624 // else. See below for more information on how we handle the sse4 options. 625 if (Name != "sse4") 626 Features[Name] = Enabled; 627 628 if (Name == "mmx") { 629 setMMXLevel(Features, MMX, Enabled); 630 } else if (Name == "sse") { 631 setSSELevel(Features, SSE1, Enabled); 632 } else if (Name == "sse2") { 633 setSSELevel(Features, SSE2, Enabled); 634 } else if (Name == "sse3") { 635 setSSELevel(Features, SSE3, Enabled); 636 } else if (Name == "ssse3") { 637 setSSELevel(Features, SSSE3, Enabled); 638 } else if (Name == "sse4.2") { 639 setSSELevel(Features, SSE42, Enabled); 640 } else if (Name == "sse4.1") { 641 setSSELevel(Features, SSE41, Enabled); 642 } else if (Name == "3dnow") { 643 setMMXLevel(Features, AMD3DNow, Enabled); 644 } else if (Name == "3dnowa") { 645 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 646 } else if (Name == "aes") { 647 if (Enabled) 648 setSSELevel(Features, SSE2, Enabled); 649 else 650 Features["vaes"] = false; 651 } else if (Name == "vaes") { 652 if (Enabled) { 653 setSSELevel(Features, AVX, Enabled); 654 Features["aes"] = true; 655 } 656 } else if (Name == "pclmul") { 657 if (Enabled) 658 setSSELevel(Features, SSE2, Enabled); 659 else 660 Features["vpclmulqdq"] = false; 661 } else if (Name == "vpclmulqdq") { 662 if (Enabled) { 663 setSSELevel(Features, AVX, Enabled); 664 Features["pclmul"] = true; 665 } 666 } else if (Name == "gfni") { 667 if (Enabled) 668 setSSELevel(Features, SSE2, Enabled); 669 } else if (Name == "avx") { 670 setSSELevel(Features, AVX, Enabled); 671 } else if (Name == "avx2") { 672 setSSELevel(Features, AVX2, Enabled); 673 } else if (Name == "avx512f") { 674 setSSELevel(Features, AVX512F, Enabled); 675 } else if (Name.startswith("avx512")) { 676 if (Enabled) 677 setSSELevel(Features, AVX512F, Enabled); 678 // Enable BWI instruction if certain features are being enabled. 679 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 680 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 681 Features["avx512bw"] = true; 682 // Also disable some features if BWI is being disabled. 683 if (Name == "avx512bw" && !Enabled) { 684 Features["avx512vbmi"] = false; 685 Features["avx512vbmi2"] = false; 686 Features["avx512bitalg"] = false; 687 Features["avx512bf16"] = false; 688 } 689 } else if (Name == "fma") { 690 if (Enabled) 691 setSSELevel(Features, AVX, Enabled); 692 else 693 setSSELevel(Features, AVX512F, Enabled); 694 } else if (Name == "fma4") { 695 setXOPLevel(Features, FMA4, Enabled); 696 } else if (Name == "xop") { 697 setXOPLevel(Features, XOP, Enabled); 698 } else if (Name == "sse4a") { 699 setXOPLevel(Features, SSE4A, Enabled); 700 } else if (Name == "f16c") { 701 if (Enabled) 702 setSSELevel(Features, AVX, Enabled); 703 else 704 setSSELevel(Features, AVX512F, Enabled); 705 } else if (Name == "sha") { 706 if (Enabled) 707 setSSELevel(Features, SSE2, Enabled); 708 } else if (Name == "sse4") { 709 // We can get here via the __target__ attribute since that's not controlled 710 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 711 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 712 // disabled. 713 if (Enabled) 714 setSSELevel(Features, SSE42, Enabled); 715 else 716 setSSELevel(Features, SSE41, Enabled); 717 } else if (Name == "xsave") { 718 if (!Enabled) 719 Features["xsaveopt"] = false; 720 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 721 if (Enabled) 722 Features["xsave"] = true; 723 } 724 } 725 726 /// handleTargetFeatures - Perform initialization based on the user 727 /// configured set of features. 728 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 729 DiagnosticsEngine &Diags) { 730 for (const auto &Feature : Features) { 731 if (Feature[0] != '+') 732 continue; 733 734 if (Feature == "+aes") { 735 HasAES = true; 736 } else if (Feature == "+vaes") { 737 HasVAES = true; 738 } else if (Feature == "+pclmul") { 739 HasPCLMUL = true; 740 } else if (Feature == "+vpclmulqdq") { 741 HasVPCLMULQDQ = true; 742 } else if (Feature == "+lzcnt") { 743 HasLZCNT = true; 744 } else if (Feature == "+rdrnd") { 745 HasRDRND = true; 746 } else if (Feature == "+fsgsbase") { 747 HasFSGSBASE = true; 748 } else if (Feature == "+bmi") { 749 HasBMI = true; 750 } else if (Feature == "+bmi2") { 751 HasBMI2 = true; 752 } else if (Feature == "+popcnt") { 753 HasPOPCNT = true; 754 } else if (Feature == "+rtm") { 755 HasRTM = true; 756 } else if (Feature == "+prfchw") { 757 HasPRFCHW = true; 758 } else if (Feature == "+rdseed") { 759 HasRDSEED = true; 760 } else if (Feature == "+adx") { 761 HasADX = true; 762 } else if (Feature == "+tbm") { 763 HasTBM = true; 764 } else if (Feature == "+lwp") { 765 HasLWP = true; 766 } else if (Feature == "+fma") { 767 HasFMA = true; 768 } else if (Feature == "+f16c") { 769 HasF16C = true; 770 } else if (Feature == "+gfni") { 771 HasGFNI = true; 772 } else if (Feature == "+avx512cd") { 773 HasAVX512CD = true; 774 } else if (Feature == "+avx512vpopcntdq") { 775 HasAVX512VPOPCNTDQ = true; 776 } else if (Feature == "+avx512vnni") { 777 HasAVX512VNNI = true; 778 } else if (Feature == "+avx512bf16") { 779 HasAVX512BF16 = true; 780 } else if (Feature == "+avx512er") { 781 HasAVX512ER = true; 782 } else if (Feature == "+avx512pf") { 783 HasAVX512PF = true; 784 } else if (Feature == "+avx512dq") { 785 HasAVX512DQ = true; 786 } else if (Feature == "+avx512bitalg") { 787 HasAVX512BITALG = true; 788 } else if (Feature == "+avx512bw") { 789 HasAVX512BW = true; 790 } else if (Feature == "+avx512vl") { 791 HasAVX512VL = true; 792 } else if (Feature == "+avx512vbmi") { 793 HasAVX512VBMI = true; 794 } else if (Feature == "+avx512vbmi2") { 795 HasAVX512VBMI2 = true; 796 } else if (Feature == "+avx512ifma") { 797 HasAVX512IFMA = true; 798 } else if (Feature == "+avx512vp2intersect") { 799 HasAVX512VP2INTERSECT = true; 800 } else if (Feature == "+sha") { 801 HasSHA = true; 802 } else if (Feature == "+shstk") { 803 HasSHSTK = true; 804 } else if (Feature == "+movbe") { 805 HasMOVBE = true; 806 } else if (Feature == "+sgx") { 807 HasSGX = true; 808 } else if (Feature == "+cx8") { 809 HasCX8 = true; 810 } else if (Feature == "+cx16") { 811 HasCX16 = true; 812 } else if (Feature == "+fxsr") { 813 HasFXSR = true; 814 } else if (Feature == "+xsave") { 815 HasXSAVE = true; 816 } else if (Feature == "+xsaveopt") { 817 HasXSAVEOPT = true; 818 } else if (Feature == "+xsavec") { 819 HasXSAVEC = true; 820 } else if (Feature == "+xsaves") { 821 HasXSAVES = true; 822 } else if (Feature == "+mwaitx") { 823 HasMWAITX = true; 824 } else if (Feature == "+pku") { 825 HasPKU = true; 826 } else if (Feature == "+clflushopt") { 827 HasCLFLUSHOPT = true; 828 } else if (Feature == "+clwb") { 829 HasCLWB = true; 830 } else if (Feature == "+wbnoinvd") { 831 HasWBNOINVD = true; 832 } else if (Feature == "+prefetchwt1") { 833 HasPREFETCHWT1 = true; 834 } else if (Feature == "+clzero") { 835 HasCLZERO = true; 836 } else if (Feature == "+cldemote") { 837 HasCLDEMOTE = true; 838 } else if (Feature == "+rdpid") { 839 HasRDPID = true; 840 } else if (Feature == "+retpoline-external-thunk") { 841 HasRetpolineExternalThunk = true; 842 } else if (Feature == "+sahf") { 843 HasLAHFSAHF = true; 844 } else if (Feature == "+waitpkg") { 845 HasWAITPKG = true; 846 } else if (Feature == "+movdiri") { 847 HasMOVDIRI = true; 848 } else if (Feature == "+movdir64b") { 849 HasMOVDIR64B = true; 850 } else if (Feature == "+pconfig") { 851 HasPCONFIG = true; 852 } else if (Feature == "+ptwrite") { 853 HasPTWRITE = true; 854 } else if (Feature == "+invpcid") { 855 HasINVPCID = true; 856 } else if (Feature == "+enqcmd") { 857 HasENQCMD = true; 858 } else if (Feature == "+serialize") { 859 HasSERIALIZE = true; 860 } else if (Feature == "+tsxldtrk") { 861 HasTSXLDTRK = true; 862 } 863 864 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 865 .Case("+avx512f", AVX512F) 866 .Case("+avx2", AVX2) 867 .Case("+avx", AVX) 868 .Case("+sse4.2", SSE42) 869 .Case("+sse4.1", SSE41) 870 .Case("+ssse3", SSSE3) 871 .Case("+sse3", SSE3) 872 .Case("+sse2", SSE2) 873 .Case("+sse", SSE1) 874 .Default(NoSSE); 875 SSELevel = std::max(SSELevel, Level); 876 877 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 878 .Case("+3dnowa", AMD3DNowAthlon) 879 .Case("+3dnow", AMD3DNow) 880 .Case("+mmx", MMX) 881 .Default(NoMMX3DNow); 882 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 883 884 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 885 .Case("+xop", XOP) 886 .Case("+fma4", FMA4) 887 .Case("+sse4a", SSE4A) 888 .Default(NoXOP); 889 XOPLevel = std::max(XOPLevel, XLevel); 890 } 891 892 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 893 // matches the selected sse level. 894 if ((FPMath == FP_SSE && SSELevel < SSE1) || 895 (FPMath == FP_387 && SSELevel >= SSE1)) { 896 Diags.Report(diag::err_target_unsupported_fpmath) 897 << (FPMath == FP_SSE ? "sse" : "387"); 898 return false; 899 } 900 901 SimdDefaultAlign = 902 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 903 return true; 904 } 905 906 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 907 /// definitions for this particular subtarget. 908 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 909 MacroBuilder &Builder) const { 910 // Inline assembly supports X86 flag outputs. 911 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 912 913 std::string CodeModel = getTargetOpts().CodeModel; 914 if (CodeModel == "default") 915 CodeModel = "small"; 916 Builder.defineMacro("__code_model_" + CodeModel + "__"); 917 918 // Target identification. 919 if (getTriple().getArch() == llvm::Triple::x86_64) { 920 Builder.defineMacro("__amd64__"); 921 Builder.defineMacro("__amd64"); 922 Builder.defineMacro("__x86_64"); 923 Builder.defineMacro("__x86_64__"); 924 if (getTriple().getArchName() == "x86_64h") { 925 Builder.defineMacro("__x86_64h"); 926 Builder.defineMacro("__x86_64h__"); 927 } 928 } else { 929 DefineStd(Builder, "i386", Opts); 930 } 931 932 Builder.defineMacro("__SEG_GS"); 933 Builder.defineMacro("__SEG_FS"); 934 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 935 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 936 937 // Subtarget options. 938 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 939 // truly should be based on -mtune options. 940 using namespace llvm::X86; 941 switch (CPU) { 942 case CK_None: 943 break; 944 case CK_i386: 945 // The rest are coming from the i386 define above. 946 Builder.defineMacro("__tune_i386__"); 947 break; 948 case CK_i486: 949 case CK_WinChipC6: 950 case CK_WinChip2: 951 case CK_C3: 952 defineCPUMacros(Builder, "i486"); 953 break; 954 case CK_PentiumMMX: 955 Builder.defineMacro("__pentium_mmx__"); 956 Builder.defineMacro("__tune_pentium_mmx__"); 957 LLVM_FALLTHROUGH; 958 case CK_i586: 959 case CK_Pentium: 960 defineCPUMacros(Builder, "i586"); 961 defineCPUMacros(Builder, "pentium"); 962 break; 963 case CK_Pentium3: 964 case CK_PentiumM: 965 Builder.defineMacro("__tune_pentium3__"); 966 LLVM_FALLTHROUGH; 967 case CK_Pentium2: 968 case CK_C3_2: 969 Builder.defineMacro("__tune_pentium2__"); 970 LLVM_FALLTHROUGH; 971 case CK_PentiumPro: 972 case CK_i686: 973 defineCPUMacros(Builder, "i686"); 974 defineCPUMacros(Builder, "pentiumpro"); 975 break; 976 case CK_Pentium4: 977 defineCPUMacros(Builder, "pentium4"); 978 break; 979 case CK_Yonah: 980 case CK_Prescott: 981 case CK_Nocona: 982 defineCPUMacros(Builder, "nocona"); 983 break; 984 case CK_Core2: 985 case CK_Penryn: 986 defineCPUMacros(Builder, "core2"); 987 break; 988 case CK_Bonnell: 989 defineCPUMacros(Builder, "atom"); 990 break; 991 case CK_Silvermont: 992 defineCPUMacros(Builder, "slm"); 993 break; 994 case CK_Goldmont: 995 defineCPUMacros(Builder, "goldmont"); 996 break; 997 case CK_GoldmontPlus: 998 defineCPUMacros(Builder, "goldmont_plus"); 999 break; 1000 case CK_Tremont: 1001 defineCPUMacros(Builder, "tremont"); 1002 break; 1003 case CK_Nehalem: 1004 case CK_Westmere: 1005 case CK_SandyBridge: 1006 case CK_IvyBridge: 1007 case CK_Haswell: 1008 case CK_Broadwell: 1009 case CK_SkylakeClient: 1010 case CK_SkylakeServer: 1011 case CK_Cascadelake: 1012 case CK_Cooperlake: 1013 case CK_Cannonlake: 1014 case CK_IcelakeClient: 1015 case CK_IcelakeServer: 1016 case CK_Tigerlake: 1017 // FIXME: Historically, we defined this legacy name, it would be nice to 1018 // remove it at some point. We've never exposed fine-grained names for 1019 // recent primary x86 CPUs, and we should keep it that way. 1020 defineCPUMacros(Builder, "corei7"); 1021 break; 1022 case CK_KNL: 1023 defineCPUMacros(Builder, "knl"); 1024 break; 1025 case CK_KNM: 1026 break; 1027 case CK_Lakemont: 1028 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1029 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1030 Builder.defineMacro("__tune_lakemont__"); 1031 break; 1032 case CK_K6_2: 1033 Builder.defineMacro("__k6_2__"); 1034 Builder.defineMacro("__tune_k6_2__"); 1035 LLVM_FALLTHROUGH; 1036 case CK_K6_3: 1037 if (CPU != CK_K6_2) { // In case of fallthrough 1038 // FIXME: GCC may be enabling these in cases where some other k6 1039 // architecture is specified but -m3dnow is explicitly provided. The 1040 // exact semantics need to be determined and emulated here. 1041 Builder.defineMacro("__k6_3__"); 1042 Builder.defineMacro("__tune_k6_3__"); 1043 } 1044 LLVM_FALLTHROUGH; 1045 case CK_K6: 1046 defineCPUMacros(Builder, "k6"); 1047 break; 1048 case CK_Athlon: 1049 case CK_AthlonXP: 1050 defineCPUMacros(Builder, "athlon"); 1051 if (SSELevel != NoSSE) { 1052 Builder.defineMacro("__athlon_sse__"); 1053 Builder.defineMacro("__tune_athlon_sse__"); 1054 } 1055 break; 1056 case CK_K8: 1057 case CK_K8SSE3: 1058 case CK_x86_64: 1059 defineCPUMacros(Builder, "k8"); 1060 break; 1061 case CK_AMDFAM10: 1062 defineCPUMacros(Builder, "amdfam10"); 1063 break; 1064 case CK_BTVER1: 1065 defineCPUMacros(Builder, "btver1"); 1066 break; 1067 case CK_BTVER2: 1068 defineCPUMacros(Builder, "btver2"); 1069 break; 1070 case CK_BDVER1: 1071 defineCPUMacros(Builder, "bdver1"); 1072 break; 1073 case CK_BDVER2: 1074 defineCPUMacros(Builder, "bdver2"); 1075 break; 1076 case CK_BDVER3: 1077 defineCPUMacros(Builder, "bdver3"); 1078 break; 1079 case CK_BDVER4: 1080 defineCPUMacros(Builder, "bdver4"); 1081 break; 1082 case CK_ZNVER1: 1083 defineCPUMacros(Builder, "znver1"); 1084 break; 1085 case CK_ZNVER2: 1086 defineCPUMacros(Builder, "znver2"); 1087 break; 1088 case CK_Geode: 1089 defineCPUMacros(Builder, "geode"); 1090 break; 1091 } 1092 1093 // Target properties. 1094 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1095 1096 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1097 // functions in glibc header files that use FP Stack inline asm which the 1098 // backend can't deal with (PR879). 1099 Builder.defineMacro("__NO_MATH_INLINES"); 1100 1101 if (HasAES) 1102 Builder.defineMacro("__AES__"); 1103 1104 if (HasVAES) 1105 Builder.defineMacro("__VAES__"); 1106 1107 if (HasPCLMUL) 1108 Builder.defineMacro("__PCLMUL__"); 1109 1110 if (HasVPCLMULQDQ) 1111 Builder.defineMacro("__VPCLMULQDQ__"); 1112 1113 if (HasLZCNT) 1114 Builder.defineMacro("__LZCNT__"); 1115 1116 if (HasRDRND) 1117 Builder.defineMacro("__RDRND__"); 1118 1119 if (HasFSGSBASE) 1120 Builder.defineMacro("__FSGSBASE__"); 1121 1122 if (HasBMI) 1123 Builder.defineMacro("__BMI__"); 1124 1125 if (HasBMI2) 1126 Builder.defineMacro("__BMI2__"); 1127 1128 if (HasPOPCNT) 1129 Builder.defineMacro("__POPCNT__"); 1130 1131 if (HasRTM) 1132 Builder.defineMacro("__RTM__"); 1133 1134 if (HasPRFCHW) 1135 Builder.defineMacro("__PRFCHW__"); 1136 1137 if (HasRDSEED) 1138 Builder.defineMacro("__RDSEED__"); 1139 1140 if (HasADX) 1141 Builder.defineMacro("__ADX__"); 1142 1143 if (HasTBM) 1144 Builder.defineMacro("__TBM__"); 1145 1146 if (HasLWP) 1147 Builder.defineMacro("__LWP__"); 1148 1149 if (HasMWAITX) 1150 Builder.defineMacro("__MWAITX__"); 1151 1152 if (HasMOVBE) 1153 Builder.defineMacro("__MOVBE__"); 1154 1155 switch (XOPLevel) { 1156 case XOP: 1157 Builder.defineMacro("__XOP__"); 1158 LLVM_FALLTHROUGH; 1159 case FMA4: 1160 Builder.defineMacro("__FMA4__"); 1161 LLVM_FALLTHROUGH; 1162 case SSE4A: 1163 Builder.defineMacro("__SSE4A__"); 1164 LLVM_FALLTHROUGH; 1165 case NoXOP: 1166 break; 1167 } 1168 1169 if (HasFMA) 1170 Builder.defineMacro("__FMA__"); 1171 1172 if (HasF16C) 1173 Builder.defineMacro("__F16C__"); 1174 1175 if (HasGFNI) 1176 Builder.defineMacro("__GFNI__"); 1177 1178 if (HasAVX512CD) 1179 Builder.defineMacro("__AVX512CD__"); 1180 if (HasAVX512VPOPCNTDQ) 1181 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1182 if (HasAVX512VNNI) 1183 Builder.defineMacro("__AVX512VNNI__"); 1184 if (HasAVX512BF16) 1185 Builder.defineMacro("__AVX512BF16__"); 1186 if (HasAVX512ER) 1187 Builder.defineMacro("__AVX512ER__"); 1188 if (HasAVX512PF) 1189 Builder.defineMacro("__AVX512PF__"); 1190 if (HasAVX512DQ) 1191 Builder.defineMacro("__AVX512DQ__"); 1192 if (HasAVX512BITALG) 1193 Builder.defineMacro("__AVX512BITALG__"); 1194 if (HasAVX512BW) 1195 Builder.defineMacro("__AVX512BW__"); 1196 if (HasAVX512VL) 1197 Builder.defineMacro("__AVX512VL__"); 1198 if (HasAVX512VBMI) 1199 Builder.defineMacro("__AVX512VBMI__"); 1200 if (HasAVX512VBMI2) 1201 Builder.defineMacro("__AVX512VBMI2__"); 1202 if (HasAVX512IFMA) 1203 Builder.defineMacro("__AVX512IFMA__"); 1204 if (HasAVX512VP2INTERSECT) 1205 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1206 if (HasSHA) 1207 Builder.defineMacro("__SHA__"); 1208 1209 if (HasFXSR) 1210 Builder.defineMacro("__FXSR__"); 1211 if (HasXSAVE) 1212 Builder.defineMacro("__XSAVE__"); 1213 if (HasXSAVEOPT) 1214 Builder.defineMacro("__XSAVEOPT__"); 1215 if (HasXSAVEC) 1216 Builder.defineMacro("__XSAVEC__"); 1217 if (HasXSAVES) 1218 Builder.defineMacro("__XSAVES__"); 1219 if (HasPKU) 1220 Builder.defineMacro("__PKU__"); 1221 if (HasCLFLUSHOPT) 1222 Builder.defineMacro("__CLFLUSHOPT__"); 1223 if (HasCLWB) 1224 Builder.defineMacro("__CLWB__"); 1225 if (HasWBNOINVD) 1226 Builder.defineMacro("__WBNOINVD__"); 1227 if (HasSHSTK) 1228 Builder.defineMacro("__SHSTK__"); 1229 if (HasSGX) 1230 Builder.defineMacro("__SGX__"); 1231 if (HasPREFETCHWT1) 1232 Builder.defineMacro("__PREFETCHWT1__"); 1233 if (HasCLZERO) 1234 Builder.defineMacro("__CLZERO__"); 1235 if (HasRDPID) 1236 Builder.defineMacro("__RDPID__"); 1237 if (HasCLDEMOTE) 1238 Builder.defineMacro("__CLDEMOTE__"); 1239 if (HasWAITPKG) 1240 Builder.defineMacro("__WAITPKG__"); 1241 if (HasMOVDIRI) 1242 Builder.defineMacro("__MOVDIRI__"); 1243 if (HasMOVDIR64B) 1244 Builder.defineMacro("__MOVDIR64B__"); 1245 if (HasPCONFIG) 1246 Builder.defineMacro("__PCONFIG__"); 1247 if (HasPTWRITE) 1248 Builder.defineMacro("__PTWRITE__"); 1249 if (HasINVPCID) 1250 Builder.defineMacro("__INVPCID__"); 1251 if (HasENQCMD) 1252 Builder.defineMacro("__ENQCMD__"); 1253 if (HasSERIALIZE) 1254 Builder.defineMacro("__SERIALIZE__"); 1255 if (HasTSXLDTRK) 1256 Builder.defineMacro("__TSXLDTRK__"); 1257 1258 // Each case falls through to the previous one here. 1259 switch (SSELevel) { 1260 case AVX512F: 1261 Builder.defineMacro("__AVX512F__"); 1262 LLVM_FALLTHROUGH; 1263 case AVX2: 1264 Builder.defineMacro("__AVX2__"); 1265 LLVM_FALLTHROUGH; 1266 case AVX: 1267 Builder.defineMacro("__AVX__"); 1268 LLVM_FALLTHROUGH; 1269 case SSE42: 1270 Builder.defineMacro("__SSE4_2__"); 1271 LLVM_FALLTHROUGH; 1272 case SSE41: 1273 Builder.defineMacro("__SSE4_1__"); 1274 LLVM_FALLTHROUGH; 1275 case SSSE3: 1276 Builder.defineMacro("__SSSE3__"); 1277 LLVM_FALLTHROUGH; 1278 case SSE3: 1279 Builder.defineMacro("__SSE3__"); 1280 LLVM_FALLTHROUGH; 1281 case SSE2: 1282 Builder.defineMacro("__SSE2__"); 1283 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1284 LLVM_FALLTHROUGH; 1285 case SSE1: 1286 Builder.defineMacro("__SSE__"); 1287 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1288 LLVM_FALLTHROUGH; 1289 case NoSSE: 1290 break; 1291 } 1292 1293 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1294 switch (SSELevel) { 1295 case AVX512F: 1296 case AVX2: 1297 case AVX: 1298 case SSE42: 1299 case SSE41: 1300 case SSSE3: 1301 case SSE3: 1302 case SSE2: 1303 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1304 break; 1305 case SSE1: 1306 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1307 break; 1308 default: 1309 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1310 break; 1311 } 1312 } 1313 1314 // Each case falls through to the previous one here. 1315 switch (MMX3DNowLevel) { 1316 case AMD3DNowAthlon: 1317 Builder.defineMacro("__3dNOW_A__"); 1318 LLVM_FALLTHROUGH; 1319 case AMD3DNow: 1320 Builder.defineMacro("__3dNOW__"); 1321 LLVM_FALLTHROUGH; 1322 case MMX: 1323 Builder.defineMacro("__MMX__"); 1324 LLVM_FALLTHROUGH; 1325 case NoMMX3DNow: 1326 break; 1327 } 1328 1329 if (CPU >= CK_i486 || CPU == CK_None) { 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1333 } 1334 if (HasCX8) 1335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1336 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1337 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1338 1339 if (HasFloat128) 1340 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1341 } 1342 1343 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1344 return llvm::StringSwitch<bool>(Name) 1345 .Case("3dnow", true) 1346 .Case("3dnowa", true) 1347 .Case("adx", true) 1348 .Case("aes", true) 1349 .Case("avx", true) 1350 .Case("avx2", true) 1351 .Case("avx512f", true) 1352 .Case("avx512cd", true) 1353 .Case("avx512vpopcntdq", true) 1354 .Case("avx512vnni", true) 1355 .Case("avx512bf16", true) 1356 .Case("avx512er", true) 1357 .Case("avx512pf", true) 1358 .Case("avx512dq", true) 1359 .Case("avx512bitalg", true) 1360 .Case("avx512bw", true) 1361 .Case("avx512vl", true) 1362 .Case("avx512vbmi", true) 1363 .Case("avx512vbmi2", true) 1364 .Case("avx512ifma", true) 1365 .Case("avx512vp2intersect", true) 1366 .Case("bmi", true) 1367 .Case("bmi2", true) 1368 .Case("cldemote", true) 1369 .Case("clflushopt", true) 1370 .Case("clwb", true) 1371 .Case("clzero", true) 1372 .Case("cx16", true) 1373 .Case("enqcmd", true) 1374 .Case("f16c", true) 1375 .Case("fma", true) 1376 .Case("fma4", true) 1377 .Case("fsgsbase", true) 1378 .Case("fxsr", true) 1379 .Case("gfni", true) 1380 .Case("invpcid", true) 1381 .Case("lwp", true) 1382 .Case("lzcnt", true) 1383 .Case("mmx", true) 1384 .Case("movbe", true) 1385 .Case("movdiri", true) 1386 .Case("movdir64b", true) 1387 .Case("mwaitx", true) 1388 .Case("pclmul", true) 1389 .Case("pconfig", true) 1390 .Case("pku", true) 1391 .Case("popcnt", true) 1392 .Case("prefetchwt1", true) 1393 .Case("prfchw", true) 1394 .Case("ptwrite", true) 1395 .Case("rdpid", true) 1396 .Case("rdrnd", true) 1397 .Case("rdseed", true) 1398 .Case("rtm", true) 1399 .Case("sahf", true) 1400 .Case("serialize", true) 1401 .Case("sgx", true) 1402 .Case("sha", true) 1403 .Case("shstk", true) 1404 .Case("sse", true) 1405 .Case("sse2", true) 1406 .Case("sse3", true) 1407 .Case("ssse3", true) 1408 .Case("sse4", true) 1409 .Case("sse4.1", true) 1410 .Case("sse4.2", true) 1411 .Case("sse4a", true) 1412 .Case("tbm", true) 1413 .Case("tsxldtrk", true) 1414 .Case("vaes", true) 1415 .Case("vpclmulqdq", true) 1416 .Case("wbnoinvd", true) 1417 .Case("waitpkg", true) 1418 .Case("x87", true) 1419 .Case("xop", true) 1420 .Case("xsave", true) 1421 .Case("xsavec", true) 1422 .Case("xsaves", true) 1423 .Case("xsaveopt", true) 1424 .Default(false); 1425 } 1426 1427 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1428 return llvm::StringSwitch<bool>(Feature) 1429 .Case("adx", HasADX) 1430 .Case("aes", HasAES) 1431 .Case("avx", SSELevel >= AVX) 1432 .Case("avx2", SSELevel >= AVX2) 1433 .Case("avx512f", SSELevel >= AVX512F) 1434 .Case("avx512cd", HasAVX512CD) 1435 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1436 .Case("avx512vnni", HasAVX512VNNI) 1437 .Case("avx512bf16", HasAVX512BF16) 1438 .Case("avx512er", HasAVX512ER) 1439 .Case("avx512pf", HasAVX512PF) 1440 .Case("avx512dq", HasAVX512DQ) 1441 .Case("avx512bitalg", HasAVX512BITALG) 1442 .Case("avx512bw", HasAVX512BW) 1443 .Case("avx512vl", HasAVX512VL) 1444 .Case("avx512vbmi", HasAVX512VBMI) 1445 .Case("avx512vbmi2", HasAVX512VBMI2) 1446 .Case("avx512ifma", HasAVX512IFMA) 1447 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1448 .Case("bmi", HasBMI) 1449 .Case("bmi2", HasBMI2) 1450 .Case("cldemote", HasCLDEMOTE) 1451 .Case("clflushopt", HasCLFLUSHOPT) 1452 .Case("clwb", HasCLWB) 1453 .Case("clzero", HasCLZERO) 1454 .Case("cx8", HasCX8) 1455 .Case("cx16", HasCX16) 1456 .Case("enqcmd", HasENQCMD) 1457 .Case("f16c", HasF16C) 1458 .Case("fma", HasFMA) 1459 .Case("fma4", XOPLevel >= FMA4) 1460 .Case("fsgsbase", HasFSGSBASE) 1461 .Case("fxsr", HasFXSR) 1462 .Case("gfni", HasGFNI) 1463 .Case("invpcid", HasINVPCID) 1464 .Case("lwp", HasLWP) 1465 .Case("lzcnt", HasLZCNT) 1466 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1467 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1468 .Case("mmx", MMX3DNowLevel >= MMX) 1469 .Case("movbe", HasMOVBE) 1470 .Case("movdiri", HasMOVDIRI) 1471 .Case("movdir64b", HasMOVDIR64B) 1472 .Case("mwaitx", HasMWAITX) 1473 .Case("pclmul", HasPCLMUL) 1474 .Case("pconfig", HasPCONFIG) 1475 .Case("pku", HasPKU) 1476 .Case("popcnt", HasPOPCNT) 1477 .Case("prefetchwt1", HasPREFETCHWT1) 1478 .Case("prfchw", HasPRFCHW) 1479 .Case("ptwrite", HasPTWRITE) 1480 .Case("rdpid", HasRDPID) 1481 .Case("rdrnd", HasRDRND) 1482 .Case("rdseed", HasRDSEED) 1483 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1484 .Case("rtm", HasRTM) 1485 .Case("sahf", HasLAHFSAHF) 1486 .Case("serialize", HasSERIALIZE) 1487 .Case("sgx", HasSGX) 1488 .Case("sha", HasSHA) 1489 .Case("shstk", HasSHSTK) 1490 .Case("sse", SSELevel >= SSE1) 1491 .Case("sse2", SSELevel >= SSE2) 1492 .Case("sse3", SSELevel >= SSE3) 1493 .Case("ssse3", SSELevel >= SSSE3) 1494 .Case("sse4.1", SSELevel >= SSE41) 1495 .Case("sse4.2", SSELevel >= SSE42) 1496 .Case("sse4a", XOPLevel >= SSE4A) 1497 .Case("tbm", HasTBM) 1498 .Case("tsxldtrk", HasTSXLDTRK) 1499 .Case("vaes", HasVAES) 1500 .Case("vpclmulqdq", HasVPCLMULQDQ) 1501 .Case("wbnoinvd", HasWBNOINVD) 1502 .Case("waitpkg", HasWAITPKG) 1503 .Case("x86", true) 1504 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1505 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1506 .Case("xop", XOPLevel >= XOP) 1507 .Case("xsave", HasXSAVE) 1508 .Case("xsavec", HasXSAVEC) 1509 .Case("xsaves", HasXSAVES) 1510 .Case("xsaveopt", HasXSAVEOPT) 1511 .Default(false); 1512 } 1513 1514 // We can't use a generic validation scheme for the features accepted here 1515 // versus subtarget features accepted in the target attribute because the 1516 // bitfield structure that's initialized in the runtime only supports the 1517 // below currently rather than the full range of subtarget features. (See 1518 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1519 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1520 return llvm::StringSwitch<bool>(FeatureStr) 1521 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1522 #include "llvm/Support/X86TargetParser.def" 1523 .Default(false); 1524 } 1525 1526 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1527 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1528 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1529 #include "llvm/Support/X86TargetParser.def" 1530 ; 1531 // Note, this function should only be used after ensuring the value is 1532 // correct, so it asserts if the value is out of range. 1533 } 1534 1535 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1536 enum class FeatPriority { 1537 #define FEATURE(FEAT) FEAT, 1538 #include "clang/Basic/X86Target.def" 1539 }; 1540 switch (Feat) { 1541 #define FEATURE(FEAT) \ 1542 case llvm::X86::FEAT: \ 1543 return static_cast<unsigned>(FeatPriority::FEAT); 1544 #include "clang/Basic/X86Target.def" 1545 default: 1546 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1547 } 1548 } 1549 1550 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1551 // Valid CPUs have a 'key feature' that compares just better than its key 1552 // feature. 1553 using namespace llvm::X86; 1554 CPUKind Kind = parseArchX86(Name); 1555 if (Kind != CK_None) { 1556 switch (Kind) { 1557 default: 1558 llvm_unreachable( 1559 "CPU Type without a key feature used in 'target' attribute"); 1560 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1561 case CK_##ENUM: \ 1562 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1563 #include "llvm/Support/X86TargetParser.def" 1564 } 1565 } 1566 1567 // Now we know we have a feature, so get its priority and shift it a few so 1568 // that we have sufficient room for the CPUs (above). 1569 return getFeaturePriority(getFeature(Name)) << 1; 1570 } 1571 1572 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1573 return llvm::StringSwitch<bool>(Name) 1574 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1575 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1576 #include "clang/Basic/X86Target.def" 1577 .Default(false); 1578 } 1579 1580 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1581 return llvm::StringSwitch<StringRef>(Name) 1582 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1583 #include "clang/Basic/X86Target.def" 1584 .Default(Name); 1585 } 1586 1587 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1588 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1589 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1590 #include "clang/Basic/X86Target.def" 1591 .Default(0); 1592 } 1593 1594 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1595 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1596 StringRef WholeList = 1597 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1598 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1599 #include "clang/Basic/X86Target.def" 1600 .Default(""); 1601 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1602 } 1603 1604 // We can't use a generic validation scheme for the cpus accepted here 1605 // versus subtarget cpus accepted in the target attribute because the 1606 // variables intitialized by the runtime only support the below currently 1607 // rather than the full range of cpus. 1608 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1609 return llvm::StringSwitch<bool>(FeatureStr) 1610 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1611 #define X86_CPU_TYPE_COMPAT_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1612 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1613 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1614 #include "llvm/Support/X86TargetParser.def" 1615 .Default(false); 1616 } 1617 1618 static unsigned matchAsmCCConstraint(const char *&Name) { 1619 auto RV = llvm::StringSwitch<unsigned>(Name) 1620 .Case("@cca", 4) 1621 .Case("@ccae", 5) 1622 .Case("@ccb", 4) 1623 .Case("@ccbe", 5) 1624 .Case("@ccc", 4) 1625 .Case("@cce", 4) 1626 .Case("@ccz", 4) 1627 .Case("@ccg", 4) 1628 .Case("@ccge", 5) 1629 .Case("@ccl", 4) 1630 .Case("@ccle", 5) 1631 .Case("@ccna", 5) 1632 .Case("@ccnae", 6) 1633 .Case("@ccnb", 5) 1634 .Case("@ccnbe", 6) 1635 .Case("@ccnc", 5) 1636 .Case("@ccne", 5) 1637 .Case("@ccnz", 5) 1638 .Case("@ccng", 5) 1639 .Case("@ccnge", 6) 1640 .Case("@ccnl", 5) 1641 .Case("@ccnle", 6) 1642 .Case("@ccno", 5) 1643 .Case("@ccnp", 5) 1644 .Case("@ccns", 5) 1645 .Case("@cco", 4) 1646 .Case("@ccp", 4) 1647 .Case("@ccs", 4) 1648 .Default(0); 1649 return RV; 1650 } 1651 1652 bool X86TargetInfo::validateAsmConstraint( 1653 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1654 switch (*Name) { 1655 default: 1656 return false; 1657 // Constant constraints. 1658 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1659 // instructions. 1660 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1661 // x86_64 instructions. 1662 case 's': 1663 Info.setRequiresImmediate(); 1664 return true; 1665 case 'I': 1666 Info.setRequiresImmediate(0, 31); 1667 return true; 1668 case 'J': 1669 Info.setRequiresImmediate(0, 63); 1670 return true; 1671 case 'K': 1672 Info.setRequiresImmediate(-128, 127); 1673 return true; 1674 case 'L': 1675 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1676 return true; 1677 case 'M': 1678 Info.setRequiresImmediate(0, 3); 1679 return true; 1680 case 'N': 1681 Info.setRequiresImmediate(0, 255); 1682 return true; 1683 case 'O': 1684 Info.setRequiresImmediate(0, 127); 1685 return true; 1686 // Register constraints. 1687 case 'Y': // 'Y' is the first character for several 2-character constraints. 1688 // Shift the pointer to the second character of the constraint. 1689 Name++; 1690 switch (*Name) { 1691 default: 1692 return false; 1693 case 'z': // First SSE register. 1694 case '2': 1695 case 't': // Any SSE register, when SSE2 is enabled. 1696 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1697 case 'm': // Any MMX register, when inter-unit moves enabled. 1698 case 'k': // AVX512 arch mask registers: k1-k7. 1699 Info.setAllowsRegister(); 1700 return true; 1701 } 1702 case 'f': // Any x87 floating point stack register. 1703 // Constraint 'f' cannot be used for output operands. 1704 if (Info.ConstraintStr[0] == '=') 1705 return false; 1706 Info.setAllowsRegister(); 1707 return true; 1708 case 'a': // eax. 1709 case 'b': // ebx. 1710 case 'c': // ecx. 1711 case 'd': // edx. 1712 case 'S': // esi. 1713 case 'D': // edi. 1714 case 'A': // edx:eax. 1715 case 't': // Top of floating point stack. 1716 case 'u': // Second from top of floating point stack. 1717 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1718 case 'y': // Any MMX register. 1719 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1720 case 'x': // Any SSE register. 1721 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1722 // for intermideate k reg operations). 1723 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1724 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1725 case 'l': // "Index" registers: any general register that can be used as an 1726 // index in a base+index memory access. 1727 Info.setAllowsRegister(); 1728 return true; 1729 // Floating point constant constraints. 1730 case 'C': // SSE floating point constant. 1731 case 'G': // x87 floating point constant. 1732 return true; 1733 case '@': 1734 // CC condition changes. 1735 if (auto Len = matchAsmCCConstraint(Name)) { 1736 Name += Len - 1; 1737 Info.setAllowsRegister(); 1738 return true; 1739 } 1740 return false; 1741 } 1742 } 1743 1744 // Below is based on the following information: 1745 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1746 // | Processor Name | Cache Line Size (Bytes) | Source | 1747 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1748 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1749 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1750 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1751 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1752 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1753 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1754 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1755 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1756 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1757 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1758 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1759 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1760 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1761 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1762 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1763 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1764 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1765 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1766 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1767 using namespace llvm::X86; 1768 switch (CPU) { 1769 // i386 1770 case CK_i386: 1771 // i486 1772 case CK_i486: 1773 case CK_WinChipC6: 1774 case CK_WinChip2: 1775 case CK_C3: 1776 // Lakemont 1777 case CK_Lakemont: 1778 return 16; 1779 1780 // i586 1781 case CK_i586: 1782 case CK_Pentium: 1783 case CK_PentiumMMX: 1784 // i686 1785 case CK_PentiumPro: 1786 case CK_i686: 1787 case CK_Pentium2: 1788 case CK_Pentium3: 1789 case CK_PentiumM: 1790 case CK_C3_2: 1791 // K6 1792 case CK_K6: 1793 case CK_K6_2: 1794 case CK_K6_3: 1795 // Geode 1796 case CK_Geode: 1797 return 32; 1798 1799 // Netburst 1800 case CK_Pentium4: 1801 case CK_Prescott: 1802 case CK_Nocona: 1803 // Atom 1804 case CK_Bonnell: 1805 case CK_Silvermont: 1806 case CK_Goldmont: 1807 case CK_GoldmontPlus: 1808 case CK_Tremont: 1809 1810 case CK_Westmere: 1811 case CK_SandyBridge: 1812 case CK_IvyBridge: 1813 case CK_Haswell: 1814 case CK_Broadwell: 1815 case CK_SkylakeClient: 1816 case CK_SkylakeServer: 1817 case CK_Cascadelake: 1818 case CK_Nehalem: 1819 case CK_Cooperlake: 1820 case CK_Cannonlake: 1821 case CK_Tigerlake: 1822 case CK_IcelakeClient: 1823 case CK_IcelakeServer: 1824 case CK_KNL: 1825 case CK_KNM: 1826 // K7 1827 case CK_Athlon: 1828 case CK_AthlonXP: 1829 // K8 1830 case CK_K8: 1831 case CK_K8SSE3: 1832 case CK_AMDFAM10: 1833 // Bobcat 1834 case CK_BTVER1: 1835 case CK_BTVER2: 1836 // Bulldozer 1837 case CK_BDVER1: 1838 case CK_BDVER2: 1839 case CK_BDVER3: 1840 case CK_BDVER4: 1841 // Zen 1842 case CK_ZNVER1: 1843 case CK_ZNVER2: 1844 // Deprecated 1845 case CK_x86_64: 1846 case CK_Yonah: 1847 case CK_Penryn: 1848 case CK_Core2: 1849 return 64; 1850 1851 // The following currently have unknown cache line sizes (but they are probably all 64): 1852 // Core 1853 case CK_None: 1854 return None; 1855 } 1856 llvm_unreachable("Unknown CPU kind"); 1857 } 1858 1859 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1860 StringRef Constraint, 1861 unsigned Size) const { 1862 // Strip off constraint modifiers. 1863 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1864 Constraint = Constraint.substr(1); 1865 1866 return validateOperandSize(FeatureMap, Constraint, Size); 1867 } 1868 1869 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1870 StringRef Constraint, 1871 unsigned Size) const { 1872 return validateOperandSize(FeatureMap, Constraint, Size); 1873 } 1874 1875 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1876 StringRef Constraint, 1877 unsigned Size) const { 1878 switch (Constraint[0]) { 1879 default: 1880 break; 1881 case 'k': 1882 // Registers k0-k7 (AVX512) size limit is 64 bit. 1883 case 'y': 1884 return Size <= 64; 1885 case 'f': 1886 case 't': 1887 case 'u': 1888 return Size <= 128; 1889 case 'Y': 1890 // 'Y' is the first character for several 2-character constraints. 1891 switch (Constraint[1]) { 1892 default: 1893 return false; 1894 case 'm': 1895 // 'Ym' is synonymous with 'y'. 1896 case 'k': 1897 return Size <= 64; 1898 case 'z': 1899 // XMM0/YMM/ZMM0 1900 if (FeatureMap.lookup("avx512f")) 1901 // ZMM0 can be used if target supports AVX512F. 1902 return Size <= 512U; 1903 else if (FeatureMap.lookup("avx")) 1904 // YMM0 can be used if target supports AVX. 1905 return Size <= 256U; 1906 else if (FeatureMap.lookup("sse")) 1907 return Size <= 128U; 1908 return false; 1909 case 'i': 1910 case 't': 1911 case '2': 1912 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1913 if (SSELevel < SSE2) 1914 return false; 1915 break; 1916 } 1917 break; 1918 case 'v': 1919 case 'x': 1920 if (FeatureMap.lookup("avx512f")) 1921 // 512-bit zmm registers can be used if target supports AVX512F. 1922 return Size <= 512U; 1923 else if (FeatureMap.lookup("avx")) 1924 // 256-bit ymm registers can be used if target supports AVX. 1925 return Size <= 256U; 1926 return Size <= 128U; 1927 1928 } 1929 1930 return true; 1931 } 1932 1933 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1934 switch (*Constraint) { 1935 case '@': 1936 if (auto Len = matchAsmCCConstraint(Constraint)) { 1937 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1938 Constraint += Len - 1; 1939 return Converted; 1940 } 1941 return std::string(1, *Constraint); 1942 case 'a': 1943 return std::string("{ax}"); 1944 case 'b': 1945 return std::string("{bx}"); 1946 case 'c': 1947 return std::string("{cx}"); 1948 case 'd': 1949 return std::string("{dx}"); 1950 case 'S': 1951 return std::string("{si}"); 1952 case 'D': 1953 return std::string("{di}"); 1954 case 'p': // address 1955 return std::string("im"); 1956 case 't': // top of floating point stack. 1957 return std::string("{st}"); 1958 case 'u': // second from top of floating point stack. 1959 return std::string("{st(1)}"); // second from top of floating point stack. 1960 case 'Y': 1961 switch (Constraint[1]) { 1962 default: 1963 // Break from inner switch and fall through (copy single char), 1964 // continue parsing after copying the current constraint into 1965 // the return string. 1966 break; 1967 case 'k': 1968 case 'm': 1969 case 'i': 1970 case 't': 1971 case 'z': 1972 case '2': 1973 // "^" hints llvm that this is a 2 letter constraint. 1974 // "Constraint++" is used to promote the string iterator 1975 // to the next constraint. 1976 return std::string("^") + std::string(Constraint++, 2); 1977 } 1978 LLVM_FALLTHROUGH; 1979 default: 1980 return std::string(1, *Constraint); 1981 } 1982 } 1983 1984 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1985 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1986 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1987 } 1988 1989 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1990 return llvm::makeArrayRef(GCCRegNames); 1991 } 1992 1993 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1994 return llvm::makeArrayRef(AddlRegNames); 1995 } 1996 1997 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1998 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1999 Builtin::FirstTSBuiltin + 1); 2000 } 2001 2002 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 2003 return llvm::makeArrayRef(BuiltinInfoX86, 2004 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 2005 } 2006