1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 }; 64 65 const TargetInfo::AddlRegName AddlRegNames[] = { 66 {{"al", "ah", "eax", "rax"}, 0}, 67 {{"bl", "bh", "ebx", "rbx"}, 3}, 68 {{"cl", "ch", "ecx", "rcx"}, 2}, 69 {{"dl", "dh", "edx", "rdx"}, 1}, 70 {{"esi", "rsi"}, 4}, 71 {{"edi", "rdi"}, 5}, 72 {{"esp", "rsp"}, 7}, 73 {{"ebp", "rbp"}, 6}, 74 {{"r8d", "r8w", "r8b"}, 38}, 75 {{"r9d", "r9w", "r9b"}, 39}, 76 {{"r10d", "r10w", "r10b"}, 40}, 77 {{"r11d", "r11w", "r11b"}, 41}, 78 {{"r12d", "r12w", "r12b"}, 42}, 79 {{"r13d", "r13w", "r13b"}, 43}, 80 {{"r14d", "r14w", "r14b"}, 44}, 81 {{"r15d", "r15w", "r15b"}, 45}, 82 }; 83 84 } // namespace targets 85 } // namespace clang 86 87 using namespace clang; 88 using namespace clang::targets; 89 90 bool X86TargetInfo::setFPMath(StringRef Name) { 91 if (Name == "387") { 92 FPMath = FP_387; 93 return true; 94 } 95 if (Name == "sse") { 96 FPMath = FP_SSE; 97 return true; 98 } 99 return false; 100 } 101 102 bool X86TargetInfo::initFeatureMap( 103 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 104 const std::vector<std::string> &FeaturesVec) const { 105 // FIXME: This *really* should not be here. 106 // X86_64 always has SSE2. 107 if (getTriple().getArch() == llvm::Triple::x86_64) 108 setFeatureEnabledImpl(Features, "sse2", true); 109 110 const CPUKind Kind = getCPUKind(CPU); 111 112 // Enable X87 for all X86 processors but Lakemont. 113 if (Kind != CK_Lakemont) 114 setFeatureEnabledImpl(Features, "x87", true); 115 116 switch (Kind) { 117 case CK_Generic: 118 case CK_i386: 119 case CK_i486: 120 case CK_i586: 121 case CK_Pentium: 122 case CK_i686: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 127 case CK_PentiumMMX: 128 case CK_Pentium2: 129 case CK_K6: 130 case CK_WinChipC6: 131 setFeatureEnabledImpl(Features, "mmx", true); 132 break; 133 134 case CK_Cannonlake: 135 setFeatureEnabledImpl(Features, "avx512ifma", true); 136 setFeatureEnabledImpl(Features, "avx512vbmi", true); 137 setFeatureEnabledImpl(Features, "sha", true); 138 LLVM_FALLTHROUGH; 139 case CK_SkylakeServer: 140 setFeatureEnabledImpl(Features, "avx512f", true); 141 setFeatureEnabledImpl(Features, "avx512cd", true); 142 setFeatureEnabledImpl(Features, "avx512dq", true); 143 setFeatureEnabledImpl(Features, "avx512bw", true); 144 setFeatureEnabledImpl(Features, "avx512vl", true); 145 setFeatureEnabledImpl(Features, "pku", true); 146 setFeatureEnabledImpl(Features, "clwb", true); 147 LLVM_FALLTHROUGH; 148 case CK_SkylakeClient: 149 setFeatureEnabledImpl(Features, "xsavec", true); 150 setFeatureEnabledImpl(Features, "xsaves", true); 151 setFeatureEnabledImpl(Features, "mpx", true); 152 setFeatureEnabledImpl(Features, "sgx", true); 153 setFeatureEnabledImpl(Features, "clflushopt", true); 154 setFeatureEnabledImpl(Features, "rtm", true); 155 LLVM_FALLTHROUGH; 156 case CK_Broadwell: 157 setFeatureEnabledImpl(Features, "rdseed", true); 158 setFeatureEnabledImpl(Features, "adx", true); 159 LLVM_FALLTHROUGH; 160 case CK_Haswell: 161 setFeatureEnabledImpl(Features, "avx2", true); 162 setFeatureEnabledImpl(Features, "lzcnt", true); 163 setFeatureEnabledImpl(Features, "bmi", true); 164 setFeatureEnabledImpl(Features, "bmi2", true); 165 setFeatureEnabledImpl(Features, "fma", true); 166 setFeatureEnabledImpl(Features, "movbe", true); 167 LLVM_FALLTHROUGH; 168 case CK_IvyBridge: 169 setFeatureEnabledImpl(Features, "rdrnd", true); 170 setFeatureEnabledImpl(Features, "f16c", true); 171 setFeatureEnabledImpl(Features, "fsgsbase", true); 172 LLVM_FALLTHROUGH; 173 case CK_SandyBridge: 174 setFeatureEnabledImpl(Features, "avx", true); 175 setFeatureEnabledImpl(Features, "xsave", true); 176 setFeatureEnabledImpl(Features, "xsaveopt", true); 177 LLVM_FALLTHROUGH; 178 case CK_Westmere: 179 setFeatureEnabledImpl(Features, "aes", true); 180 setFeatureEnabledImpl(Features, "pclmul", true); 181 LLVM_FALLTHROUGH; 182 case CK_Nehalem: 183 setFeatureEnabledImpl(Features, "sse4.2", true); 184 LLVM_FALLTHROUGH; 185 case CK_Penryn: 186 setFeatureEnabledImpl(Features, "sse4.1", true); 187 LLVM_FALLTHROUGH; 188 case CK_Core2: 189 setFeatureEnabledImpl(Features, "ssse3", true); 190 LLVM_FALLTHROUGH; 191 case CK_Yonah: 192 case CK_Prescott: 193 case CK_Nocona: 194 setFeatureEnabledImpl(Features, "sse3", true); 195 setFeatureEnabledImpl(Features, "cx16", true); 196 LLVM_FALLTHROUGH; 197 case CK_PentiumM: 198 case CK_Pentium4: 199 case CK_x86_64: 200 setFeatureEnabledImpl(Features, "sse2", true); 201 LLVM_FALLTHROUGH; 202 case CK_Pentium3: 203 case CK_C3_2: 204 setFeatureEnabledImpl(Features, "sse", true); 205 setFeatureEnabledImpl(Features, "fxsr", true); 206 break; 207 208 case CK_Goldmont: 209 setFeatureEnabledImpl(Features, "sha", true); 210 setFeatureEnabledImpl(Features, "rdrnd", true); 211 setFeatureEnabledImpl(Features, "rdseed", true); 212 setFeatureEnabledImpl(Features, "xsave", true); 213 setFeatureEnabledImpl(Features, "xsaveopt", true); 214 setFeatureEnabledImpl(Features, "xsavec", true); 215 setFeatureEnabledImpl(Features, "xsaves", true); 216 setFeatureEnabledImpl(Features, "clflushopt", true); 217 setFeatureEnabledImpl(Features, "mpx", true); 218 LLVM_FALLTHROUGH; 219 case CK_Silvermont: 220 setFeatureEnabledImpl(Features, "aes", true); 221 setFeatureEnabledImpl(Features, "pclmul", true); 222 setFeatureEnabledImpl(Features, "sse4.2", true); 223 LLVM_FALLTHROUGH; 224 case CK_Bonnell: 225 setFeatureEnabledImpl(Features, "movbe", true); 226 setFeatureEnabledImpl(Features, "ssse3", true); 227 setFeatureEnabledImpl(Features, "fxsr", true); 228 setFeatureEnabledImpl(Features, "cx16", true); 229 break; 230 231 case CK_KNL: 232 setFeatureEnabledImpl(Features, "avx512f", true); 233 setFeatureEnabledImpl(Features, "avx512cd", true); 234 setFeatureEnabledImpl(Features, "avx512er", true); 235 setFeatureEnabledImpl(Features, "avx512pf", true); 236 setFeatureEnabledImpl(Features, "prefetchwt1", true); 237 setFeatureEnabledImpl(Features, "fxsr", true); 238 setFeatureEnabledImpl(Features, "rdseed", true); 239 setFeatureEnabledImpl(Features, "adx", true); 240 setFeatureEnabledImpl(Features, "lzcnt", true); 241 setFeatureEnabledImpl(Features, "bmi", true); 242 setFeatureEnabledImpl(Features, "bmi2", true); 243 setFeatureEnabledImpl(Features, "rtm", true); 244 setFeatureEnabledImpl(Features, "fma", true); 245 setFeatureEnabledImpl(Features, "rdrnd", true); 246 setFeatureEnabledImpl(Features, "f16c", true); 247 setFeatureEnabledImpl(Features, "fsgsbase", true); 248 setFeatureEnabledImpl(Features, "aes", true); 249 setFeatureEnabledImpl(Features, "pclmul", true); 250 setFeatureEnabledImpl(Features, "cx16", true); 251 setFeatureEnabledImpl(Features, "xsaveopt", true); 252 setFeatureEnabledImpl(Features, "xsave", true); 253 setFeatureEnabledImpl(Features, "movbe", true); 254 break; 255 256 case CK_K6_2: 257 case CK_K6_3: 258 case CK_WinChip2: 259 case CK_C3: 260 setFeatureEnabledImpl(Features, "3dnow", true); 261 break; 262 263 case CK_AMDFAM10: 264 setFeatureEnabledImpl(Features, "sse4a", true); 265 setFeatureEnabledImpl(Features, "lzcnt", true); 266 setFeatureEnabledImpl(Features, "popcnt", true); 267 LLVM_FALLTHROUGH; 268 case CK_K8SSE3: 269 setFeatureEnabledImpl(Features, "sse3", true); 270 LLVM_FALLTHROUGH; 271 case CK_K8: 272 setFeatureEnabledImpl(Features, "sse2", true); 273 LLVM_FALLTHROUGH; 274 case CK_AthlonXP: 275 setFeatureEnabledImpl(Features, "sse", true); 276 setFeatureEnabledImpl(Features, "fxsr", true); 277 LLVM_FALLTHROUGH; 278 case CK_Athlon: 279 case CK_Geode: 280 setFeatureEnabledImpl(Features, "3dnowa", true); 281 break; 282 283 case CK_BTVER2: 284 setFeatureEnabledImpl(Features, "avx", true); 285 setFeatureEnabledImpl(Features, "aes", true); 286 setFeatureEnabledImpl(Features, "pclmul", true); 287 setFeatureEnabledImpl(Features, "bmi", true); 288 setFeatureEnabledImpl(Features, "f16c", true); 289 setFeatureEnabledImpl(Features, "xsaveopt", true); 290 setFeatureEnabledImpl(Features, "movbe", true); 291 LLVM_FALLTHROUGH; 292 case CK_BTVER1: 293 setFeatureEnabledImpl(Features, "ssse3", true); 294 setFeatureEnabledImpl(Features, "sse4a", true); 295 setFeatureEnabledImpl(Features, "lzcnt", true); 296 setFeatureEnabledImpl(Features, "popcnt", true); 297 setFeatureEnabledImpl(Features, "prfchw", true); 298 setFeatureEnabledImpl(Features, "cx16", true); 299 setFeatureEnabledImpl(Features, "fxsr", true); 300 break; 301 302 case CK_ZNVER1: 303 setFeatureEnabledImpl(Features, "adx", true); 304 setFeatureEnabledImpl(Features, "aes", true); 305 setFeatureEnabledImpl(Features, "avx2", true); 306 setFeatureEnabledImpl(Features, "bmi", true); 307 setFeatureEnabledImpl(Features, "bmi2", true); 308 setFeatureEnabledImpl(Features, "clflushopt", true); 309 setFeatureEnabledImpl(Features, "clzero", true); 310 setFeatureEnabledImpl(Features, "cx16", true); 311 setFeatureEnabledImpl(Features, "f16c", true); 312 setFeatureEnabledImpl(Features, "fma", true); 313 setFeatureEnabledImpl(Features, "fsgsbase", true); 314 setFeatureEnabledImpl(Features, "fxsr", true); 315 setFeatureEnabledImpl(Features, "lzcnt", true); 316 setFeatureEnabledImpl(Features, "mwaitx", true); 317 setFeatureEnabledImpl(Features, "movbe", true); 318 setFeatureEnabledImpl(Features, "pclmul", true); 319 setFeatureEnabledImpl(Features, "popcnt", true); 320 setFeatureEnabledImpl(Features, "prfchw", true); 321 setFeatureEnabledImpl(Features, "rdrnd", true); 322 setFeatureEnabledImpl(Features, "rdseed", true); 323 setFeatureEnabledImpl(Features, "sha", true); 324 setFeatureEnabledImpl(Features, "sse4a", true); 325 setFeatureEnabledImpl(Features, "xsave", true); 326 setFeatureEnabledImpl(Features, "xsavec", true); 327 setFeatureEnabledImpl(Features, "xsaveopt", true); 328 setFeatureEnabledImpl(Features, "xsaves", true); 329 break; 330 331 case CK_BDVER4: 332 setFeatureEnabledImpl(Features, "avx2", true); 333 setFeatureEnabledImpl(Features, "bmi2", true); 334 setFeatureEnabledImpl(Features, "mwaitx", true); 335 LLVM_FALLTHROUGH; 336 case CK_BDVER3: 337 setFeatureEnabledImpl(Features, "fsgsbase", true); 338 setFeatureEnabledImpl(Features, "xsaveopt", true); 339 LLVM_FALLTHROUGH; 340 case CK_BDVER2: 341 setFeatureEnabledImpl(Features, "bmi", true); 342 setFeatureEnabledImpl(Features, "fma", true); 343 setFeatureEnabledImpl(Features, "f16c", true); 344 setFeatureEnabledImpl(Features, "tbm", true); 345 LLVM_FALLTHROUGH; 346 case CK_BDVER1: 347 // xop implies avx, sse4a and fma4. 348 setFeatureEnabledImpl(Features, "xop", true); 349 setFeatureEnabledImpl(Features, "lwp", true); 350 setFeatureEnabledImpl(Features, "lzcnt", true); 351 setFeatureEnabledImpl(Features, "aes", true); 352 setFeatureEnabledImpl(Features, "pclmul", true); 353 setFeatureEnabledImpl(Features, "prfchw", true); 354 setFeatureEnabledImpl(Features, "cx16", true); 355 setFeatureEnabledImpl(Features, "fxsr", true); 356 setFeatureEnabledImpl(Features, "xsave", true); 357 break; 358 } 359 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 360 return false; 361 362 // Can't do this earlier because we need to be able to explicitly enable 363 // or disable these features and the things that they depend upon. 364 365 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 366 auto I = Features.find("sse4.2"); 367 if (I != Features.end() && I->getValue() && 368 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 369 FeaturesVec.end()) 370 Features["popcnt"] = true; 371 372 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 373 I = Features.find("3dnow"); 374 if (I != Features.end() && I->getValue() && 375 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 376 FeaturesVec.end()) 377 Features["prfchw"] = true; 378 379 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 380 // then enable MMX. 381 I = Features.find("sse"); 382 if (I != Features.end() && I->getValue() && 383 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 384 FeaturesVec.end()) 385 Features["mmx"] = true; 386 387 return true; 388 } 389 390 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 391 X86SSEEnum Level, bool Enabled) { 392 if (Enabled) { 393 switch (Level) { 394 case AVX512F: 395 Features["avx512f"] = true; 396 LLVM_FALLTHROUGH; 397 case AVX2: 398 Features["avx2"] = true; 399 LLVM_FALLTHROUGH; 400 case AVX: 401 Features["avx"] = true; 402 Features["xsave"] = true; 403 LLVM_FALLTHROUGH; 404 case SSE42: 405 Features["sse4.2"] = true; 406 LLVM_FALLTHROUGH; 407 case SSE41: 408 Features["sse4.1"] = true; 409 LLVM_FALLTHROUGH; 410 case SSSE3: 411 Features["ssse3"] = true; 412 LLVM_FALLTHROUGH; 413 case SSE3: 414 Features["sse3"] = true; 415 LLVM_FALLTHROUGH; 416 case SSE2: 417 Features["sse2"] = true; 418 LLVM_FALLTHROUGH; 419 case SSE1: 420 Features["sse"] = true; 421 LLVM_FALLTHROUGH; 422 case NoSSE: 423 break; 424 } 425 return; 426 } 427 428 switch (Level) { 429 case NoSSE: 430 case SSE1: 431 Features["sse"] = false; 432 LLVM_FALLTHROUGH; 433 case SSE2: 434 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 435 false; 436 LLVM_FALLTHROUGH; 437 case SSE3: 438 Features["sse3"] = false; 439 setXOPLevel(Features, NoXOP, false); 440 LLVM_FALLTHROUGH; 441 case SSSE3: 442 Features["ssse3"] = false; 443 LLVM_FALLTHROUGH; 444 case SSE41: 445 Features["sse4.1"] = false; 446 LLVM_FALLTHROUGH; 447 case SSE42: 448 Features["sse4.2"] = false; 449 LLVM_FALLTHROUGH; 450 case AVX: 451 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 452 Features["xsaveopt"] = false; 453 setXOPLevel(Features, FMA4, false); 454 LLVM_FALLTHROUGH; 455 case AVX2: 456 Features["avx2"] = false; 457 LLVM_FALLTHROUGH; 458 case AVX512F: 459 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 460 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 461 Features["avx512vl"] = Features["avx512vbmi"] = 462 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 463 break; 464 } 465 } 466 467 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 468 MMX3DNowEnum Level, bool Enabled) { 469 if (Enabled) { 470 switch (Level) { 471 case AMD3DNowAthlon: 472 Features["3dnowa"] = true; 473 LLVM_FALLTHROUGH; 474 case AMD3DNow: 475 Features["3dnow"] = true; 476 LLVM_FALLTHROUGH; 477 case MMX: 478 Features["mmx"] = true; 479 LLVM_FALLTHROUGH; 480 case NoMMX3DNow: 481 break; 482 } 483 return; 484 } 485 486 switch (Level) { 487 case NoMMX3DNow: 488 case MMX: 489 Features["mmx"] = false; 490 LLVM_FALLTHROUGH; 491 case AMD3DNow: 492 Features["3dnow"] = false; 493 LLVM_FALLTHROUGH; 494 case AMD3DNowAthlon: 495 Features["3dnowa"] = false; 496 break; 497 } 498 } 499 500 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 501 bool Enabled) { 502 if (Enabled) { 503 switch (Level) { 504 case XOP: 505 Features["xop"] = true; 506 LLVM_FALLTHROUGH; 507 case FMA4: 508 Features["fma4"] = true; 509 setSSELevel(Features, AVX, true); 510 LLVM_FALLTHROUGH; 511 case SSE4A: 512 Features["sse4a"] = true; 513 setSSELevel(Features, SSE3, true); 514 LLVM_FALLTHROUGH; 515 case NoXOP: 516 break; 517 } 518 return; 519 } 520 521 switch (Level) { 522 case NoXOP: 523 case SSE4A: 524 Features["sse4a"] = false; 525 LLVM_FALLTHROUGH; 526 case FMA4: 527 Features["fma4"] = false; 528 LLVM_FALLTHROUGH; 529 case XOP: 530 Features["xop"] = false; 531 break; 532 } 533 } 534 535 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 536 StringRef Name, bool Enabled) { 537 // This is a bit of a hack to deal with the sse4 target feature when used 538 // as part of the target attribute. We handle sse4 correctly everywhere 539 // else. See below for more information on how we handle the sse4 options. 540 if (Name != "sse4") 541 Features[Name] = Enabled; 542 543 if (Name == "mmx") { 544 setMMXLevel(Features, MMX, Enabled); 545 } else if (Name == "sse") { 546 setSSELevel(Features, SSE1, Enabled); 547 } else if (Name == "sse2") { 548 setSSELevel(Features, SSE2, Enabled); 549 } else if (Name == "sse3") { 550 setSSELevel(Features, SSE3, Enabled); 551 } else if (Name == "ssse3") { 552 setSSELevel(Features, SSSE3, Enabled); 553 } else if (Name == "sse4.2") { 554 setSSELevel(Features, SSE42, Enabled); 555 } else if (Name == "sse4.1") { 556 setSSELevel(Features, SSE41, Enabled); 557 } else if (Name == "3dnow") { 558 setMMXLevel(Features, AMD3DNow, Enabled); 559 } else if (Name == "3dnowa") { 560 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 561 } else if (Name == "aes") { 562 if (Enabled) 563 setSSELevel(Features, SSE2, Enabled); 564 } else if (Name == "pclmul") { 565 if (Enabled) 566 setSSELevel(Features, SSE2, Enabled); 567 } else if (Name == "avx") { 568 setSSELevel(Features, AVX, Enabled); 569 } else if (Name == "avx2") { 570 setSSELevel(Features, AVX2, Enabled); 571 } else if (Name == "avx512f") { 572 setSSELevel(Features, AVX512F, Enabled); 573 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 574 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 575 Name == "avx512vbmi" || Name == "avx512ifma" || 576 Name == "avx512vpopcntdq") { 577 if (Enabled) 578 setSSELevel(Features, AVX512F, Enabled); 579 // Enable BWI instruction if VBMI is being enabled. 580 if (Name == "avx512vbmi" && Enabled) 581 Features["avx512bw"] = true; 582 // Also disable VBMI if BWI is being disabled. 583 if (Name == "avx512bw" && !Enabled) 584 Features["avx512vbmi"] = false; 585 } else if (Name == "fma") { 586 if (Enabled) 587 setSSELevel(Features, AVX, Enabled); 588 } else if (Name == "fma4") { 589 setXOPLevel(Features, FMA4, Enabled); 590 } else if (Name == "xop") { 591 setXOPLevel(Features, XOP, Enabled); 592 } else if (Name == "sse4a") { 593 setXOPLevel(Features, SSE4A, Enabled); 594 } else if (Name == "f16c") { 595 if (Enabled) 596 setSSELevel(Features, AVX, Enabled); 597 } else if (Name == "sha") { 598 if (Enabled) 599 setSSELevel(Features, SSE2, Enabled); 600 } else if (Name == "sse4") { 601 // We can get here via the __target__ attribute since that's not controlled 602 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 603 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 604 // disabled. 605 if (Enabled) 606 setSSELevel(Features, SSE42, Enabled); 607 else 608 setSSELevel(Features, SSE41, Enabled); 609 } else if (Name == "xsave") { 610 if (!Enabled) 611 Features["xsaveopt"] = false; 612 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 613 if (Enabled) 614 Features["xsave"] = true; 615 } 616 } 617 618 /// handleTargetFeatures - Perform initialization based on the user 619 /// configured set of features. 620 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 621 DiagnosticsEngine &Diags) { 622 for (const auto &Feature : Features) { 623 if (Feature[0] != '+') 624 continue; 625 626 if (Feature == "+aes") { 627 HasAES = true; 628 } else if (Feature == "+pclmul") { 629 HasPCLMUL = true; 630 } else if (Feature == "+lzcnt") { 631 HasLZCNT = true; 632 } else if (Feature == "+rdrnd") { 633 HasRDRND = true; 634 } else if (Feature == "+fsgsbase") { 635 HasFSGSBASE = true; 636 } else if (Feature == "+bmi") { 637 HasBMI = true; 638 } else if (Feature == "+bmi2") { 639 HasBMI2 = true; 640 } else if (Feature == "+popcnt") { 641 HasPOPCNT = true; 642 } else if (Feature == "+rtm") { 643 HasRTM = true; 644 } else if (Feature == "+prfchw") { 645 HasPRFCHW = true; 646 } else if (Feature == "+rdseed") { 647 HasRDSEED = true; 648 } else if (Feature == "+adx") { 649 HasADX = true; 650 } else if (Feature == "+tbm") { 651 HasTBM = true; 652 } else if (Feature == "+lwp") { 653 HasLWP = true; 654 } else if (Feature == "+fma") { 655 HasFMA = true; 656 } else if (Feature == "+f16c") { 657 HasF16C = true; 658 } else if (Feature == "+avx512cd") { 659 HasAVX512CD = true; 660 } else if (Feature == "+avx512vpopcntdq") { 661 HasAVX512VPOPCNTDQ = true; 662 } else if (Feature == "+avx512er") { 663 HasAVX512ER = true; 664 } else if (Feature == "+avx512pf") { 665 HasAVX512PF = true; 666 } else if (Feature == "+avx512dq") { 667 HasAVX512DQ = true; 668 } else if (Feature == "+avx512bw") { 669 HasAVX512BW = true; 670 } else if (Feature == "+avx512vl") { 671 HasAVX512VL = true; 672 } else if (Feature == "+avx512vbmi") { 673 HasAVX512VBMI = true; 674 } else if (Feature == "+avx512ifma") { 675 HasAVX512IFMA = true; 676 } else if (Feature == "+sha") { 677 HasSHA = true; 678 } else if (Feature == "+mpx") { 679 HasMPX = true; 680 } else if (Feature == "+movbe") { 681 HasMOVBE = true; 682 } else if (Feature == "+sgx") { 683 HasSGX = true; 684 } else if (Feature == "+cx16") { 685 HasCX16 = true; 686 } else if (Feature == "+fxsr") { 687 HasFXSR = true; 688 } else if (Feature == "+xsave") { 689 HasXSAVE = true; 690 } else if (Feature == "+xsaveopt") { 691 HasXSAVEOPT = true; 692 } else if (Feature == "+xsavec") { 693 HasXSAVEC = true; 694 } else if (Feature == "+xsaves") { 695 HasXSAVES = true; 696 } else if (Feature == "+mwaitx") { 697 HasMWAITX = true; 698 } else if (Feature == "+pku") { 699 HasPKU = true; 700 } else if (Feature == "+clflushopt") { 701 HasCLFLUSHOPT = true; 702 } else if (Feature == "+clwb") { 703 HasCLWB = true; 704 } else if (Feature == "+prefetchwt1") { 705 HasPREFETCHWT1 = true; 706 } else if (Feature == "+clzero") { 707 HasCLZERO = true; 708 } 709 710 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 711 .Case("+avx512f", AVX512F) 712 .Case("+avx2", AVX2) 713 .Case("+avx", AVX) 714 .Case("+sse4.2", SSE42) 715 .Case("+sse4.1", SSE41) 716 .Case("+ssse3", SSSE3) 717 .Case("+sse3", SSE3) 718 .Case("+sse2", SSE2) 719 .Case("+sse", SSE1) 720 .Default(NoSSE); 721 SSELevel = std::max(SSELevel, Level); 722 723 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 724 .Case("+3dnowa", AMD3DNowAthlon) 725 .Case("+3dnow", AMD3DNow) 726 .Case("+mmx", MMX) 727 .Default(NoMMX3DNow); 728 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 729 730 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 731 .Case("+xop", XOP) 732 .Case("+fma4", FMA4) 733 .Case("+sse4a", SSE4A) 734 .Default(NoXOP); 735 XOPLevel = std::max(XOPLevel, XLevel); 736 } 737 738 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 739 // matches the selected sse level. 740 if ((FPMath == FP_SSE && SSELevel < SSE1) || 741 (FPMath == FP_387 && SSELevel >= SSE1)) { 742 Diags.Report(diag::err_target_unsupported_fpmath) 743 << (FPMath == FP_SSE ? "sse" : "387"); 744 return false; 745 } 746 747 SimdDefaultAlign = 748 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 749 return true; 750 } 751 752 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 753 /// definitions for this particular subtarget. 754 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 755 MacroBuilder &Builder) const { 756 // Target identification. 757 if (getTriple().getArch() == llvm::Triple::x86_64) { 758 Builder.defineMacro("__amd64__"); 759 Builder.defineMacro("__amd64"); 760 Builder.defineMacro("__x86_64"); 761 Builder.defineMacro("__x86_64__"); 762 if (getTriple().getArchName() == "x86_64h") { 763 Builder.defineMacro("__x86_64h"); 764 Builder.defineMacro("__x86_64h__"); 765 } 766 } else { 767 DefineStd(Builder, "i386", Opts); 768 } 769 770 // Subtarget options. 771 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 772 // truly should be based on -mtune options. 773 switch (CPU) { 774 case CK_Generic: 775 break; 776 case CK_i386: 777 // The rest are coming from the i386 define above. 778 Builder.defineMacro("__tune_i386__"); 779 break; 780 case CK_i486: 781 case CK_WinChipC6: 782 case CK_WinChip2: 783 case CK_C3: 784 defineCPUMacros(Builder, "i486"); 785 break; 786 case CK_PentiumMMX: 787 Builder.defineMacro("__pentium_mmx__"); 788 Builder.defineMacro("__tune_pentium_mmx__"); 789 LLVM_FALLTHROUGH; 790 case CK_i586: 791 case CK_Pentium: 792 defineCPUMacros(Builder, "i586"); 793 defineCPUMacros(Builder, "pentium"); 794 break; 795 case CK_Pentium3: 796 case CK_PentiumM: 797 Builder.defineMacro("__tune_pentium3__"); 798 LLVM_FALLTHROUGH; 799 case CK_Pentium2: 800 case CK_C3_2: 801 Builder.defineMacro("__tune_pentium2__"); 802 LLVM_FALLTHROUGH; 803 case CK_PentiumPro: 804 Builder.defineMacro("__tune_i686__"); 805 Builder.defineMacro("__tune_pentiumpro__"); 806 LLVM_FALLTHROUGH; 807 case CK_i686: 808 Builder.defineMacro("__i686"); 809 Builder.defineMacro("__i686__"); 810 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 811 Builder.defineMacro("__pentiumpro"); 812 Builder.defineMacro("__pentiumpro__"); 813 break; 814 case CK_Pentium4: 815 defineCPUMacros(Builder, "pentium4"); 816 break; 817 case CK_Yonah: 818 case CK_Prescott: 819 case CK_Nocona: 820 defineCPUMacros(Builder, "nocona"); 821 break; 822 case CK_Core2: 823 case CK_Penryn: 824 defineCPUMacros(Builder, "core2"); 825 break; 826 case CK_Bonnell: 827 defineCPUMacros(Builder, "atom"); 828 break; 829 case CK_Silvermont: 830 defineCPUMacros(Builder, "slm"); 831 break; 832 case CK_Goldmont: 833 defineCPUMacros(Builder, "goldmont"); 834 break; 835 case CK_Nehalem: 836 case CK_Westmere: 837 case CK_SandyBridge: 838 case CK_IvyBridge: 839 case CK_Haswell: 840 case CK_Broadwell: 841 case CK_SkylakeClient: 842 // FIXME: Historically, we defined this legacy name, it would be nice to 843 // remove it at some point. We've never exposed fine-grained names for 844 // recent primary x86 CPUs, and we should keep it that way. 845 defineCPUMacros(Builder, "corei7"); 846 break; 847 case CK_SkylakeServer: 848 defineCPUMacros(Builder, "skx"); 849 break; 850 case CK_Cannonlake: 851 break; 852 case CK_KNL: 853 defineCPUMacros(Builder, "knl"); 854 break; 855 case CK_Lakemont: 856 Builder.defineMacro("__tune_lakemont__"); 857 break; 858 case CK_K6_2: 859 Builder.defineMacro("__k6_2__"); 860 Builder.defineMacro("__tune_k6_2__"); 861 LLVM_FALLTHROUGH; 862 case CK_K6_3: 863 if (CPU != CK_K6_2) { // In case of fallthrough 864 // FIXME: GCC may be enabling these in cases where some other k6 865 // architecture is specified but -m3dnow is explicitly provided. The 866 // exact semantics need to be determined and emulated here. 867 Builder.defineMacro("__k6_3__"); 868 Builder.defineMacro("__tune_k6_3__"); 869 } 870 LLVM_FALLTHROUGH; 871 case CK_K6: 872 defineCPUMacros(Builder, "k6"); 873 break; 874 case CK_Athlon: 875 case CK_AthlonXP: 876 defineCPUMacros(Builder, "athlon"); 877 if (SSELevel != NoSSE) { 878 Builder.defineMacro("__athlon_sse__"); 879 Builder.defineMacro("__tune_athlon_sse__"); 880 } 881 break; 882 case CK_K8: 883 case CK_K8SSE3: 884 case CK_x86_64: 885 defineCPUMacros(Builder, "k8"); 886 break; 887 case CK_AMDFAM10: 888 defineCPUMacros(Builder, "amdfam10"); 889 break; 890 case CK_BTVER1: 891 defineCPUMacros(Builder, "btver1"); 892 break; 893 case CK_BTVER2: 894 defineCPUMacros(Builder, "btver2"); 895 break; 896 case CK_BDVER1: 897 defineCPUMacros(Builder, "bdver1"); 898 break; 899 case CK_BDVER2: 900 defineCPUMacros(Builder, "bdver2"); 901 break; 902 case CK_BDVER3: 903 defineCPUMacros(Builder, "bdver3"); 904 break; 905 case CK_BDVER4: 906 defineCPUMacros(Builder, "bdver4"); 907 break; 908 case CK_ZNVER1: 909 defineCPUMacros(Builder, "znver1"); 910 break; 911 case CK_Geode: 912 defineCPUMacros(Builder, "geode"); 913 break; 914 } 915 916 // Target properties. 917 Builder.defineMacro("__REGISTER_PREFIX__", ""); 918 919 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 920 // functions in glibc header files that use FP Stack inline asm which the 921 // backend can't deal with (PR879). 922 Builder.defineMacro("__NO_MATH_INLINES"); 923 924 if (HasAES) 925 Builder.defineMacro("__AES__"); 926 927 if (HasPCLMUL) 928 Builder.defineMacro("__PCLMUL__"); 929 930 if (HasLZCNT) 931 Builder.defineMacro("__LZCNT__"); 932 933 if (HasRDRND) 934 Builder.defineMacro("__RDRND__"); 935 936 if (HasFSGSBASE) 937 Builder.defineMacro("__FSGSBASE__"); 938 939 if (HasBMI) 940 Builder.defineMacro("__BMI__"); 941 942 if (HasBMI2) 943 Builder.defineMacro("__BMI2__"); 944 945 if (HasPOPCNT) 946 Builder.defineMacro("__POPCNT__"); 947 948 if (HasRTM) 949 Builder.defineMacro("__RTM__"); 950 951 if (HasPRFCHW) 952 Builder.defineMacro("__PRFCHW__"); 953 954 if (HasRDSEED) 955 Builder.defineMacro("__RDSEED__"); 956 957 if (HasADX) 958 Builder.defineMacro("__ADX__"); 959 960 if (HasTBM) 961 Builder.defineMacro("__TBM__"); 962 963 if (HasLWP) 964 Builder.defineMacro("__LWP__"); 965 966 if (HasMWAITX) 967 Builder.defineMacro("__MWAITX__"); 968 969 switch (XOPLevel) { 970 case XOP: 971 Builder.defineMacro("__XOP__"); 972 LLVM_FALLTHROUGH; 973 case FMA4: 974 Builder.defineMacro("__FMA4__"); 975 LLVM_FALLTHROUGH; 976 case SSE4A: 977 Builder.defineMacro("__SSE4A__"); 978 LLVM_FALLTHROUGH; 979 case NoXOP: 980 break; 981 } 982 983 if (HasFMA) 984 Builder.defineMacro("__FMA__"); 985 986 if (HasF16C) 987 Builder.defineMacro("__F16C__"); 988 989 if (HasAVX512CD) 990 Builder.defineMacro("__AVX512CD__"); 991 if (HasAVX512VPOPCNTDQ) 992 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 993 if (HasAVX512ER) 994 Builder.defineMacro("__AVX512ER__"); 995 if (HasAVX512PF) 996 Builder.defineMacro("__AVX512PF__"); 997 if (HasAVX512DQ) 998 Builder.defineMacro("__AVX512DQ__"); 999 if (HasAVX512BW) 1000 Builder.defineMacro("__AVX512BW__"); 1001 if (HasAVX512VL) 1002 Builder.defineMacro("__AVX512VL__"); 1003 if (HasAVX512VBMI) 1004 Builder.defineMacro("__AVX512VBMI__"); 1005 if (HasAVX512IFMA) 1006 Builder.defineMacro("__AVX512IFMA__"); 1007 1008 if (HasSHA) 1009 Builder.defineMacro("__SHA__"); 1010 1011 if (HasFXSR) 1012 Builder.defineMacro("__FXSR__"); 1013 if (HasXSAVE) 1014 Builder.defineMacro("__XSAVE__"); 1015 if (HasXSAVEOPT) 1016 Builder.defineMacro("__XSAVEOPT__"); 1017 if (HasXSAVEC) 1018 Builder.defineMacro("__XSAVEC__"); 1019 if (HasXSAVES) 1020 Builder.defineMacro("__XSAVES__"); 1021 if (HasPKU) 1022 Builder.defineMacro("__PKU__"); 1023 if (HasCX16) 1024 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1025 if (HasCLFLUSHOPT) 1026 Builder.defineMacro("__CLFLUSHOPT__"); 1027 if (HasCLWB) 1028 Builder.defineMacro("__CLWB__"); 1029 if (HasMPX) 1030 Builder.defineMacro("__MPX__"); 1031 if (HasSGX) 1032 Builder.defineMacro("__SGX__"); 1033 if (HasPREFETCHWT1) 1034 Builder.defineMacro("__PREFETCHWT1__"); 1035 if (HasCLZERO) 1036 Builder.defineMacro("__CLZERO__"); 1037 1038 // Each case falls through to the previous one here. 1039 switch (SSELevel) { 1040 case AVX512F: 1041 Builder.defineMacro("__AVX512F__"); 1042 LLVM_FALLTHROUGH; 1043 case AVX2: 1044 Builder.defineMacro("__AVX2__"); 1045 LLVM_FALLTHROUGH; 1046 case AVX: 1047 Builder.defineMacro("__AVX__"); 1048 LLVM_FALLTHROUGH; 1049 case SSE42: 1050 Builder.defineMacro("__SSE4_2__"); 1051 LLVM_FALLTHROUGH; 1052 case SSE41: 1053 Builder.defineMacro("__SSE4_1__"); 1054 LLVM_FALLTHROUGH; 1055 case SSSE3: 1056 Builder.defineMacro("__SSSE3__"); 1057 LLVM_FALLTHROUGH; 1058 case SSE3: 1059 Builder.defineMacro("__SSE3__"); 1060 LLVM_FALLTHROUGH; 1061 case SSE2: 1062 Builder.defineMacro("__SSE2__"); 1063 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1064 LLVM_FALLTHROUGH; 1065 case SSE1: 1066 Builder.defineMacro("__SSE__"); 1067 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1068 LLVM_FALLTHROUGH; 1069 case NoSSE: 1070 break; 1071 } 1072 1073 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1074 switch (SSELevel) { 1075 case AVX512F: 1076 case AVX2: 1077 case AVX: 1078 case SSE42: 1079 case SSE41: 1080 case SSSE3: 1081 case SSE3: 1082 case SSE2: 1083 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1084 break; 1085 case SSE1: 1086 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1087 break; 1088 default: 1089 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1090 break; 1091 } 1092 } 1093 1094 // Each case falls through to the previous one here. 1095 switch (MMX3DNowLevel) { 1096 case AMD3DNowAthlon: 1097 Builder.defineMacro("__3dNOW_A__"); 1098 LLVM_FALLTHROUGH; 1099 case AMD3DNow: 1100 Builder.defineMacro("__3dNOW__"); 1101 LLVM_FALLTHROUGH; 1102 case MMX: 1103 Builder.defineMacro("__MMX__"); 1104 LLVM_FALLTHROUGH; 1105 case NoMMX3DNow: 1106 break; 1107 } 1108 1109 if (CPU >= CK_i486) { 1110 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1111 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1112 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1113 } 1114 if (CPU >= CK_i586) 1115 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1116 1117 if (HasFloat128) 1118 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1119 } 1120 1121 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1122 return llvm::StringSwitch<bool>(Name) 1123 .Case("aes", true) 1124 .Case("avx", true) 1125 .Case("avx2", true) 1126 .Case("avx512f", true) 1127 .Case("avx512cd", true) 1128 .Case("avx512vpopcntdq", true) 1129 .Case("avx512er", true) 1130 .Case("avx512pf", true) 1131 .Case("avx512dq", true) 1132 .Case("avx512bw", true) 1133 .Case("avx512vl", true) 1134 .Case("avx512vbmi", true) 1135 .Case("avx512ifma", true) 1136 .Case("bmi", true) 1137 .Case("bmi2", true) 1138 .Case("clflushopt", true) 1139 .Case("clwb", true) 1140 .Case("clzero", true) 1141 .Case("cx16", true) 1142 .Case("f16c", true) 1143 .Case("fma", true) 1144 .Case("fma4", true) 1145 .Case("fsgsbase", true) 1146 .Case("fxsr", true) 1147 .Case("lwp", true) 1148 .Case("lzcnt", true) 1149 .Case("mm3dnow", true) 1150 .Case("mm3dnowa", true) 1151 .Case("mmx", true) 1152 .Case("movbe", true) 1153 .Case("mpx", true) 1154 .Case("pclmul", true) 1155 .Case("pku", true) 1156 .Case("popcnt", true) 1157 .Case("prefetchwt1", true) 1158 .Case("prfchw", true) 1159 .Case("rdrnd", true) 1160 .Case("rdseed", true) 1161 .Case("rtm", true) 1162 .Case("sgx", true) 1163 .Case("sha", true) 1164 .Case("sse", true) 1165 .Case("sse2", true) 1166 .Case("sse3", true) 1167 .Case("ssse3", true) 1168 .Case("sse4.1", true) 1169 .Case("sse4.2", true) 1170 .Case("sse4a", true) 1171 .Case("tbm", true) 1172 .Case("x86", true) 1173 .Case("x86_32", true) 1174 .Case("x86_64", true) 1175 .Case("xop", true) 1176 .Case("xsave", true) 1177 .Case("xsavec", true) 1178 .Case("xsaves", true) 1179 .Case("xsaveopt", true) 1180 .Default(false); 1181 } 1182 1183 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1184 return llvm::StringSwitch<bool>(Feature) 1185 .Case("aes", HasAES) 1186 .Case("avx", SSELevel >= AVX) 1187 .Case("avx2", SSELevel >= AVX2) 1188 .Case("avx512f", SSELevel >= AVX512F) 1189 .Case("avx512cd", HasAVX512CD) 1190 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1191 .Case("avx512er", HasAVX512ER) 1192 .Case("avx512pf", HasAVX512PF) 1193 .Case("avx512dq", HasAVX512DQ) 1194 .Case("avx512bw", HasAVX512BW) 1195 .Case("avx512vl", HasAVX512VL) 1196 .Case("avx512vbmi", HasAVX512VBMI) 1197 .Case("avx512ifma", HasAVX512IFMA) 1198 .Case("bmi", HasBMI) 1199 .Case("bmi2", HasBMI2) 1200 .Case("clflushopt", HasCLFLUSHOPT) 1201 .Case("clwb", HasCLWB) 1202 .Case("clzero", HasCLZERO) 1203 .Case("cx16", HasCX16) 1204 .Case("f16c", HasF16C) 1205 .Case("fma", HasFMA) 1206 .Case("fma4", XOPLevel >= FMA4) 1207 .Case("fsgsbase", HasFSGSBASE) 1208 .Case("fxsr", HasFXSR) 1209 .Case("lwp", HasLWP) 1210 .Case("lzcnt", HasLZCNT) 1211 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1212 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1213 .Case("mmx", MMX3DNowLevel >= MMX) 1214 .Case("movbe", HasMOVBE) 1215 .Case("mpx", HasMPX) 1216 .Case("pclmul", HasPCLMUL) 1217 .Case("pku", HasPKU) 1218 .Case("popcnt", HasPOPCNT) 1219 .Case("prefetchwt1", HasPREFETCHWT1) 1220 .Case("prfchw", HasPRFCHW) 1221 .Case("rdrnd", HasRDRND) 1222 .Case("rdseed", HasRDSEED) 1223 .Case("rtm", HasRTM) 1224 .Case("sgx", HasSGX) 1225 .Case("sha", HasSHA) 1226 .Case("sse", SSELevel >= SSE1) 1227 .Case("sse2", SSELevel >= SSE2) 1228 .Case("sse3", SSELevel >= SSE3) 1229 .Case("ssse3", SSELevel >= SSSE3) 1230 .Case("sse4.1", SSELevel >= SSE41) 1231 .Case("sse4.2", SSELevel >= SSE42) 1232 .Case("sse4a", XOPLevel >= SSE4A) 1233 .Case("tbm", HasTBM) 1234 .Case("x86", true) 1235 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1236 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1237 .Case("xop", XOPLevel >= XOP) 1238 .Case("xsave", HasXSAVE) 1239 .Case("xsavec", HasXSAVEC) 1240 .Case("xsaves", HasXSAVES) 1241 .Case("xsaveopt", HasXSAVEOPT) 1242 .Default(false); 1243 } 1244 1245 // We can't use a generic validation scheme for the features accepted here 1246 // versus subtarget features accepted in the target attribute because the 1247 // bitfield structure that's initialized in the runtime only supports the 1248 // below currently rather than the full range of subtarget features. (See 1249 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1250 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1251 return llvm::StringSwitch<bool>(FeatureStr) 1252 .Case("cmov", true) 1253 .Case("mmx", true) 1254 .Case("popcnt", true) 1255 .Case("sse", true) 1256 .Case("sse2", true) 1257 .Case("sse3", true) 1258 .Case("ssse3", true) 1259 .Case("sse4.1", true) 1260 .Case("sse4.2", true) 1261 .Case("avx", true) 1262 .Case("avx2", true) 1263 .Case("sse4a", true) 1264 .Case("fma4", true) 1265 .Case("xop", true) 1266 .Case("fma", true) 1267 .Case("avx512f", true) 1268 .Case("bmi", true) 1269 .Case("bmi2", true) 1270 .Case("aes", true) 1271 .Case("pclmul", true) 1272 .Case("avx512vl", true) 1273 .Case("avx512bw", true) 1274 .Case("avx512dq", true) 1275 .Case("avx512cd", true) 1276 .Case("avx512er", true) 1277 .Case("avx512pf", true) 1278 .Case("avx512vbmi", true) 1279 .Case("avx512ifma", true) 1280 .Case("avx5124vnniw", true) 1281 .Case("avx5124fmaps", true) 1282 .Case("avx512vpopcntdq", true) 1283 .Default(false); 1284 } 1285 1286 // We can't use a generic validation scheme for the cpus accepted here 1287 // versus subtarget cpus accepted in the target attribute because the 1288 // variables intitialized by the runtime only support the below currently 1289 // rather than the full range of cpus. 1290 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1291 return llvm::StringSwitch<bool>(FeatureStr) 1292 .Case("amd", true) 1293 .Case("amdfam10h", true) 1294 .Case("amdfam15h", true) 1295 .Case("atom", true) 1296 .Case("barcelona", true) 1297 .Case("bdver1", true) 1298 .Case("bdver2", true) 1299 .Case("bdver3", true) 1300 .Case("bdver4", true) 1301 .Case("bonnell", true) 1302 .Case("broadwell", true) 1303 .Case("btver1", true) 1304 .Case("btver2", true) 1305 .Case("core2", true) 1306 .Case("corei7", true) 1307 .Case("haswell", true) 1308 .Case("intel", true) 1309 .Case("istanbul", true) 1310 .Case("ivybridge", true) 1311 .Case("knl", true) 1312 .Case("nehalem", true) 1313 .Case("sandybridge", true) 1314 .Case("shanghai", true) 1315 .Case("silvermont", true) 1316 .Case("skylake", true) 1317 .Case("skylake-avx512", true) 1318 .Case("slm", true) 1319 .Case("westmere", true) 1320 .Case("znver1", true) 1321 .Default(false); 1322 } 1323 1324 bool X86TargetInfo::validateAsmConstraint( 1325 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1326 switch (*Name) { 1327 default: 1328 return false; 1329 // Constant constraints. 1330 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1331 // instructions. 1332 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1333 // x86_64 instructions. 1334 case 's': 1335 Info.setRequiresImmediate(); 1336 return true; 1337 case 'I': 1338 Info.setRequiresImmediate(0, 31); 1339 return true; 1340 case 'J': 1341 Info.setRequiresImmediate(0, 63); 1342 return true; 1343 case 'K': 1344 Info.setRequiresImmediate(-128, 127); 1345 return true; 1346 case 'L': 1347 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1348 return true; 1349 case 'M': 1350 Info.setRequiresImmediate(0, 3); 1351 return true; 1352 case 'N': 1353 Info.setRequiresImmediate(0, 255); 1354 return true; 1355 case 'O': 1356 Info.setRequiresImmediate(0, 127); 1357 return true; 1358 // Register constraints. 1359 case 'Y': // 'Y' is the first character for several 2-character constraints. 1360 // Shift the pointer to the second character of the constraint. 1361 Name++; 1362 switch (*Name) { 1363 default: 1364 return false; 1365 case 'z': 1366 case '0': // First SSE register. 1367 case '2': 1368 case 't': // Any SSE register, when SSE2 is enabled. 1369 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1370 case 'm': // Any MMX register, when inter-unit moves enabled. 1371 case 'k': // AVX512 arch mask registers: k1-k7. 1372 Info.setAllowsRegister(); 1373 return true; 1374 } 1375 case 'f': // Any x87 floating point stack register. 1376 // Constraint 'f' cannot be used for output operands. 1377 if (Info.ConstraintStr[0] == '=') 1378 return false; 1379 Info.setAllowsRegister(); 1380 return true; 1381 case 'a': // eax. 1382 case 'b': // ebx. 1383 case 'c': // ecx. 1384 case 'd': // edx. 1385 case 'S': // esi. 1386 case 'D': // edi. 1387 case 'A': // edx:eax. 1388 case 't': // Top of floating point stack. 1389 case 'u': // Second from top of floating point stack. 1390 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1391 case 'y': // Any MMX register. 1392 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1393 case 'x': // Any SSE register. 1394 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1395 // for intermideate k reg operations). 1396 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1397 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1398 case 'l': // "Index" registers: any general register that can be used as an 1399 // index in a base+index memory access. 1400 Info.setAllowsRegister(); 1401 return true; 1402 // Floating point constant constraints. 1403 case 'C': // SSE floating point constant. 1404 case 'G': // x87 floating point constant. 1405 return true; 1406 } 1407 } 1408 1409 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1410 unsigned Size) const { 1411 // Strip off constraint modifiers. 1412 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1413 Constraint = Constraint.substr(1); 1414 1415 return validateOperandSize(Constraint, Size); 1416 } 1417 1418 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1419 unsigned Size) const { 1420 return validateOperandSize(Constraint, Size); 1421 } 1422 1423 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1424 unsigned Size) const { 1425 switch (Constraint[0]) { 1426 default: 1427 break; 1428 case 'k': 1429 // Registers k0-k7 (AVX512) size limit is 64 bit. 1430 case 'y': 1431 return Size <= 64; 1432 case 'f': 1433 case 't': 1434 case 'u': 1435 return Size <= 128; 1436 case 'Y': 1437 // 'Y' is the first character for several 2-character constraints. 1438 switch (Constraint[1]) { 1439 default: 1440 return false; 1441 case 'm': 1442 // 'Ym' is synonymous with 'y'. 1443 case 'k': 1444 return Size <= 64; 1445 case 'z': 1446 case '0': 1447 // XMM0 1448 if (SSELevel >= SSE1) 1449 return Size <= 128U; 1450 return false; 1451 case 'i': 1452 case 't': 1453 case '2': 1454 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1455 if (SSELevel < SSE2) 1456 return false; 1457 break; 1458 } 1459 case 'v': 1460 case 'x': 1461 if (SSELevel >= AVX512F) 1462 // 512-bit zmm registers can be used if target supports AVX512F. 1463 return Size <= 512U; 1464 else if (SSELevel >= AVX) 1465 // 256-bit ymm registers can be used if target supports AVX. 1466 return Size <= 256U; 1467 return Size <= 128U; 1468 1469 } 1470 1471 return true; 1472 } 1473 1474 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1475 switch (*Constraint) { 1476 case 'a': 1477 return std::string("{ax}"); 1478 case 'b': 1479 return std::string("{bx}"); 1480 case 'c': 1481 return std::string("{cx}"); 1482 case 'd': 1483 return std::string("{dx}"); 1484 case 'S': 1485 return std::string("{si}"); 1486 case 'D': 1487 return std::string("{di}"); 1488 case 'p': // address 1489 return std::string("im"); 1490 case 't': // top of floating point stack. 1491 return std::string("{st}"); 1492 case 'u': // second from top of floating point stack. 1493 return std::string("{st(1)}"); // second from top of floating point stack. 1494 case 'Y': 1495 switch (Constraint[1]) { 1496 default: 1497 // Break from inner switch and fall through (copy single char), 1498 // continue parsing after copying the current constraint into 1499 // the return string. 1500 break; 1501 case 'k': 1502 case 'm': 1503 case 'i': 1504 case 't': 1505 case 'z': 1506 case '0': 1507 case '2': 1508 // "^" hints llvm that this is a 2 letter constraint. 1509 // "Constraint++" is used to promote the string iterator 1510 // to the next constraint. 1511 return std::string("^") + std::string(Constraint++, 2); 1512 } 1513 LLVM_FALLTHROUGH; 1514 default: 1515 return std::string(1, *Constraint); 1516 } 1517 } 1518 1519 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1520 return llvm::StringSwitch<CPUKind>(CPU) 1521 .Case("i386", CK_i386) 1522 .Case("i486", CK_i486) 1523 .Case("winchip-c6", CK_WinChipC6) 1524 .Case("winchip2", CK_WinChip2) 1525 .Case("c3", CK_C3) 1526 .Case("i586", CK_i586) 1527 .Case("pentium", CK_Pentium) 1528 .Case("pentium-mmx", CK_PentiumMMX) 1529 .Case("i686", CK_i686) 1530 .Case("pentiumpro", CK_PentiumPro) 1531 .Case("pentium2", CK_Pentium2) 1532 .Cases("pentium3", "pentium3m", CK_Pentium3) 1533 .Case("pentium-m", CK_PentiumM) 1534 .Case("c3-2", CK_C3_2) 1535 .Case("yonah", CK_Yonah) 1536 .Cases("pentium4", "pentium4m", CK_Pentium4) 1537 .Case("prescott", CK_Prescott) 1538 .Case("nocona", CK_Nocona) 1539 .Case("core2", CK_Core2) 1540 .Case("penryn", CK_Penryn) 1541 .Cases("bonnell", "atom", CK_Bonnell) 1542 .Cases("silvermont", "slm", CK_Silvermont) 1543 .Case("goldmont", CK_Goldmont) 1544 .Cases("nehalem", "corei7", CK_Nehalem) 1545 .Case("westmere", CK_Westmere) 1546 .Cases("sandybridge", "corei7-avx", CK_SandyBridge) 1547 .Cases("ivybridge", "core-avx-i", CK_IvyBridge) 1548 .Cases("haswell", "core-avx2", CK_Haswell) 1549 .Case("broadwell", CK_Broadwell) 1550 .Case("skylake", CK_SkylakeClient) 1551 .Cases("skylake-avx512", "skx", CK_SkylakeServer) 1552 .Case("cannonlake", CK_Cannonlake) 1553 .Case("knl", CK_KNL) 1554 .Case("lakemont", CK_Lakemont) 1555 .Case("k6", CK_K6) 1556 .Case("k6-2", CK_K6_2) 1557 .Case("k6-3", CK_K6_3) 1558 .Cases("athlon", "athlon-tbird", CK_Athlon) 1559 .Cases("athlon-xp", "athlon-mp", "athlon-4", CK_AthlonXP) 1560 .Cases("k8", "athlon64", "athlon-fx", "opteron", CK_K8) 1561 .Cases("k8-sse3", "athlon64-sse3", "opteron-sse3", CK_K8SSE3) 1562 .Cases("amdfam10", "barcelona", CK_AMDFAM10) 1563 .Case("btver1", CK_BTVER1) 1564 .Case("btver2", CK_BTVER2) 1565 .Case("bdver1", CK_BDVER1) 1566 .Case("bdver2", CK_BDVER2) 1567 .Case("bdver3", CK_BDVER3) 1568 .Case("bdver4", CK_BDVER4) 1569 .Case("znver1", CK_ZNVER1) 1570 .Case("x86-64", CK_x86_64) 1571 .Case("geode", CK_Geode) 1572 .Default(CK_Generic); 1573 } 1574 1575 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1576 return llvm::makeArrayRef(GCCRegNames); 1577 } 1578 1579 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1580 return llvm::makeArrayRef(AddlRegNames); 1581 } 1582 1583 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1584 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1585 Builtin::FirstTSBuiltin + 1); 1586 } 1587 1588 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1589 return llvm::makeArrayRef(BuiltinInfoX86, 1590 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1591 } 1592