1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 }; 62 63 const TargetInfo::AddlRegName AddlRegNames[] = { 64 {{"al", "ah", "eax", "rax"}, 0}, 65 {{"bl", "bh", "ebx", "rbx"}, 3}, 66 {{"cl", "ch", "ecx", "rcx"}, 2}, 67 {{"dl", "dh", "edx", "rdx"}, 1}, 68 {{"esi", "rsi"}, 4}, 69 {{"edi", "rdi"}, 5}, 70 {{"esp", "rsp"}, 7}, 71 {{"ebp", "rbp"}, 6}, 72 {{"r8d", "r8w", "r8b"}, 38}, 73 {{"r9d", "r9w", "r9b"}, 39}, 74 {{"r10d", "r10w", "r10b"}, 40}, 75 {{"r11d", "r11w", "r11b"}, 41}, 76 {{"r12d", "r12w", "r12b"}, 42}, 77 {{"r13d", "r13w", "r13b"}, 43}, 78 {{"r14d", "r14w", "r14b"}, 44}, 79 {{"r15d", "r15w", "r15b"}, 45}, 80 }; 81 82 } // namespace targets 83 } // namespace clang 84 85 using namespace clang; 86 using namespace clang::targets; 87 88 bool X86TargetInfo::setFPMath(StringRef Name) { 89 if (Name == "387") { 90 FPMath = FP_387; 91 return true; 92 } 93 if (Name == "sse") { 94 FPMath = FP_SSE; 95 return true; 96 } 97 return false; 98 } 99 100 bool X86TargetInfo::initFeatureMap( 101 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 102 const std::vector<std::string> &FeaturesVec) const { 103 // FIXME: This *really* should not be here. 104 // X86_64 always has SSE2. 105 if (getTriple().getArch() == llvm::Triple::x86_64) 106 setFeatureEnabledImpl(Features, "sse2", true); 107 108 const CPUKind Kind = getCPUKind(CPU); 109 110 // Enable X87 for all X86 processors but Lakemont. 111 if (Kind != CK_Lakemont) 112 setFeatureEnabledImpl(Features, "x87", true); 113 114 switch (Kind) { 115 case CK_Generic: 116 case CK_i386: 117 case CK_i486: 118 case CK_i586: 119 case CK_Pentium: 120 case CK_i686: 121 case CK_PentiumPro: 122 case CK_Lakemont: 123 break; 124 case CK_PentiumMMX: 125 case CK_Pentium2: 126 case CK_K6: 127 case CK_WinChipC6: 128 setFeatureEnabledImpl(Features, "mmx", true); 129 break; 130 case CK_Pentium3: 131 case CK_Pentium3M: 132 case CK_C3_2: 133 setFeatureEnabledImpl(Features, "sse", true); 134 setFeatureEnabledImpl(Features, "fxsr", true); 135 break; 136 case CK_PentiumM: 137 case CK_Pentium4: 138 case CK_Pentium4M: 139 case CK_x86_64: 140 setFeatureEnabledImpl(Features, "sse2", true); 141 setFeatureEnabledImpl(Features, "fxsr", true); 142 break; 143 case CK_Yonah: 144 case CK_Prescott: 145 case CK_Nocona: 146 setFeatureEnabledImpl(Features, "sse3", true); 147 setFeatureEnabledImpl(Features, "fxsr", true); 148 setFeatureEnabledImpl(Features, "cx16", true); 149 break; 150 case CK_Core2: 151 setFeatureEnabledImpl(Features, "ssse3", true); 152 setFeatureEnabledImpl(Features, "fxsr", true); 153 setFeatureEnabledImpl(Features, "cx16", true); 154 break; 155 case CK_Penryn: 156 setFeatureEnabledImpl(Features, "sse4.1", true); 157 setFeatureEnabledImpl(Features, "fxsr", true); 158 setFeatureEnabledImpl(Features, "cx16", true); 159 break; 160 case CK_Cannonlake: 161 setFeatureEnabledImpl(Features, "avx512ifma", true); 162 setFeatureEnabledImpl(Features, "avx512vbmi", true); 163 setFeatureEnabledImpl(Features, "sha", true); 164 LLVM_FALLTHROUGH; 165 case CK_SkylakeServer: 166 setFeatureEnabledImpl(Features, "avx512f", true); 167 setFeatureEnabledImpl(Features, "avx512cd", true); 168 setFeatureEnabledImpl(Features, "avx512dq", true); 169 setFeatureEnabledImpl(Features, "avx512bw", true); 170 setFeatureEnabledImpl(Features, "avx512vl", true); 171 setFeatureEnabledImpl(Features, "pku", true); 172 setFeatureEnabledImpl(Features, "clwb", true); 173 LLVM_FALLTHROUGH; 174 case CK_SkylakeClient: 175 setFeatureEnabledImpl(Features, "xsavec", true); 176 setFeatureEnabledImpl(Features, "xsaves", true); 177 setFeatureEnabledImpl(Features, "mpx", true); 178 setFeatureEnabledImpl(Features, "sgx", true); 179 setFeatureEnabledImpl(Features, "clflushopt", true); 180 setFeatureEnabledImpl(Features, "rtm", true); 181 LLVM_FALLTHROUGH; 182 case CK_Broadwell: 183 setFeatureEnabledImpl(Features, "rdseed", true); 184 setFeatureEnabledImpl(Features, "adx", true); 185 LLVM_FALLTHROUGH; 186 case CK_Haswell: 187 setFeatureEnabledImpl(Features, "avx2", true); 188 setFeatureEnabledImpl(Features, "lzcnt", true); 189 setFeatureEnabledImpl(Features, "bmi", true); 190 setFeatureEnabledImpl(Features, "bmi2", true); 191 setFeatureEnabledImpl(Features, "fma", true); 192 setFeatureEnabledImpl(Features, "movbe", true); 193 LLVM_FALLTHROUGH; 194 case CK_IvyBridge: 195 setFeatureEnabledImpl(Features, "rdrnd", true); 196 setFeatureEnabledImpl(Features, "f16c", true); 197 setFeatureEnabledImpl(Features, "fsgsbase", true); 198 LLVM_FALLTHROUGH; 199 case CK_SandyBridge: 200 setFeatureEnabledImpl(Features, "avx", true); 201 setFeatureEnabledImpl(Features, "xsave", true); 202 setFeatureEnabledImpl(Features, "xsaveopt", true); 203 LLVM_FALLTHROUGH; 204 case CK_Westmere: 205 setFeatureEnabledImpl(Features, "aes", true); 206 setFeatureEnabledImpl(Features, "pclmul", true); 207 LLVM_FALLTHROUGH; 208 case CK_Nehalem: 209 setFeatureEnabledImpl(Features, "sse4.2", true); 210 setFeatureEnabledImpl(Features, "fxsr", true); 211 setFeatureEnabledImpl(Features, "cx16", true); 212 break; 213 case CK_Goldmont: 214 setFeatureEnabledImpl(Features, "sha", true); 215 setFeatureEnabledImpl(Features, "rdrnd", true); 216 setFeatureEnabledImpl(Features, "rdseed", true); 217 setFeatureEnabledImpl(Features, "xsave", true); 218 setFeatureEnabledImpl(Features, "xsaveopt", true); 219 setFeatureEnabledImpl(Features, "xsavec", true); 220 setFeatureEnabledImpl(Features, "xsaves", true); 221 setFeatureEnabledImpl(Features, "clflushopt", true); 222 setFeatureEnabledImpl(Features, "mpx", true); 223 LLVM_FALLTHROUGH; 224 case CK_Silvermont: 225 setFeatureEnabledImpl(Features, "aes", true); 226 setFeatureEnabledImpl(Features, "pclmul", true); 227 setFeatureEnabledImpl(Features, "sse4.2", true); 228 LLVM_FALLTHROUGH; 229 case CK_Bonnell: 230 setFeatureEnabledImpl(Features, "movbe", true); 231 setFeatureEnabledImpl(Features, "ssse3", true); 232 setFeatureEnabledImpl(Features, "fxsr", true); 233 setFeatureEnabledImpl(Features, "cx16", true); 234 break; 235 case CK_KNL: 236 setFeatureEnabledImpl(Features, "avx512f", true); 237 setFeatureEnabledImpl(Features, "avx512cd", true); 238 setFeatureEnabledImpl(Features, "avx512er", true); 239 setFeatureEnabledImpl(Features, "avx512pf", true); 240 setFeatureEnabledImpl(Features, "prefetchwt1", true); 241 setFeatureEnabledImpl(Features, "fxsr", true); 242 setFeatureEnabledImpl(Features, "rdseed", true); 243 setFeatureEnabledImpl(Features, "adx", true); 244 setFeatureEnabledImpl(Features, "lzcnt", true); 245 setFeatureEnabledImpl(Features, "bmi", true); 246 setFeatureEnabledImpl(Features, "bmi2", true); 247 setFeatureEnabledImpl(Features, "rtm", true); 248 setFeatureEnabledImpl(Features, "fma", true); 249 setFeatureEnabledImpl(Features, "rdrnd", true); 250 setFeatureEnabledImpl(Features, "f16c", true); 251 setFeatureEnabledImpl(Features, "fsgsbase", true); 252 setFeatureEnabledImpl(Features, "aes", true); 253 setFeatureEnabledImpl(Features, "pclmul", true); 254 setFeatureEnabledImpl(Features, "cx16", true); 255 setFeatureEnabledImpl(Features, "xsaveopt", true); 256 setFeatureEnabledImpl(Features, "xsave", true); 257 setFeatureEnabledImpl(Features, "movbe", true); 258 break; 259 case CK_K6_2: 260 case CK_K6_3: 261 case CK_WinChip2: 262 case CK_C3: 263 setFeatureEnabledImpl(Features, "3dnow", true); 264 break; 265 case CK_Athlon: 266 case CK_AthlonThunderbird: 267 case CK_Geode: 268 setFeatureEnabledImpl(Features, "3dnowa", true); 269 break; 270 case CK_Athlon4: 271 case CK_AthlonXP: 272 case CK_AthlonMP: 273 setFeatureEnabledImpl(Features, "sse", true); 274 setFeatureEnabledImpl(Features, "3dnowa", true); 275 setFeatureEnabledImpl(Features, "fxsr", true); 276 break; 277 case CK_K8: 278 case CK_Opteron: 279 case CK_Athlon64: 280 case CK_AthlonFX: 281 setFeatureEnabledImpl(Features, "sse2", true); 282 setFeatureEnabledImpl(Features, "3dnowa", true); 283 setFeatureEnabledImpl(Features, "fxsr", true); 284 break; 285 case CK_AMDFAM10: 286 setFeatureEnabledImpl(Features, "sse4a", true); 287 setFeatureEnabledImpl(Features, "lzcnt", true); 288 setFeatureEnabledImpl(Features, "popcnt", true); 289 LLVM_FALLTHROUGH; 290 case CK_K8SSE3: 291 case CK_OpteronSSE3: 292 case CK_Athlon64SSE3: 293 setFeatureEnabledImpl(Features, "sse3", true); 294 setFeatureEnabledImpl(Features, "3dnowa", true); 295 setFeatureEnabledImpl(Features, "fxsr", true); 296 break; 297 case CK_BTVER2: 298 setFeatureEnabledImpl(Features, "avx", true); 299 setFeatureEnabledImpl(Features, "aes", true); 300 setFeatureEnabledImpl(Features, "pclmul", true); 301 setFeatureEnabledImpl(Features, "bmi", true); 302 setFeatureEnabledImpl(Features, "f16c", true); 303 setFeatureEnabledImpl(Features, "xsaveopt", true); 304 setFeatureEnabledImpl(Features, "movbe", true); 305 LLVM_FALLTHROUGH; 306 case CK_BTVER1: 307 setFeatureEnabledImpl(Features, "ssse3", true); 308 setFeatureEnabledImpl(Features, "sse4a", true); 309 setFeatureEnabledImpl(Features, "lzcnt", true); 310 setFeatureEnabledImpl(Features, "popcnt", true); 311 setFeatureEnabledImpl(Features, "prfchw", true); 312 setFeatureEnabledImpl(Features, "cx16", true); 313 setFeatureEnabledImpl(Features, "fxsr", true); 314 break; 315 case CK_ZNVER1: 316 setFeatureEnabledImpl(Features, "adx", true); 317 setFeatureEnabledImpl(Features, "aes", true); 318 setFeatureEnabledImpl(Features, "avx2", true); 319 setFeatureEnabledImpl(Features, "bmi", true); 320 setFeatureEnabledImpl(Features, "bmi2", true); 321 setFeatureEnabledImpl(Features, "clflushopt", true); 322 setFeatureEnabledImpl(Features, "clzero", true); 323 setFeatureEnabledImpl(Features, "cx16", true); 324 setFeatureEnabledImpl(Features, "f16c", true); 325 setFeatureEnabledImpl(Features, "fma", true); 326 setFeatureEnabledImpl(Features, "fsgsbase", true); 327 setFeatureEnabledImpl(Features, "fxsr", true); 328 setFeatureEnabledImpl(Features, "lzcnt", true); 329 setFeatureEnabledImpl(Features, "mwaitx", true); 330 setFeatureEnabledImpl(Features, "movbe", true); 331 setFeatureEnabledImpl(Features, "pclmul", true); 332 setFeatureEnabledImpl(Features, "popcnt", true); 333 setFeatureEnabledImpl(Features, "prfchw", true); 334 setFeatureEnabledImpl(Features, "rdrnd", true); 335 setFeatureEnabledImpl(Features, "rdseed", true); 336 setFeatureEnabledImpl(Features, "sha", true); 337 setFeatureEnabledImpl(Features, "sse4a", true); 338 setFeatureEnabledImpl(Features, "xsave", true); 339 setFeatureEnabledImpl(Features, "xsavec", true); 340 setFeatureEnabledImpl(Features, "xsaveopt", true); 341 setFeatureEnabledImpl(Features, "xsaves", true); 342 break; 343 case CK_BDVER4: 344 setFeatureEnabledImpl(Features, "avx2", true); 345 setFeatureEnabledImpl(Features, "bmi2", true); 346 setFeatureEnabledImpl(Features, "mwaitx", true); 347 LLVM_FALLTHROUGH; 348 case CK_BDVER3: 349 setFeatureEnabledImpl(Features, "fsgsbase", true); 350 setFeatureEnabledImpl(Features, "xsaveopt", true); 351 LLVM_FALLTHROUGH; 352 case CK_BDVER2: 353 setFeatureEnabledImpl(Features, "bmi", true); 354 setFeatureEnabledImpl(Features, "fma", true); 355 setFeatureEnabledImpl(Features, "f16c", true); 356 setFeatureEnabledImpl(Features, "tbm", true); 357 LLVM_FALLTHROUGH; 358 case CK_BDVER1: 359 // xop implies avx, sse4a and fma4. 360 setFeatureEnabledImpl(Features, "xop", true); 361 setFeatureEnabledImpl(Features, "lwp", true); 362 setFeatureEnabledImpl(Features, "lzcnt", true); 363 setFeatureEnabledImpl(Features, "aes", true); 364 setFeatureEnabledImpl(Features, "pclmul", true); 365 setFeatureEnabledImpl(Features, "prfchw", true); 366 setFeatureEnabledImpl(Features, "cx16", true); 367 setFeatureEnabledImpl(Features, "fxsr", true); 368 setFeatureEnabledImpl(Features, "xsave", true); 369 break; 370 } 371 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 372 return false; 373 374 // Can't do this earlier because we need to be able to explicitly enable 375 // or disable these features and the things that they depend upon. 376 377 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 378 auto I = Features.find("sse4.2"); 379 if (I != Features.end() && I->getValue() && 380 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 381 FeaturesVec.end()) 382 Features["popcnt"] = true; 383 384 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 385 I = Features.find("3dnow"); 386 if (I != Features.end() && I->getValue() && 387 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 388 FeaturesVec.end()) 389 Features["prfchw"] = true; 390 391 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 392 // then enable MMX. 393 I = Features.find("sse"); 394 if (I != Features.end() && I->getValue() && 395 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 396 FeaturesVec.end()) 397 Features["mmx"] = true; 398 399 return true; 400 } 401 402 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 403 X86SSEEnum Level, bool Enabled) { 404 if (Enabled) { 405 switch (Level) { 406 case AVX512F: 407 Features["avx512f"] = true; 408 LLVM_FALLTHROUGH; 409 case AVX2: 410 Features["avx2"] = true; 411 LLVM_FALLTHROUGH; 412 case AVX: 413 Features["avx"] = true; 414 Features["xsave"] = true; 415 LLVM_FALLTHROUGH; 416 case SSE42: 417 Features["sse4.2"] = true; 418 LLVM_FALLTHROUGH; 419 case SSE41: 420 Features["sse4.1"] = true; 421 LLVM_FALLTHROUGH; 422 case SSSE3: 423 Features["ssse3"] = true; 424 LLVM_FALLTHROUGH; 425 case SSE3: 426 Features["sse3"] = true; 427 LLVM_FALLTHROUGH; 428 case SSE2: 429 Features["sse2"] = true; 430 LLVM_FALLTHROUGH; 431 case SSE1: 432 Features["sse"] = true; 433 LLVM_FALLTHROUGH; 434 case NoSSE: 435 break; 436 } 437 return; 438 } 439 440 switch (Level) { 441 case NoSSE: 442 case SSE1: 443 Features["sse"] = false; 444 LLVM_FALLTHROUGH; 445 case SSE2: 446 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 447 false; 448 LLVM_FALLTHROUGH; 449 case SSE3: 450 Features["sse3"] = false; 451 setXOPLevel(Features, NoXOP, false); 452 LLVM_FALLTHROUGH; 453 case SSSE3: 454 Features["ssse3"] = false; 455 LLVM_FALLTHROUGH; 456 case SSE41: 457 Features["sse4.1"] = false; 458 LLVM_FALLTHROUGH; 459 case SSE42: 460 Features["sse4.2"] = false; 461 LLVM_FALLTHROUGH; 462 case AVX: 463 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 464 Features["xsaveopt"] = false; 465 setXOPLevel(Features, FMA4, false); 466 LLVM_FALLTHROUGH; 467 case AVX2: 468 Features["avx2"] = false; 469 LLVM_FALLTHROUGH; 470 case AVX512F: 471 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 472 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 473 Features["avx512vl"] = Features["avx512vbmi"] = 474 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 475 break; 476 } 477 } 478 479 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 480 MMX3DNowEnum Level, bool Enabled) { 481 if (Enabled) { 482 switch (Level) { 483 case AMD3DNowAthlon: 484 Features["3dnowa"] = true; 485 LLVM_FALLTHROUGH; 486 case AMD3DNow: 487 Features["3dnow"] = true; 488 LLVM_FALLTHROUGH; 489 case MMX: 490 Features["mmx"] = true; 491 LLVM_FALLTHROUGH; 492 case NoMMX3DNow: 493 break; 494 } 495 return; 496 } 497 498 switch (Level) { 499 case NoMMX3DNow: 500 case MMX: 501 Features["mmx"] = false; 502 LLVM_FALLTHROUGH; 503 case AMD3DNow: 504 Features["3dnow"] = false; 505 LLVM_FALLTHROUGH; 506 case AMD3DNowAthlon: 507 Features["3dnowa"] = false; 508 break; 509 } 510 } 511 512 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 513 bool Enabled) { 514 if (Enabled) { 515 switch (Level) { 516 case XOP: 517 Features["xop"] = true; 518 LLVM_FALLTHROUGH; 519 case FMA4: 520 Features["fma4"] = true; 521 setSSELevel(Features, AVX, true); 522 LLVM_FALLTHROUGH; 523 case SSE4A: 524 Features["sse4a"] = true; 525 setSSELevel(Features, SSE3, true); 526 LLVM_FALLTHROUGH; 527 case NoXOP: 528 break; 529 } 530 return; 531 } 532 533 switch (Level) { 534 case NoXOP: 535 case SSE4A: 536 Features["sse4a"] = false; 537 LLVM_FALLTHROUGH; 538 case FMA4: 539 Features["fma4"] = false; 540 LLVM_FALLTHROUGH; 541 case XOP: 542 Features["xop"] = false; 543 break; 544 } 545 } 546 547 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 548 StringRef Name, bool Enabled) { 549 // This is a bit of a hack to deal with the sse4 target feature when used 550 // as part of the target attribute. We handle sse4 correctly everywhere 551 // else. See below for more information on how we handle the sse4 options. 552 if (Name != "sse4") 553 Features[Name] = Enabled; 554 555 if (Name == "mmx") { 556 setMMXLevel(Features, MMX, Enabled); 557 } else if (Name == "sse") { 558 setSSELevel(Features, SSE1, Enabled); 559 } else if (Name == "sse2") { 560 setSSELevel(Features, SSE2, Enabled); 561 } else if (Name == "sse3") { 562 setSSELevel(Features, SSE3, Enabled); 563 } else if (Name == "ssse3") { 564 setSSELevel(Features, SSSE3, Enabled); 565 } else if (Name == "sse4.2") { 566 setSSELevel(Features, SSE42, Enabled); 567 } else if (Name == "sse4.1") { 568 setSSELevel(Features, SSE41, Enabled); 569 } else if (Name == "3dnow") { 570 setMMXLevel(Features, AMD3DNow, Enabled); 571 } else if (Name == "3dnowa") { 572 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 573 } else if (Name == "aes") { 574 if (Enabled) 575 setSSELevel(Features, SSE2, Enabled); 576 } else if (Name == "pclmul") { 577 if (Enabled) 578 setSSELevel(Features, SSE2, Enabled); 579 } else if (Name == "avx") { 580 setSSELevel(Features, AVX, Enabled); 581 } else if (Name == "avx2") { 582 setSSELevel(Features, AVX2, Enabled); 583 } else if (Name == "avx512f") { 584 setSSELevel(Features, AVX512F, Enabled); 585 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 586 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 587 Name == "avx512vbmi" || Name == "avx512ifma" || 588 Name == "avx512vpopcntdq") { 589 if (Enabled) 590 setSSELevel(Features, AVX512F, Enabled); 591 // Enable BWI instruction if VBMI is being enabled. 592 if (Name == "avx512vbmi" && Enabled) 593 Features["avx512bw"] = true; 594 // Also disable VBMI if BWI is being disabled. 595 if (Name == "avx512bw" && !Enabled) 596 Features["avx512vbmi"] = false; 597 } else if (Name == "fma") { 598 if (Enabled) 599 setSSELevel(Features, AVX, Enabled); 600 } else if (Name == "fma4") { 601 setXOPLevel(Features, FMA4, Enabled); 602 } else if (Name == "xop") { 603 setXOPLevel(Features, XOP, Enabled); 604 } else if (Name == "sse4a") { 605 setXOPLevel(Features, SSE4A, Enabled); 606 } else if (Name == "f16c") { 607 if (Enabled) 608 setSSELevel(Features, AVX, Enabled); 609 } else if (Name == "sha") { 610 if (Enabled) 611 setSSELevel(Features, SSE2, Enabled); 612 } else if (Name == "sse4") { 613 // We can get here via the __target__ attribute since that's not controlled 614 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 615 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 616 // disabled. 617 if (Enabled) 618 setSSELevel(Features, SSE42, Enabled); 619 else 620 setSSELevel(Features, SSE41, Enabled); 621 } else if (Name == "xsave") { 622 if (!Enabled) 623 Features["xsaveopt"] = false; 624 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 625 if (Enabled) 626 Features["xsave"] = true; 627 } 628 } 629 630 /// handleTargetFeatures - Perform initialization based on the user 631 /// configured set of features. 632 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 633 DiagnosticsEngine &Diags) { 634 for (const auto &Feature : Features) { 635 if (Feature[0] != '+') 636 continue; 637 638 if (Feature == "+aes") { 639 HasAES = true; 640 } else if (Feature == "+pclmul") { 641 HasPCLMUL = true; 642 } else if (Feature == "+lzcnt") { 643 HasLZCNT = true; 644 } else if (Feature == "+rdrnd") { 645 HasRDRND = true; 646 } else if (Feature == "+fsgsbase") { 647 HasFSGSBASE = true; 648 } else if (Feature == "+bmi") { 649 HasBMI = true; 650 } else if (Feature == "+bmi2") { 651 HasBMI2 = true; 652 } else if (Feature == "+popcnt") { 653 HasPOPCNT = true; 654 } else if (Feature == "+rtm") { 655 HasRTM = true; 656 } else if (Feature == "+prfchw") { 657 HasPRFCHW = true; 658 } else if (Feature == "+rdseed") { 659 HasRDSEED = true; 660 } else if (Feature == "+adx") { 661 HasADX = true; 662 } else if (Feature == "+tbm") { 663 HasTBM = true; 664 } else if (Feature == "+lwp") { 665 HasLWP = true; 666 } else if (Feature == "+fma") { 667 HasFMA = true; 668 } else if (Feature == "+f16c") { 669 HasF16C = true; 670 } else if (Feature == "+avx512cd") { 671 HasAVX512CD = true; 672 } else if (Feature == "+avx512vpopcntdq") { 673 HasAVX512VPOPCNTDQ = true; 674 } else if (Feature == "+avx512er") { 675 HasAVX512ER = true; 676 } else if (Feature == "+avx512pf") { 677 HasAVX512PF = true; 678 } else if (Feature == "+avx512dq") { 679 HasAVX512DQ = true; 680 } else if (Feature == "+avx512bw") { 681 HasAVX512BW = true; 682 } else if (Feature == "+avx512vl") { 683 HasAVX512VL = true; 684 } else if (Feature == "+avx512vbmi") { 685 HasAVX512VBMI = true; 686 } else if (Feature == "+avx512ifma") { 687 HasAVX512IFMA = true; 688 } else if (Feature == "+sha") { 689 HasSHA = true; 690 } else if (Feature == "+mpx") { 691 HasMPX = true; 692 } else if (Feature == "+movbe") { 693 HasMOVBE = true; 694 } else if (Feature == "+sgx") { 695 HasSGX = true; 696 } else if (Feature == "+cx16") { 697 HasCX16 = true; 698 } else if (Feature == "+fxsr") { 699 HasFXSR = true; 700 } else if (Feature == "+xsave") { 701 HasXSAVE = true; 702 } else if (Feature == "+xsaveopt") { 703 HasXSAVEOPT = true; 704 } else if (Feature == "+xsavec") { 705 HasXSAVEC = true; 706 } else if (Feature == "+xsaves") { 707 HasXSAVES = true; 708 } else if (Feature == "+mwaitx") { 709 HasMWAITX = true; 710 } else if (Feature == "+pku") { 711 HasPKU = true; 712 } else if (Feature == "+clflushopt") { 713 HasCLFLUSHOPT = true; 714 } else if (Feature == "+clwb") { 715 HasCLWB = true; 716 } else if (Feature == "+prefetchwt1") { 717 HasPREFETCHWT1 = true; 718 } else if (Feature == "+clzero") { 719 HasCLZERO = true; 720 } 721 722 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 723 .Case("+avx512f", AVX512F) 724 .Case("+avx2", AVX2) 725 .Case("+avx", AVX) 726 .Case("+sse4.2", SSE42) 727 .Case("+sse4.1", SSE41) 728 .Case("+ssse3", SSSE3) 729 .Case("+sse3", SSE3) 730 .Case("+sse2", SSE2) 731 .Case("+sse", SSE1) 732 .Default(NoSSE); 733 SSELevel = std::max(SSELevel, Level); 734 735 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 736 .Case("+3dnowa", AMD3DNowAthlon) 737 .Case("+3dnow", AMD3DNow) 738 .Case("+mmx", MMX) 739 .Default(NoMMX3DNow); 740 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 741 742 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 743 .Case("+xop", XOP) 744 .Case("+fma4", FMA4) 745 .Case("+sse4a", SSE4A) 746 .Default(NoXOP); 747 XOPLevel = std::max(XOPLevel, XLevel); 748 } 749 750 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 751 // matches the selected sse level. 752 if ((FPMath == FP_SSE && SSELevel < SSE1) || 753 (FPMath == FP_387 && SSELevel >= SSE1)) { 754 Diags.Report(diag::err_target_unsupported_fpmath) 755 << (FPMath == FP_SSE ? "sse" : "387"); 756 return false; 757 } 758 759 SimdDefaultAlign = 760 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 761 return true; 762 } 763 764 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 765 /// definitions for this particular subtarget. 766 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 767 MacroBuilder &Builder) const { 768 // Target identification. 769 if (getTriple().getArch() == llvm::Triple::x86_64) { 770 Builder.defineMacro("__amd64__"); 771 Builder.defineMacro("__amd64"); 772 Builder.defineMacro("__x86_64"); 773 Builder.defineMacro("__x86_64__"); 774 if (getTriple().getArchName() == "x86_64h") { 775 Builder.defineMacro("__x86_64h"); 776 Builder.defineMacro("__x86_64h__"); 777 } 778 } else { 779 DefineStd(Builder, "i386", Opts); 780 } 781 782 // Subtarget options. 783 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 784 // truly should be based on -mtune options. 785 switch (CPU) { 786 case CK_Generic: 787 break; 788 case CK_i386: 789 // The rest are coming from the i386 define above. 790 Builder.defineMacro("__tune_i386__"); 791 break; 792 case CK_i486: 793 case CK_WinChipC6: 794 case CK_WinChip2: 795 case CK_C3: 796 defineCPUMacros(Builder, "i486"); 797 break; 798 case CK_PentiumMMX: 799 Builder.defineMacro("__pentium_mmx__"); 800 Builder.defineMacro("__tune_pentium_mmx__"); 801 LLVM_FALLTHROUGH; 802 case CK_i586: 803 case CK_Pentium: 804 defineCPUMacros(Builder, "i586"); 805 defineCPUMacros(Builder, "pentium"); 806 break; 807 case CK_Pentium3: 808 case CK_Pentium3M: 809 case CK_PentiumM: 810 Builder.defineMacro("__tune_pentium3__"); 811 LLVM_FALLTHROUGH; 812 case CK_Pentium2: 813 case CK_C3_2: 814 Builder.defineMacro("__tune_pentium2__"); 815 LLVM_FALLTHROUGH; 816 case CK_PentiumPro: 817 Builder.defineMacro("__tune_i686__"); 818 Builder.defineMacro("__tune_pentiumpro__"); 819 LLVM_FALLTHROUGH; 820 case CK_i686: 821 Builder.defineMacro("__i686"); 822 Builder.defineMacro("__i686__"); 823 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 824 Builder.defineMacro("__pentiumpro"); 825 Builder.defineMacro("__pentiumpro__"); 826 break; 827 case CK_Pentium4: 828 case CK_Pentium4M: 829 defineCPUMacros(Builder, "pentium4"); 830 break; 831 case CK_Yonah: 832 case CK_Prescott: 833 case CK_Nocona: 834 defineCPUMacros(Builder, "nocona"); 835 break; 836 case CK_Core2: 837 case CK_Penryn: 838 defineCPUMacros(Builder, "core2"); 839 break; 840 case CK_Bonnell: 841 defineCPUMacros(Builder, "atom"); 842 break; 843 case CK_Silvermont: 844 defineCPUMacros(Builder, "slm"); 845 break; 846 case CK_Goldmont: 847 defineCPUMacros(Builder, "goldmont"); 848 break; 849 case CK_Nehalem: 850 case CK_Westmere: 851 case CK_SandyBridge: 852 case CK_IvyBridge: 853 case CK_Haswell: 854 case CK_Broadwell: 855 case CK_SkylakeClient: 856 // FIXME: Historically, we defined this legacy name, it would be nice to 857 // remove it at some point. We've never exposed fine-grained names for 858 // recent primary x86 CPUs, and we should keep it that way. 859 defineCPUMacros(Builder, "corei7"); 860 break; 861 case CK_SkylakeServer: 862 defineCPUMacros(Builder, "skx"); 863 break; 864 case CK_Cannonlake: 865 break; 866 case CK_KNL: 867 defineCPUMacros(Builder, "knl"); 868 break; 869 case CK_Lakemont: 870 Builder.defineMacro("__tune_lakemont__"); 871 break; 872 case CK_K6_2: 873 Builder.defineMacro("__k6_2__"); 874 Builder.defineMacro("__tune_k6_2__"); 875 LLVM_FALLTHROUGH; 876 case CK_K6_3: 877 if (CPU != CK_K6_2) { // In case of fallthrough 878 // FIXME: GCC may be enabling these in cases where some other k6 879 // architecture is specified but -m3dnow is explicitly provided. The 880 // exact semantics need to be determined and emulated here. 881 Builder.defineMacro("__k6_3__"); 882 Builder.defineMacro("__tune_k6_3__"); 883 } 884 LLVM_FALLTHROUGH; 885 case CK_K6: 886 defineCPUMacros(Builder, "k6"); 887 break; 888 case CK_Athlon: 889 case CK_AthlonThunderbird: 890 case CK_Athlon4: 891 case CK_AthlonXP: 892 case CK_AthlonMP: 893 defineCPUMacros(Builder, "athlon"); 894 if (SSELevel != NoSSE) { 895 Builder.defineMacro("__athlon_sse__"); 896 Builder.defineMacro("__tune_athlon_sse__"); 897 } 898 break; 899 case CK_K8: 900 case CK_K8SSE3: 901 case CK_x86_64: 902 case CK_Opteron: 903 case CK_OpteronSSE3: 904 case CK_Athlon64: 905 case CK_Athlon64SSE3: 906 case CK_AthlonFX: 907 defineCPUMacros(Builder, "k8"); 908 break; 909 case CK_AMDFAM10: 910 defineCPUMacros(Builder, "amdfam10"); 911 break; 912 case CK_BTVER1: 913 defineCPUMacros(Builder, "btver1"); 914 break; 915 case CK_BTVER2: 916 defineCPUMacros(Builder, "btver2"); 917 break; 918 case CK_BDVER1: 919 defineCPUMacros(Builder, "bdver1"); 920 break; 921 case CK_BDVER2: 922 defineCPUMacros(Builder, "bdver2"); 923 break; 924 case CK_BDVER3: 925 defineCPUMacros(Builder, "bdver3"); 926 break; 927 case CK_BDVER4: 928 defineCPUMacros(Builder, "bdver4"); 929 break; 930 case CK_ZNVER1: 931 defineCPUMacros(Builder, "znver1"); 932 break; 933 case CK_Geode: 934 defineCPUMacros(Builder, "geode"); 935 break; 936 } 937 938 // Target properties. 939 Builder.defineMacro("__REGISTER_PREFIX__", ""); 940 941 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 942 // functions in glibc header files that use FP Stack inline asm which the 943 // backend can't deal with (PR879). 944 Builder.defineMacro("__NO_MATH_INLINES"); 945 946 if (HasAES) 947 Builder.defineMacro("__AES__"); 948 949 if (HasPCLMUL) 950 Builder.defineMacro("__PCLMUL__"); 951 952 if (HasLZCNT) 953 Builder.defineMacro("__LZCNT__"); 954 955 if (HasRDRND) 956 Builder.defineMacro("__RDRND__"); 957 958 if (HasFSGSBASE) 959 Builder.defineMacro("__FSGSBASE__"); 960 961 if (HasBMI) 962 Builder.defineMacro("__BMI__"); 963 964 if (HasBMI2) 965 Builder.defineMacro("__BMI2__"); 966 967 if (HasPOPCNT) 968 Builder.defineMacro("__POPCNT__"); 969 970 if (HasRTM) 971 Builder.defineMacro("__RTM__"); 972 973 if (HasPRFCHW) 974 Builder.defineMacro("__PRFCHW__"); 975 976 if (HasRDSEED) 977 Builder.defineMacro("__RDSEED__"); 978 979 if (HasADX) 980 Builder.defineMacro("__ADX__"); 981 982 if (HasTBM) 983 Builder.defineMacro("__TBM__"); 984 985 if (HasLWP) 986 Builder.defineMacro("__LWP__"); 987 988 if (HasMWAITX) 989 Builder.defineMacro("__MWAITX__"); 990 991 switch (XOPLevel) { 992 case XOP: 993 Builder.defineMacro("__XOP__"); 994 LLVM_FALLTHROUGH; 995 case FMA4: 996 Builder.defineMacro("__FMA4__"); 997 LLVM_FALLTHROUGH; 998 case SSE4A: 999 Builder.defineMacro("__SSE4A__"); 1000 LLVM_FALLTHROUGH; 1001 case NoXOP: 1002 break; 1003 } 1004 1005 if (HasFMA) 1006 Builder.defineMacro("__FMA__"); 1007 1008 if (HasF16C) 1009 Builder.defineMacro("__F16C__"); 1010 1011 if (HasAVX512CD) 1012 Builder.defineMacro("__AVX512CD__"); 1013 if (HasAVX512VPOPCNTDQ) 1014 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1015 if (HasAVX512ER) 1016 Builder.defineMacro("__AVX512ER__"); 1017 if (HasAVX512PF) 1018 Builder.defineMacro("__AVX512PF__"); 1019 if (HasAVX512DQ) 1020 Builder.defineMacro("__AVX512DQ__"); 1021 if (HasAVX512BW) 1022 Builder.defineMacro("__AVX512BW__"); 1023 if (HasAVX512VL) 1024 Builder.defineMacro("__AVX512VL__"); 1025 if (HasAVX512VBMI) 1026 Builder.defineMacro("__AVX512VBMI__"); 1027 if (HasAVX512IFMA) 1028 Builder.defineMacro("__AVX512IFMA__"); 1029 1030 if (HasSHA) 1031 Builder.defineMacro("__SHA__"); 1032 1033 if (HasFXSR) 1034 Builder.defineMacro("__FXSR__"); 1035 if (HasXSAVE) 1036 Builder.defineMacro("__XSAVE__"); 1037 if (HasXSAVEOPT) 1038 Builder.defineMacro("__XSAVEOPT__"); 1039 if (HasXSAVEC) 1040 Builder.defineMacro("__XSAVEC__"); 1041 if (HasXSAVES) 1042 Builder.defineMacro("__XSAVES__"); 1043 if (HasPKU) 1044 Builder.defineMacro("__PKU__"); 1045 if (HasCX16) 1046 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1047 if (HasCLFLUSHOPT) 1048 Builder.defineMacro("__CLFLUSHOPT__"); 1049 if (HasCLWB) 1050 Builder.defineMacro("__CLWB__"); 1051 if (HasMPX) 1052 Builder.defineMacro("__MPX__"); 1053 if (HasSGX) 1054 Builder.defineMacro("__SGX__"); 1055 if (HasPREFETCHWT1) 1056 Builder.defineMacro("__PREFETCHWT1__"); 1057 if (HasCLZERO) 1058 Builder.defineMacro("__CLZERO__"); 1059 1060 // Each case falls through to the previous one here. 1061 switch (SSELevel) { 1062 case AVX512F: 1063 Builder.defineMacro("__AVX512F__"); 1064 LLVM_FALLTHROUGH; 1065 case AVX2: 1066 Builder.defineMacro("__AVX2__"); 1067 LLVM_FALLTHROUGH; 1068 case AVX: 1069 Builder.defineMacro("__AVX__"); 1070 LLVM_FALLTHROUGH; 1071 case SSE42: 1072 Builder.defineMacro("__SSE4_2__"); 1073 LLVM_FALLTHROUGH; 1074 case SSE41: 1075 Builder.defineMacro("__SSE4_1__"); 1076 LLVM_FALLTHROUGH; 1077 case SSSE3: 1078 Builder.defineMacro("__SSSE3__"); 1079 LLVM_FALLTHROUGH; 1080 case SSE3: 1081 Builder.defineMacro("__SSE3__"); 1082 LLVM_FALLTHROUGH; 1083 case SSE2: 1084 Builder.defineMacro("__SSE2__"); 1085 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1086 LLVM_FALLTHROUGH; 1087 case SSE1: 1088 Builder.defineMacro("__SSE__"); 1089 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1090 LLVM_FALLTHROUGH; 1091 case NoSSE: 1092 break; 1093 } 1094 1095 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1096 switch (SSELevel) { 1097 case AVX512F: 1098 case AVX2: 1099 case AVX: 1100 case SSE42: 1101 case SSE41: 1102 case SSSE3: 1103 case SSE3: 1104 case SSE2: 1105 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1106 break; 1107 case SSE1: 1108 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1109 break; 1110 default: 1111 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1112 break; 1113 } 1114 } 1115 1116 // Each case falls through to the previous one here. 1117 switch (MMX3DNowLevel) { 1118 case AMD3DNowAthlon: 1119 Builder.defineMacro("__3dNOW_A__"); 1120 LLVM_FALLTHROUGH; 1121 case AMD3DNow: 1122 Builder.defineMacro("__3dNOW__"); 1123 LLVM_FALLTHROUGH; 1124 case MMX: 1125 Builder.defineMacro("__MMX__"); 1126 LLVM_FALLTHROUGH; 1127 case NoMMX3DNow: 1128 break; 1129 } 1130 1131 if (CPU >= CK_i486) { 1132 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1133 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1134 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1135 } 1136 if (CPU >= CK_i586) 1137 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1138 1139 if (HasFloat128) 1140 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1141 } 1142 1143 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1144 return llvm::StringSwitch<bool>(Name) 1145 .Case("aes", true) 1146 .Case("avx", true) 1147 .Case("avx2", true) 1148 .Case("avx512f", true) 1149 .Case("avx512cd", true) 1150 .Case("avx512vpopcntdq", true) 1151 .Case("avx512er", true) 1152 .Case("avx512pf", true) 1153 .Case("avx512dq", true) 1154 .Case("avx512bw", true) 1155 .Case("avx512vl", true) 1156 .Case("avx512vbmi", true) 1157 .Case("avx512ifma", true) 1158 .Case("bmi", true) 1159 .Case("bmi2", true) 1160 .Case("clflushopt", true) 1161 .Case("clwb", true) 1162 .Case("clzero", true) 1163 .Case("cx16", true) 1164 .Case("f16c", true) 1165 .Case("fma", true) 1166 .Case("fma4", true) 1167 .Case("fsgsbase", true) 1168 .Case("fxsr", true) 1169 .Case("lwp", true) 1170 .Case("lzcnt", true) 1171 .Case("mm3dnow", true) 1172 .Case("mm3dnowa", true) 1173 .Case("mmx", true) 1174 .Case("movbe", true) 1175 .Case("mpx", true) 1176 .Case("pclmul", true) 1177 .Case("pku", true) 1178 .Case("popcnt", true) 1179 .Case("prefetchwt1", true) 1180 .Case("prfchw", true) 1181 .Case("rdrnd", true) 1182 .Case("rdseed", true) 1183 .Case("rtm", true) 1184 .Case("sgx", true) 1185 .Case("sha", true) 1186 .Case("sse", true) 1187 .Case("sse2", true) 1188 .Case("sse3", true) 1189 .Case("ssse3", true) 1190 .Case("sse4.1", true) 1191 .Case("sse4.2", true) 1192 .Case("sse4a", true) 1193 .Case("tbm", true) 1194 .Case("x86", true) 1195 .Case("x86_32", true) 1196 .Case("x86_64", true) 1197 .Case("xop", true) 1198 .Case("xsave", true) 1199 .Case("xsavec", true) 1200 .Case("xsaves", true) 1201 .Case("xsaveopt", true) 1202 .Default(false); 1203 } 1204 1205 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1206 return llvm::StringSwitch<bool>(Feature) 1207 .Case("aes", HasAES) 1208 .Case("avx", SSELevel >= AVX) 1209 .Case("avx2", SSELevel >= AVX2) 1210 .Case("avx512f", SSELevel >= AVX512F) 1211 .Case("avx512cd", HasAVX512CD) 1212 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1213 .Case("avx512er", HasAVX512ER) 1214 .Case("avx512pf", HasAVX512PF) 1215 .Case("avx512dq", HasAVX512DQ) 1216 .Case("avx512bw", HasAVX512BW) 1217 .Case("avx512vl", HasAVX512VL) 1218 .Case("avx512vbmi", HasAVX512VBMI) 1219 .Case("avx512ifma", HasAVX512IFMA) 1220 .Case("bmi", HasBMI) 1221 .Case("bmi2", HasBMI2) 1222 .Case("clflushopt", HasCLFLUSHOPT) 1223 .Case("clwb", HasCLWB) 1224 .Case("clzero", HasCLZERO) 1225 .Case("cx16", HasCX16) 1226 .Case("f16c", HasF16C) 1227 .Case("fma", HasFMA) 1228 .Case("fma4", XOPLevel >= FMA4) 1229 .Case("fsgsbase", HasFSGSBASE) 1230 .Case("fxsr", HasFXSR) 1231 .Case("lwp", HasLWP) 1232 .Case("lzcnt", HasLZCNT) 1233 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1234 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1235 .Case("mmx", MMX3DNowLevel >= MMX) 1236 .Case("movbe", HasMOVBE) 1237 .Case("mpx", HasMPX) 1238 .Case("pclmul", HasPCLMUL) 1239 .Case("pku", HasPKU) 1240 .Case("popcnt", HasPOPCNT) 1241 .Case("prefetchwt1", HasPREFETCHWT1) 1242 .Case("prfchw", HasPRFCHW) 1243 .Case("rdrnd", HasRDRND) 1244 .Case("rdseed", HasRDSEED) 1245 .Case("rtm", HasRTM) 1246 .Case("sgx", HasSGX) 1247 .Case("sha", HasSHA) 1248 .Case("sse", SSELevel >= SSE1) 1249 .Case("sse2", SSELevel >= SSE2) 1250 .Case("sse3", SSELevel >= SSE3) 1251 .Case("ssse3", SSELevel >= SSSE3) 1252 .Case("sse4.1", SSELevel >= SSE41) 1253 .Case("sse4.2", SSELevel >= SSE42) 1254 .Case("sse4a", XOPLevel >= SSE4A) 1255 .Case("tbm", HasTBM) 1256 .Case("x86", true) 1257 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1258 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1259 .Case("xop", XOPLevel >= XOP) 1260 .Case("xsave", HasXSAVE) 1261 .Case("xsavec", HasXSAVEC) 1262 .Case("xsaves", HasXSAVES) 1263 .Case("xsaveopt", HasXSAVEOPT) 1264 .Default(false); 1265 } 1266 1267 // We can't use a generic validation scheme for the features accepted here 1268 // versus subtarget features accepted in the target attribute because the 1269 // bitfield structure that's initialized in the runtime only supports the 1270 // below currently rather than the full range of subtarget features. (See 1271 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1272 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1273 return llvm::StringSwitch<bool>(FeatureStr) 1274 .Case("cmov", true) 1275 .Case("mmx", true) 1276 .Case("popcnt", true) 1277 .Case("sse", true) 1278 .Case("sse2", true) 1279 .Case("sse3", true) 1280 .Case("ssse3", true) 1281 .Case("sse4.1", true) 1282 .Case("sse4.2", true) 1283 .Case("avx", true) 1284 .Case("avx2", true) 1285 .Case("sse4a", true) 1286 .Case("fma4", true) 1287 .Case("xop", true) 1288 .Case("fma", true) 1289 .Case("avx512f", true) 1290 .Case("bmi", true) 1291 .Case("bmi2", true) 1292 .Case("aes", true) 1293 .Case("pclmul", true) 1294 .Case("avx512vl", true) 1295 .Case("avx512bw", true) 1296 .Case("avx512dq", true) 1297 .Case("avx512cd", true) 1298 .Case("avx512er", true) 1299 .Case("avx512pf", true) 1300 .Case("avx512vbmi", true) 1301 .Case("avx512ifma", true) 1302 .Case("avx512vpopcntdq", true) 1303 .Default(false); 1304 } 1305 1306 bool X86TargetInfo::validateAsmConstraint( 1307 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1308 switch (*Name) { 1309 default: 1310 return false; 1311 // Constant constraints. 1312 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1313 // instructions. 1314 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1315 // x86_64 instructions. 1316 case 's': 1317 Info.setRequiresImmediate(); 1318 return true; 1319 case 'I': 1320 Info.setRequiresImmediate(0, 31); 1321 return true; 1322 case 'J': 1323 Info.setRequiresImmediate(0, 63); 1324 return true; 1325 case 'K': 1326 Info.setRequiresImmediate(-128, 127); 1327 return true; 1328 case 'L': 1329 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1330 return true; 1331 case 'M': 1332 Info.setRequiresImmediate(0, 3); 1333 return true; 1334 case 'N': 1335 Info.setRequiresImmediate(0, 255); 1336 return true; 1337 case 'O': 1338 Info.setRequiresImmediate(0, 127); 1339 return true; 1340 // Register constraints. 1341 case 'Y': // 'Y' is the first character for several 2-character constraints. 1342 // Shift the pointer to the second character of the constraint. 1343 Name++; 1344 switch (*Name) { 1345 default: 1346 return false; 1347 case '0': // First SSE register. 1348 case 't': // Any SSE register, when SSE2 is enabled. 1349 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1350 case 'm': // Any MMX register, when inter-unit moves enabled. 1351 case 'k': // AVX512 arch mask registers: k1-k7. 1352 Info.setAllowsRegister(); 1353 return true; 1354 } 1355 case 'f': // Any x87 floating point stack register. 1356 // Constraint 'f' cannot be used for output operands. 1357 if (Info.ConstraintStr[0] == '=') 1358 return false; 1359 Info.setAllowsRegister(); 1360 return true; 1361 case 'a': // eax. 1362 case 'b': // ebx. 1363 case 'c': // ecx. 1364 case 'd': // edx. 1365 case 'S': // esi. 1366 case 'D': // edi. 1367 case 'A': // edx:eax. 1368 case 't': // Top of floating point stack. 1369 case 'u': // Second from top of floating point stack. 1370 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1371 case 'y': // Any MMX register. 1372 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1373 case 'x': // Any SSE register. 1374 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1375 // for intermideate k reg operations). 1376 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1377 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1378 case 'l': // "Index" registers: any general register that can be used as an 1379 // index in a base+index memory access. 1380 Info.setAllowsRegister(); 1381 return true; 1382 // Floating point constant constraints. 1383 case 'C': // SSE floating point constant. 1384 case 'G': // x87 floating point constant. 1385 return true; 1386 } 1387 } 1388 1389 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1390 unsigned Size) const { 1391 // Strip off constraint modifiers. 1392 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1393 Constraint = Constraint.substr(1); 1394 1395 return validateOperandSize(Constraint, Size); 1396 } 1397 1398 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1399 unsigned Size) const { 1400 return validateOperandSize(Constraint, Size); 1401 } 1402 1403 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1404 unsigned Size) const { 1405 switch (Constraint[0]) { 1406 default: 1407 break; 1408 case 'k': 1409 // Registers k0-k7 (AVX512) size limit is 64 bit. 1410 case 'y': 1411 return Size <= 64; 1412 case 'f': 1413 case 't': 1414 case 'u': 1415 return Size <= 128; 1416 case 'v': 1417 case 'x': 1418 if (SSELevel >= AVX512F) 1419 // 512-bit zmm registers can be used if target supports AVX512F. 1420 return Size <= 512U; 1421 else if (SSELevel >= AVX) 1422 // 256-bit ymm registers can be used if target supports AVX. 1423 return Size <= 256U; 1424 return Size <= 128U; 1425 case 'Y': 1426 // 'Y' is the first character for several 2-character constraints. 1427 switch (Constraint[1]) { 1428 default: 1429 break; 1430 case 'm': 1431 // 'Ym' is synonymous with 'y'. 1432 case 'k': 1433 return Size <= 64; 1434 case 'i': 1435 case 't': 1436 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 1437 if (SSELevel >= AVX512F) 1438 return Size <= 512U; 1439 else if (SSELevel >= AVX) 1440 return Size <= 256U; 1441 return SSELevel >= SSE2 && Size <= 128U; 1442 } 1443 } 1444 1445 return true; 1446 } 1447 1448 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1449 switch (*Constraint) { 1450 case 'a': 1451 return std::string("{ax}"); 1452 case 'b': 1453 return std::string("{bx}"); 1454 case 'c': 1455 return std::string("{cx}"); 1456 case 'd': 1457 return std::string("{dx}"); 1458 case 'S': 1459 return std::string("{si}"); 1460 case 'D': 1461 return std::string("{di}"); 1462 case 'p': // address 1463 return std::string("im"); 1464 case 't': // top of floating point stack. 1465 return std::string("{st}"); 1466 case 'u': // second from top of floating point stack. 1467 return std::string("{st(1)}"); // second from top of floating point stack. 1468 case 'Y': 1469 switch (Constraint[1]) { 1470 default: 1471 // Break from inner switch and fall through (copy single char), 1472 // continue parsing after copying the current constraint into 1473 // the return string. 1474 break; 1475 case 'k': 1476 // "^" hints llvm that this is a 2 letter constraint. 1477 // "Constraint++" is used to promote the string iterator 1478 // to the next constraint. 1479 return std::string("^") + std::string(Constraint++, 2); 1480 } 1481 LLVM_FALLTHROUGH; 1482 default: 1483 return std::string(1, *Constraint); 1484 } 1485 } 1486 1487 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1488 return llvm::StringSwitch<CPUKind>(CPU) 1489 .Case("i386", CK_i386) 1490 .Case("i486", CK_i486) 1491 .Case("winchip-c6", CK_WinChipC6) 1492 .Case("winchip2", CK_WinChip2) 1493 .Case("c3", CK_C3) 1494 .Case("i586", CK_i586) 1495 .Case("pentium", CK_Pentium) 1496 .Case("pentium-mmx", CK_PentiumMMX) 1497 .Case("i686", CK_i686) 1498 .Case("pentiumpro", CK_PentiumPro) 1499 .Case("pentium2", CK_Pentium2) 1500 .Case("pentium3", CK_Pentium3) 1501 .Case("pentium3m", CK_Pentium3M) 1502 .Case("pentium-m", CK_PentiumM) 1503 .Case("c3-2", CK_C3_2) 1504 .Case("yonah", CK_Yonah) 1505 .Case("pentium4", CK_Pentium4) 1506 .Case("pentium4m", CK_Pentium4M) 1507 .Case("prescott", CK_Prescott) 1508 .Case("nocona", CK_Nocona) 1509 .Case("core2", CK_Core2) 1510 .Case("penryn", CK_Penryn) 1511 .Case("bonnell", CK_Bonnell) 1512 .Case("atom", CK_Bonnell) // Legacy name. 1513 .Case("silvermont", CK_Silvermont) 1514 .Case("slm", CK_Silvermont) // Legacy name. 1515 .Case("goldmont", CK_Goldmont) 1516 .Case("nehalem", CK_Nehalem) 1517 .Case("corei7", CK_Nehalem) // Legacy name. 1518 .Case("westmere", CK_Westmere) 1519 .Case("sandybridge", CK_SandyBridge) 1520 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 1521 .Case("ivybridge", CK_IvyBridge) 1522 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 1523 .Case("haswell", CK_Haswell) 1524 .Case("core-avx2", CK_Haswell) // Legacy name. 1525 .Case("broadwell", CK_Broadwell) 1526 .Case("skylake", CK_SkylakeClient) 1527 .Case("skylake-avx512", CK_SkylakeServer) 1528 .Case("skx", CK_SkylakeServer) // Legacy name. 1529 .Case("cannonlake", CK_Cannonlake) 1530 .Case("knl", CK_KNL) 1531 .Case("lakemont", CK_Lakemont) 1532 .Case("k6", CK_K6) 1533 .Case("k6-2", CK_K6_2) 1534 .Case("k6-3", CK_K6_3) 1535 .Case("athlon", CK_Athlon) 1536 .Case("athlon-tbird", CK_AthlonThunderbird) 1537 .Case("athlon-4", CK_Athlon4) 1538 .Case("athlon-xp", CK_AthlonXP) 1539 .Case("athlon-mp", CK_AthlonMP) 1540 .Case("athlon64", CK_Athlon64) 1541 .Case("athlon64-sse3", CK_Athlon64SSE3) 1542 .Case("athlon-fx", CK_AthlonFX) 1543 .Case("k8", CK_K8) 1544 .Case("k8-sse3", CK_K8SSE3) 1545 .Case("opteron", CK_Opteron) 1546 .Case("opteron-sse3", CK_OpteronSSE3) 1547 .Case("barcelona", CK_AMDFAM10) 1548 .Case("amdfam10", CK_AMDFAM10) 1549 .Case("btver1", CK_BTVER1) 1550 .Case("btver2", CK_BTVER2) 1551 .Case("bdver1", CK_BDVER1) 1552 .Case("bdver2", CK_BDVER2) 1553 .Case("bdver3", CK_BDVER3) 1554 .Case("bdver4", CK_BDVER4) 1555 .Case("znver1", CK_ZNVER1) 1556 .Case("x86-64", CK_x86_64) 1557 .Case("geode", CK_Geode) 1558 .Default(CK_Generic); 1559 } 1560 1561 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1562 return llvm::makeArrayRef(GCCRegNames); 1563 } 1564 1565 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1566 return llvm::makeArrayRef(AddlRegNames); 1567 } 1568 1569 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1570 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1571 Builtin::FirstTSBuiltin + 1); 1572 } 1573 1574 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1575 return llvm::makeArrayRef(BuiltinInfoX86, 1576 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1577 } 1578