1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 #include <numeric> 22 23 namespace clang { 24 namespace targets { 25 26 const Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 33 #include "clang/Basic/BuiltinsX86.def" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 41 #include "clang/Basic/BuiltinsX86_64.def" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 67 }; 68 69 const TargetInfo::AddlRegName AddlRegNames[] = { 70 {{"al", "ah", "eax", "rax"}, 0}, 71 {{"bl", "bh", "ebx", "rbx"}, 3}, 72 {{"cl", "ch", "ecx", "rcx"}, 2}, 73 {{"dl", "dh", "edx", "rdx"}, 1}, 74 {{"esi", "rsi"}, 4}, 75 {{"edi", "rdi"}, 5}, 76 {{"esp", "rsp"}, 7}, 77 {{"ebp", "rbp"}, 6}, 78 {{"r8d", "r8w", "r8b"}, 38}, 79 {{"r9d", "r9w", "r9b"}, 39}, 80 {{"r10d", "r10w", "r10b"}, 40}, 81 {{"r11d", "r11w", "r11b"}, 41}, 82 {{"r12d", "r12w", "r12b"}, 42}, 83 {{"r13d", "r13w", "r13b"}, 43}, 84 {{"r14d", "r14w", "r14b"}, 44}, 85 {{"r15d", "r15w", "r15b"}, 45}, 86 }; 87 88 } // namespace targets 89 } // namespace clang 90 91 using namespace clang; 92 using namespace clang::targets; 93 94 bool X86TargetInfo::setFPMath(StringRef Name) { 95 if (Name == "387") { 96 FPMath = FP_387; 97 return true; 98 } 99 if (Name == "sse") { 100 FPMath = FP_SSE; 101 return true; 102 } 103 return false; 104 } 105 106 bool X86TargetInfo::initFeatureMap( 107 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 108 const std::vector<std::string> &FeaturesVec) const { 109 // FIXME: This *really* should not be here. 110 // X86_64 always has SSE2. 111 if (getTriple().getArch() == llvm::Triple::x86_64) 112 setFeatureEnabled(Features, "sse2", true); 113 114 using namespace llvm::X86; 115 116 SmallVector<StringRef, 16> CPUFeatures; 117 getFeaturesForCPU(CPU, CPUFeatures); 118 for (auto &F : CPUFeatures) 119 setFeatureEnabled(Features, F, true); 120 121 std::vector<std::string> UpdatedFeaturesVec; 122 for (const auto &Feature : FeaturesVec) { 123 // Expand general-regs-only to -x86, -mmx and -sse 124 if (Feature == "+general-regs-only") { 125 UpdatedFeaturesVec.push_back("-x87"); 126 UpdatedFeaturesVec.push_back("-mmx"); 127 UpdatedFeaturesVec.push_back("-sse"); 128 continue; 129 } 130 131 UpdatedFeaturesVec.push_back(Feature); 132 } 133 134 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 135 return false; 136 137 // Can't do this earlier because we need to be able to explicitly enable 138 // or disable these features and the things that they depend upon. 139 140 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 141 auto I = Features.find("sse4.2"); 142 if (I != Features.end() && I->getValue() && 143 llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end()) 144 Features["popcnt"] = true; 145 146 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 147 // then enable MMX. 148 I = Features.find("sse"); 149 if (I != Features.end() && I->getValue() && 150 llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end()) 151 Features["mmx"] = true; 152 153 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 154 I = Features.find("avx"); 155 if (I != Features.end() && I->getValue() && 156 llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end()) 157 Features["xsave"] = true; 158 159 return true; 160 } 161 162 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 163 StringRef Name, bool Enabled) const { 164 if (Name == "sse4") { 165 // We can get here via the __target__ attribute since that's not controlled 166 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 167 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 168 // disabled. 169 if (Enabled) 170 Name = "sse4.2"; 171 else 172 Name = "sse4.1"; 173 } 174 175 Features[Name] = Enabled; 176 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 177 } 178 179 /// handleTargetFeatures - Perform initialization based on the user 180 /// configured set of features. 181 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 182 DiagnosticsEngine &Diags) { 183 for (const auto &Feature : Features) { 184 if (Feature[0] != '+') 185 continue; 186 187 if (Feature == "+aes") { 188 HasAES = true; 189 } else if (Feature == "+vaes") { 190 HasVAES = true; 191 } else if (Feature == "+pclmul") { 192 HasPCLMUL = true; 193 } else if (Feature == "+vpclmulqdq") { 194 HasVPCLMULQDQ = true; 195 } else if (Feature == "+lzcnt") { 196 HasLZCNT = true; 197 } else if (Feature == "+rdrnd") { 198 HasRDRND = true; 199 } else if (Feature == "+fsgsbase") { 200 HasFSGSBASE = true; 201 } else if (Feature == "+bmi") { 202 HasBMI = true; 203 } else if (Feature == "+bmi2") { 204 HasBMI2 = true; 205 } else if (Feature == "+popcnt") { 206 HasPOPCNT = true; 207 } else if (Feature == "+rtm") { 208 HasRTM = true; 209 } else if (Feature == "+prfchw") { 210 HasPRFCHW = true; 211 } else if (Feature == "+rdseed") { 212 HasRDSEED = true; 213 } else if (Feature == "+adx") { 214 HasADX = true; 215 } else if (Feature == "+tbm") { 216 HasTBM = true; 217 } else if (Feature == "+lwp") { 218 HasLWP = true; 219 } else if (Feature == "+fma") { 220 HasFMA = true; 221 } else if (Feature == "+f16c") { 222 HasF16C = true; 223 } else if (Feature == "+gfni") { 224 HasGFNI = true; 225 } else if (Feature == "+avx512cd") { 226 HasAVX512CD = true; 227 } else if (Feature == "+avx512vpopcntdq") { 228 HasAVX512VPOPCNTDQ = true; 229 } else if (Feature == "+avx512vnni") { 230 HasAVX512VNNI = true; 231 } else if (Feature == "+avx512bf16") { 232 HasAVX512BF16 = true; 233 } else if (Feature == "+avx512er") { 234 HasAVX512ER = true; 235 } else if (Feature == "+avx512fp16") { 236 HasAVX512FP16 = true; 237 HasFloat16 = true; 238 } else if (Feature == "+avx512pf") { 239 HasAVX512PF = true; 240 } else if (Feature == "+avx512dq") { 241 HasAVX512DQ = true; 242 } else if (Feature == "+avx512bitalg") { 243 HasAVX512BITALG = true; 244 } else if (Feature == "+avx512bw") { 245 HasAVX512BW = true; 246 } else if (Feature == "+avx512vl") { 247 HasAVX512VL = true; 248 } else if (Feature == "+avx512vbmi") { 249 HasAVX512VBMI = true; 250 } else if (Feature == "+avx512vbmi2") { 251 HasAVX512VBMI2 = true; 252 } else if (Feature == "+avx512ifma") { 253 HasAVX512IFMA = true; 254 } else if (Feature == "+avx512vp2intersect") { 255 HasAVX512VP2INTERSECT = true; 256 } else if (Feature == "+sha") { 257 HasSHA = true; 258 } else if (Feature == "+shstk") { 259 HasSHSTK = true; 260 } else if (Feature == "+movbe") { 261 HasMOVBE = true; 262 } else if (Feature == "+sgx") { 263 HasSGX = true; 264 } else if (Feature == "+cx8") { 265 HasCX8 = true; 266 } else if (Feature == "+cx16") { 267 HasCX16 = true; 268 } else if (Feature == "+fxsr") { 269 HasFXSR = true; 270 } else if (Feature == "+xsave") { 271 HasXSAVE = true; 272 } else if (Feature == "+xsaveopt") { 273 HasXSAVEOPT = true; 274 } else if (Feature == "+xsavec") { 275 HasXSAVEC = true; 276 } else if (Feature == "+xsaves") { 277 HasXSAVES = true; 278 } else if (Feature == "+mwaitx") { 279 HasMWAITX = true; 280 } else if (Feature == "+pku") { 281 HasPKU = true; 282 } else if (Feature == "+clflushopt") { 283 HasCLFLUSHOPT = true; 284 } else if (Feature == "+clwb") { 285 HasCLWB = true; 286 } else if (Feature == "+wbnoinvd") { 287 HasWBNOINVD = true; 288 } else if (Feature == "+prefetchwt1") { 289 HasPREFETCHWT1 = true; 290 } else if (Feature == "+clzero") { 291 HasCLZERO = true; 292 } else if (Feature == "+cldemote") { 293 HasCLDEMOTE = true; 294 } else if (Feature == "+rdpid") { 295 HasRDPID = true; 296 } else if (Feature == "+kl") { 297 HasKL = true; 298 } else if (Feature == "+widekl") { 299 HasWIDEKL = true; 300 } else if (Feature == "+retpoline-external-thunk") { 301 HasRetpolineExternalThunk = true; 302 } else if (Feature == "+sahf") { 303 HasLAHFSAHF = true; 304 } else if (Feature == "+waitpkg") { 305 HasWAITPKG = true; 306 } else if (Feature == "+movdiri") { 307 HasMOVDIRI = true; 308 } else if (Feature == "+movdir64b") { 309 HasMOVDIR64B = true; 310 } else if (Feature == "+pconfig") { 311 HasPCONFIG = true; 312 } else if (Feature == "+ptwrite") { 313 HasPTWRITE = true; 314 } else if (Feature == "+invpcid") { 315 HasINVPCID = true; 316 } else if (Feature == "+enqcmd") { 317 HasENQCMD = true; 318 } else if (Feature == "+hreset") { 319 HasHRESET = true; 320 } else if (Feature == "+amx-bf16") { 321 HasAMXBF16 = true; 322 } else if (Feature == "+amx-int8") { 323 HasAMXINT8 = true; 324 } else if (Feature == "+amx-tile") { 325 HasAMXTILE = true; 326 } else if (Feature == "+avxvnni") { 327 HasAVXVNNI = true; 328 } else if (Feature == "+serialize") { 329 HasSERIALIZE = true; 330 } else if (Feature == "+tsxldtrk") { 331 HasTSXLDTRK = true; 332 } else if (Feature == "+uintr") { 333 HasUINTR = true; 334 } 335 336 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 337 .Case("+avx512f", AVX512F) 338 .Case("+avx2", AVX2) 339 .Case("+avx", AVX) 340 .Case("+sse4.2", SSE42) 341 .Case("+sse4.1", SSE41) 342 .Case("+ssse3", SSSE3) 343 .Case("+sse3", SSE3) 344 .Case("+sse2", SSE2) 345 .Case("+sse", SSE1) 346 .Default(NoSSE); 347 SSELevel = std::max(SSELevel, Level); 348 349 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 350 .Case("+3dnowa", AMD3DNowAthlon) 351 .Case("+3dnow", AMD3DNow) 352 .Case("+mmx", MMX) 353 .Default(NoMMX3DNow); 354 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 355 356 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 357 .Case("+xop", XOP) 358 .Case("+fma4", FMA4) 359 .Case("+sse4a", SSE4A) 360 .Default(NoXOP); 361 XOPLevel = std::max(XOPLevel, XLevel); 362 } 363 364 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 365 // matches the selected sse level. 366 if ((FPMath == FP_SSE && SSELevel < SSE1) || 367 (FPMath == FP_387 && SSELevel >= SSE1)) { 368 Diags.Report(diag::err_target_unsupported_fpmath) 369 << (FPMath == FP_SSE ? "sse" : "387"); 370 return false; 371 } 372 373 SimdDefaultAlign = 374 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 375 return true; 376 } 377 378 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 379 /// definitions for this particular subtarget. 380 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 381 MacroBuilder &Builder) const { 382 // Inline assembly supports X86 flag outputs. 383 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 384 385 std::string CodeModel = getTargetOpts().CodeModel; 386 if (CodeModel == "default") 387 CodeModel = "small"; 388 Builder.defineMacro("__code_model_" + CodeModel + "__"); 389 390 // Target identification. 391 if (getTriple().getArch() == llvm::Triple::x86_64) { 392 Builder.defineMacro("__amd64__"); 393 Builder.defineMacro("__amd64"); 394 Builder.defineMacro("__x86_64"); 395 Builder.defineMacro("__x86_64__"); 396 if (getTriple().getArchName() == "x86_64h") { 397 Builder.defineMacro("__x86_64h"); 398 Builder.defineMacro("__x86_64h__"); 399 } 400 } else { 401 DefineStd(Builder, "i386", Opts); 402 } 403 404 Builder.defineMacro("__SEG_GS"); 405 Builder.defineMacro("__SEG_FS"); 406 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 407 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 408 409 // Subtarget options. 410 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 411 // truly should be based on -mtune options. 412 using namespace llvm::X86; 413 switch (CPU) { 414 case CK_None: 415 break; 416 case CK_i386: 417 // The rest are coming from the i386 define above. 418 Builder.defineMacro("__tune_i386__"); 419 break; 420 case CK_i486: 421 case CK_WinChipC6: 422 case CK_WinChip2: 423 case CK_C3: 424 defineCPUMacros(Builder, "i486"); 425 break; 426 case CK_PentiumMMX: 427 Builder.defineMacro("__pentium_mmx__"); 428 Builder.defineMacro("__tune_pentium_mmx__"); 429 LLVM_FALLTHROUGH; 430 case CK_i586: 431 case CK_Pentium: 432 defineCPUMacros(Builder, "i586"); 433 defineCPUMacros(Builder, "pentium"); 434 break; 435 case CK_Pentium3: 436 case CK_PentiumM: 437 Builder.defineMacro("__tune_pentium3__"); 438 LLVM_FALLTHROUGH; 439 case CK_Pentium2: 440 case CK_C3_2: 441 Builder.defineMacro("__tune_pentium2__"); 442 LLVM_FALLTHROUGH; 443 case CK_PentiumPro: 444 case CK_i686: 445 defineCPUMacros(Builder, "i686"); 446 defineCPUMacros(Builder, "pentiumpro"); 447 break; 448 case CK_Pentium4: 449 defineCPUMacros(Builder, "pentium4"); 450 break; 451 case CK_Yonah: 452 case CK_Prescott: 453 case CK_Nocona: 454 defineCPUMacros(Builder, "nocona"); 455 break; 456 case CK_Core2: 457 case CK_Penryn: 458 defineCPUMacros(Builder, "core2"); 459 break; 460 case CK_Bonnell: 461 defineCPUMacros(Builder, "atom"); 462 break; 463 case CK_Silvermont: 464 defineCPUMacros(Builder, "slm"); 465 break; 466 case CK_Goldmont: 467 defineCPUMacros(Builder, "goldmont"); 468 break; 469 case CK_GoldmontPlus: 470 defineCPUMacros(Builder, "goldmont_plus"); 471 break; 472 case CK_Tremont: 473 defineCPUMacros(Builder, "tremont"); 474 break; 475 case CK_Nehalem: 476 case CK_Westmere: 477 case CK_SandyBridge: 478 case CK_IvyBridge: 479 case CK_Haswell: 480 case CK_Broadwell: 481 case CK_SkylakeClient: 482 case CK_SkylakeServer: 483 case CK_Cascadelake: 484 case CK_Cooperlake: 485 case CK_Cannonlake: 486 case CK_IcelakeClient: 487 case CK_Rocketlake: 488 case CK_IcelakeServer: 489 case CK_Tigerlake: 490 case CK_SapphireRapids: 491 case CK_Alderlake: 492 // FIXME: Historically, we defined this legacy name, it would be nice to 493 // remove it at some point. We've never exposed fine-grained names for 494 // recent primary x86 CPUs, and we should keep it that way. 495 defineCPUMacros(Builder, "corei7"); 496 break; 497 case CK_KNL: 498 defineCPUMacros(Builder, "knl"); 499 break; 500 case CK_KNM: 501 break; 502 case CK_Lakemont: 503 defineCPUMacros(Builder, "i586", /*Tuning*/false); 504 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 505 Builder.defineMacro("__tune_lakemont__"); 506 break; 507 case CK_K6_2: 508 Builder.defineMacro("__k6_2__"); 509 Builder.defineMacro("__tune_k6_2__"); 510 LLVM_FALLTHROUGH; 511 case CK_K6_3: 512 if (CPU != CK_K6_2) { // In case of fallthrough 513 // FIXME: GCC may be enabling these in cases where some other k6 514 // architecture is specified but -m3dnow is explicitly provided. The 515 // exact semantics need to be determined and emulated here. 516 Builder.defineMacro("__k6_3__"); 517 Builder.defineMacro("__tune_k6_3__"); 518 } 519 LLVM_FALLTHROUGH; 520 case CK_K6: 521 defineCPUMacros(Builder, "k6"); 522 break; 523 case CK_Athlon: 524 case CK_AthlonXP: 525 defineCPUMacros(Builder, "athlon"); 526 if (SSELevel != NoSSE) { 527 Builder.defineMacro("__athlon_sse__"); 528 Builder.defineMacro("__tune_athlon_sse__"); 529 } 530 break; 531 case CK_K8: 532 case CK_K8SSE3: 533 case CK_x86_64: 534 defineCPUMacros(Builder, "k8"); 535 break; 536 case CK_x86_64_v2: 537 case CK_x86_64_v3: 538 case CK_x86_64_v4: 539 break; 540 case CK_AMDFAM10: 541 defineCPUMacros(Builder, "amdfam10"); 542 break; 543 case CK_BTVER1: 544 defineCPUMacros(Builder, "btver1"); 545 break; 546 case CK_BTVER2: 547 defineCPUMacros(Builder, "btver2"); 548 break; 549 case CK_BDVER1: 550 defineCPUMacros(Builder, "bdver1"); 551 break; 552 case CK_BDVER2: 553 defineCPUMacros(Builder, "bdver2"); 554 break; 555 case CK_BDVER3: 556 defineCPUMacros(Builder, "bdver3"); 557 break; 558 case CK_BDVER4: 559 defineCPUMacros(Builder, "bdver4"); 560 break; 561 case CK_ZNVER1: 562 defineCPUMacros(Builder, "znver1"); 563 break; 564 case CK_ZNVER2: 565 defineCPUMacros(Builder, "znver2"); 566 break; 567 case CK_ZNVER3: 568 defineCPUMacros(Builder, "znver3"); 569 break; 570 case CK_Geode: 571 defineCPUMacros(Builder, "geode"); 572 break; 573 } 574 575 // Target properties. 576 Builder.defineMacro("__REGISTER_PREFIX__", ""); 577 578 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 579 // functions in glibc header files that use FP Stack inline asm which the 580 // backend can't deal with (PR879). 581 Builder.defineMacro("__NO_MATH_INLINES"); 582 583 if (HasAES) 584 Builder.defineMacro("__AES__"); 585 586 if (HasVAES) 587 Builder.defineMacro("__VAES__"); 588 589 if (HasPCLMUL) 590 Builder.defineMacro("__PCLMUL__"); 591 592 if (HasVPCLMULQDQ) 593 Builder.defineMacro("__VPCLMULQDQ__"); 594 595 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 596 // the feature flag only applies to 64-bit mode. 597 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 598 Builder.defineMacro("__LAHF_SAHF__"); 599 600 if (HasLZCNT) 601 Builder.defineMacro("__LZCNT__"); 602 603 if (HasRDRND) 604 Builder.defineMacro("__RDRND__"); 605 606 if (HasFSGSBASE) 607 Builder.defineMacro("__FSGSBASE__"); 608 609 if (HasBMI) 610 Builder.defineMacro("__BMI__"); 611 612 if (HasBMI2) 613 Builder.defineMacro("__BMI2__"); 614 615 if (HasPOPCNT) 616 Builder.defineMacro("__POPCNT__"); 617 618 if (HasRTM) 619 Builder.defineMacro("__RTM__"); 620 621 if (HasPRFCHW) 622 Builder.defineMacro("__PRFCHW__"); 623 624 if (HasRDSEED) 625 Builder.defineMacro("__RDSEED__"); 626 627 if (HasADX) 628 Builder.defineMacro("__ADX__"); 629 630 if (HasTBM) 631 Builder.defineMacro("__TBM__"); 632 633 if (HasLWP) 634 Builder.defineMacro("__LWP__"); 635 636 if (HasMWAITX) 637 Builder.defineMacro("__MWAITX__"); 638 639 if (HasMOVBE) 640 Builder.defineMacro("__MOVBE__"); 641 642 switch (XOPLevel) { 643 case XOP: 644 Builder.defineMacro("__XOP__"); 645 LLVM_FALLTHROUGH; 646 case FMA4: 647 Builder.defineMacro("__FMA4__"); 648 LLVM_FALLTHROUGH; 649 case SSE4A: 650 Builder.defineMacro("__SSE4A__"); 651 LLVM_FALLTHROUGH; 652 case NoXOP: 653 break; 654 } 655 656 if (HasFMA) 657 Builder.defineMacro("__FMA__"); 658 659 if (HasF16C) 660 Builder.defineMacro("__F16C__"); 661 662 if (HasGFNI) 663 Builder.defineMacro("__GFNI__"); 664 665 if (HasAVX512CD) 666 Builder.defineMacro("__AVX512CD__"); 667 if (HasAVX512VPOPCNTDQ) 668 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 669 if (HasAVX512VNNI) 670 Builder.defineMacro("__AVX512VNNI__"); 671 if (HasAVX512BF16) 672 Builder.defineMacro("__AVX512BF16__"); 673 if (HasAVX512ER) 674 Builder.defineMacro("__AVX512ER__"); 675 if (HasAVX512FP16) 676 Builder.defineMacro("__AVX512FP16__"); 677 if (HasAVX512PF) 678 Builder.defineMacro("__AVX512PF__"); 679 if (HasAVX512DQ) 680 Builder.defineMacro("__AVX512DQ__"); 681 if (HasAVX512BITALG) 682 Builder.defineMacro("__AVX512BITALG__"); 683 if (HasAVX512BW) 684 Builder.defineMacro("__AVX512BW__"); 685 if (HasAVX512VL) 686 Builder.defineMacro("__AVX512VL__"); 687 if (HasAVX512VBMI) 688 Builder.defineMacro("__AVX512VBMI__"); 689 if (HasAVX512VBMI2) 690 Builder.defineMacro("__AVX512VBMI2__"); 691 if (HasAVX512IFMA) 692 Builder.defineMacro("__AVX512IFMA__"); 693 if (HasAVX512VP2INTERSECT) 694 Builder.defineMacro("__AVX512VP2INTERSECT__"); 695 if (HasSHA) 696 Builder.defineMacro("__SHA__"); 697 698 if (HasFXSR) 699 Builder.defineMacro("__FXSR__"); 700 if (HasXSAVE) 701 Builder.defineMacro("__XSAVE__"); 702 if (HasXSAVEOPT) 703 Builder.defineMacro("__XSAVEOPT__"); 704 if (HasXSAVEC) 705 Builder.defineMacro("__XSAVEC__"); 706 if (HasXSAVES) 707 Builder.defineMacro("__XSAVES__"); 708 if (HasPKU) 709 Builder.defineMacro("__PKU__"); 710 if (HasCLFLUSHOPT) 711 Builder.defineMacro("__CLFLUSHOPT__"); 712 if (HasCLWB) 713 Builder.defineMacro("__CLWB__"); 714 if (HasWBNOINVD) 715 Builder.defineMacro("__WBNOINVD__"); 716 if (HasSHSTK) 717 Builder.defineMacro("__SHSTK__"); 718 if (HasSGX) 719 Builder.defineMacro("__SGX__"); 720 if (HasPREFETCHWT1) 721 Builder.defineMacro("__PREFETCHWT1__"); 722 if (HasCLZERO) 723 Builder.defineMacro("__CLZERO__"); 724 if (HasKL) 725 Builder.defineMacro("__KL__"); 726 if (HasWIDEKL) 727 Builder.defineMacro("__WIDEKL__"); 728 if (HasRDPID) 729 Builder.defineMacro("__RDPID__"); 730 if (HasCLDEMOTE) 731 Builder.defineMacro("__CLDEMOTE__"); 732 if (HasWAITPKG) 733 Builder.defineMacro("__WAITPKG__"); 734 if (HasMOVDIRI) 735 Builder.defineMacro("__MOVDIRI__"); 736 if (HasMOVDIR64B) 737 Builder.defineMacro("__MOVDIR64B__"); 738 if (HasPCONFIG) 739 Builder.defineMacro("__PCONFIG__"); 740 if (HasPTWRITE) 741 Builder.defineMacro("__PTWRITE__"); 742 if (HasINVPCID) 743 Builder.defineMacro("__INVPCID__"); 744 if (HasENQCMD) 745 Builder.defineMacro("__ENQCMD__"); 746 if (HasHRESET) 747 Builder.defineMacro("__HRESET__"); 748 if (HasAMXTILE) 749 Builder.defineMacro("__AMXTILE__"); 750 if (HasAMXINT8) 751 Builder.defineMacro("__AMXINT8__"); 752 if (HasAMXBF16) 753 Builder.defineMacro("__AMXBF16__"); 754 if (HasAVXVNNI) 755 Builder.defineMacro("__AVXVNNI__"); 756 if (HasSERIALIZE) 757 Builder.defineMacro("__SERIALIZE__"); 758 if (HasTSXLDTRK) 759 Builder.defineMacro("__TSXLDTRK__"); 760 if (HasUINTR) 761 Builder.defineMacro("__UINTR__"); 762 763 // Each case falls through to the previous one here. 764 switch (SSELevel) { 765 case AVX512F: 766 Builder.defineMacro("__AVX512F__"); 767 LLVM_FALLTHROUGH; 768 case AVX2: 769 Builder.defineMacro("__AVX2__"); 770 LLVM_FALLTHROUGH; 771 case AVX: 772 Builder.defineMacro("__AVX__"); 773 LLVM_FALLTHROUGH; 774 case SSE42: 775 Builder.defineMacro("__SSE4_2__"); 776 LLVM_FALLTHROUGH; 777 case SSE41: 778 Builder.defineMacro("__SSE4_1__"); 779 LLVM_FALLTHROUGH; 780 case SSSE3: 781 Builder.defineMacro("__SSSE3__"); 782 LLVM_FALLTHROUGH; 783 case SSE3: 784 Builder.defineMacro("__SSE3__"); 785 LLVM_FALLTHROUGH; 786 case SSE2: 787 Builder.defineMacro("__SSE2__"); 788 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 789 LLVM_FALLTHROUGH; 790 case SSE1: 791 Builder.defineMacro("__SSE__"); 792 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 793 LLVM_FALLTHROUGH; 794 case NoSSE: 795 break; 796 } 797 798 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 799 switch (SSELevel) { 800 case AVX512F: 801 case AVX2: 802 case AVX: 803 case SSE42: 804 case SSE41: 805 case SSSE3: 806 case SSE3: 807 case SSE2: 808 Builder.defineMacro("_M_IX86_FP", Twine(2)); 809 break; 810 case SSE1: 811 Builder.defineMacro("_M_IX86_FP", Twine(1)); 812 break; 813 default: 814 Builder.defineMacro("_M_IX86_FP", Twine(0)); 815 break; 816 } 817 } 818 819 // Each case falls through to the previous one here. 820 switch (MMX3DNowLevel) { 821 case AMD3DNowAthlon: 822 Builder.defineMacro("__3dNOW_A__"); 823 LLVM_FALLTHROUGH; 824 case AMD3DNow: 825 Builder.defineMacro("__3dNOW__"); 826 LLVM_FALLTHROUGH; 827 case MMX: 828 Builder.defineMacro("__MMX__"); 829 LLVM_FALLTHROUGH; 830 case NoMMX3DNow: 831 break; 832 } 833 834 if (CPU >= CK_i486 || CPU == CK_None) { 835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 838 } 839 if (HasCX8) 840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 841 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 842 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 843 844 if (HasFloat128) 845 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 846 } 847 848 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 849 return llvm::StringSwitch<bool>(Name) 850 .Case("3dnow", true) 851 .Case("3dnowa", true) 852 .Case("adx", true) 853 .Case("aes", true) 854 .Case("amx-bf16", true) 855 .Case("amx-int8", true) 856 .Case("amx-tile", true) 857 .Case("avx", true) 858 .Case("avx2", true) 859 .Case("avx512f", true) 860 .Case("avx512cd", true) 861 .Case("avx512vpopcntdq", true) 862 .Case("avx512vnni", true) 863 .Case("avx512bf16", true) 864 .Case("avx512er", true) 865 .Case("avx512fp16", true) 866 .Case("avx512pf", true) 867 .Case("avx512dq", true) 868 .Case("avx512bitalg", true) 869 .Case("avx512bw", true) 870 .Case("avx512vl", true) 871 .Case("avx512vbmi", true) 872 .Case("avx512vbmi2", true) 873 .Case("avx512ifma", true) 874 .Case("avx512vp2intersect", true) 875 .Case("avxvnni", true) 876 .Case("bmi", true) 877 .Case("bmi2", true) 878 .Case("cldemote", true) 879 .Case("clflushopt", true) 880 .Case("clwb", true) 881 .Case("clzero", true) 882 .Case("cx16", true) 883 .Case("enqcmd", true) 884 .Case("f16c", true) 885 .Case("fma", true) 886 .Case("fma4", true) 887 .Case("fsgsbase", true) 888 .Case("fxsr", true) 889 .Case("general-regs-only", true) 890 .Case("gfni", true) 891 .Case("hreset", true) 892 .Case("invpcid", true) 893 .Case("kl", true) 894 .Case("widekl", true) 895 .Case("lwp", true) 896 .Case("lzcnt", true) 897 .Case("mmx", true) 898 .Case("movbe", true) 899 .Case("movdiri", true) 900 .Case("movdir64b", true) 901 .Case("mwaitx", true) 902 .Case("pclmul", true) 903 .Case("pconfig", true) 904 .Case("pku", true) 905 .Case("popcnt", true) 906 .Case("prefetchwt1", true) 907 .Case("prfchw", true) 908 .Case("ptwrite", true) 909 .Case("rdpid", true) 910 .Case("rdrnd", true) 911 .Case("rdseed", true) 912 .Case("rtm", true) 913 .Case("sahf", true) 914 .Case("serialize", true) 915 .Case("sgx", true) 916 .Case("sha", true) 917 .Case("shstk", true) 918 .Case("sse", true) 919 .Case("sse2", true) 920 .Case("sse3", true) 921 .Case("ssse3", true) 922 .Case("sse4", true) 923 .Case("sse4.1", true) 924 .Case("sse4.2", true) 925 .Case("sse4a", true) 926 .Case("tbm", true) 927 .Case("tsxldtrk", true) 928 .Case("uintr", true) 929 .Case("vaes", true) 930 .Case("vpclmulqdq", true) 931 .Case("wbnoinvd", true) 932 .Case("waitpkg", true) 933 .Case("x87", true) 934 .Case("xop", true) 935 .Case("xsave", true) 936 .Case("xsavec", true) 937 .Case("xsaves", true) 938 .Case("xsaveopt", true) 939 .Default(false); 940 } 941 942 bool X86TargetInfo::hasFeature(StringRef Feature) const { 943 return llvm::StringSwitch<bool>(Feature) 944 .Case("adx", HasADX) 945 .Case("aes", HasAES) 946 .Case("amx-bf16", HasAMXBF16) 947 .Case("amx-int8", HasAMXINT8) 948 .Case("amx-tile", HasAMXTILE) 949 .Case("avxvnni", HasAVXVNNI) 950 .Case("avx", SSELevel >= AVX) 951 .Case("avx2", SSELevel >= AVX2) 952 .Case("avx512f", SSELevel >= AVX512F) 953 .Case("avx512cd", HasAVX512CD) 954 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 955 .Case("avx512vnni", HasAVX512VNNI) 956 .Case("avx512bf16", HasAVX512BF16) 957 .Case("avx512er", HasAVX512ER) 958 .Case("avx512fp16", HasAVX512FP16) 959 .Case("avx512pf", HasAVX512PF) 960 .Case("avx512dq", HasAVX512DQ) 961 .Case("avx512bitalg", HasAVX512BITALG) 962 .Case("avx512bw", HasAVX512BW) 963 .Case("avx512vl", HasAVX512VL) 964 .Case("avx512vbmi", HasAVX512VBMI) 965 .Case("avx512vbmi2", HasAVX512VBMI2) 966 .Case("avx512ifma", HasAVX512IFMA) 967 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 968 .Case("bmi", HasBMI) 969 .Case("bmi2", HasBMI2) 970 .Case("cldemote", HasCLDEMOTE) 971 .Case("clflushopt", HasCLFLUSHOPT) 972 .Case("clwb", HasCLWB) 973 .Case("clzero", HasCLZERO) 974 .Case("cx8", HasCX8) 975 .Case("cx16", HasCX16) 976 .Case("enqcmd", HasENQCMD) 977 .Case("f16c", HasF16C) 978 .Case("fma", HasFMA) 979 .Case("fma4", XOPLevel >= FMA4) 980 .Case("fsgsbase", HasFSGSBASE) 981 .Case("fxsr", HasFXSR) 982 .Case("gfni", HasGFNI) 983 .Case("hreset", HasHRESET) 984 .Case("invpcid", HasINVPCID) 985 .Case("kl", HasKL) 986 .Case("widekl", HasWIDEKL) 987 .Case("lwp", HasLWP) 988 .Case("lzcnt", HasLZCNT) 989 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 990 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 991 .Case("mmx", MMX3DNowLevel >= MMX) 992 .Case("movbe", HasMOVBE) 993 .Case("movdiri", HasMOVDIRI) 994 .Case("movdir64b", HasMOVDIR64B) 995 .Case("mwaitx", HasMWAITX) 996 .Case("pclmul", HasPCLMUL) 997 .Case("pconfig", HasPCONFIG) 998 .Case("pku", HasPKU) 999 .Case("popcnt", HasPOPCNT) 1000 .Case("prefetchwt1", HasPREFETCHWT1) 1001 .Case("prfchw", HasPRFCHW) 1002 .Case("ptwrite", HasPTWRITE) 1003 .Case("rdpid", HasRDPID) 1004 .Case("rdrnd", HasRDRND) 1005 .Case("rdseed", HasRDSEED) 1006 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1007 .Case("rtm", HasRTM) 1008 .Case("sahf", HasLAHFSAHF) 1009 .Case("serialize", HasSERIALIZE) 1010 .Case("sgx", HasSGX) 1011 .Case("sha", HasSHA) 1012 .Case("shstk", HasSHSTK) 1013 .Case("sse", SSELevel >= SSE1) 1014 .Case("sse2", SSELevel >= SSE2) 1015 .Case("sse3", SSELevel >= SSE3) 1016 .Case("ssse3", SSELevel >= SSSE3) 1017 .Case("sse4.1", SSELevel >= SSE41) 1018 .Case("sse4.2", SSELevel >= SSE42) 1019 .Case("sse4a", XOPLevel >= SSE4A) 1020 .Case("tbm", HasTBM) 1021 .Case("tsxldtrk", HasTSXLDTRK) 1022 .Case("uintr", HasUINTR) 1023 .Case("vaes", HasVAES) 1024 .Case("vpclmulqdq", HasVPCLMULQDQ) 1025 .Case("wbnoinvd", HasWBNOINVD) 1026 .Case("waitpkg", HasWAITPKG) 1027 .Case("x86", true) 1028 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1029 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1030 .Case("xop", XOPLevel >= XOP) 1031 .Case("xsave", HasXSAVE) 1032 .Case("xsavec", HasXSAVEC) 1033 .Case("xsaves", HasXSAVES) 1034 .Case("xsaveopt", HasXSAVEOPT) 1035 .Default(false); 1036 } 1037 1038 // We can't use a generic validation scheme for the features accepted here 1039 // versus subtarget features accepted in the target attribute because the 1040 // bitfield structure that's initialized in the runtime only supports the 1041 // below currently rather than the full range of subtarget features. (See 1042 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1043 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1044 return llvm::StringSwitch<bool>(FeatureStr) 1045 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1046 #include "llvm/Support/X86TargetParser.def" 1047 .Default(false); 1048 } 1049 1050 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1051 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1052 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1053 .Case(STR, llvm::X86::FEATURE_##ENUM) 1054 1055 #include "llvm/Support/X86TargetParser.def" 1056 ; 1057 // Note, this function should only be used after ensuring the value is 1058 // correct, so it asserts if the value is out of range. 1059 } 1060 1061 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1062 #ifndef NDEBUG 1063 // Check that priorities are set properly in the .def file. We expect that 1064 // "compat" features are assigned non-duplicate consecutive priorities 1065 // starting from zero (0, 1, ..., num_features - 1). 1066 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, 1067 unsigned Priorities[] = { 1068 #include "llvm/Support/X86TargetParser.def" 1069 std::numeric_limits<unsigned>::max() // Need to consume last comma. 1070 }; 1071 std::array<unsigned, llvm::array_lengthof(Priorities) - 1> HelperList; 1072 std::iota(HelperList.begin(), HelperList.end(), 0); 1073 assert(std::is_permutation(HelperList.begin(), HelperList.end(), 1074 std::begin(Priorities), 1075 std::prev(std::end(Priorities))) && 1076 "Priorities don't form consecutive range!"); 1077 #endif 1078 1079 switch (Feat) { 1080 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1081 case llvm::X86::FEATURE_##ENUM: \ 1082 return PRIORITY; 1083 #include "llvm/Support/X86TargetParser.def" 1084 default: 1085 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1086 } 1087 } 1088 1089 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1090 // Valid CPUs have a 'key feature' that compares just better than its key 1091 // feature. 1092 using namespace llvm::X86; 1093 CPUKind Kind = parseArchX86(Name); 1094 if (Kind != CK_None) { 1095 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1096 return (getFeaturePriority(KeyFeature) << 1) + 1; 1097 } 1098 1099 // Now we know we have a feature, so get its priority and shift it a few so 1100 // that we have sufficient room for the CPUs (above). 1101 return getFeaturePriority(getFeature(Name)) << 1; 1102 } 1103 1104 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1105 return llvm::StringSwitch<bool>(Name) 1106 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1107 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1108 #include "llvm/Support/X86TargetParser.def" 1109 .Default(false); 1110 } 1111 1112 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1113 return llvm::StringSwitch<StringRef>(Name) 1114 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1115 #include "llvm/Support/X86TargetParser.def" 1116 .Default(Name); 1117 } 1118 1119 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1120 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1121 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1122 #include "llvm/Support/X86TargetParser.def" 1123 .Default(0); 1124 } 1125 1126 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1127 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1128 StringRef WholeList = 1129 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1130 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1131 #include "llvm/Support/X86TargetParser.def" 1132 .Default(""); 1133 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1134 } 1135 1136 // We can't use a generic validation scheme for the cpus accepted here 1137 // versus subtarget cpus accepted in the target attribute because the 1138 // variables intitialized by the runtime only support the below currently 1139 // rather than the full range of cpus. 1140 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1141 return llvm::StringSwitch<bool>(FeatureStr) 1142 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1143 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1144 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1145 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1146 #include "llvm/Support/X86TargetParser.def" 1147 .Default(false); 1148 } 1149 1150 static unsigned matchAsmCCConstraint(const char *&Name) { 1151 auto RV = llvm::StringSwitch<unsigned>(Name) 1152 .Case("@cca", 4) 1153 .Case("@ccae", 5) 1154 .Case("@ccb", 4) 1155 .Case("@ccbe", 5) 1156 .Case("@ccc", 4) 1157 .Case("@cce", 4) 1158 .Case("@ccz", 4) 1159 .Case("@ccg", 4) 1160 .Case("@ccge", 5) 1161 .Case("@ccl", 4) 1162 .Case("@ccle", 5) 1163 .Case("@ccna", 5) 1164 .Case("@ccnae", 6) 1165 .Case("@ccnb", 5) 1166 .Case("@ccnbe", 6) 1167 .Case("@ccnc", 5) 1168 .Case("@ccne", 5) 1169 .Case("@ccnz", 5) 1170 .Case("@ccng", 5) 1171 .Case("@ccnge", 6) 1172 .Case("@ccnl", 5) 1173 .Case("@ccnle", 6) 1174 .Case("@ccno", 5) 1175 .Case("@ccnp", 5) 1176 .Case("@ccns", 5) 1177 .Case("@cco", 4) 1178 .Case("@ccp", 4) 1179 .Case("@ccs", 4) 1180 .Default(0); 1181 return RV; 1182 } 1183 1184 bool X86TargetInfo::validateAsmConstraint( 1185 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1186 switch (*Name) { 1187 default: 1188 return false; 1189 // Constant constraints. 1190 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1191 // instructions. 1192 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1193 // x86_64 instructions. 1194 case 's': 1195 Info.setRequiresImmediate(); 1196 return true; 1197 case 'I': 1198 Info.setRequiresImmediate(0, 31); 1199 return true; 1200 case 'J': 1201 Info.setRequiresImmediate(0, 63); 1202 return true; 1203 case 'K': 1204 Info.setRequiresImmediate(-128, 127); 1205 return true; 1206 case 'L': 1207 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1208 return true; 1209 case 'M': 1210 Info.setRequiresImmediate(0, 3); 1211 return true; 1212 case 'N': 1213 Info.setRequiresImmediate(0, 255); 1214 return true; 1215 case 'O': 1216 Info.setRequiresImmediate(0, 127); 1217 return true; 1218 // Register constraints. 1219 case 'Y': // 'Y' is the first character for several 2-character constraints. 1220 // Shift the pointer to the second character of the constraint. 1221 Name++; 1222 switch (*Name) { 1223 default: 1224 return false; 1225 case 'z': // First SSE register. 1226 case '2': 1227 case 't': // Any SSE register, when SSE2 is enabled. 1228 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1229 case 'm': // Any MMX register, when inter-unit moves enabled. 1230 case 'k': // AVX512 arch mask registers: k1-k7. 1231 Info.setAllowsRegister(); 1232 return true; 1233 } 1234 case 'f': // Any x87 floating point stack register. 1235 // Constraint 'f' cannot be used for output operands. 1236 if (Info.ConstraintStr[0] == '=') 1237 return false; 1238 Info.setAllowsRegister(); 1239 return true; 1240 case 'a': // eax. 1241 case 'b': // ebx. 1242 case 'c': // ecx. 1243 case 'd': // edx. 1244 case 'S': // esi. 1245 case 'D': // edi. 1246 case 'A': // edx:eax. 1247 case 't': // Top of floating point stack. 1248 case 'u': // Second from top of floating point stack. 1249 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1250 case 'y': // Any MMX register. 1251 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1252 case 'x': // Any SSE register. 1253 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1254 // for intermideate k reg operations). 1255 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1256 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1257 case 'l': // "Index" registers: any general register that can be used as an 1258 // index in a base+index memory access. 1259 Info.setAllowsRegister(); 1260 return true; 1261 // Floating point constant constraints. 1262 case 'C': // SSE floating point constant. 1263 case 'G': // x87 floating point constant. 1264 return true; 1265 case '@': 1266 // CC condition changes. 1267 if (auto Len = matchAsmCCConstraint(Name)) { 1268 Name += Len - 1; 1269 Info.setAllowsRegister(); 1270 return true; 1271 } 1272 return false; 1273 } 1274 } 1275 1276 // Below is based on the following information: 1277 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1278 // | Processor Name | Cache Line Size (Bytes) | Source | 1279 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1280 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1281 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1282 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1283 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1284 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1285 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1286 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1287 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1288 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1289 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1290 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1291 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1292 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1293 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1294 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1295 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1296 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1297 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1298 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1299 using namespace llvm::X86; 1300 switch (CPU) { 1301 // i386 1302 case CK_i386: 1303 // i486 1304 case CK_i486: 1305 case CK_WinChipC6: 1306 case CK_WinChip2: 1307 case CK_C3: 1308 // Lakemont 1309 case CK_Lakemont: 1310 return 16; 1311 1312 // i586 1313 case CK_i586: 1314 case CK_Pentium: 1315 case CK_PentiumMMX: 1316 // i686 1317 case CK_PentiumPro: 1318 case CK_i686: 1319 case CK_Pentium2: 1320 case CK_Pentium3: 1321 case CK_PentiumM: 1322 case CK_C3_2: 1323 // K6 1324 case CK_K6: 1325 case CK_K6_2: 1326 case CK_K6_3: 1327 // Geode 1328 case CK_Geode: 1329 return 32; 1330 1331 // Netburst 1332 case CK_Pentium4: 1333 case CK_Prescott: 1334 case CK_Nocona: 1335 // Atom 1336 case CK_Bonnell: 1337 case CK_Silvermont: 1338 case CK_Goldmont: 1339 case CK_GoldmontPlus: 1340 case CK_Tremont: 1341 1342 case CK_Westmere: 1343 case CK_SandyBridge: 1344 case CK_IvyBridge: 1345 case CK_Haswell: 1346 case CK_Broadwell: 1347 case CK_SkylakeClient: 1348 case CK_SkylakeServer: 1349 case CK_Cascadelake: 1350 case CK_Nehalem: 1351 case CK_Cooperlake: 1352 case CK_Cannonlake: 1353 case CK_Tigerlake: 1354 case CK_SapphireRapids: 1355 case CK_IcelakeClient: 1356 case CK_Rocketlake: 1357 case CK_IcelakeServer: 1358 case CK_Alderlake: 1359 case CK_KNL: 1360 case CK_KNM: 1361 // K7 1362 case CK_Athlon: 1363 case CK_AthlonXP: 1364 // K8 1365 case CK_K8: 1366 case CK_K8SSE3: 1367 case CK_AMDFAM10: 1368 // Bobcat 1369 case CK_BTVER1: 1370 case CK_BTVER2: 1371 // Bulldozer 1372 case CK_BDVER1: 1373 case CK_BDVER2: 1374 case CK_BDVER3: 1375 case CK_BDVER4: 1376 // Zen 1377 case CK_ZNVER1: 1378 case CK_ZNVER2: 1379 case CK_ZNVER3: 1380 // Deprecated 1381 case CK_x86_64: 1382 case CK_x86_64_v2: 1383 case CK_x86_64_v3: 1384 case CK_x86_64_v4: 1385 case CK_Yonah: 1386 case CK_Penryn: 1387 case CK_Core2: 1388 return 64; 1389 1390 // The following currently have unknown cache line sizes (but they are probably all 64): 1391 // Core 1392 case CK_None: 1393 return None; 1394 } 1395 llvm_unreachable("Unknown CPU kind"); 1396 } 1397 1398 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1399 StringRef Constraint, 1400 unsigned Size) const { 1401 // Strip off constraint modifiers. 1402 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1403 Constraint = Constraint.substr(1); 1404 1405 return validateOperandSize(FeatureMap, Constraint, Size); 1406 } 1407 1408 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1409 StringRef Constraint, 1410 unsigned Size) const { 1411 return validateOperandSize(FeatureMap, Constraint, Size); 1412 } 1413 1414 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1415 StringRef Constraint, 1416 unsigned Size) const { 1417 switch (Constraint[0]) { 1418 default: 1419 break; 1420 case 'k': 1421 // Registers k0-k7 (AVX512) size limit is 64 bit. 1422 case 'y': 1423 return Size <= 64; 1424 case 'f': 1425 case 't': 1426 case 'u': 1427 return Size <= 128; 1428 case 'Y': 1429 // 'Y' is the first character for several 2-character constraints. 1430 switch (Constraint[1]) { 1431 default: 1432 return false; 1433 case 'm': 1434 // 'Ym' is synonymous with 'y'. 1435 case 'k': 1436 return Size <= 64; 1437 case 'z': 1438 // XMM0/YMM/ZMM0 1439 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1440 // ZMM0 can be used if target supports AVX512F. 1441 return Size <= 512U; 1442 else if (hasFeatureEnabled(FeatureMap, "avx")) 1443 // YMM0 can be used if target supports AVX. 1444 return Size <= 256U; 1445 else if (hasFeatureEnabled(FeatureMap, "sse")) 1446 return Size <= 128U; 1447 return false; 1448 case 'i': 1449 case 't': 1450 case '2': 1451 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1452 if (SSELevel < SSE2) 1453 return false; 1454 break; 1455 } 1456 break; 1457 case 'v': 1458 case 'x': 1459 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1460 // 512-bit zmm registers can be used if target supports AVX512F. 1461 return Size <= 512U; 1462 else if (hasFeatureEnabled(FeatureMap, "avx")) 1463 // 256-bit ymm registers can be used if target supports AVX. 1464 return Size <= 256U; 1465 return Size <= 128U; 1466 1467 } 1468 1469 return true; 1470 } 1471 1472 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1473 switch (*Constraint) { 1474 case '@': 1475 if (auto Len = matchAsmCCConstraint(Constraint)) { 1476 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1477 Constraint += Len - 1; 1478 return Converted; 1479 } 1480 return std::string(1, *Constraint); 1481 case 'a': 1482 return std::string("{ax}"); 1483 case 'b': 1484 return std::string("{bx}"); 1485 case 'c': 1486 return std::string("{cx}"); 1487 case 'd': 1488 return std::string("{dx}"); 1489 case 'S': 1490 return std::string("{si}"); 1491 case 'D': 1492 return std::string("{di}"); 1493 case 'p': // address 1494 return std::string("im"); 1495 case 't': // top of floating point stack. 1496 return std::string("{st}"); 1497 case 'u': // second from top of floating point stack. 1498 return std::string("{st(1)}"); // second from top of floating point stack. 1499 case 'Y': 1500 switch (Constraint[1]) { 1501 default: 1502 // Break from inner switch and fall through (copy single char), 1503 // continue parsing after copying the current constraint into 1504 // the return string. 1505 break; 1506 case 'k': 1507 case 'm': 1508 case 'i': 1509 case 't': 1510 case 'z': 1511 case '2': 1512 // "^" hints llvm that this is a 2 letter constraint. 1513 // "Constraint++" is used to promote the string iterator 1514 // to the next constraint. 1515 return std::string("^") + std::string(Constraint++, 2); 1516 } 1517 LLVM_FALLTHROUGH; 1518 default: 1519 return std::string(1, *Constraint); 1520 } 1521 } 1522 1523 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1524 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1525 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1526 } 1527 1528 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1529 llvm::X86::fillValidTuneCPUList(Values); 1530 } 1531 1532 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1533 return llvm::makeArrayRef(GCCRegNames); 1534 } 1535 1536 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1537 return llvm::makeArrayRef(AddlRegNames); 1538 } 1539 1540 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1541 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1542 Builtin::FirstTSBuiltin + 1); 1543 } 1544 1545 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1546 return llvm::makeArrayRef(BuiltinInfoX86, 1547 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1548 } 1549