1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_PentiumMMX: 135 case CK_Pentium2: 136 case CK_K6: 137 case CK_WinChipC6: 138 setFeatureEnabledImpl(Features, "mmx", true); 139 break; 140 141 case CK_Cooperlake: 142 // CPX inherits all CLX features plus AVX512BF16 143 setFeatureEnabledImpl(Features, "avx512bf16", true); 144 LLVM_FALLTHROUGH; 145 case CK_Cascadelake: 146 // CLX inherits all SKX features plus AVX512VNNI 147 setFeatureEnabledImpl(Features, "avx512vnni", true); 148 LLVM_FALLTHROUGH; 149 case CK_SkylakeServer: 150 setFeatureEnabledImpl(Features, "avx512f", true); 151 setFeatureEnabledImpl(Features, "avx512cd", true); 152 setFeatureEnabledImpl(Features, "avx512dq", true); 153 setFeatureEnabledImpl(Features, "avx512bw", true); 154 setFeatureEnabledImpl(Features, "avx512vl", true); 155 setFeatureEnabledImpl(Features, "clwb", true); 156 setFeatureEnabledImpl(Features, "pku", true); 157 // SkylakeServer cores inherits all SKL features, except SGX 158 goto SkylakeCommon; 159 160 case CK_IcelakeServer: 161 setFeatureEnabledImpl(Features, "pconfig", true); 162 setFeatureEnabledImpl(Features, "wbnoinvd", true); 163 LLVM_FALLTHROUGH; 164 case CK_IcelakeClient: 165 setFeatureEnabledImpl(Features, "vaes", true); 166 setFeatureEnabledImpl(Features, "gfni", true); 167 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 168 setFeatureEnabledImpl(Features, "avx512bitalg", true); 169 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 170 setFeatureEnabledImpl(Features, "avx512vnni", true); 171 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 172 setFeatureEnabledImpl(Features, "rdpid", true); 173 setFeatureEnabledImpl(Features, "clwb", true); 174 LLVM_FALLTHROUGH; 175 case CK_Cannonlake: 176 setFeatureEnabledImpl(Features, "avx512f", true); 177 setFeatureEnabledImpl(Features, "avx512cd", true); 178 setFeatureEnabledImpl(Features, "avx512dq", true); 179 setFeatureEnabledImpl(Features, "avx512bw", true); 180 setFeatureEnabledImpl(Features, "avx512vl", true); 181 setFeatureEnabledImpl(Features, "avx512ifma", true); 182 setFeatureEnabledImpl(Features, "avx512vbmi", true); 183 setFeatureEnabledImpl(Features, "pku", true); 184 setFeatureEnabledImpl(Features, "sha", true); 185 LLVM_FALLTHROUGH; 186 case CK_SkylakeClient: 187 setFeatureEnabledImpl(Features, "sgx", true); 188 // SkylakeServer cores inherits all SKL features, except SGX 189 SkylakeCommon: 190 setFeatureEnabledImpl(Features, "xsavec", true); 191 setFeatureEnabledImpl(Features, "xsaves", true); 192 setFeatureEnabledImpl(Features, "mpx", true); 193 setFeatureEnabledImpl(Features, "clflushopt", true); 194 setFeatureEnabledImpl(Features, "aes", true); 195 LLVM_FALLTHROUGH; 196 case CK_Broadwell: 197 setFeatureEnabledImpl(Features, "rdseed", true); 198 setFeatureEnabledImpl(Features, "adx", true); 199 setFeatureEnabledImpl(Features, "prfchw", true); 200 LLVM_FALLTHROUGH; 201 case CK_Haswell: 202 setFeatureEnabledImpl(Features, "avx2", true); 203 setFeatureEnabledImpl(Features, "lzcnt", true); 204 setFeatureEnabledImpl(Features, "bmi", true); 205 setFeatureEnabledImpl(Features, "bmi2", true); 206 setFeatureEnabledImpl(Features, "fma", true); 207 setFeatureEnabledImpl(Features, "invpcid", true); 208 setFeatureEnabledImpl(Features, "movbe", true); 209 LLVM_FALLTHROUGH; 210 case CK_IvyBridge: 211 setFeatureEnabledImpl(Features, "rdrnd", true); 212 setFeatureEnabledImpl(Features, "f16c", true); 213 setFeatureEnabledImpl(Features, "fsgsbase", true); 214 LLVM_FALLTHROUGH; 215 case CK_SandyBridge: 216 setFeatureEnabledImpl(Features, "avx", true); 217 setFeatureEnabledImpl(Features, "xsave", true); 218 setFeatureEnabledImpl(Features, "xsaveopt", true); 219 LLVM_FALLTHROUGH; 220 case CK_Westmere: 221 setFeatureEnabledImpl(Features, "pclmul", true); 222 LLVM_FALLTHROUGH; 223 case CK_Nehalem: 224 setFeatureEnabledImpl(Features, "sse4.2", true); 225 LLVM_FALLTHROUGH; 226 case CK_Penryn: 227 setFeatureEnabledImpl(Features, "sse4.1", true); 228 LLVM_FALLTHROUGH; 229 case CK_Core2: 230 setFeatureEnabledImpl(Features, "ssse3", true); 231 setFeatureEnabledImpl(Features, "sahf", true); 232 LLVM_FALLTHROUGH; 233 case CK_Nocona: 234 setFeatureEnabledImpl(Features, "cx16", true); 235 LLVM_FALLTHROUGH; 236 case CK_Yonah: 237 case CK_Prescott: 238 setFeatureEnabledImpl(Features, "sse3", true); 239 LLVM_FALLTHROUGH; 240 case CK_PentiumM: 241 case CK_Pentium4: 242 case CK_x86_64: 243 setFeatureEnabledImpl(Features, "sse2", true); 244 LLVM_FALLTHROUGH; 245 case CK_Pentium3: 246 case CK_C3_2: 247 setFeatureEnabledImpl(Features, "sse", true); 248 setFeatureEnabledImpl(Features, "fxsr", true); 249 break; 250 251 case CK_Tremont: 252 setFeatureEnabledImpl(Features, "cldemote", true); 253 setFeatureEnabledImpl(Features, "movdiri", true); 254 setFeatureEnabledImpl(Features, "movdir64b", true); 255 setFeatureEnabledImpl(Features, "gfni", true); 256 setFeatureEnabledImpl(Features, "waitpkg", true); 257 LLVM_FALLTHROUGH; 258 case CK_GoldmontPlus: 259 setFeatureEnabledImpl(Features, "ptwrite", true); 260 setFeatureEnabledImpl(Features, "rdpid", true); 261 setFeatureEnabledImpl(Features, "sgx", true); 262 LLVM_FALLTHROUGH; 263 case CK_Goldmont: 264 setFeatureEnabledImpl(Features, "sha", true); 265 setFeatureEnabledImpl(Features, "rdseed", true); 266 setFeatureEnabledImpl(Features, "xsave", true); 267 setFeatureEnabledImpl(Features, "xsaveopt", true); 268 setFeatureEnabledImpl(Features, "xsavec", true); 269 setFeatureEnabledImpl(Features, "xsaves", true); 270 setFeatureEnabledImpl(Features, "clflushopt", true); 271 setFeatureEnabledImpl(Features, "mpx", true); 272 setFeatureEnabledImpl(Features, "fsgsbase", true); 273 setFeatureEnabledImpl(Features, "aes", true); 274 LLVM_FALLTHROUGH; 275 case CK_Silvermont: 276 setFeatureEnabledImpl(Features, "rdrnd", true); 277 setFeatureEnabledImpl(Features, "pclmul", true); 278 setFeatureEnabledImpl(Features, "sse4.2", true); 279 setFeatureEnabledImpl(Features, "prfchw", true); 280 LLVM_FALLTHROUGH; 281 case CK_Bonnell: 282 setFeatureEnabledImpl(Features, "movbe", true); 283 setFeatureEnabledImpl(Features, "ssse3", true); 284 setFeatureEnabledImpl(Features, "fxsr", true); 285 setFeatureEnabledImpl(Features, "cx16", true); 286 setFeatureEnabledImpl(Features, "sahf", true); 287 break; 288 289 case CK_KNM: 290 // TODO: Add avx5124fmaps/avx5124vnniw. 291 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 292 LLVM_FALLTHROUGH; 293 case CK_KNL: 294 setFeatureEnabledImpl(Features, "avx512f", true); 295 setFeatureEnabledImpl(Features, "avx512cd", true); 296 setFeatureEnabledImpl(Features, "avx512er", true); 297 setFeatureEnabledImpl(Features, "avx512pf", true); 298 setFeatureEnabledImpl(Features, "prfchw", true); 299 setFeatureEnabledImpl(Features, "prefetchwt1", true); 300 setFeatureEnabledImpl(Features, "fxsr", true); 301 setFeatureEnabledImpl(Features, "rdseed", true); 302 setFeatureEnabledImpl(Features, "adx", true); 303 setFeatureEnabledImpl(Features, "lzcnt", true); 304 setFeatureEnabledImpl(Features, "bmi", true); 305 setFeatureEnabledImpl(Features, "bmi2", true); 306 setFeatureEnabledImpl(Features, "fma", true); 307 setFeatureEnabledImpl(Features, "rdrnd", true); 308 setFeatureEnabledImpl(Features, "f16c", true); 309 setFeatureEnabledImpl(Features, "fsgsbase", true); 310 setFeatureEnabledImpl(Features, "aes", true); 311 setFeatureEnabledImpl(Features, "pclmul", true); 312 setFeatureEnabledImpl(Features, "cx16", true); 313 setFeatureEnabledImpl(Features, "xsaveopt", true); 314 setFeatureEnabledImpl(Features, "xsave", true); 315 setFeatureEnabledImpl(Features, "movbe", true); 316 setFeatureEnabledImpl(Features, "sahf", true); 317 break; 318 319 case CK_K6_2: 320 case CK_K6_3: 321 case CK_WinChip2: 322 case CK_C3: 323 setFeatureEnabledImpl(Features, "3dnow", true); 324 break; 325 326 case CK_AMDFAM10: 327 setFeatureEnabledImpl(Features, "sse4a", true); 328 setFeatureEnabledImpl(Features, "lzcnt", true); 329 setFeatureEnabledImpl(Features, "popcnt", true); 330 setFeatureEnabledImpl(Features, "sahf", true); 331 LLVM_FALLTHROUGH; 332 case CK_K8SSE3: 333 setFeatureEnabledImpl(Features, "sse3", true); 334 LLVM_FALLTHROUGH; 335 case CK_K8: 336 setFeatureEnabledImpl(Features, "sse2", true); 337 LLVM_FALLTHROUGH; 338 case CK_AthlonXP: 339 setFeatureEnabledImpl(Features, "sse", true); 340 setFeatureEnabledImpl(Features, "fxsr", true); 341 LLVM_FALLTHROUGH; 342 case CK_Athlon: 343 case CK_Geode: 344 setFeatureEnabledImpl(Features, "3dnowa", true); 345 break; 346 347 case CK_BTVER2: 348 setFeatureEnabledImpl(Features, "avx", true); 349 setFeatureEnabledImpl(Features, "aes", true); 350 setFeatureEnabledImpl(Features, "pclmul", true); 351 setFeatureEnabledImpl(Features, "bmi", true); 352 setFeatureEnabledImpl(Features, "f16c", true); 353 setFeatureEnabledImpl(Features, "xsaveopt", true); 354 setFeatureEnabledImpl(Features, "movbe", true); 355 LLVM_FALLTHROUGH; 356 case CK_BTVER1: 357 setFeatureEnabledImpl(Features, "ssse3", true); 358 setFeatureEnabledImpl(Features, "sse4a", true); 359 setFeatureEnabledImpl(Features, "lzcnt", true); 360 setFeatureEnabledImpl(Features, "popcnt", true); 361 setFeatureEnabledImpl(Features, "prfchw", true); 362 setFeatureEnabledImpl(Features, "cx16", true); 363 setFeatureEnabledImpl(Features, "fxsr", true); 364 setFeatureEnabledImpl(Features, "sahf", true); 365 break; 366 367 case CK_ZNVER2: 368 setFeatureEnabledImpl(Features, "clwb", true); 369 setFeatureEnabledImpl(Features, "rdpid", true); 370 setFeatureEnabledImpl(Features, "wbnoinvd", true); 371 LLVM_FALLTHROUGH; 372 case CK_ZNVER1: 373 setFeatureEnabledImpl(Features, "adx", true); 374 setFeatureEnabledImpl(Features, "aes", true); 375 setFeatureEnabledImpl(Features, "avx2", true); 376 setFeatureEnabledImpl(Features, "bmi", true); 377 setFeatureEnabledImpl(Features, "bmi2", true); 378 setFeatureEnabledImpl(Features, "clflushopt", true); 379 setFeatureEnabledImpl(Features, "clzero", true); 380 setFeatureEnabledImpl(Features, "cx16", true); 381 setFeatureEnabledImpl(Features, "f16c", true); 382 setFeatureEnabledImpl(Features, "fma", true); 383 setFeatureEnabledImpl(Features, "fsgsbase", true); 384 setFeatureEnabledImpl(Features, "fxsr", true); 385 setFeatureEnabledImpl(Features, "lzcnt", true); 386 setFeatureEnabledImpl(Features, "mwaitx", true); 387 setFeatureEnabledImpl(Features, "movbe", true); 388 setFeatureEnabledImpl(Features, "pclmul", true); 389 setFeatureEnabledImpl(Features, "popcnt", true); 390 setFeatureEnabledImpl(Features, "prfchw", true); 391 setFeatureEnabledImpl(Features, "rdrnd", true); 392 setFeatureEnabledImpl(Features, "rdseed", true); 393 setFeatureEnabledImpl(Features, "sahf", true); 394 setFeatureEnabledImpl(Features, "sha", true); 395 setFeatureEnabledImpl(Features, "sse4a", true); 396 setFeatureEnabledImpl(Features, "xsave", true); 397 setFeatureEnabledImpl(Features, "xsavec", true); 398 setFeatureEnabledImpl(Features, "xsaveopt", true); 399 setFeatureEnabledImpl(Features, "xsaves", true); 400 break; 401 402 case CK_BDVER4: 403 setFeatureEnabledImpl(Features, "avx2", true); 404 setFeatureEnabledImpl(Features, "bmi2", true); 405 setFeatureEnabledImpl(Features, "mwaitx", true); 406 LLVM_FALLTHROUGH; 407 case CK_BDVER3: 408 setFeatureEnabledImpl(Features, "fsgsbase", true); 409 setFeatureEnabledImpl(Features, "xsaveopt", true); 410 LLVM_FALLTHROUGH; 411 case CK_BDVER2: 412 setFeatureEnabledImpl(Features, "bmi", true); 413 setFeatureEnabledImpl(Features, "fma", true); 414 setFeatureEnabledImpl(Features, "f16c", true); 415 setFeatureEnabledImpl(Features, "tbm", true); 416 LLVM_FALLTHROUGH; 417 case CK_BDVER1: 418 // xop implies avx, sse4a and fma4. 419 setFeatureEnabledImpl(Features, "xop", true); 420 setFeatureEnabledImpl(Features, "lwp", true); 421 setFeatureEnabledImpl(Features, "lzcnt", true); 422 setFeatureEnabledImpl(Features, "aes", true); 423 setFeatureEnabledImpl(Features, "pclmul", true); 424 setFeatureEnabledImpl(Features, "prfchw", true); 425 setFeatureEnabledImpl(Features, "cx16", true); 426 setFeatureEnabledImpl(Features, "fxsr", true); 427 setFeatureEnabledImpl(Features, "xsave", true); 428 setFeatureEnabledImpl(Features, "sahf", true); 429 break; 430 } 431 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 432 return false; 433 434 // Can't do this earlier because we need to be able to explicitly enable 435 // or disable these features and the things that they depend upon. 436 437 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 438 auto I = Features.find("sse4.2"); 439 if (I != Features.end() && I->getValue() && 440 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 441 Features["popcnt"] = true; 442 443 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 444 I = Features.find("3dnow"); 445 if (I != Features.end() && I->getValue() && 446 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 447 Features["prfchw"] = true; 448 449 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 450 // then enable MMX. 451 I = Features.find("sse"); 452 if (I != Features.end() && I->getValue() && 453 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 454 Features["mmx"] = true; 455 456 return true; 457 } 458 459 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 460 X86SSEEnum Level, bool Enabled) { 461 if (Enabled) { 462 switch (Level) { 463 case AVX512F: 464 Features["avx512f"] = true; 465 Features["fma"] = true; 466 Features["f16c"] = true; 467 LLVM_FALLTHROUGH; 468 case AVX2: 469 Features["avx2"] = true; 470 LLVM_FALLTHROUGH; 471 case AVX: 472 Features["avx"] = true; 473 Features["xsave"] = true; 474 LLVM_FALLTHROUGH; 475 case SSE42: 476 Features["sse4.2"] = true; 477 LLVM_FALLTHROUGH; 478 case SSE41: 479 Features["sse4.1"] = true; 480 LLVM_FALLTHROUGH; 481 case SSSE3: 482 Features["ssse3"] = true; 483 LLVM_FALLTHROUGH; 484 case SSE3: 485 Features["sse3"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE2: 488 Features["sse2"] = true; 489 LLVM_FALLTHROUGH; 490 case SSE1: 491 Features["sse"] = true; 492 LLVM_FALLTHROUGH; 493 case NoSSE: 494 break; 495 } 496 return; 497 } 498 499 switch (Level) { 500 case NoSSE: 501 case SSE1: 502 Features["sse"] = false; 503 LLVM_FALLTHROUGH; 504 case SSE2: 505 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 506 Features["sha"] = Features["gfni"] = false; 507 LLVM_FALLTHROUGH; 508 case SSE3: 509 Features["sse3"] = false; 510 setXOPLevel(Features, NoXOP, false); 511 LLVM_FALLTHROUGH; 512 case SSSE3: 513 Features["ssse3"] = false; 514 LLVM_FALLTHROUGH; 515 case SSE41: 516 Features["sse4.1"] = false; 517 LLVM_FALLTHROUGH; 518 case SSE42: 519 Features["sse4.2"] = false; 520 LLVM_FALLTHROUGH; 521 case AVX: 522 Features["fma"] = Features["avx"] = Features["f16c"] = false; 523 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 524 Features["vpclmulqdq"] = false; 525 setXOPLevel(Features, FMA4, false); 526 LLVM_FALLTHROUGH; 527 case AVX2: 528 Features["avx2"] = false; 529 LLVM_FALLTHROUGH; 530 case AVX512F: 531 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 532 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 533 Features["avx512vl"] = Features["avx512vbmi"] = false; 534 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 535 Features["avx512bitalg"] = Features["avx512vnni"] = false; 536 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 537 Features["avx512vp2intersect"] = false; 538 break; 539 } 540 } 541 542 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 543 MMX3DNowEnum Level, bool Enabled) { 544 if (Enabled) { 545 switch (Level) { 546 case AMD3DNowAthlon: 547 Features["3dnowa"] = true; 548 LLVM_FALLTHROUGH; 549 case AMD3DNow: 550 Features["3dnow"] = true; 551 LLVM_FALLTHROUGH; 552 case MMX: 553 Features["mmx"] = true; 554 LLVM_FALLTHROUGH; 555 case NoMMX3DNow: 556 break; 557 } 558 return; 559 } 560 561 switch (Level) { 562 case NoMMX3DNow: 563 case MMX: 564 Features["mmx"] = false; 565 LLVM_FALLTHROUGH; 566 case AMD3DNow: 567 Features["3dnow"] = false; 568 LLVM_FALLTHROUGH; 569 case AMD3DNowAthlon: 570 Features["3dnowa"] = false; 571 break; 572 } 573 } 574 575 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 576 bool Enabled) { 577 if (Enabled) { 578 switch (Level) { 579 case XOP: 580 Features["xop"] = true; 581 LLVM_FALLTHROUGH; 582 case FMA4: 583 Features["fma4"] = true; 584 setSSELevel(Features, AVX, true); 585 LLVM_FALLTHROUGH; 586 case SSE4A: 587 Features["sse4a"] = true; 588 setSSELevel(Features, SSE3, true); 589 LLVM_FALLTHROUGH; 590 case NoXOP: 591 break; 592 } 593 return; 594 } 595 596 switch (Level) { 597 case NoXOP: 598 case SSE4A: 599 Features["sse4a"] = false; 600 LLVM_FALLTHROUGH; 601 case FMA4: 602 Features["fma4"] = false; 603 LLVM_FALLTHROUGH; 604 case XOP: 605 Features["xop"] = false; 606 break; 607 } 608 } 609 610 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 611 StringRef Name, bool Enabled) { 612 // This is a bit of a hack to deal with the sse4 target feature when used 613 // as part of the target attribute. We handle sse4 correctly everywhere 614 // else. See below for more information on how we handle the sse4 options. 615 if (Name != "sse4") 616 Features[Name] = Enabled; 617 618 if (Name == "mmx") { 619 setMMXLevel(Features, MMX, Enabled); 620 } else if (Name == "sse") { 621 setSSELevel(Features, SSE1, Enabled); 622 } else if (Name == "sse2") { 623 setSSELevel(Features, SSE2, Enabled); 624 } else if (Name == "sse3") { 625 setSSELevel(Features, SSE3, Enabled); 626 } else if (Name == "ssse3") { 627 setSSELevel(Features, SSSE3, Enabled); 628 } else if (Name == "sse4.2") { 629 setSSELevel(Features, SSE42, Enabled); 630 } else if (Name == "sse4.1") { 631 setSSELevel(Features, SSE41, Enabled); 632 } else if (Name == "3dnow") { 633 setMMXLevel(Features, AMD3DNow, Enabled); 634 } else if (Name == "3dnowa") { 635 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 636 } else if (Name == "aes") { 637 if (Enabled) 638 setSSELevel(Features, SSE2, Enabled); 639 else 640 Features["vaes"] = false; 641 } else if (Name == "vaes") { 642 if (Enabled) { 643 setSSELevel(Features, AVX, Enabled); 644 Features["aes"] = true; 645 } 646 } else if (Name == "pclmul") { 647 if (Enabled) 648 setSSELevel(Features, SSE2, Enabled); 649 else 650 Features["vpclmulqdq"] = false; 651 } else if (Name == "vpclmulqdq") { 652 if (Enabled) { 653 setSSELevel(Features, AVX, Enabled); 654 Features["pclmul"] = true; 655 } 656 } else if (Name == "gfni") { 657 if (Enabled) 658 setSSELevel(Features, SSE2, Enabled); 659 } else if (Name == "avx") { 660 setSSELevel(Features, AVX, Enabled); 661 } else if (Name == "avx2") { 662 setSSELevel(Features, AVX2, Enabled); 663 } else if (Name == "avx512f") { 664 setSSELevel(Features, AVX512F, Enabled); 665 } else if (Name.startswith("avx512")) { 666 if (Enabled) 667 setSSELevel(Features, AVX512F, Enabled); 668 // Enable BWI instruction if certain features are being enabled. 669 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 670 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 671 Features["avx512bw"] = true; 672 // Also disable some features if BWI is being disabled. 673 if (Name == "avx512bw" && !Enabled) { 674 Features["avx512vbmi"] = false; 675 Features["avx512vbmi2"] = false; 676 Features["avx512bitalg"] = false; 677 Features["avx512bf16"] = false; 678 } 679 } else if (Name == "fma") { 680 if (Enabled) 681 setSSELevel(Features, AVX, Enabled); 682 else 683 setSSELevel(Features, AVX512F, Enabled); 684 } else if (Name == "fma4") { 685 setXOPLevel(Features, FMA4, Enabled); 686 } else if (Name == "xop") { 687 setXOPLevel(Features, XOP, Enabled); 688 } else if (Name == "sse4a") { 689 setXOPLevel(Features, SSE4A, Enabled); 690 } else if (Name == "f16c") { 691 if (Enabled) 692 setSSELevel(Features, AVX, Enabled); 693 else 694 setSSELevel(Features, AVX512F, Enabled); 695 } else if (Name == "sha") { 696 if (Enabled) 697 setSSELevel(Features, SSE2, Enabled); 698 } else if (Name == "sse4") { 699 // We can get here via the __target__ attribute since that's not controlled 700 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 701 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 702 // disabled. 703 if (Enabled) 704 setSSELevel(Features, SSE42, Enabled); 705 else 706 setSSELevel(Features, SSE41, Enabled); 707 } else if (Name == "xsave") { 708 if (!Enabled) 709 Features["xsaveopt"] = false; 710 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 711 if (Enabled) 712 Features["xsave"] = true; 713 } 714 } 715 716 /// handleTargetFeatures - Perform initialization based on the user 717 /// configured set of features. 718 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 719 DiagnosticsEngine &Diags) { 720 for (const auto &Feature : Features) { 721 if (Feature[0] != '+') 722 continue; 723 724 if (Feature == "+aes") { 725 HasAES = true; 726 } else if (Feature == "+vaes") { 727 HasVAES = true; 728 } else if (Feature == "+pclmul") { 729 HasPCLMUL = true; 730 } else if (Feature == "+vpclmulqdq") { 731 HasVPCLMULQDQ = true; 732 } else if (Feature == "+lzcnt") { 733 HasLZCNT = true; 734 } else if (Feature == "+rdrnd") { 735 HasRDRND = true; 736 } else if (Feature == "+fsgsbase") { 737 HasFSGSBASE = true; 738 } else if (Feature == "+bmi") { 739 HasBMI = true; 740 } else if (Feature == "+bmi2") { 741 HasBMI2 = true; 742 } else if (Feature == "+popcnt") { 743 HasPOPCNT = true; 744 } else if (Feature == "+rtm") { 745 HasRTM = true; 746 } else if (Feature == "+prfchw") { 747 HasPRFCHW = true; 748 } else if (Feature == "+rdseed") { 749 HasRDSEED = true; 750 } else if (Feature == "+adx") { 751 HasADX = true; 752 } else if (Feature == "+tbm") { 753 HasTBM = true; 754 } else if (Feature == "+lwp") { 755 HasLWP = true; 756 } else if (Feature == "+fma") { 757 HasFMA = true; 758 } else if (Feature == "+f16c") { 759 HasF16C = true; 760 } else if (Feature == "+gfni") { 761 HasGFNI = true; 762 } else if (Feature == "+avx512cd") { 763 HasAVX512CD = true; 764 } else if (Feature == "+avx512vpopcntdq") { 765 HasAVX512VPOPCNTDQ = true; 766 } else if (Feature == "+avx512vnni") { 767 HasAVX512VNNI = true; 768 } else if (Feature == "+avx512bf16") { 769 HasAVX512BF16 = true; 770 } else if (Feature == "+avx512er") { 771 HasAVX512ER = true; 772 } else if (Feature == "+avx512pf") { 773 HasAVX512PF = true; 774 } else if (Feature == "+avx512dq") { 775 HasAVX512DQ = true; 776 } else if (Feature == "+avx512bitalg") { 777 HasAVX512BITALG = true; 778 } else if (Feature == "+avx512bw") { 779 HasAVX512BW = true; 780 } else if (Feature == "+avx512vl") { 781 HasAVX512VL = true; 782 } else if (Feature == "+avx512vbmi") { 783 HasAVX512VBMI = true; 784 } else if (Feature == "+avx512vbmi2") { 785 HasAVX512VBMI2 = true; 786 } else if (Feature == "+avx512ifma") { 787 HasAVX512IFMA = true; 788 } else if (Feature == "+avx512vp2intersect") { 789 HasAVX512VP2INTERSECT = true; 790 } else if (Feature == "+sha") { 791 HasSHA = true; 792 } else if (Feature == "+mpx") { 793 HasMPX = true; 794 } else if (Feature == "+shstk") { 795 HasSHSTK = true; 796 } else if (Feature == "+movbe") { 797 HasMOVBE = true; 798 } else if (Feature == "+sgx") { 799 HasSGX = true; 800 } else if (Feature == "+cx8") { 801 HasCX8 = true; 802 } else if (Feature == "+cx16") { 803 HasCX16 = true; 804 } else if (Feature == "+fxsr") { 805 HasFXSR = true; 806 } else if (Feature == "+xsave") { 807 HasXSAVE = true; 808 } else if (Feature == "+xsaveopt") { 809 HasXSAVEOPT = true; 810 } else if (Feature == "+xsavec") { 811 HasXSAVEC = true; 812 } else if (Feature == "+xsaves") { 813 HasXSAVES = true; 814 } else if (Feature == "+mwaitx") { 815 HasMWAITX = true; 816 } else if (Feature == "+pku") { 817 HasPKU = true; 818 } else if (Feature == "+clflushopt") { 819 HasCLFLUSHOPT = true; 820 } else if (Feature == "+clwb") { 821 HasCLWB = true; 822 } else if (Feature == "+wbnoinvd") { 823 HasWBNOINVD = true; 824 } else if (Feature == "+prefetchwt1") { 825 HasPREFETCHWT1 = true; 826 } else if (Feature == "+clzero") { 827 HasCLZERO = true; 828 } else if (Feature == "+cldemote") { 829 HasCLDEMOTE = true; 830 } else if (Feature == "+rdpid") { 831 HasRDPID = true; 832 } else if (Feature == "+retpoline-external-thunk") { 833 HasRetpolineExternalThunk = true; 834 } else if (Feature == "+sahf") { 835 HasLAHFSAHF = true; 836 } else if (Feature == "+waitpkg") { 837 HasWAITPKG = true; 838 } else if (Feature == "+movdiri") { 839 HasMOVDIRI = true; 840 } else if (Feature == "+movdir64b") { 841 HasMOVDIR64B = true; 842 } else if (Feature == "+pconfig") { 843 HasPCONFIG = true; 844 } else if (Feature == "+ptwrite") { 845 HasPTWRITE = true; 846 } else if (Feature == "+invpcid") { 847 HasINVPCID = true; 848 } else if (Feature == "+enqcmd") { 849 HasENQCMD = true; 850 } 851 852 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 853 .Case("+avx512f", AVX512F) 854 .Case("+avx2", AVX2) 855 .Case("+avx", AVX) 856 .Case("+sse4.2", SSE42) 857 .Case("+sse4.1", SSE41) 858 .Case("+ssse3", SSSE3) 859 .Case("+sse3", SSE3) 860 .Case("+sse2", SSE2) 861 .Case("+sse", SSE1) 862 .Default(NoSSE); 863 SSELevel = std::max(SSELevel, Level); 864 865 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 866 .Case("+3dnowa", AMD3DNowAthlon) 867 .Case("+3dnow", AMD3DNow) 868 .Case("+mmx", MMX) 869 .Default(NoMMX3DNow); 870 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 871 872 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 873 .Case("+xop", XOP) 874 .Case("+fma4", FMA4) 875 .Case("+sse4a", SSE4A) 876 .Default(NoXOP); 877 XOPLevel = std::max(XOPLevel, XLevel); 878 } 879 880 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 881 // matches the selected sse level. 882 if ((FPMath == FP_SSE && SSELevel < SSE1) || 883 (FPMath == FP_387 && SSELevel >= SSE1)) { 884 Diags.Report(diag::err_target_unsupported_fpmath) 885 << (FPMath == FP_SSE ? "sse" : "387"); 886 return false; 887 } 888 889 SimdDefaultAlign = 890 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 891 return true; 892 } 893 894 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 895 /// definitions for this particular subtarget. 896 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 897 MacroBuilder &Builder) const { 898 // Inline assembly supports X86 flag outputs. 899 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 900 901 std::string CodeModel = getTargetOpts().CodeModel; 902 if (CodeModel == "default") 903 CodeModel = "small"; 904 Builder.defineMacro("__code_model_" + CodeModel + "_"); 905 906 // Target identification. 907 if (getTriple().getArch() == llvm::Triple::x86_64) { 908 Builder.defineMacro("__amd64__"); 909 Builder.defineMacro("__amd64"); 910 Builder.defineMacro("__x86_64"); 911 Builder.defineMacro("__x86_64__"); 912 if (getTriple().getArchName() == "x86_64h") { 913 Builder.defineMacro("__x86_64h"); 914 Builder.defineMacro("__x86_64h__"); 915 } 916 } else { 917 DefineStd(Builder, "i386", Opts); 918 } 919 920 // Subtarget options. 921 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 922 // truly should be based on -mtune options. 923 switch (CPU) { 924 case CK_Generic: 925 break; 926 case CK_i386: 927 // The rest are coming from the i386 define above. 928 Builder.defineMacro("__tune_i386__"); 929 break; 930 case CK_i486: 931 case CK_WinChipC6: 932 case CK_WinChip2: 933 case CK_C3: 934 defineCPUMacros(Builder, "i486"); 935 break; 936 case CK_PentiumMMX: 937 Builder.defineMacro("__pentium_mmx__"); 938 Builder.defineMacro("__tune_pentium_mmx__"); 939 LLVM_FALLTHROUGH; 940 case CK_i586: 941 case CK_Pentium: 942 defineCPUMacros(Builder, "i586"); 943 defineCPUMacros(Builder, "pentium"); 944 break; 945 case CK_Pentium3: 946 case CK_PentiumM: 947 Builder.defineMacro("__tune_pentium3__"); 948 LLVM_FALLTHROUGH; 949 case CK_Pentium2: 950 case CK_C3_2: 951 Builder.defineMacro("__tune_pentium2__"); 952 LLVM_FALLTHROUGH; 953 case CK_PentiumPro: 954 case CK_i686: 955 defineCPUMacros(Builder, "i686"); 956 defineCPUMacros(Builder, "pentiumpro"); 957 break; 958 case CK_Pentium4: 959 defineCPUMacros(Builder, "pentium4"); 960 break; 961 case CK_Yonah: 962 case CK_Prescott: 963 case CK_Nocona: 964 defineCPUMacros(Builder, "nocona"); 965 break; 966 case CK_Core2: 967 case CK_Penryn: 968 defineCPUMacros(Builder, "core2"); 969 break; 970 case CK_Bonnell: 971 defineCPUMacros(Builder, "atom"); 972 break; 973 case CK_Silvermont: 974 defineCPUMacros(Builder, "slm"); 975 break; 976 case CK_Goldmont: 977 defineCPUMacros(Builder, "goldmont"); 978 break; 979 case CK_GoldmontPlus: 980 defineCPUMacros(Builder, "goldmont_plus"); 981 break; 982 case CK_Tremont: 983 defineCPUMacros(Builder, "tremont"); 984 break; 985 case CK_Nehalem: 986 case CK_Westmere: 987 case CK_SandyBridge: 988 case CK_IvyBridge: 989 case CK_Haswell: 990 case CK_Broadwell: 991 case CK_SkylakeClient: 992 case CK_SkylakeServer: 993 case CK_Cascadelake: 994 case CK_Cooperlake: 995 case CK_Cannonlake: 996 case CK_IcelakeClient: 997 case CK_IcelakeServer: 998 // FIXME: Historically, we defined this legacy name, it would be nice to 999 // remove it at some point. We've never exposed fine-grained names for 1000 // recent primary x86 CPUs, and we should keep it that way. 1001 defineCPUMacros(Builder, "corei7"); 1002 break; 1003 case CK_KNL: 1004 defineCPUMacros(Builder, "knl"); 1005 break; 1006 case CK_KNM: 1007 break; 1008 case CK_Lakemont: 1009 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1010 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1011 Builder.defineMacro("__tune_lakemont__"); 1012 break; 1013 case CK_K6_2: 1014 Builder.defineMacro("__k6_2__"); 1015 Builder.defineMacro("__tune_k6_2__"); 1016 LLVM_FALLTHROUGH; 1017 case CK_K6_3: 1018 if (CPU != CK_K6_2) { // In case of fallthrough 1019 // FIXME: GCC may be enabling these in cases where some other k6 1020 // architecture is specified but -m3dnow is explicitly provided. The 1021 // exact semantics need to be determined and emulated here. 1022 Builder.defineMacro("__k6_3__"); 1023 Builder.defineMacro("__tune_k6_3__"); 1024 } 1025 LLVM_FALLTHROUGH; 1026 case CK_K6: 1027 defineCPUMacros(Builder, "k6"); 1028 break; 1029 case CK_Athlon: 1030 case CK_AthlonXP: 1031 defineCPUMacros(Builder, "athlon"); 1032 if (SSELevel != NoSSE) { 1033 Builder.defineMacro("__athlon_sse__"); 1034 Builder.defineMacro("__tune_athlon_sse__"); 1035 } 1036 break; 1037 case CK_K8: 1038 case CK_K8SSE3: 1039 case CK_x86_64: 1040 defineCPUMacros(Builder, "k8"); 1041 break; 1042 case CK_AMDFAM10: 1043 defineCPUMacros(Builder, "amdfam10"); 1044 break; 1045 case CK_BTVER1: 1046 defineCPUMacros(Builder, "btver1"); 1047 break; 1048 case CK_BTVER2: 1049 defineCPUMacros(Builder, "btver2"); 1050 break; 1051 case CK_BDVER1: 1052 defineCPUMacros(Builder, "bdver1"); 1053 break; 1054 case CK_BDVER2: 1055 defineCPUMacros(Builder, "bdver2"); 1056 break; 1057 case CK_BDVER3: 1058 defineCPUMacros(Builder, "bdver3"); 1059 break; 1060 case CK_BDVER4: 1061 defineCPUMacros(Builder, "bdver4"); 1062 break; 1063 case CK_ZNVER1: 1064 defineCPUMacros(Builder, "znver1"); 1065 break; 1066 case CK_ZNVER2: 1067 defineCPUMacros(Builder, "znver2"); 1068 break; 1069 case CK_Geode: 1070 defineCPUMacros(Builder, "geode"); 1071 break; 1072 } 1073 1074 // Target properties. 1075 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1076 1077 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1078 // functions in glibc header files that use FP Stack inline asm which the 1079 // backend can't deal with (PR879). 1080 Builder.defineMacro("__NO_MATH_INLINES"); 1081 1082 if (HasAES) 1083 Builder.defineMacro("__AES__"); 1084 1085 if (HasVAES) 1086 Builder.defineMacro("__VAES__"); 1087 1088 if (HasPCLMUL) 1089 Builder.defineMacro("__PCLMUL__"); 1090 1091 if (HasVPCLMULQDQ) 1092 Builder.defineMacro("__VPCLMULQDQ__"); 1093 1094 if (HasLZCNT) 1095 Builder.defineMacro("__LZCNT__"); 1096 1097 if (HasRDRND) 1098 Builder.defineMacro("__RDRND__"); 1099 1100 if (HasFSGSBASE) 1101 Builder.defineMacro("__FSGSBASE__"); 1102 1103 if (HasBMI) 1104 Builder.defineMacro("__BMI__"); 1105 1106 if (HasBMI2) 1107 Builder.defineMacro("__BMI2__"); 1108 1109 if (HasPOPCNT) 1110 Builder.defineMacro("__POPCNT__"); 1111 1112 if (HasRTM) 1113 Builder.defineMacro("__RTM__"); 1114 1115 if (HasPRFCHW) 1116 Builder.defineMacro("__PRFCHW__"); 1117 1118 if (HasRDSEED) 1119 Builder.defineMacro("__RDSEED__"); 1120 1121 if (HasADX) 1122 Builder.defineMacro("__ADX__"); 1123 1124 if (HasTBM) 1125 Builder.defineMacro("__TBM__"); 1126 1127 if (HasLWP) 1128 Builder.defineMacro("__LWP__"); 1129 1130 if (HasMWAITX) 1131 Builder.defineMacro("__MWAITX__"); 1132 1133 if (HasMOVBE) 1134 Builder.defineMacro("__MOVBE__"); 1135 1136 switch (XOPLevel) { 1137 case XOP: 1138 Builder.defineMacro("__XOP__"); 1139 LLVM_FALLTHROUGH; 1140 case FMA4: 1141 Builder.defineMacro("__FMA4__"); 1142 LLVM_FALLTHROUGH; 1143 case SSE4A: 1144 Builder.defineMacro("__SSE4A__"); 1145 LLVM_FALLTHROUGH; 1146 case NoXOP: 1147 break; 1148 } 1149 1150 if (HasFMA) 1151 Builder.defineMacro("__FMA__"); 1152 1153 if (HasF16C) 1154 Builder.defineMacro("__F16C__"); 1155 1156 if (HasGFNI) 1157 Builder.defineMacro("__GFNI__"); 1158 1159 if (HasAVX512CD) 1160 Builder.defineMacro("__AVX512CD__"); 1161 if (HasAVX512VPOPCNTDQ) 1162 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1163 if (HasAVX512VNNI) 1164 Builder.defineMacro("__AVX512VNNI__"); 1165 if (HasAVX512BF16) 1166 Builder.defineMacro("__AVX512BF16__"); 1167 if (HasAVX512ER) 1168 Builder.defineMacro("__AVX512ER__"); 1169 if (HasAVX512PF) 1170 Builder.defineMacro("__AVX512PF__"); 1171 if (HasAVX512DQ) 1172 Builder.defineMacro("__AVX512DQ__"); 1173 if (HasAVX512BITALG) 1174 Builder.defineMacro("__AVX512BITALG__"); 1175 if (HasAVX512BW) 1176 Builder.defineMacro("__AVX512BW__"); 1177 if (HasAVX512VL) 1178 Builder.defineMacro("__AVX512VL__"); 1179 if (HasAVX512VBMI) 1180 Builder.defineMacro("__AVX512VBMI__"); 1181 if (HasAVX512VBMI2) 1182 Builder.defineMacro("__AVX512VBMI2__"); 1183 if (HasAVX512IFMA) 1184 Builder.defineMacro("__AVX512IFMA__"); 1185 if (HasAVX512VP2INTERSECT) 1186 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1187 if (HasSHA) 1188 Builder.defineMacro("__SHA__"); 1189 1190 if (HasFXSR) 1191 Builder.defineMacro("__FXSR__"); 1192 if (HasXSAVE) 1193 Builder.defineMacro("__XSAVE__"); 1194 if (HasXSAVEOPT) 1195 Builder.defineMacro("__XSAVEOPT__"); 1196 if (HasXSAVEC) 1197 Builder.defineMacro("__XSAVEC__"); 1198 if (HasXSAVES) 1199 Builder.defineMacro("__XSAVES__"); 1200 if (HasPKU) 1201 Builder.defineMacro("__PKU__"); 1202 if (HasCLFLUSHOPT) 1203 Builder.defineMacro("__CLFLUSHOPT__"); 1204 if (HasCLWB) 1205 Builder.defineMacro("__CLWB__"); 1206 if (HasWBNOINVD) 1207 Builder.defineMacro("__WBNOINVD__"); 1208 if (HasMPX) 1209 Builder.defineMacro("__MPX__"); 1210 if (HasSHSTK) 1211 Builder.defineMacro("__SHSTK__"); 1212 if (HasSGX) 1213 Builder.defineMacro("__SGX__"); 1214 if (HasPREFETCHWT1) 1215 Builder.defineMacro("__PREFETCHWT1__"); 1216 if (HasCLZERO) 1217 Builder.defineMacro("__CLZERO__"); 1218 if (HasRDPID) 1219 Builder.defineMacro("__RDPID__"); 1220 if (HasCLDEMOTE) 1221 Builder.defineMacro("__CLDEMOTE__"); 1222 if (HasWAITPKG) 1223 Builder.defineMacro("__WAITPKG__"); 1224 if (HasMOVDIRI) 1225 Builder.defineMacro("__MOVDIRI__"); 1226 if (HasMOVDIR64B) 1227 Builder.defineMacro("__MOVDIR64B__"); 1228 if (HasPCONFIG) 1229 Builder.defineMacro("__PCONFIG__"); 1230 if (HasPTWRITE) 1231 Builder.defineMacro("__PTWRITE__"); 1232 if (HasINVPCID) 1233 Builder.defineMacro("__INVPCID__"); 1234 if (HasENQCMD) 1235 Builder.defineMacro("__ENQCMD__"); 1236 1237 // Each case falls through to the previous one here. 1238 switch (SSELevel) { 1239 case AVX512F: 1240 Builder.defineMacro("__AVX512F__"); 1241 LLVM_FALLTHROUGH; 1242 case AVX2: 1243 Builder.defineMacro("__AVX2__"); 1244 LLVM_FALLTHROUGH; 1245 case AVX: 1246 Builder.defineMacro("__AVX__"); 1247 LLVM_FALLTHROUGH; 1248 case SSE42: 1249 Builder.defineMacro("__SSE4_2__"); 1250 LLVM_FALLTHROUGH; 1251 case SSE41: 1252 Builder.defineMacro("__SSE4_1__"); 1253 LLVM_FALLTHROUGH; 1254 case SSSE3: 1255 Builder.defineMacro("__SSSE3__"); 1256 LLVM_FALLTHROUGH; 1257 case SSE3: 1258 Builder.defineMacro("__SSE3__"); 1259 LLVM_FALLTHROUGH; 1260 case SSE2: 1261 Builder.defineMacro("__SSE2__"); 1262 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1263 LLVM_FALLTHROUGH; 1264 case SSE1: 1265 Builder.defineMacro("__SSE__"); 1266 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1267 LLVM_FALLTHROUGH; 1268 case NoSSE: 1269 break; 1270 } 1271 1272 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1273 switch (SSELevel) { 1274 case AVX512F: 1275 case AVX2: 1276 case AVX: 1277 case SSE42: 1278 case SSE41: 1279 case SSSE3: 1280 case SSE3: 1281 case SSE2: 1282 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1283 break; 1284 case SSE1: 1285 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1286 break; 1287 default: 1288 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1289 break; 1290 } 1291 } 1292 1293 // Each case falls through to the previous one here. 1294 switch (MMX3DNowLevel) { 1295 case AMD3DNowAthlon: 1296 Builder.defineMacro("__3dNOW_A__"); 1297 LLVM_FALLTHROUGH; 1298 case AMD3DNow: 1299 Builder.defineMacro("__3dNOW__"); 1300 LLVM_FALLTHROUGH; 1301 case MMX: 1302 Builder.defineMacro("__MMX__"); 1303 LLVM_FALLTHROUGH; 1304 case NoMMX3DNow: 1305 break; 1306 } 1307 1308 if (CPU >= CK_i486 || CPU == CK_Generic) { 1309 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1310 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1312 } 1313 if (HasCX8) 1314 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1315 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1316 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1317 1318 if (HasFloat128) 1319 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1320 } 1321 1322 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1323 return llvm::StringSwitch<bool>(Name) 1324 .Case("3dnow", true) 1325 .Case("3dnowa", true) 1326 .Case("adx", true) 1327 .Case("aes", true) 1328 .Case("avx", true) 1329 .Case("avx2", true) 1330 .Case("avx512f", true) 1331 .Case("avx512cd", true) 1332 .Case("avx512vpopcntdq", true) 1333 .Case("avx512vnni", true) 1334 .Case("avx512bf16", true) 1335 .Case("avx512er", true) 1336 .Case("avx512pf", true) 1337 .Case("avx512dq", true) 1338 .Case("avx512bitalg", true) 1339 .Case("avx512bw", true) 1340 .Case("avx512vl", true) 1341 .Case("avx512vbmi", true) 1342 .Case("avx512vbmi2", true) 1343 .Case("avx512ifma", true) 1344 .Case("avx512vp2intersect", true) 1345 .Case("bmi", true) 1346 .Case("bmi2", true) 1347 .Case("cldemote", true) 1348 .Case("clflushopt", true) 1349 .Case("clwb", true) 1350 .Case("clzero", true) 1351 .Case("cx16", true) 1352 .Case("enqcmd", true) 1353 .Case("f16c", true) 1354 .Case("fma", true) 1355 .Case("fma4", true) 1356 .Case("fsgsbase", true) 1357 .Case("fxsr", true) 1358 .Case("gfni", true) 1359 .Case("invpcid", true) 1360 .Case("lwp", true) 1361 .Case("lzcnt", true) 1362 .Case("mmx", true) 1363 .Case("movbe", true) 1364 .Case("movdiri", true) 1365 .Case("movdir64b", true) 1366 .Case("mpx", true) 1367 .Case("mwaitx", true) 1368 .Case("pclmul", true) 1369 .Case("pconfig", true) 1370 .Case("pku", true) 1371 .Case("popcnt", true) 1372 .Case("prefetchwt1", true) 1373 .Case("prfchw", true) 1374 .Case("ptwrite", true) 1375 .Case("rdpid", true) 1376 .Case("rdrnd", true) 1377 .Case("rdseed", true) 1378 .Case("rtm", true) 1379 .Case("sahf", true) 1380 .Case("sgx", true) 1381 .Case("sha", true) 1382 .Case("shstk", true) 1383 .Case("sse", true) 1384 .Case("sse2", true) 1385 .Case("sse3", true) 1386 .Case("ssse3", true) 1387 .Case("sse4", true) 1388 .Case("sse4.1", true) 1389 .Case("sse4.2", true) 1390 .Case("sse4a", true) 1391 .Case("tbm", true) 1392 .Case("vaes", true) 1393 .Case("vpclmulqdq", true) 1394 .Case("wbnoinvd", true) 1395 .Case("waitpkg", true) 1396 .Case("x87", true) 1397 .Case("xop", true) 1398 .Case("xsave", true) 1399 .Case("xsavec", true) 1400 .Case("xsaves", true) 1401 .Case("xsaveopt", true) 1402 .Default(false); 1403 } 1404 1405 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1406 return llvm::StringSwitch<bool>(Feature) 1407 .Case("adx", HasADX) 1408 .Case("aes", HasAES) 1409 .Case("avx", SSELevel >= AVX) 1410 .Case("avx2", SSELevel >= AVX2) 1411 .Case("avx512f", SSELevel >= AVX512F) 1412 .Case("avx512cd", HasAVX512CD) 1413 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1414 .Case("avx512vnni", HasAVX512VNNI) 1415 .Case("avx512bf16", HasAVX512BF16) 1416 .Case("avx512er", HasAVX512ER) 1417 .Case("avx512pf", HasAVX512PF) 1418 .Case("avx512dq", HasAVX512DQ) 1419 .Case("avx512bitalg", HasAVX512BITALG) 1420 .Case("avx512bw", HasAVX512BW) 1421 .Case("avx512vl", HasAVX512VL) 1422 .Case("avx512vbmi", HasAVX512VBMI) 1423 .Case("avx512vbmi2", HasAVX512VBMI2) 1424 .Case("avx512ifma", HasAVX512IFMA) 1425 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1426 .Case("bmi", HasBMI) 1427 .Case("bmi2", HasBMI2) 1428 .Case("cldemote", HasCLDEMOTE) 1429 .Case("clflushopt", HasCLFLUSHOPT) 1430 .Case("clwb", HasCLWB) 1431 .Case("clzero", HasCLZERO) 1432 .Case("cx8", HasCX8) 1433 .Case("cx16", HasCX16) 1434 .Case("enqcmd", HasENQCMD) 1435 .Case("f16c", HasF16C) 1436 .Case("fma", HasFMA) 1437 .Case("fma4", XOPLevel >= FMA4) 1438 .Case("fsgsbase", HasFSGSBASE) 1439 .Case("fxsr", HasFXSR) 1440 .Case("gfni", HasGFNI) 1441 .Case("invpcid", HasINVPCID) 1442 .Case("lwp", HasLWP) 1443 .Case("lzcnt", HasLZCNT) 1444 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1445 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1446 .Case("mmx", MMX3DNowLevel >= MMX) 1447 .Case("movbe", HasMOVBE) 1448 .Case("movdiri", HasMOVDIRI) 1449 .Case("movdir64b", HasMOVDIR64B) 1450 .Case("mpx", HasMPX) 1451 .Case("mwaitx", HasMWAITX) 1452 .Case("pclmul", HasPCLMUL) 1453 .Case("pconfig", HasPCONFIG) 1454 .Case("pku", HasPKU) 1455 .Case("popcnt", HasPOPCNT) 1456 .Case("prefetchwt1", HasPREFETCHWT1) 1457 .Case("prfchw", HasPRFCHW) 1458 .Case("ptwrite", HasPTWRITE) 1459 .Case("rdpid", HasRDPID) 1460 .Case("rdrnd", HasRDRND) 1461 .Case("rdseed", HasRDSEED) 1462 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1463 .Case("rtm", HasRTM) 1464 .Case("sahf", HasLAHFSAHF) 1465 .Case("sgx", HasSGX) 1466 .Case("sha", HasSHA) 1467 .Case("shstk", HasSHSTK) 1468 .Case("sse", SSELevel >= SSE1) 1469 .Case("sse2", SSELevel >= SSE2) 1470 .Case("sse3", SSELevel >= SSE3) 1471 .Case("ssse3", SSELevel >= SSSE3) 1472 .Case("sse4.1", SSELevel >= SSE41) 1473 .Case("sse4.2", SSELevel >= SSE42) 1474 .Case("sse4a", XOPLevel >= SSE4A) 1475 .Case("tbm", HasTBM) 1476 .Case("vaes", HasVAES) 1477 .Case("vpclmulqdq", HasVPCLMULQDQ) 1478 .Case("wbnoinvd", HasWBNOINVD) 1479 .Case("waitpkg", HasWAITPKG) 1480 .Case("x86", true) 1481 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1482 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1483 .Case("xop", XOPLevel >= XOP) 1484 .Case("xsave", HasXSAVE) 1485 .Case("xsavec", HasXSAVEC) 1486 .Case("xsaves", HasXSAVES) 1487 .Case("xsaveopt", HasXSAVEOPT) 1488 .Default(false); 1489 } 1490 1491 // We can't use a generic validation scheme for the features accepted here 1492 // versus subtarget features accepted in the target attribute because the 1493 // bitfield structure that's initialized in the runtime only supports the 1494 // below currently rather than the full range of subtarget features. (See 1495 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1496 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1497 return llvm::StringSwitch<bool>(FeatureStr) 1498 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1499 #include "llvm/Support/X86TargetParser.def" 1500 .Default(false); 1501 } 1502 1503 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1504 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1505 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1506 #include "llvm/Support/X86TargetParser.def" 1507 ; 1508 // Note, this function should only be used after ensuring the value is 1509 // correct, so it asserts if the value is out of range. 1510 } 1511 1512 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1513 enum class FeatPriority { 1514 #define FEATURE(FEAT) FEAT, 1515 #include "clang/Basic/X86Target.def" 1516 }; 1517 switch (Feat) { 1518 #define FEATURE(FEAT) \ 1519 case llvm::X86::FEAT: \ 1520 return static_cast<unsigned>(FeatPriority::FEAT); 1521 #include "clang/Basic/X86Target.def" 1522 default: 1523 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1524 } 1525 } 1526 1527 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1528 // Valid CPUs have a 'key feature' that compares just better than its key 1529 // feature. 1530 CPUKind Kind = getCPUKind(Name); 1531 if (Kind != CK_Generic) { 1532 switch (Kind) { 1533 default: 1534 llvm_unreachable( 1535 "CPU Type without a key feature used in 'target' attribute"); 1536 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1537 case CK_##ENUM: \ 1538 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1539 #include "clang/Basic/X86Target.def" 1540 } 1541 } 1542 1543 // Now we know we have a feature, so get its priority and shift it a few so 1544 // that we have sufficient room for the CPUs (above). 1545 return getFeaturePriority(getFeature(Name)) << 1; 1546 } 1547 1548 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1549 return llvm::StringSwitch<bool>(Name) 1550 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1551 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1552 #include "clang/Basic/X86Target.def" 1553 .Default(false); 1554 } 1555 1556 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1557 return llvm::StringSwitch<StringRef>(Name) 1558 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1559 #include "clang/Basic/X86Target.def" 1560 .Default(Name); 1561 } 1562 1563 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1564 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1565 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1566 #include "clang/Basic/X86Target.def" 1567 .Default(0); 1568 } 1569 1570 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1571 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1572 StringRef WholeList = 1573 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1574 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1575 #include "clang/Basic/X86Target.def" 1576 .Default(""); 1577 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1578 } 1579 1580 // We can't use a generic validation scheme for the cpus accepted here 1581 // versus subtarget cpus accepted in the target attribute because the 1582 // variables intitialized by the runtime only support the below currently 1583 // rather than the full range of cpus. 1584 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1585 return llvm::StringSwitch<bool>(FeatureStr) 1586 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1587 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1588 .Cases(STR, ALIAS, true) 1589 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1590 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1591 #include "llvm/Support/X86TargetParser.def" 1592 .Default(false); 1593 } 1594 1595 static unsigned matchAsmCCConstraint(const char *&Name) { 1596 auto RV = llvm::StringSwitch<unsigned>(Name) 1597 .Case("@cca", 4) 1598 .Case("@ccae", 5) 1599 .Case("@ccb", 4) 1600 .Case("@ccbe", 5) 1601 .Case("@ccc", 4) 1602 .Case("@cce", 4) 1603 .Case("@ccz", 4) 1604 .Case("@ccg", 4) 1605 .Case("@ccge", 5) 1606 .Case("@ccl", 4) 1607 .Case("@ccle", 5) 1608 .Case("@ccna", 5) 1609 .Case("@ccnae", 6) 1610 .Case("@ccnb", 5) 1611 .Case("@ccnbe", 6) 1612 .Case("@ccnc", 5) 1613 .Case("@ccne", 5) 1614 .Case("@ccnz", 5) 1615 .Case("@ccng", 5) 1616 .Case("@ccnge", 6) 1617 .Case("@ccnl", 5) 1618 .Case("@ccnle", 6) 1619 .Case("@ccno", 5) 1620 .Case("@ccnp", 5) 1621 .Case("@ccns", 5) 1622 .Case("@cco", 4) 1623 .Case("@ccp", 4) 1624 .Case("@ccs", 4) 1625 .Default(0); 1626 return RV; 1627 } 1628 1629 bool X86TargetInfo::validateAsmConstraint( 1630 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1631 switch (*Name) { 1632 default: 1633 return false; 1634 // Constant constraints. 1635 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1636 // instructions. 1637 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1638 // x86_64 instructions. 1639 case 's': 1640 Info.setRequiresImmediate(); 1641 return true; 1642 case 'I': 1643 Info.setRequiresImmediate(0, 31); 1644 return true; 1645 case 'J': 1646 Info.setRequiresImmediate(0, 63); 1647 return true; 1648 case 'K': 1649 Info.setRequiresImmediate(-128, 127); 1650 return true; 1651 case 'L': 1652 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1653 return true; 1654 case 'M': 1655 Info.setRequiresImmediate(0, 3); 1656 return true; 1657 case 'N': 1658 Info.setRequiresImmediate(0, 255); 1659 return true; 1660 case 'O': 1661 Info.setRequiresImmediate(0, 127); 1662 return true; 1663 // Register constraints. 1664 case 'Y': // 'Y' is the first character for several 2-character constraints. 1665 // Shift the pointer to the second character of the constraint. 1666 Name++; 1667 switch (*Name) { 1668 default: 1669 return false; 1670 case 'z': 1671 case '0': // First SSE register. 1672 case '2': 1673 case 't': // Any SSE register, when SSE2 is enabled. 1674 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1675 case 'm': // Any MMX register, when inter-unit moves enabled. 1676 case 'k': // AVX512 arch mask registers: k1-k7. 1677 Info.setAllowsRegister(); 1678 return true; 1679 } 1680 case 'f': // Any x87 floating point stack register. 1681 // Constraint 'f' cannot be used for output operands. 1682 if (Info.ConstraintStr[0] == '=') 1683 return false; 1684 Info.setAllowsRegister(); 1685 return true; 1686 case 'a': // eax. 1687 case 'b': // ebx. 1688 case 'c': // ecx. 1689 case 'd': // edx. 1690 case 'S': // esi. 1691 case 'D': // edi. 1692 case 'A': // edx:eax. 1693 case 't': // Top of floating point stack. 1694 case 'u': // Second from top of floating point stack. 1695 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1696 case 'y': // Any MMX register. 1697 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1698 case 'x': // Any SSE register. 1699 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1700 // for intermideate k reg operations). 1701 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1702 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1703 case 'l': // "Index" registers: any general register that can be used as an 1704 // index in a base+index memory access. 1705 Info.setAllowsRegister(); 1706 return true; 1707 // Floating point constant constraints. 1708 case 'C': // SSE floating point constant. 1709 case 'G': // x87 floating point constant. 1710 return true; 1711 case '@': 1712 // CC condition changes. 1713 if (auto Len = matchAsmCCConstraint(Name)) { 1714 Name += Len - 1; 1715 Info.setAllowsRegister(); 1716 return true; 1717 } 1718 return false; 1719 } 1720 } 1721 1722 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1723 unsigned Size) const { 1724 // Strip off constraint modifiers. 1725 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1726 Constraint = Constraint.substr(1); 1727 1728 return validateOperandSize(Constraint, Size); 1729 } 1730 1731 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1732 unsigned Size) const { 1733 return validateOperandSize(Constraint, Size); 1734 } 1735 1736 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1737 unsigned Size) const { 1738 switch (Constraint[0]) { 1739 default: 1740 break; 1741 case 'k': 1742 // Registers k0-k7 (AVX512) size limit is 64 bit. 1743 case 'y': 1744 return Size <= 64; 1745 case 'f': 1746 case 't': 1747 case 'u': 1748 return Size <= 128; 1749 case 'Y': 1750 // 'Y' is the first character for several 2-character constraints. 1751 switch (Constraint[1]) { 1752 default: 1753 return false; 1754 case 'm': 1755 // 'Ym' is synonymous with 'y'. 1756 case 'k': 1757 return Size <= 64; 1758 case 'z': 1759 case '0': 1760 // XMM0 1761 if (SSELevel >= SSE1) 1762 return Size <= 128U; 1763 return false; 1764 case 'i': 1765 case 't': 1766 case '2': 1767 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1768 if (SSELevel < SSE2) 1769 return false; 1770 break; 1771 } 1772 LLVM_FALLTHROUGH; 1773 case 'v': 1774 case 'x': 1775 if (SSELevel >= AVX512F) 1776 // 512-bit zmm registers can be used if target supports AVX512F. 1777 return Size <= 512U; 1778 else if (SSELevel >= AVX) 1779 // 256-bit ymm registers can be used if target supports AVX. 1780 return Size <= 256U; 1781 return Size <= 128U; 1782 1783 } 1784 1785 return true; 1786 } 1787 1788 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1789 switch (*Constraint) { 1790 case '@': 1791 if (auto Len = matchAsmCCConstraint(Constraint)) { 1792 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1793 Constraint += Len - 1; 1794 return Converted; 1795 } 1796 return std::string(1, *Constraint); 1797 case 'a': 1798 return std::string("{ax}"); 1799 case 'b': 1800 return std::string("{bx}"); 1801 case 'c': 1802 return std::string("{cx}"); 1803 case 'd': 1804 return std::string("{dx}"); 1805 case 'S': 1806 return std::string("{si}"); 1807 case 'D': 1808 return std::string("{di}"); 1809 case 'p': // address 1810 return std::string("im"); 1811 case 't': // top of floating point stack. 1812 return std::string("{st}"); 1813 case 'u': // second from top of floating point stack. 1814 return std::string("{st(1)}"); // second from top of floating point stack. 1815 case 'Y': 1816 switch (Constraint[1]) { 1817 default: 1818 // Break from inner switch and fall through (copy single char), 1819 // continue parsing after copying the current constraint into 1820 // the return string. 1821 break; 1822 case 'k': 1823 case 'm': 1824 case 'i': 1825 case 't': 1826 case 'z': 1827 case '0': 1828 case '2': 1829 // "^" hints llvm that this is a 2 letter constraint. 1830 // "Constraint++" is used to promote the string iterator 1831 // to the next constraint. 1832 return std::string("^") + std::string(Constraint++, 2); 1833 } 1834 LLVM_FALLTHROUGH; 1835 default: 1836 return std::string(1, *Constraint); 1837 } 1838 } 1839 1840 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1841 // Perform any per-CPU checks necessary to determine if this CPU is 1842 // acceptable. 1843 switch (Kind) { 1844 case CK_Generic: 1845 // No processor selected! 1846 return false; 1847 #define PROC(ENUM, STRING, IS64BIT) \ 1848 case CK_##ENUM: \ 1849 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1850 #include "clang/Basic/X86Target.def" 1851 } 1852 llvm_unreachable("Unhandled CPU kind"); 1853 } 1854 1855 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1856 #define PROC(ENUM, STRING, IS64BIT) \ 1857 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1858 Values.emplace_back(STRING); 1859 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1860 #define PROC_ALIAS(ENUM, ALIAS) \ 1861 if (checkCPUKind(CK_##ENUM)) \ 1862 Values.emplace_back(ALIAS); 1863 #include "clang/Basic/X86Target.def" 1864 } 1865 1866 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1867 return llvm::StringSwitch<CPUKind>(CPU) 1868 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1869 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1870 #include "clang/Basic/X86Target.def" 1871 .Default(CK_Generic); 1872 } 1873 1874 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1875 return llvm::makeArrayRef(GCCRegNames); 1876 } 1877 1878 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1879 return llvm::makeArrayRef(AddlRegNames); 1880 } 1881 1882 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1883 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1884 Builtin::FirstTSBuiltin + 1); 1885 } 1886 1887 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1888 return llvm::makeArrayRef(BuiltinInfoX86, 1889 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1890 } 1891