1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 }; 66 67 const TargetInfo::AddlRegName AddlRegNames[] = { 68 {{"al", "ah", "eax", "rax"}, 0}, 69 {{"bl", "bh", "ebx", "rbx"}, 3}, 70 {{"cl", "ch", "ecx", "rcx"}, 2}, 71 {{"dl", "dh", "edx", "rdx"}, 1}, 72 {{"esi", "rsi"}, 4}, 73 {{"edi", "rdi"}, 5}, 74 {{"esp", "rsp"}, 7}, 75 {{"ebp", "rbp"}, 6}, 76 {{"r8d", "r8w", "r8b"}, 38}, 77 {{"r9d", "r9w", "r9b"}, 39}, 78 {{"r10d", "r10w", "r10b"}, 40}, 79 {{"r11d", "r11w", "r11b"}, 41}, 80 {{"r12d", "r12w", "r12b"}, 42}, 81 {{"r13d", "r13w", "r13b"}, 43}, 82 {{"r14d", "r14w", "r14b"}, 44}, 83 {{"r15d", "r15w", "r15b"}, 45}, 84 }; 85 86 } // namespace targets 87 } // namespace clang 88 89 using namespace clang; 90 using namespace clang::targets; 91 92 bool X86TargetInfo::setFPMath(StringRef Name) { 93 if (Name == "387") { 94 FPMath = FP_387; 95 return true; 96 } 97 if (Name == "sse") { 98 FPMath = FP_SSE; 99 return true; 100 } 101 return false; 102 } 103 104 bool X86TargetInfo::initFeatureMap( 105 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 106 const std::vector<std::string> &FeaturesVec) const { 107 // FIXME: This *really* should not be here. 108 // X86_64 always has SSE2. 109 if (getTriple().getArch() == llvm::Triple::x86_64) 110 setFeatureEnabledImpl(Features, "sse2", true); 111 112 const CPUKind Kind = getCPUKind(CPU); 113 114 // Enable X87 for all X86 processors but Lakemont. 115 if (Kind != CK_Lakemont) 116 setFeatureEnabledImpl(Features, "x87", true); 117 118 // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards 119 // compatibility. 120 if (Kind >= CK_i586 || Kind == CK_Generic) 121 setFeatureEnabledImpl(Features, "cx8", true); 122 123 switch (Kind) { 124 case CK_Generic: 125 case CK_i386: 126 case CK_i486: 127 case CK_i586: 128 case CK_Pentium: 129 case CK_PentiumPro: 130 case CK_i686: 131 case CK_Lakemont: 132 break; 133 134 case CK_Cooperlake: 135 // CPX inherits all CLX features plus AVX512BF16 136 setFeatureEnabledImpl(Features, "avx512bf16", true); 137 LLVM_FALLTHROUGH; 138 case CK_Cascadelake: 139 // CLX inherits all SKX features plus AVX512VNNI 140 setFeatureEnabledImpl(Features, "avx512vnni", true); 141 LLVM_FALLTHROUGH; 142 case CK_SkylakeServer: 143 setFeatureEnabledImpl(Features, "avx512f", true); 144 setFeatureEnabledImpl(Features, "avx512cd", true); 145 setFeatureEnabledImpl(Features, "avx512dq", true); 146 setFeatureEnabledImpl(Features, "avx512bw", true); 147 setFeatureEnabledImpl(Features, "avx512vl", true); 148 setFeatureEnabledImpl(Features, "clwb", true); 149 setFeatureEnabledImpl(Features, "pku", true); 150 // SkylakeServer cores inherits all SKL features, except SGX 151 goto SkylakeCommon; 152 153 case CK_Tigerlake: 154 setFeatureEnabledImpl(Features, "avx512vp2intersect", true); 155 setFeatureEnabledImpl(Features, "movdiri", true); 156 setFeatureEnabledImpl(Features, "movdir64b", true); 157 setFeatureEnabledImpl(Features, "shstk", true); 158 // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd 159 goto IcelakeCommon; 160 161 case CK_IcelakeServer: 162 setFeatureEnabledImpl(Features, "pconfig", true); 163 setFeatureEnabledImpl(Features, "wbnoinvd", true); 164 LLVM_FALLTHROUGH; 165 case CK_IcelakeClient: 166 IcelakeCommon: 167 setFeatureEnabledImpl(Features, "vaes", true); 168 setFeatureEnabledImpl(Features, "gfni", true); 169 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 170 setFeatureEnabledImpl(Features, "avx512bitalg", true); 171 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 172 setFeatureEnabledImpl(Features, "avx512vnni", true); 173 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 174 setFeatureEnabledImpl(Features, "rdpid", true); 175 setFeatureEnabledImpl(Features, "clwb", true); 176 LLVM_FALLTHROUGH; 177 case CK_Cannonlake: 178 setFeatureEnabledImpl(Features, "avx512f", true); 179 setFeatureEnabledImpl(Features, "avx512cd", true); 180 setFeatureEnabledImpl(Features, "avx512dq", true); 181 setFeatureEnabledImpl(Features, "avx512bw", true); 182 setFeatureEnabledImpl(Features, "avx512vl", true); 183 setFeatureEnabledImpl(Features, "avx512ifma", true); 184 setFeatureEnabledImpl(Features, "avx512vbmi", true); 185 setFeatureEnabledImpl(Features, "pku", true); 186 setFeatureEnabledImpl(Features, "sha", true); 187 LLVM_FALLTHROUGH; 188 case CK_SkylakeClient: 189 setFeatureEnabledImpl(Features, "sgx", true); 190 // SkylakeServer cores inherits all SKL features, except SGX 191 SkylakeCommon: 192 setFeatureEnabledImpl(Features, "xsavec", true); 193 setFeatureEnabledImpl(Features, "xsaves", true); 194 setFeatureEnabledImpl(Features, "clflushopt", true); 195 setFeatureEnabledImpl(Features, "aes", true); 196 LLVM_FALLTHROUGH; 197 case CK_Broadwell: 198 setFeatureEnabledImpl(Features, "rdseed", true); 199 setFeatureEnabledImpl(Features, "adx", true); 200 setFeatureEnabledImpl(Features, "prfchw", true); 201 LLVM_FALLTHROUGH; 202 case CK_Haswell: 203 setFeatureEnabledImpl(Features, "avx2", true); 204 setFeatureEnabledImpl(Features, "lzcnt", true); 205 setFeatureEnabledImpl(Features, "bmi", true); 206 setFeatureEnabledImpl(Features, "bmi2", true); 207 setFeatureEnabledImpl(Features, "fma", true); 208 setFeatureEnabledImpl(Features, "invpcid", true); 209 setFeatureEnabledImpl(Features, "movbe", true); 210 LLVM_FALLTHROUGH; 211 case CK_IvyBridge: 212 setFeatureEnabledImpl(Features, "rdrnd", true); 213 setFeatureEnabledImpl(Features, "f16c", true); 214 setFeatureEnabledImpl(Features, "fsgsbase", true); 215 LLVM_FALLTHROUGH; 216 case CK_SandyBridge: 217 setFeatureEnabledImpl(Features, "avx", true); 218 setFeatureEnabledImpl(Features, "xsave", true); 219 setFeatureEnabledImpl(Features, "xsaveopt", true); 220 LLVM_FALLTHROUGH; 221 case CK_Westmere: 222 setFeatureEnabledImpl(Features, "pclmul", true); 223 LLVM_FALLTHROUGH; 224 case CK_Nehalem: 225 setFeatureEnabledImpl(Features, "sse4.2", true); 226 LLVM_FALLTHROUGH; 227 case CK_Penryn: 228 setFeatureEnabledImpl(Features, "sse4.1", true); 229 LLVM_FALLTHROUGH; 230 case CK_Core2: 231 setFeatureEnabledImpl(Features, "ssse3", true); 232 setFeatureEnabledImpl(Features, "sahf", true); 233 LLVM_FALLTHROUGH; 234 case CK_Nocona: 235 setFeatureEnabledImpl(Features, "cx16", true); 236 LLVM_FALLTHROUGH; 237 case CK_Yonah: 238 case CK_Prescott: 239 setFeatureEnabledImpl(Features, "sse3", true); 240 LLVM_FALLTHROUGH; 241 case CK_PentiumM: 242 case CK_Pentium4: 243 case CK_x86_64: 244 setFeatureEnabledImpl(Features, "sse2", true); 245 LLVM_FALLTHROUGH; 246 case CK_Pentium3: 247 case CK_C3_2: 248 setFeatureEnabledImpl(Features, "sse", true); 249 LLVM_FALLTHROUGH; 250 case CK_Pentium2: 251 setFeatureEnabledImpl(Features, "fxsr", true); 252 LLVM_FALLTHROUGH; 253 case CK_PentiumMMX: 254 case CK_K6: 255 case CK_WinChipC6: 256 setFeatureEnabledImpl(Features, "mmx", true); 257 break; 258 259 case CK_Tremont: 260 setFeatureEnabledImpl(Features, "cldemote", true); 261 setFeatureEnabledImpl(Features, "movdiri", true); 262 setFeatureEnabledImpl(Features, "movdir64b", true); 263 setFeatureEnabledImpl(Features, "gfni", true); 264 setFeatureEnabledImpl(Features, "waitpkg", true); 265 LLVM_FALLTHROUGH; 266 case CK_GoldmontPlus: 267 setFeatureEnabledImpl(Features, "ptwrite", true); 268 setFeatureEnabledImpl(Features, "rdpid", true); 269 setFeatureEnabledImpl(Features, "sgx", true); 270 LLVM_FALLTHROUGH; 271 case CK_Goldmont: 272 setFeatureEnabledImpl(Features, "sha", true); 273 setFeatureEnabledImpl(Features, "rdseed", true); 274 setFeatureEnabledImpl(Features, "xsave", true); 275 setFeatureEnabledImpl(Features, "xsaveopt", true); 276 setFeatureEnabledImpl(Features, "xsavec", true); 277 setFeatureEnabledImpl(Features, "xsaves", true); 278 setFeatureEnabledImpl(Features, "clflushopt", true); 279 setFeatureEnabledImpl(Features, "fsgsbase", true); 280 setFeatureEnabledImpl(Features, "aes", true); 281 LLVM_FALLTHROUGH; 282 case CK_Silvermont: 283 setFeatureEnabledImpl(Features, "rdrnd", true); 284 setFeatureEnabledImpl(Features, "pclmul", true); 285 setFeatureEnabledImpl(Features, "sse4.2", true); 286 setFeatureEnabledImpl(Features, "prfchw", true); 287 LLVM_FALLTHROUGH; 288 case CK_Bonnell: 289 setFeatureEnabledImpl(Features, "movbe", true); 290 setFeatureEnabledImpl(Features, "ssse3", true); 291 setFeatureEnabledImpl(Features, "fxsr", true); 292 setFeatureEnabledImpl(Features, "cx16", true); 293 setFeatureEnabledImpl(Features, "sahf", true); 294 setFeatureEnabledImpl(Features, "mmx", true); 295 break; 296 297 case CK_KNM: 298 // TODO: Add avx5124fmaps/avx5124vnniw. 299 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 300 LLVM_FALLTHROUGH; 301 case CK_KNL: 302 setFeatureEnabledImpl(Features, "avx512f", true); 303 setFeatureEnabledImpl(Features, "avx512cd", true); 304 setFeatureEnabledImpl(Features, "avx512er", true); 305 setFeatureEnabledImpl(Features, "avx512pf", true); 306 setFeatureEnabledImpl(Features, "prfchw", true); 307 setFeatureEnabledImpl(Features, "prefetchwt1", true); 308 setFeatureEnabledImpl(Features, "fxsr", true); 309 setFeatureEnabledImpl(Features, "rdseed", true); 310 setFeatureEnabledImpl(Features, "adx", true); 311 setFeatureEnabledImpl(Features, "lzcnt", true); 312 setFeatureEnabledImpl(Features, "bmi", true); 313 setFeatureEnabledImpl(Features, "bmi2", true); 314 setFeatureEnabledImpl(Features, "fma", true); 315 setFeatureEnabledImpl(Features, "rdrnd", true); 316 setFeatureEnabledImpl(Features, "f16c", true); 317 setFeatureEnabledImpl(Features, "fsgsbase", true); 318 setFeatureEnabledImpl(Features, "aes", true); 319 setFeatureEnabledImpl(Features, "pclmul", true); 320 setFeatureEnabledImpl(Features, "cx16", true); 321 setFeatureEnabledImpl(Features, "xsaveopt", true); 322 setFeatureEnabledImpl(Features, "xsave", true); 323 setFeatureEnabledImpl(Features, "movbe", true); 324 setFeatureEnabledImpl(Features, "sahf", true); 325 setFeatureEnabledImpl(Features, "mmx", true); 326 break; 327 328 case CK_K6_2: 329 case CK_K6_3: 330 case CK_WinChip2: 331 case CK_C3: 332 setFeatureEnabledImpl(Features, "3dnow", true); 333 break; 334 335 case CK_AMDFAM10: 336 setFeatureEnabledImpl(Features, "sse4a", true); 337 setFeatureEnabledImpl(Features, "lzcnt", true); 338 setFeatureEnabledImpl(Features, "popcnt", true); 339 setFeatureEnabledImpl(Features, "sahf", true); 340 LLVM_FALLTHROUGH; 341 case CK_K8SSE3: 342 setFeatureEnabledImpl(Features, "sse3", true); 343 LLVM_FALLTHROUGH; 344 case CK_K8: 345 setFeatureEnabledImpl(Features, "sse2", true); 346 LLVM_FALLTHROUGH; 347 case CK_AthlonXP: 348 setFeatureEnabledImpl(Features, "sse", true); 349 setFeatureEnabledImpl(Features, "fxsr", true); 350 LLVM_FALLTHROUGH; 351 case CK_Athlon: 352 case CK_Geode: 353 setFeatureEnabledImpl(Features, "3dnowa", true); 354 break; 355 356 case CK_BTVER2: 357 setFeatureEnabledImpl(Features, "avx", true); 358 setFeatureEnabledImpl(Features, "aes", true); 359 setFeatureEnabledImpl(Features, "pclmul", true); 360 setFeatureEnabledImpl(Features, "bmi", true); 361 setFeatureEnabledImpl(Features, "f16c", true); 362 setFeatureEnabledImpl(Features, "xsaveopt", true); 363 setFeatureEnabledImpl(Features, "movbe", true); 364 LLVM_FALLTHROUGH; 365 case CK_BTVER1: 366 setFeatureEnabledImpl(Features, "ssse3", true); 367 setFeatureEnabledImpl(Features, "sse4a", true); 368 setFeatureEnabledImpl(Features, "lzcnt", true); 369 setFeatureEnabledImpl(Features, "popcnt", true); 370 setFeatureEnabledImpl(Features, "prfchw", true); 371 setFeatureEnabledImpl(Features, "cx16", true); 372 setFeatureEnabledImpl(Features, "fxsr", true); 373 setFeatureEnabledImpl(Features, "sahf", true); 374 setFeatureEnabledImpl(Features, "mmx", true); 375 break; 376 377 case CK_ZNVER2: 378 setFeatureEnabledImpl(Features, "clwb", true); 379 setFeatureEnabledImpl(Features, "rdpid", true); 380 setFeatureEnabledImpl(Features, "wbnoinvd", true); 381 LLVM_FALLTHROUGH; 382 case CK_ZNVER1: 383 setFeatureEnabledImpl(Features, "adx", true); 384 setFeatureEnabledImpl(Features, "aes", true); 385 setFeatureEnabledImpl(Features, "avx2", true); 386 setFeatureEnabledImpl(Features, "bmi", true); 387 setFeatureEnabledImpl(Features, "bmi2", true); 388 setFeatureEnabledImpl(Features, "clflushopt", true); 389 setFeatureEnabledImpl(Features, "clzero", true); 390 setFeatureEnabledImpl(Features, "cx16", true); 391 setFeatureEnabledImpl(Features, "f16c", true); 392 setFeatureEnabledImpl(Features, "fma", true); 393 setFeatureEnabledImpl(Features, "fsgsbase", true); 394 setFeatureEnabledImpl(Features, "fxsr", true); 395 setFeatureEnabledImpl(Features, "lzcnt", true); 396 setFeatureEnabledImpl(Features, "mmx", true); 397 setFeatureEnabledImpl(Features, "mwaitx", true); 398 setFeatureEnabledImpl(Features, "movbe", true); 399 setFeatureEnabledImpl(Features, "pclmul", true); 400 setFeatureEnabledImpl(Features, "popcnt", true); 401 setFeatureEnabledImpl(Features, "prfchw", true); 402 setFeatureEnabledImpl(Features, "rdrnd", true); 403 setFeatureEnabledImpl(Features, "rdseed", true); 404 setFeatureEnabledImpl(Features, "sahf", true); 405 setFeatureEnabledImpl(Features, "sha", true); 406 setFeatureEnabledImpl(Features, "sse4a", true); 407 setFeatureEnabledImpl(Features, "xsave", true); 408 setFeatureEnabledImpl(Features, "xsavec", true); 409 setFeatureEnabledImpl(Features, "xsaveopt", true); 410 setFeatureEnabledImpl(Features, "xsaves", true); 411 break; 412 413 case CK_BDVER4: 414 setFeatureEnabledImpl(Features, "avx2", true); 415 setFeatureEnabledImpl(Features, "bmi2", true); 416 setFeatureEnabledImpl(Features, "mwaitx", true); 417 LLVM_FALLTHROUGH; 418 case CK_BDVER3: 419 setFeatureEnabledImpl(Features, "fsgsbase", true); 420 setFeatureEnabledImpl(Features, "xsaveopt", true); 421 LLVM_FALLTHROUGH; 422 case CK_BDVER2: 423 setFeatureEnabledImpl(Features, "bmi", true); 424 setFeatureEnabledImpl(Features, "fma", true); 425 setFeatureEnabledImpl(Features, "f16c", true); 426 setFeatureEnabledImpl(Features, "tbm", true); 427 LLVM_FALLTHROUGH; 428 case CK_BDVER1: 429 // xop implies avx, sse4a and fma4. 430 setFeatureEnabledImpl(Features, "xop", true); 431 setFeatureEnabledImpl(Features, "lwp", true); 432 setFeatureEnabledImpl(Features, "lzcnt", true); 433 setFeatureEnabledImpl(Features, "aes", true); 434 setFeatureEnabledImpl(Features, "pclmul", true); 435 setFeatureEnabledImpl(Features, "prfchw", true); 436 setFeatureEnabledImpl(Features, "cx16", true); 437 setFeatureEnabledImpl(Features, "fxsr", true); 438 setFeatureEnabledImpl(Features, "xsave", true); 439 setFeatureEnabledImpl(Features, "sahf", true); 440 setFeatureEnabledImpl(Features, "mmx", true); 441 break; 442 } 443 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 444 return false; 445 446 // Can't do this earlier because we need to be able to explicitly enable 447 // or disable these features and the things that they depend upon. 448 449 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 450 auto I = Features.find("sse4.2"); 451 if (I != Features.end() && I->getValue() && 452 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 453 Features["popcnt"] = true; 454 455 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 456 I = Features.find("3dnow"); 457 if (I != Features.end() && I->getValue() && 458 llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) 459 Features["prfchw"] = true; 460 461 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 462 // then enable MMX. 463 I = Features.find("sse"); 464 if (I != Features.end() && I->getValue() && 465 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 466 Features["mmx"] = true; 467 468 return true; 469 } 470 471 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 472 X86SSEEnum Level, bool Enabled) { 473 if (Enabled) { 474 switch (Level) { 475 case AVX512F: 476 Features["avx512f"] = true; 477 Features["fma"] = true; 478 Features["f16c"] = true; 479 LLVM_FALLTHROUGH; 480 case AVX2: 481 Features["avx2"] = true; 482 LLVM_FALLTHROUGH; 483 case AVX: 484 Features["avx"] = true; 485 Features["xsave"] = true; 486 LLVM_FALLTHROUGH; 487 case SSE42: 488 Features["sse4.2"] = true; 489 LLVM_FALLTHROUGH; 490 case SSE41: 491 Features["sse4.1"] = true; 492 LLVM_FALLTHROUGH; 493 case SSSE3: 494 Features["ssse3"] = true; 495 LLVM_FALLTHROUGH; 496 case SSE3: 497 Features["sse3"] = true; 498 LLVM_FALLTHROUGH; 499 case SSE2: 500 Features["sse2"] = true; 501 LLVM_FALLTHROUGH; 502 case SSE1: 503 Features["sse"] = true; 504 LLVM_FALLTHROUGH; 505 case NoSSE: 506 break; 507 } 508 return; 509 } 510 511 switch (Level) { 512 case NoSSE: 513 case SSE1: 514 Features["sse"] = false; 515 LLVM_FALLTHROUGH; 516 case SSE2: 517 Features["sse2"] = Features["pclmul"] = Features["aes"] = false; 518 Features["sha"] = Features["gfni"] = false; 519 LLVM_FALLTHROUGH; 520 case SSE3: 521 Features["sse3"] = false; 522 setXOPLevel(Features, NoXOP, false); 523 LLVM_FALLTHROUGH; 524 case SSSE3: 525 Features["ssse3"] = false; 526 LLVM_FALLTHROUGH; 527 case SSE41: 528 Features["sse4.1"] = false; 529 LLVM_FALLTHROUGH; 530 case SSE42: 531 Features["sse4.2"] = false; 532 LLVM_FALLTHROUGH; 533 case AVX: 534 Features["fma"] = Features["avx"] = Features["f16c"] = false; 535 Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; 536 Features["vpclmulqdq"] = false; 537 setXOPLevel(Features, FMA4, false); 538 LLVM_FALLTHROUGH; 539 case AVX2: 540 Features["avx2"] = false; 541 LLVM_FALLTHROUGH; 542 case AVX512F: 543 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; 544 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; 545 Features["avx512vl"] = Features["avx512vbmi"] = false; 546 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 547 Features["avx512bitalg"] = Features["avx512vnni"] = false; 548 Features["avx512vbmi2"] = Features["avx512bf16"] = false; 549 Features["avx512vp2intersect"] = false; 550 break; 551 } 552 } 553 554 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 555 MMX3DNowEnum Level, bool Enabled) { 556 if (Enabled) { 557 switch (Level) { 558 case AMD3DNowAthlon: 559 Features["3dnowa"] = true; 560 LLVM_FALLTHROUGH; 561 case AMD3DNow: 562 Features["3dnow"] = true; 563 LLVM_FALLTHROUGH; 564 case MMX: 565 Features["mmx"] = true; 566 LLVM_FALLTHROUGH; 567 case NoMMX3DNow: 568 break; 569 } 570 return; 571 } 572 573 switch (Level) { 574 case NoMMX3DNow: 575 case MMX: 576 Features["mmx"] = false; 577 LLVM_FALLTHROUGH; 578 case AMD3DNow: 579 Features["3dnow"] = false; 580 LLVM_FALLTHROUGH; 581 case AMD3DNowAthlon: 582 Features["3dnowa"] = false; 583 break; 584 } 585 } 586 587 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 588 bool Enabled) { 589 if (Enabled) { 590 switch (Level) { 591 case XOP: 592 Features["xop"] = true; 593 LLVM_FALLTHROUGH; 594 case FMA4: 595 Features["fma4"] = true; 596 setSSELevel(Features, AVX, true); 597 LLVM_FALLTHROUGH; 598 case SSE4A: 599 Features["sse4a"] = true; 600 setSSELevel(Features, SSE3, true); 601 LLVM_FALLTHROUGH; 602 case NoXOP: 603 break; 604 } 605 return; 606 } 607 608 switch (Level) { 609 case NoXOP: 610 case SSE4A: 611 Features["sse4a"] = false; 612 LLVM_FALLTHROUGH; 613 case FMA4: 614 Features["fma4"] = false; 615 LLVM_FALLTHROUGH; 616 case XOP: 617 Features["xop"] = false; 618 break; 619 } 620 } 621 622 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 623 StringRef Name, bool Enabled) { 624 // This is a bit of a hack to deal with the sse4 target feature when used 625 // as part of the target attribute. We handle sse4 correctly everywhere 626 // else. See below for more information on how we handle the sse4 options. 627 if (Name != "sse4") 628 Features[Name] = Enabled; 629 630 if (Name == "mmx") { 631 setMMXLevel(Features, MMX, Enabled); 632 } else if (Name == "sse") { 633 setSSELevel(Features, SSE1, Enabled); 634 } else if (Name == "sse2") { 635 setSSELevel(Features, SSE2, Enabled); 636 } else if (Name == "sse3") { 637 setSSELevel(Features, SSE3, Enabled); 638 } else if (Name == "ssse3") { 639 setSSELevel(Features, SSSE3, Enabled); 640 } else if (Name == "sse4.2") { 641 setSSELevel(Features, SSE42, Enabled); 642 } else if (Name == "sse4.1") { 643 setSSELevel(Features, SSE41, Enabled); 644 } else if (Name == "3dnow") { 645 setMMXLevel(Features, AMD3DNow, Enabled); 646 } else if (Name == "3dnowa") { 647 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 648 } else if (Name == "aes") { 649 if (Enabled) 650 setSSELevel(Features, SSE2, Enabled); 651 else 652 Features["vaes"] = false; 653 } else if (Name == "vaes") { 654 if (Enabled) { 655 setSSELevel(Features, AVX, Enabled); 656 Features["aes"] = true; 657 } 658 } else if (Name == "pclmul") { 659 if (Enabled) 660 setSSELevel(Features, SSE2, Enabled); 661 else 662 Features["vpclmulqdq"] = false; 663 } else if (Name == "vpclmulqdq") { 664 if (Enabled) { 665 setSSELevel(Features, AVX, Enabled); 666 Features["pclmul"] = true; 667 } 668 } else if (Name == "gfni") { 669 if (Enabled) 670 setSSELevel(Features, SSE2, Enabled); 671 } else if (Name == "avx") { 672 setSSELevel(Features, AVX, Enabled); 673 } else if (Name == "avx2") { 674 setSSELevel(Features, AVX2, Enabled); 675 } else if (Name == "avx512f") { 676 setSSELevel(Features, AVX512F, Enabled); 677 } else if (Name.startswith("avx512")) { 678 if (Enabled) 679 setSSELevel(Features, AVX512F, Enabled); 680 // Enable BWI instruction if certain features are being enabled. 681 if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || 682 Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) 683 Features["avx512bw"] = true; 684 // Also disable some features if BWI is being disabled. 685 if (Name == "avx512bw" && !Enabled) { 686 Features["avx512vbmi"] = false; 687 Features["avx512vbmi2"] = false; 688 Features["avx512bitalg"] = false; 689 Features["avx512bf16"] = false; 690 } 691 } else if (Name == "fma") { 692 if (Enabled) 693 setSSELevel(Features, AVX, Enabled); 694 else 695 setSSELevel(Features, AVX512F, Enabled); 696 } else if (Name == "fma4") { 697 setXOPLevel(Features, FMA4, Enabled); 698 } else if (Name == "xop") { 699 setXOPLevel(Features, XOP, Enabled); 700 } else if (Name == "sse4a") { 701 setXOPLevel(Features, SSE4A, Enabled); 702 } else if (Name == "f16c") { 703 if (Enabled) 704 setSSELevel(Features, AVX, Enabled); 705 else 706 setSSELevel(Features, AVX512F, Enabled); 707 } else if (Name == "sha") { 708 if (Enabled) 709 setSSELevel(Features, SSE2, Enabled); 710 } else if (Name == "sse4") { 711 // We can get here via the __target__ attribute since that's not controlled 712 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 713 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 714 // disabled. 715 if (Enabled) 716 setSSELevel(Features, SSE42, Enabled); 717 else 718 setSSELevel(Features, SSE41, Enabled); 719 } else if (Name == "xsave") { 720 if (!Enabled) 721 Features["xsaveopt"] = false; 722 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 723 if (Enabled) 724 Features["xsave"] = true; 725 } 726 } 727 728 /// handleTargetFeatures - Perform initialization based on the user 729 /// configured set of features. 730 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 731 DiagnosticsEngine &Diags) { 732 for (const auto &Feature : Features) { 733 if (Feature[0] != '+') 734 continue; 735 736 if (Feature == "+aes") { 737 HasAES = true; 738 } else if (Feature == "+vaes") { 739 HasVAES = true; 740 } else if (Feature == "+pclmul") { 741 HasPCLMUL = true; 742 } else if (Feature == "+vpclmulqdq") { 743 HasVPCLMULQDQ = true; 744 } else if (Feature == "+lzcnt") { 745 HasLZCNT = true; 746 } else if (Feature == "+rdrnd") { 747 HasRDRND = true; 748 } else if (Feature == "+fsgsbase") { 749 HasFSGSBASE = true; 750 } else if (Feature == "+bmi") { 751 HasBMI = true; 752 } else if (Feature == "+bmi2") { 753 HasBMI2 = true; 754 } else if (Feature == "+popcnt") { 755 HasPOPCNT = true; 756 } else if (Feature == "+rtm") { 757 HasRTM = true; 758 } else if (Feature == "+prfchw") { 759 HasPRFCHW = true; 760 } else if (Feature == "+rdseed") { 761 HasRDSEED = true; 762 } else if (Feature == "+adx") { 763 HasADX = true; 764 } else if (Feature == "+tbm") { 765 HasTBM = true; 766 } else if (Feature == "+lwp") { 767 HasLWP = true; 768 } else if (Feature == "+fma") { 769 HasFMA = true; 770 } else if (Feature == "+f16c") { 771 HasF16C = true; 772 } else if (Feature == "+gfni") { 773 HasGFNI = true; 774 } else if (Feature == "+avx512cd") { 775 HasAVX512CD = true; 776 } else if (Feature == "+avx512vpopcntdq") { 777 HasAVX512VPOPCNTDQ = true; 778 } else if (Feature == "+avx512vnni") { 779 HasAVX512VNNI = true; 780 } else if (Feature == "+avx512bf16") { 781 HasAVX512BF16 = true; 782 } else if (Feature == "+avx512er") { 783 HasAVX512ER = true; 784 } else if (Feature == "+avx512pf") { 785 HasAVX512PF = true; 786 } else if (Feature == "+avx512dq") { 787 HasAVX512DQ = true; 788 } else if (Feature == "+avx512bitalg") { 789 HasAVX512BITALG = true; 790 } else if (Feature == "+avx512bw") { 791 HasAVX512BW = true; 792 } else if (Feature == "+avx512vl") { 793 HasAVX512VL = true; 794 } else if (Feature == "+avx512vbmi") { 795 HasAVX512VBMI = true; 796 } else if (Feature == "+avx512vbmi2") { 797 HasAVX512VBMI2 = true; 798 } else if (Feature == "+avx512ifma") { 799 HasAVX512IFMA = true; 800 } else if (Feature == "+avx512vp2intersect") { 801 HasAVX512VP2INTERSECT = true; 802 } else if (Feature == "+sha") { 803 HasSHA = true; 804 } else if (Feature == "+shstk") { 805 HasSHSTK = true; 806 } else if (Feature == "+movbe") { 807 HasMOVBE = true; 808 } else if (Feature == "+sgx") { 809 HasSGX = true; 810 } else if (Feature == "+cx8") { 811 HasCX8 = true; 812 } else if (Feature == "+cx16") { 813 HasCX16 = true; 814 } else if (Feature == "+fxsr") { 815 HasFXSR = true; 816 } else if (Feature == "+xsave") { 817 HasXSAVE = true; 818 } else if (Feature == "+xsaveopt") { 819 HasXSAVEOPT = true; 820 } else if (Feature == "+xsavec") { 821 HasXSAVEC = true; 822 } else if (Feature == "+xsaves") { 823 HasXSAVES = true; 824 } else if (Feature == "+mwaitx") { 825 HasMWAITX = true; 826 } else if (Feature == "+pku") { 827 HasPKU = true; 828 } else if (Feature == "+clflushopt") { 829 HasCLFLUSHOPT = true; 830 } else if (Feature == "+clwb") { 831 HasCLWB = true; 832 } else if (Feature == "+wbnoinvd") { 833 HasWBNOINVD = true; 834 } else if (Feature == "+prefetchwt1") { 835 HasPREFETCHWT1 = true; 836 } else if (Feature == "+clzero") { 837 HasCLZERO = true; 838 } else if (Feature == "+cldemote") { 839 HasCLDEMOTE = true; 840 } else if (Feature == "+rdpid") { 841 HasRDPID = true; 842 } else if (Feature == "+retpoline-external-thunk") { 843 HasRetpolineExternalThunk = true; 844 } else if (Feature == "+sahf") { 845 HasLAHFSAHF = true; 846 } else if (Feature == "+waitpkg") { 847 HasWAITPKG = true; 848 } else if (Feature == "+movdiri") { 849 HasMOVDIRI = true; 850 } else if (Feature == "+movdir64b") { 851 HasMOVDIR64B = true; 852 } else if (Feature == "+pconfig") { 853 HasPCONFIG = true; 854 } else if (Feature == "+ptwrite") { 855 HasPTWRITE = true; 856 } else if (Feature == "+invpcid") { 857 HasINVPCID = true; 858 } else if (Feature == "+enqcmd") { 859 HasENQCMD = true; 860 } else if (Feature == "+serialize") { 861 HasSERIALIZE = true; 862 } 863 864 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 865 .Case("+avx512f", AVX512F) 866 .Case("+avx2", AVX2) 867 .Case("+avx", AVX) 868 .Case("+sse4.2", SSE42) 869 .Case("+sse4.1", SSE41) 870 .Case("+ssse3", SSSE3) 871 .Case("+sse3", SSE3) 872 .Case("+sse2", SSE2) 873 .Case("+sse", SSE1) 874 .Default(NoSSE); 875 SSELevel = std::max(SSELevel, Level); 876 877 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 878 .Case("+3dnowa", AMD3DNowAthlon) 879 .Case("+3dnow", AMD3DNow) 880 .Case("+mmx", MMX) 881 .Default(NoMMX3DNow); 882 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 883 884 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 885 .Case("+xop", XOP) 886 .Case("+fma4", FMA4) 887 .Case("+sse4a", SSE4A) 888 .Default(NoXOP); 889 XOPLevel = std::max(XOPLevel, XLevel); 890 } 891 892 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 893 // matches the selected sse level. 894 if ((FPMath == FP_SSE && SSELevel < SSE1) || 895 (FPMath == FP_387 && SSELevel >= SSE1)) { 896 Diags.Report(diag::err_target_unsupported_fpmath) 897 << (FPMath == FP_SSE ? "sse" : "387"); 898 return false; 899 } 900 901 SimdDefaultAlign = 902 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 903 return true; 904 } 905 906 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 907 /// definitions for this particular subtarget. 908 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 909 MacroBuilder &Builder) const { 910 // Inline assembly supports X86 flag outputs. 911 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 912 913 std::string CodeModel = getTargetOpts().CodeModel; 914 if (CodeModel == "default") 915 CodeModel = "small"; 916 Builder.defineMacro("__code_model_" + CodeModel + "__"); 917 918 // Target identification. 919 if (getTriple().getArch() == llvm::Triple::x86_64) { 920 Builder.defineMacro("__amd64__"); 921 Builder.defineMacro("__amd64"); 922 Builder.defineMacro("__x86_64"); 923 Builder.defineMacro("__x86_64__"); 924 if (getTriple().getArchName() == "x86_64h") { 925 Builder.defineMacro("__x86_64h"); 926 Builder.defineMacro("__x86_64h__"); 927 } 928 } else { 929 DefineStd(Builder, "i386", Opts); 930 } 931 932 Builder.defineMacro("__SEG_GS"); 933 Builder.defineMacro("__SEG_FS"); 934 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 935 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 936 937 // Subtarget options. 938 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 939 // truly should be based on -mtune options. 940 switch (CPU) { 941 case CK_Generic: 942 break; 943 case CK_i386: 944 // The rest are coming from the i386 define above. 945 Builder.defineMacro("__tune_i386__"); 946 break; 947 case CK_i486: 948 case CK_WinChipC6: 949 case CK_WinChip2: 950 case CK_C3: 951 defineCPUMacros(Builder, "i486"); 952 break; 953 case CK_PentiumMMX: 954 Builder.defineMacro("__pentium_mmx__"); 955 Builder.defineMacro("__tune_pentium_mmx__"); 956 LLVM_FALLTHROUGH; 957 case CK_i586: 958 case CK_Pentium: 959 defineCPUMacros(Builder, "i586"); 960 defineCPUMacros(Builder, "pentium"); 961 break; 962 case CK_Pentium3: 963 case CK_PentiumM: 964 Builder.defineMacro("__tune_pentium3__"); 965 LLVM_FALLTHROUGH; 966 case CK_Pentium2: 967 case CK_C3_2: 968 Builder.defineMacro("__tune_pentium2__"); 969 LLVM_FALLTHROUGH; 970 case CK_PentiumPro: 971 case CK_i686: 972 defineCPUMacros(Builder, "i686"); 973 defineCPUMacros(Builder, "pentiumpro"); 974 break; 975 case CK_Pentium4: 976 defineCPUMacros(Builder, "pentium4"); 977 break; 978 case CK_Yonah: 979 case CK_Prescott: 980 case CK_Nocona: 981 defineCPUMacros(Builder, "nocona"); 982 break; 983 case CK_Core2: 984 case CK_Penryn: 985 defineCPUMacros(Builder, "core2"); 986 break; 987 case CK_Bonnell: 988 defineCPUMacros(Builder, "atom"); 989 break; 990 case CK_Silvermont: 991 defineCPUMacros(Builder, "slm"); 992 break; 993 case CK_Goldmont: 994 defineCPUMacros(Builder, "goldmont"); 995 break; 996 case CK_GoldmontPlus: 997 defineCPUMacros(Builder, "goldmont_plus"); 998 break; 999 case CK_Tremont: 1000 defineCPUMacros(Builder, "tremont"); 1001 break; 1002 case CK_Nehalem: 1003 case CK_Westmere: 1004 case CK_SandyBridge: 1005 case CK_IvyBridge: 1006 case CK_Haswell: 1007 case CK_Broadwell: 1008 case CK_SkylakeClient: 1009 case CK_SkylakeServer: 1010 case CK_Cascadelake: 1011 case CK_Cooperlake: 1012 case CK_Cannonlake: 1013 case CK_IcelakeClient: 1014 case CK_IcelakeServer: 1015 case CK_Tigerlake: 1016 // FIXME: Historically, we defined this legacy name, it would be nice to 1017 // remove it at some point. We've never exposed fine-grained names for 1018 // recent primary x86 CPUs, and we should keep it that way. 1019 defineCPUMacros(Builder, "corei7"); 1020 break; 1021 case CK_KNL: 1022 defineCPUMacros(Builder, "knl"); 1023 break; 1024 case CK_KNM: 1025 break; 1026 case CK_Lakemont: 1027 defineCPUMacros(Builder, "i586", /*Tuning*/false); 1028 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 1029 Builder.defineMacro("__tune_lakemont__"); 1030 break; 1031 case CK_K6_2: 1032 Builder.defineMacro("__k6_2__"); 1033 Builder.defineMacro("__tune_k6_2__"); 1034 LLVM_FALLTHROUGH; 1035 case CK_K6_3: 1036 if (CPU != CK_K6_2) { // In case of fallthrough 1037 // FIXME: GCC may be enabling these in cases where some other k6 1038 // architecture is specified but -m3dnow is explicitly provided. The 1039 // exact semantics need to be determined and emulated here. 1040 Builder.defineMacro("__k6_3__"); 1041 Builder.defineMacro("__tune_k6_3__"); 1042 } 1043 LLVM_FALLTHROUGH; 1044 case CK_K6: 1045 defineCPUMacros(Builder, "k6"); 1046 break; 1047 case CK_Athlon: 1048 case CK_AthlonXP: 1049 defineCPUMacros(Builder, "athlon"); 1050 if (SSELevel != NoSSE) { 1051 Builder.defineMacro("__athlon_sse__"); 1052 Builder.defineMacro("__tune_athlon_sse__"); 1053 } 1054 break; 1055 case CK_K8: 1056 case CK_K8SSE3: 1057 case CK_x86_64: 1058 defineCPUMacros(Builder, "k8"); 1059 break; 1060 case CK_AMDFAM10: 1061 defineCPUMacros(Builder, "amdfam10"); 1062 break; 1063 case CK_BTVER1: 1064 defineCPUMacros(Builder, "btver1"); 1065 break; 1066 case CK_BTVER2: 1067 defineCPUMacros(Builder, "btver2"); 1068 break; 1069 case CK_BDVER1: 1070 defineCPUMacros(Builder, "bdver1"); 1071 break; 1072 case CK_BDVER2: 1073 defineCPUMacros(Builder, "bdver2"); 1074 break; 1075 case CK_BDVER3: 1076 defineCPUMacros(Builder, "bdver3"); 1077 break; 1078 case CK_BDVER4: 1079 defineCPUMacros(Builder, "bdver4"); 1080 break; 1081 case CK_ZNVER1: 1082 defineCPUMacros(Builder, "znver1"); 1083 break; 1084 case CK_ZNVER2: 1085 defineCPUMacros(Builder, "znver2"); 1086 break; 1087 case CK_Geode: 1088 defineCPUMacros(Builder, "geode"); 1089 break; 1090 } 1091 1092 // Target properties. 1093 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1094 1095 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 1096 // functions in glibc header files that use FP Stack inline asm which the 1097 // backend can't deal with (PR879). 1098 Builder.defineMacro("__NO_MATH_INLINES"); 1099 1100 if (HasAES) 1101 Builder.defineMacro("__AES__"); 1102 1103 if (HasVAES) 1104 Builder.defineMacro("__VAES__"); 1105 1106 if (HasPCLMUL) 1107 Builder.defineMacro("__PCLMUL__"); 1108 1109 if (HasVPCLMULQDQ) 1110 Builder.defineMacro("__VPCLMULQDQ__"); 1111 1112 if (HasLZCNT) 1113 Builder.defineMacro("__LZCNT__"); 1114 1115 if (HasRDRND) 1116 Builder.defineMacro("__RDRND__"); 1117 1118 if (HasFSGSBASE) 1119 Builder.defineMacro("__FSGSBASE__"); 1120 1121 if (HasBMI) 1122 Builder.defineMacro("__BMI__"); 1123 1124 if (HasBMI2) 1125 Builder.defineMacro("__BMI2__"); 1126 1127 if (HasPOPCNT) 1128 Builder.defineMacro("__POPCNT__"); 1129 1130 if (HasRTM) 1131 Builder.defineMacro("__RTM__"); 1132 1133 if (HasPRFCHW) 1134 Builder.defineMacro("__PRFCHW__"); 1135 1136 if (HasRDSEED) 1137 Builder.defineMacro("__RDSEED__"); 1138 1139 if (HasADX) 1140 Builder.defineMacro("__ADX__"); 1141 1142 if (HasTBM) 1143 Builder.defineMacro("__TBM__"); 1144 1145 if (HasLWP) 1146 Builder.defineMacro("__LWP__"); 1147 1148 if (HasMWAITX) 1149 Builder.defineMacro("__MWAITX__"); 1150 1151 if (HasMOVBE) 1152 Builder.defineMacro("__MOVBE__"); 1153 1154 switch (XOPLevel) { 1155 case XOP: 1156 Builder.defineMacro("__XOP__"); 1157 LLVM_FALLTHROUGH; 1158 case FMA4: 1159 Builder.defineMacro("__FMA4__"); 1160 LLVM_FALLTHROUGH; 1161 case SSE4A: 1162 Builder.defineMacro("__SSE4A__"); 1163 LLVM_FALLTHROUGH; 1164 case NoXOP: 1165 break; 1166 } 1167 1168 if (HasFMA) 1169 Builder.defineMacro("__FMA__"); 1170 1171 if (HasF16C) 1172 Builder.defineMacro("__F16C__"); 1173 1174 if (HasGFNI) 1175 Builder.defineMacro("__GFNI__"); 1176 1177 if (HasAVX512CD) 1178 Builder.defineMacro("__AVX512CD__"); 1179 if (HasAVX512VPOPCNTDQ) 1180 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1181 if (HasAVX512VNNI) 1182 Builder.defineMacro("__AVX512VNNI__"); 1183 if (HasAVX512BF16) 1184 Builder.defineMacro("__AVX512BF16__"); 1185 if (HasAVX512ER) 1186 Builder.defineMacro("__AVX512ER__"); 1187 if (HasAVX512PF) 1188 Builder.defineMacro("__AVX512PF__"); 1189 if (HasAVX512DQ) 1190 Builder.defineMacro("__AVX512DQ__"); 1191 if (HasAVX512BITALG) 1192 Builder.defineMacro("__AVX512BITALG__"); 1193 if (HasAVX512BW) 1194 Builder.defineMacro("__AVX512BW__"); 1195 if (HasAVX512VL) 1196 Builder.defineMacro("__AVX512VL__"); 1197 if (HasAVX512VBMI) 1198 Builder.defineMacro("__AVX512VBMI__"); 1199 if (HasAVX512VBMI2) 1200 Builder.defineMacro("__AVX512VBMI2__"); 1201 if (HasAVX512IFMA) 1202 Builder.defineMacro("__AVX512IFMA__"); 1203 if (HasAVX512VP2INTERSECT) 1204 Builder.defineMacro("__AVX512VP2INTERSECT__"); 1205 if (HasSHA) 1206 Builder.defineMacro("__SHA__"); 1207 1208 if (HasFXSR) 1209 Builder.defineMacro("__FXSR__"); 1210 if (HasXSAVE) 1211 Builder.defineMacro("__XSAVE__"); 1212 if (HasXSAVEOPT) 1213 Builder.defineMacro("__XSAVEOPT__"); 1214 if (HasXSAVEC) 1215 Builder.defineMacro("__XSAVEC__"); 1216 if (HasXSAVES) 1217 Builder.defineMacro("__XSAVES__"); 1218 if (HasPKU) 1219 Builder.defineMacro("__PKU__"); 1220 if (HasCLFLUSHOPT) 1221 Builder.defineMacro("__CLFLUSHOPT__"); 1222 if (HasCLWB) 1223 Builder.defineMacro("__CLWB__"); 1224 if (HasWBNOINVD) 1225 Builder.defineMacro("__WBNOINVD__"); 1226 if (HasSHSTK) 1227 Builder.defineMacro("__SHSTK__"); 1228 if (HasSGX) 1229 Builder.defineMacro("__SGX__"); 1230 if (HasPREFETCHWT1) 1231 Builder.defineMacro("__PREFETCHWT1__"); 1232 if (HasCLZERO) 1233 Builder.defineMacro("__CLZERO__"); 1234 if (HasRDPID) 1235 Builder.defineMacro("__RDPID__"); 1236 if (HasCLDEMOTE) 1237 Builder.defineMacro("__CLDEMOTE__"); 1238 if (HasWAITPKG) 1239 Builder.defineMacro("__WAITPKG__"); 1240 if (HasMOVDIRI) 1241 Builder.defineMacro("__MOVDIRI__"); 1242 if (HasMOVDIR64B) 1243 Builder.defineMacro("__MOVDIR64B__"); 1244 if (HasPCONFIG) 1245 Builder.defineMacro("__PCONFIG__"); 1246 if (HasPTWRITE) 1247 Builder.defineMacro("__PTWRITE__"); 1248 if (HasINVPCID) 1249 Builder.defineMacro("__INVPCID__"); 1250 if (HasENQCMD) 1251 Builder.defineMacro("__ENQCMD__"); 1252 if (HasSERIALIZE) 1253 Builder.defineMacro("__SERIALIZE__"); 1254 1255 // Each case falls through to the previous one here. 1256 switch (SSELevel) { 1257 case AVX512F: 1258 Builder.defineMacro("__AVX512F__"); 1259 LLVM_FALLTHROUGH; 1260 case AVX2: 1261 Builder.defineMacro("__AVX2__"); 1262 LLVM_FALLTHROUGH; 1263 case AVX: 1264 Builder.defineMacro("__AVX__"); 1265 LLVM_FALLTHROUGH; 1266 case SSE42: 1267 Builder.defineMacro("__SSE4_2__"); 1268 LLVM_FALLTHROUGH; 1269 case SSE41: 1270 Builder.defineMacro("__SSE4_1__"); 1271 LLVM_FALLTHROUGH; 1272 case SSSE3: 1273 Builder.defineMacro("__SSSE3__"); 1274 LLVM_FALLTHROUGH; 1275 case SSE3: 1276 Builder.defineMacro("__SSE3__"); 1277 LLVM_FALLTHROUGH; 1278 case SSE2: 1279 Builder.defineMacro("__SSE2__"); 1280 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1281 LLVM_FALLTHROUGH; 1282 case SSE1: 1283 Builder.defineMacro("__SSE__"); 1284 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1285 LLVM_FALLTHROUGH; 1286 case NoSSE: 1287 break; 1288 } 1289 1290 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1291 switch (SSELevel) { 1292 case AVX512F: 1293 case AVX2: 1294 case AVX: 1295 case SSE42: 1296 case SSE41: 1297 case SSSE3: 1298 case SSE3: 1299 case SSE2: 1300 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1301 break; 1302 case SSE1: 1303 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1304 break; 1305 default: 1306 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1307 break; 1308 } 1309 } 1310 1311 // Each case falls through to the previous one here. 1312 switch (MMX3DNowLevel) { 1313 case AMD3DNowAthlon: 1314 Builder.defineMacro("__3dNOW_A__"); 1315 LLVM_FALLTHROUGH; 1316 case AMD3DNow: 1317 Builder.defineMacro("__3dNOW__"); 1318 LLVM_FALLTHROUGH; 1319 case MMX: 1320 Builder.defineMacro("__MMX__"); 1321 LLVM_FALLTHROUGH; 1322 case NoMMX3DNow: 1323 break; 1324 } 1325 1326 if (CPU >= CK_i486 || CPU == CK_Generic) { 1327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1330 } 1331 if (HasCX8) 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1333 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1335 1336 if (HasFloat128) 1337 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1338 } 1339 1340 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1341 return llvm::StringSwitch<bool>(Name) 1342 .Case("3dnow", true) 1343 .Case("3dnowa", true) 1344 .Case("adx", true) 1345 .Case("aes", true) 1346 .Case("avx", true) 1347 .Case("avx2", true) 1348 .Case("avx512f", true) 1349 .Case("avx512cd", true) 1350 .Case("avx512vpopcntdq", true) 1351 .Case("avx512vnni", true) 1352 .Case("avx512bf16", true) 1353 .Case("avx512er", true) 1354 .Case("avx512pf", true) 1355 .Case("avx512dq", true) 1356 .Case("avx512bitalg", true) 1357 .Case("avx512bw", true) 1358 .Case("avx512vl", true) 1359 .Case("avx512vbmi", true) 1360 .Case("avx512vbmi2", true) 1361 .Case("avx512ifma", true) 1362 .Case("avx512vp2intersect", true) 1363 .Case("bmi", true) 1364 .Case("bmi2", true) 1365 .Case("cldemote", true) 1366 .Case("clflushopt", true) 1367 .Case("clwb", true) 1368 .Case("clzero", true) 1369 .Case("cx16", true) 1370 .Case("enqcmd", true) 1371 .Case("f16c", true) 1372 .Case("fma", true) 1373 .Case("fma4", true) 1374 .Case("fsgsbase", true) 1375 .Case("fxsr", true) 1376 .Case("gfni", true) 1377 .Case("invpcid", true) 1378 .Case("lwp", true) 1379 .Case("lzcnt", true) 1380 .Case("mmx", true) 1381 .Case("movbe", true) 1382 .Case("movdiri", true) 1383 .Case("movdir64b", true) 1384 .Case("mwaitx", true) 1385 .Case("pclmul", true) 1386 .Case("pconfig", true) 1387 .Case("pku", true) 1388 .Case("popcnt", true) 1389 .Case("prefetchwt1", true) 1390 .Case("prfchw", true) 1391 .Case("ptwrite", true) 1392 .Case("rdpid", true) 1393 .Case("rdrnd", true) 1394 .Case("rdseed", true) 1395 .Case("rtm", true) 1396 .Case("sahf", true) 1397 .Case("serialize", true) 1398 .Case("sgx", true) 1399 .Case("sha", true) 1400 .Case("shstk", true) 1401 .Case("sse", true) 1402 .Case("sse2", true) 1403 .Case("sse3", true) 1404 .Case("ssse3", true) 1405 .Case("sse4", true) 1406 .Case("sse4.1", true) 1407 .Case("sse4.2", true) 1408 .Case("sse4a", true) 1409 .Case("tbm", true) 1410 .Case("vaes", true) 1411 .Case("vpclmulqdq", true) 1412 .Case("wbnoinvd", true) 1413 .Case("waitpkg", true) 1414 .Case("x87", true) 1415 .Case("xop", true) 1416 .Case("xsave", true) 1417 .Case("xsavec", true) 1418 .Case("xsaves", true) 1419 .Case("xsaveopt", true) 1420 .Default(false); 1421 } 1422 1423 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1424 return llvm::StringSwitch<bool>(Feature) 1425 .Case("adx", HasADX) 1426 .Case("aes", HasAES) 1427 .Case("avx", SSELevel >= AVX) 1428 .Case("avx2", SSELevel >= AVX2) 1429 .Case("avx512f", SSELevel >= AVX512F) 1430 .Case("avx512cd", HasAVX512CD) 1431 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1432 .Case("avx512vnni", HasAVX512VNNI) 1433 .Case("avx512bf16", HasAVX512BF16) 1434 .Case("avx512er", HasAVX512ER) 1435 .Case("avx512pf", HasAVX512PF) 1436 .Case("avx512dq", HasAVX512DQ) 1437 .Case("avx512bitalg", HasAVX512BITALG) 1438 .Case("avx512bw", HasAVX512BW) 1439 .Case("avx512vl", HasAVX512VL) 1440 .Case("avx512vbmi", HasAVX512VBMI) 1441 .Case("avx512vbmi2", HasAVX512VBMI2) 1442 .Case("avx512ifma", HasAVX512IFMA) 1443 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1444 .Case("bmi", HasBMI) 1445 .Case("bmi2", HasBMI2) 1446 .Case("cldemote", HasCLDEMOTE) 1447 .Case("clflushopt", HasCLFLUSHOPT) 1448 .Case("clwb", HasCLWB) 1449 .Case("clzero", HasCLZERO) 1450 .Case("cx8", HasCX8) 1451 .Case("cx16", HasCX16) 1452 .Case("enqcmd", HasENQCMD) 1453 .Case("f16c", HasF16C) 1454 .Case("fma", HasFMA) 1455 .Case("fma4", XOPLevel >= FMA4) 1456 .Case("fsgsbase", HasFSGSBASE) 1457 .Case("fxsr", HasFXSR) 1458 .Case("gfni", HasGFNI) 1459 .Case("invpcid", HasINVPCID) 1460 .Case("lwp", HasLWP) 1461 .Case("lzcnt", HasLZCNT) 1462 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1463 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1464 .Case("mmx", MMX3DNowLevel >= MMX) 1465 .Case("movbe", HasMOVBE) 1466 .Case("movdiri", HasMOVDIRI) 1467 .Case("movdir64b", HasMOVDIR64B) 1468 .Case("mwaitx", HasMWAITX) 1469 .Case("pclmul", HasPCLMUL) 1470 .Case("pconfig", HasPCONFIG) 1471 .Case("pku", HasPKU) 1472 .Case("popcnt", HasPOPCNT) 1473 .Case("prefetchwt1", HasPREFETCHWT1) 1474 .Case("prfchw", HasPRFCHW) 1475 .Case("ptwrite", HasPTWRITE) 1476 .Case("rdpid", HasRDPID) 1477 .Case("rdrnd", HasRDRND) 1478 .Case("rdseed", HasRDSEED) 1479 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1480 .Case("rtm", HasRTM) 1481 .Case("sahf", HasLAHFSAHF) 1482 .Case("serialize", HasSERIALIZE) 1483 .Case("sgx", HasSGX) 1484 .Case("sha", HasSHA) 1485 .Case("shstk", HasSHSTK) 1486 .Case("sse", SSELevel >= SSE1) 1487 .Case("sse2", SSELevel >= SSE2) 1488 .Case("sse3", SSELevel >= SSE3) 1489 .Case("ssse3", SSELevel >= SSSE3) 1490 .Case("sse4.1", SSELevel >= SSE41) 1491 .Case("sse4.2", SSELevel >= SSE42) 1492 .Case("sse4a", XOPLevel >= SSE4A) 1493 .Case("tbm", HasTBM) 1494 .Case("vaes", HasVAES) 1495 .Case("vpclmulqdq", HasVPCLMULQDQ) 1496 .Case("wbnoinvd", HasWBNOINVD) 1497 .Case("waitpkg", HasWAITPKG) 1498 .Case("x86", true) 1499 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1500 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1501 .Case("xop", XOPLevel >= XOP) 1502 .Case("xsave", HasXSAVE) 1503 .Case("xsavec", HasXSAVEC) 1504 .Case("xsaves", HasXSAVES) 1505 .Case("xsaveopt", HasXSAVEOPT) 1506 .Default(false); 1507 } 1508 1509 // We can't use a generic validation scheme for the features accepted here 1510 // versus subtarget features accepted in the target attribute because the 1511 // bitfield structure that's initialized in the runtime only supports the 1512 // below currently rather than the full range of subtarget features. (See 1513 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1514 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1515 return llvm::StringSwitch<bool>(FeatureStr) 1516 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1517 #include "llvm/Support/X86TargetParser.def" 1518 .Default(false); 1519 } 1520 1521 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1522 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1523 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) 1524 #include "llvm/Support/X86TargetParser.def" 1525 ; 1526 // Note, this function should only be used after ensuring the value is 1527 // correct, so it asserts if the value is out of range. 1528 } 1529 1530 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 1531 enum class FeatPriority { 1532 #define FEATURE(FEAT) FEAT, 1533 #include "clang/Basic/X86Target.def" 1534 }; 1535 switch (Feat) { 1536 #define FEATURE(FEAT) \ 1537 case llvm::X86::FEAT: \ 1538 return static_cast<unsigned>(FeatPriority::FEAT); 1539 #include "clang/Basic/X86Target.def" 1540 default: 1541 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1542 } 1543 } 1544 1545 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1546 // Valid CPUs have a 'key feature' that compares just better than its key 1547 // feature. 1548 CPUKind Kind = getCPUKind(Name); 1549 if (Kind != CK_Generic) { 1550 switch (Kind) { 1551 default: 1552 llvm_unreachable( 1553 "CPU Type without a key feature used in 'target' attribute"); 1554 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ 1555 case CK_##ENUM: \ 1556 return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; 1557 #include "clang/Basic/X86Target.def" 1558 } 1559 } 1560 1561 // Now we know we have a feature, so get its priority and shift it a few so 1562 // that we have sufficient room for the CPUs (above). 1563 return getFeaturePriority(getFeature(Name)) << 1; 1564 } 1565 1566 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1567 return llvm::StringSwitch<bool>(Name) 1568 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1569 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1570 #include "clang/Basic/X86Target.def" 1571 .Default(false); 1572 } 1573 1574 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1575 return llvm::StringSwitch<StringRef>(Name) 1576 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1577 #include "clang/Basic/X86Target.def" 1578 .Default(Name); 1579 } 1580 1581 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1582 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1583 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1584 #include "clang/Basic/X86Target.def" 1585 .Default(0); 1586 } 1587 1588 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1589 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1590 StringRef WholeList = 1591 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1592 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1593 #include "clang/Basic/X86Target.def" 1594 .Default(""); 1595 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1596 } 1597 1598 // We can't use a generic validation scheme for the cpus accepted here 1599 // versus subtarget cpus accepted in the target attribute because the 1600 // variables intitialized by the runtime only support the below currently 1601 // rather than the full range of cpus. 1602 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1603 return llvm::StringSwitch<bool>(FeatureStr) 1604 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1605 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1606 .Cases(STR, ALIAS, true) 1607 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1608 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1609 #include "llvm/Support/X86TargetParser.def" 1610 .Default(false); 1611 } 1612 1613 static unsigned matchAsmCCConstraint(const char *&Name) { 1614 auto RV = llvm::StringSwitch<unsigned>(Name) 1615 .Case("@cca", 4) 1616 .Case("@ccae", 5) 1617 .Case("@ccb", 4) 1618 .Case("@ccbe", 5) 1619 .Case("@ccc", 4) 1620 .Case("@cce", 4) 1621 .Case("@ccz", 4) 1622 .Case("@ccg", 4) 1623 .Case("@ccge", 5) 1624 .Case("@ccl", 4) 1625 .Case("@ccle", 5) 1626 .Case("@ccna", 5) 1627 .Case("@ccnae", 6) 1628 .Case("@ccnb", 5) 1629 .Case("@ccnbe", 6) 1630 .Case("@ccnc", 5) 1631 .Case("@ccne", 5) 1632 .Case("@ccnz", 5) 1633 .Case("@ccng", 5) 1634 .Case("@ccnge", 6) 1635 .Case("@ccnl", 5) 1636 .Case("@ccnle", 6) 1637 .Case("@ccno", 5) 1638 .Case("@ccnp", 5) 1639 .Case("@ccns", 5) 1640 .Case("@cco", 4) 1641 .Case("@ccp", 4) 1642 .Case("@ccs", 4) 1643 .Default(0); 1644 return RV; 1645 } 1646 1647 bool X86TargetInfo::validateAsmConstraint( 1648 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1649 switch (*Name) { 1650 default: 1651 return false; 1652 // Constant constraints. 1653 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1654 // instructions. 1655 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1656 // x86_64 instructions. 1657 case 's': 1658 Info.setRequiresImmediate(); 1659 return true; 1660 case 'I': 1661 Info.setRequiresImmediate(0, 31); 1662 return true; 1663 case 'J': 1664 Info.setRequiresImmediate(0, 63); 1665 return true; 1666 case 'K': 1667 Info.setRequiresImmediate(-128, 127); 1668 return true; 1669 case 'L': 1670 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1671 return true; 1672 case 'M': 1673 Info.setRequiresImmediate(0, 3); 1674 return true; 1675 case 'N': 1676 Info.setRequiresImmediate(0, 255); 1677 return true; 1678 case 'O': 1679 Info.setRequiresImmediate(0, 127); 1680 return true; 1681 // Register constraints. 1682 case 'Y': // 'Y' is the first character for several 2-character constraints. 1683 // Shift the pointer to the second character of the constraint. 1684 Name++; 1685 switch (*Name) { 1686 default: 1687 return false; 1688 case 'z': 1689 case '0': // First SSE register. 1690 case '2': 1691 case 't': // Any SSE register, when SSE2 is enabled. 1692 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1693 case 'm': // Any MMX register, when inter-unit moves enabled. 1694 case 'k': // AVX512 arch mask registers: k1-k7. 1695 Info.setAllowsRegister(); 1696 return true; 1697 } 1698 case 'f': // Any x87 floating point stack register. 1699 // Constraint 'f' cannot be used for output operands. 1700 if (Info.ConstraintStr[0] == '=') 1701 return false; 1702 Info.setAllowsRegister(); 1703 return true; 1704 case 'a': // eax. 1705 case 'b': // ebx. 1706 case 'c': // ecx. 1707 case 'd': // edx. 1708 case 'S': // esi. 1709 case 'D': // edi. 1710 case 'A': // edx:eax. 1711 case 't': // Top of floating point stack. 1712 case 'u': // Second from top of floating point stack. 1713 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1714 case 'y': // Any MMX register. 1715 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1716 case 'x': // Any SSE register. 1717 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1718 // for intermideate k reg operations). 1719 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1720 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1721 case 'l': // "Index" registers: any general register that can be used as an 1722 // index in a base+index memory access. 1723 Info.setAllowsRegister(); 1724 return true; 1725 // Floating point constant constraints. 1726 case 'C': // SSE floating point constant. 1727 case 'G': // x87 floating point constant. 1728 return true; 1729 case '@': 1730 // CC condition changes. 1731 if (auto Len = matchAsmCCConstraint(Name)) { 1732 Name += Len - 1; 1733 Info.setAllowsRegister(); 1734 return true; 1735 } 1736 return false; 1737 } 1738 } 1739 1740 // Below is based on the following information: 1741 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1742 // | Processor Name | Cache Line Size (Bytes) | Source | 1743 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1744 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1745 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1746 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1747 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1748 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1749 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1750 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1751 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1752 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1753 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1754 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1755 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1756 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1757 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1758 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1759 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1760 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1761 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1762 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1763 switch (CPU) { 1764 // i386 1765 case CK_i386: 1766 // i486 1767 case CK_i486: 1768 case CK_WinChipC6: 1769 case CK_WinChip2: 1770 case CK_C3: 1771 // Lakemont 1772 case CK_Lakemont: 1773 return 16; 1774 1775 // i586 1776 case CK_i586: 1777 case CK_Pentium: 1778 case CK_PentiumMMX: 1779 // i686 1780 case CK_PentiumPro: 1781 case CK_i686: 1782 case CK_Pentium2: 1783 case CK_Pentium3: 1784 case CK_PentiumM: 1785 case CK_C3_2: 1786 // K6 1787 case CK_K6: 1788 case CK_K6_2: 1789 case CK_K6_3: 1790 // Geode 1791 case CK_Geode: 1792 return 32; 1793 1794 // Netburst 1795 case CK_Pentium4: 1796 case CK_Prescott: 1797 case CK_Nocona: 1798 // Atom 1799 case CK_Bonnell: 1800 case CK_Silvermont: 1801 case CK_Goldmont: 1802 case CK_GoldmontPlus: 1803 case CK_Tremont: 1804 1805 case CK_Westmere: 1806 case CK_SandyBridge: 1807 case CK_IvyBridge: 1808 case CK_Haswell: 1809 case CK_Broadwell: 1810 case CK_SkylakeClient: 1811 case CK_SkylakeServer: 1812 case CK_Cascadelake: 1813 case CK_Nehalem: 1814 case CK_Cooperlake: 1815 case CK_Cannonlake: 1816 case CK_Tigerlake: 1817 case CK_IcelakeClient: 1818 case CK_IcelakeServer: 1819 case CK_KNL: 1820 case CK_KNM: 1821 // K7 1822 case CK_Athlon: 1823 case CK_AthlonXP: 1824 // K8 1825 case CK_K8: 1826 case CK_K8SSE3: 1827 case CK_AMDFAM10: 1828 // Bobcat 1829 case CK_BTVER1: 1830 case CK_BTVER2: 1831 // Bulldozer 1832 case CK_BDVER1: 1833 case CK_BDVER2: 1834 case CK_BDVER3: 1835 case CK_BDVER4: 1836 // Zen 1837 case CK_ZNVER1: 1838 case CK_ZNVER2: 1839 // Deprecated 1840 case CK_x86_64: 1841 case CK_Yonah: 1842 case CK_Penryn: 1843 case CK_Core2: 1844 return 64; 1845 1846 // The following currently have unknown cache line sizes (but they are probably all 64): 1847 // Core 1848 case CK_Generic: 1849 return None; 1850 } 1851 llvm_unreachable("Unknown CPU kind"); 1852 } 1853 1854 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1855 StringRef Constraint, 1856 unsigned Size) const { 1857 // Strip off constraint modifiers. 1858 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1859 Constraint = Constraint.substr(1); 1860 1861 return validateOperandSize(FeatureMap, Constraint, Size); 1862 } 1863 1864 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1865 StringRef Constraint, 1866 unsigned Size) const { 1867 return validateOperandSize(FeatureMap, Constraint, Size); 1868 } 1869 1870 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1871 StringRef Constraint, 1872 unsigned Size) const { 1873 switch (Constraint[0]) { 1874 default: 1875 break; 1876 case 'k': 1877 // Registers k0-k7 (AVX512) size limit is 64 bit. 1878 case 'y': 1879 return Size <= 64; 1880 case 'f': 1881 case 't': 1882 case 'u': 1883 return Size <= 128; 1884 case 'Y': 1885 // 'Y' is the first character for several 2-character constraints. 1886 switch (Constraint[1]) { 1887 default: 1888 return false; 1889 case 'm': 1890 // 'Ym' is synonymous with 'y'. 1891 case 'k': 1892 return Size <= 64; 1893 case 'z': 1894 case '0': 1895 // XMM0 1896 if (FeatureMap.lookup("sse")) 1897 return Size <= 128U; 1898 return false; 1899 case 'i': 1900 case 't': 1901 case '2': 1902 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1903 if (SSELevel < SSE2) 1904 return false; 1905 break; 1906 } 1907 LLVM_FALLTHROUGH; 1908 case 'v': 1909 case 'x': 1910 if (FeatureMap.lookup("avx512f")) 1911 // 512-bit zmm registers can be used if target supports AVX512F. 1912 return Size <= 512U; 1913 else if (FeatureMap.lookup("avx")) 1914 // 256-bit ymm registers can be used if target supports AVX. 1915 return Size <= 256U; 1916 return Size <= 128U; 1917 1918 } 1919 1920 return true; 1921 } 1922 1923 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1924 switch (*Constraint) { 1925 case '@': 1926 if (auto Len = matchAsmCCConstraint(Constraint)) { 1927 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1928 Constraint += Len - 1; 1929 return Converted; 1930 } 1931 return std::string(1, *Constraint); 1932 case 'a': 1933 return std::string("{ax}"); 1934 case 'b': 1935 return std::string("{bx}"); 1936 case 'c': 1937 return std::string("{cx}"); 1938 case 'd': 1939 return std::string("{dx}"); 1940 case 'S': 1941 return std::string("{si}"); 1942 case 'D': 1943 return std::string("{di}"); 1944 case 'p': // address 1945 return std::string("im"); 1946 case 't': // top of floating point stack. 1947 return std::string("{st}"); 1948 case 'u': // second from top of floating point stack. 1949 return std::string("{st(1)}"); // second from top of floating point stack. 1950 case 'Y': 1951 switch (Constraint[1]) { 1952 default: 1953 // Break from inner switch and fall through (copy single char), 1954 // continue parsing after copying the current constraint into 1955 // the return string. 1956 break; 1957 case 'k': 1958 case 'm': 1959 case 'i': 1960 case 't': 1961 case 'z': 1962 case '0': 1963 case '2': 1964 // "^" hints llvm that this is a 2 letter constraint. 1965 // "Constraint++" is used to promote the string iterator 1966 // to the next constraint. 1967 return std::string("^") + std::string(Constraint++, 2); 1968 } 1969 LLVM_FALLTHROUGH; 1970 default: 1971 return std::string(1, *Constraint); 1972 } 1973 } 1974 1975 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1976 // Perform any per-CPU checks necessary to determine if this CPU is 1977 // acceptable. 1978 switch (Kind) { 1979 case CK_Generic: 1980 // No processor selected! 1981 return false; 1982 #define PROC(ENUM, STRING, IS64BIT) \ 1983 case CK_##ENUM: \ 1984 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1985 #include "clang/Basic/X86Target.def" 1986 } 1987 llvm_unreachable("Unhandled CPU kind"); 1988 } 1989 1990 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1991 #define PROC(ENUM, STRING, IS64BIT) \ 1992 if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ 1993 Values.emplace_back(STRING); 1994 // For aliases we need to lookup the CPUKind to check get the 64-bit ness. 1995 #define PROC_ALIAS(ENUM, ALIAS) \ 1996 if (checkCPUKind(CK_##ENUM)) \ 1997 Values.emplace_back(ALIAS); 1998 #include "clang/Basic/X86Target.def" 1999 } 2000 2001 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 2002 return llvm::StringSwitch<CPUKind>(CPU) 2003 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 2004 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 2005 #include "clang/Basic/X86Target.def" 2006 .Default(CK_Generic); 2007 } 2008 2009 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 2010 return llvm::makeArrayRef(GCCRegNames); 2011 } 2012 2013 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 2014 return llvm::makeArrayRef(AddlRegNames); 2015 } 2016 2017 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 2018 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 2019 Builtin::FirstTSBuiltin + 1); 2020 } 2021 2022 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 2023 return llvm::makeArrayRef(BuiltinInfoX86, 2024 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 2025 } 2026