1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 121 return false; 122 123 // Can't do this earlier because we need to be able to explicitly enable 124 // or disable these features and the things that they depend upon. 125 126 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 127 auto I = Features.find("sse4.2"); 128 if (I != Features.end() && I->getValue() && 129 llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) 130 Features["popcnt"] = true; 131 132 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 133 // then enable MMX. 134 I = Features.find("sse"); 135 if (I != Features.end() && I->getValue() && 136 llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) 137 Features["mmx"] = true; 138 139 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 140 I = Features.find("avx"); 141 if (I != Features.end() && I->getValue() && 142 llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end()) 143 Features["xsave"] = true; 144 145 return true; 146 } 147 148 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 149 StringRef Name, bool Enabled) const { 150 if (Name == "sse4") { 151 // We can get here via the __target__ attribute since that's not controlled 152 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 153 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 154 // disabled. 155 if (Enabled) 156 Name = "sse4.2"; 157 else 158 Name = "sse4.1"; 159 } 160 161 Features[Name] = Enabled; 162 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 163 } 164 165 /// handleTargetFeatures - Perform initialization based on the user 166 /// configured set of features. 167 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 168 DiagnosticsEngine &Diags) { 169 for (const auto &Feature : Features) { 170 if (Feature[0] != '+') 171 continue; 172 173 if (Feature == "+aes") { 174 HasAES = true; 175 } else if (Feature == "+vaes") { 176 HasVAES = true; 177 } else if (Feature == "+pclmul") { 178 HasPCLMUL = true; 179 } else if (Feature == "+vpclmulqdq") { 180 HasVPCLMULQDQ = true; 181 } else if (Feature == "+lzcnt") { 182 HasLZCNT = true; 183 } else if (Feature == "+rdrnd") { 184 HasRDRND = true; 185 } else if (Feature == "+fsgsbase") { 186 HasFSGSBASE = true; 187 } else if (Feature == "+bmi") { 188 HasBMI = true; 189 } else if (Feature == "+bmi2") { 190 HasBMI2 = true; 191 } else if (Feature == "+popcnt") { 192 HasPOPCNT = true; 193 } else if (Feature == "+rtm") { 194 HasRTM = true; 195 } else if (Feature == "+prfchw") { 196 HasPRFCHW = true; 197 } else if (Feature == "+rdseed") { 198 HasRDSEED = true; 199 } else if (Feature == "+adx") { 200 HasADX = true; 201 } else if (Feature == "+tbm") { 202 HasTBM = true; 203 } else if (Feature == "+lwp") { 204 HasLWP = true; 205 } else if (Feature == "+fma") { 206 HasFMA = true; 207 } else if (Feature == "+f16c") { 208 HasF16C = true; 209 } else if (Feature == "+gfni") { 210 HasGFNI = true; 211 } else if (Feature == "+avx512cd") { 212 HasAVX512CD = true; 213 } else if (Feature == "+avx512vpopcntdq") { 214 HasAVX512VPOPCNTDQ = true; 215 } else if (Feature == "+avx512vnni") { 216 HasAVX512VNNI = true; 217 } else if (Feature == "+avx512bf16") { 218 HasAVX512BF16 = true; 219 } else if (Feature == "+avx512er") { 220 HasAVX512ER = true; 221 } else if (Feature == "+avx512pf") { 222 HasAVX512PF = true; 223 } else if (Feature == "+avx512dq") { 224 HasAVX512DQ = true; 225 } else if (Feature == "+avx512bitalg") { 226 HasAVX512BITALG = true; 227 } else if (Feature == "+avx512bw") { 228 HasAVX512BW = true; 229 } else if (Feature == "+avx512vl") { 230 HasAVX512VL = true; 231 } else if (Feature == "+avx512vbmi") { 232 HasAVX512VBMI = true; 233 } else if (Feature == "+avx512vbmi2") { 234 HasAVX512VBMI2 = true; 235 } else if (Feature == "+avx512ifma") { 236 HasAVX512IFMA = true; 237 } else if (Feature == "+avx512vp2intersect") { 238 HasAVX512VP2INTERSECT = true; 239 } else if (Feature == "+sha") { 240 HasSHA = true; 241 } else if (Feature == "+shstk") { 242 HasSHSTK = true; 243 } else if (Feature == "+movbe") { 244 HasMOVBE = true; 245 } else if (Feature == "+sgx") { 246 HasSGX = true; 247 } else if (Feature == "+cx8") { 248 HasCX8 = true; 249 } else if (Feature == "+cx16") { 250 HasCX16 = true; 251 } else if (Feature == "+fxsr") { 252 HasFXSR = true; 253 } else if (Feature == "+xsave") { 254 HasXSAVE = true; 255 } else if (Feature == "+xsaveopt") { 256 HasXSAVEOPT = true; 257 } else if (Feature == "+xsavec") { 258 HasXSAVEC = true; 259 } else if (Feature == "+xsaves") { 260 HasXSAVES = true; 261 } else if (Feature == "+mwaitx") { 262 HasMWAITX = true; 263 } else if (Feature == "+pku") { 264 HasPKU = true; 265 } else if (Feature == "+clflushopt") { 266 HasCLFLUSHOPT = true; 267 } else if (Feature == "+clwb") { 268 HasCLWB = true; 269 } else if (Feature == "+wbnoinvd") { 270 HasWBNOINVD = true; 271 } else if (Feature == "+prefetchwt1") { 272 HasPREFETCHWT1 = true; 273 } else if (Feature == "+clzero") { 274 HasCLZERO = true; 275 } else if (Feature == "+cldemote") { 276 HasCLDEMOTE = true; 277 } else if (Feature == "+rdpid") { 278 HasRDPID = true; 279 } else if (Feature == "+retpoline-external-thunk") { 280 HasRetpolineExternalThunk = true; 281 } else if (Feature == "+sahf") { 282 HasLAHFSAHF = true; 283 } else if (Feature == "+waitpkg") { 284 HasWAITPKG = true; 285 } else if (Feature == "+movdiri") { 286 HasMOVDIRI = true; 287 } else if (Feature == "+movdir64b") { 288 HasMOVDIR64B = true; 289 } else if (Feature == "+pconfig") { 290 HasPCONFIG = true; 291 } else if (Feature == "+ptwrite") { 292 HasPTWRITE = true; 293 } else if (Feature == "+invpcid") { 294 HasINVPCID = true; 295 } else if (Feature == "+enqcmd") { 296 HasENQCMD = true; 297 } else if (Feature == "+amx-bf16") { 298 HasAMXBF16 = true; 299 } else if (Feature == "+amx-int8") { 300 HasAMXINT8 = true; 301 } else if (Feature == "+amx-tile") { 302 HasAMXTILE = true; 303 } else if (Feature == "+serialize") { 304 HasSERIALIZE = true; 305 } else if (Feature == "+tsxldtrk") { 306 HasTSXLDTRK = true; 307 } 308 309 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 310 .Case("+avx512f", AVX512F) 311 .Case("+avx2", AVX2) 312 .Case("+avx", AVX) 313 .Case("+sse4.2", SSE42) 314 .Case("+sse4.1", SSE41) 315 .Case("+ssse3", SSSE3) 316 .Case("+sse3", SSE3) 317 .Case("+sse2", SSE2) 318 .Case("+sse", SSE1) 319 .Default(NoSSE); 320 SSELevel = std::max(SSELevel, Level); 321 322 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 323 .Case("+3dnowa", AMD3DNowAthlon) 324 .Case("+3dnow", AMD3DNow) 325 .Case("+mmx", MMX) 326 .Default(NoMMX3DNow); 327 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 328 329 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 330 .Case("+xop", XOP) 331 .Case("+fma4", FMA4) 332 .Case("+sse4a", SSE4A) 333 .Default(NoXOP); 334 XOPLevel = std::max(XOPLevel, XLevel); 335 } 336 337 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 338 // matches the selected sse level. 339 if ((FPMath == FP_SSE && SSELevel < SSE1) || 340 (FPMath == FP_387 && SSELevel >= SSE1)) { 341 Diags.Report(diag::err_target_unsupported_fpmath) 342 << (FPMath == FP_SSE ? "sse" : "387"); 343 return false; 344 } 345 346 SimdDefaultAlign = 347 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 348 return true; 349 } 350 351 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 352 /// definitions for this particular subtarget. 353 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 354 MacroBuilder &Builder) const { 355 // Inline assembly supports X86 flag outputs. 356 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 357 358 std::string CodeModel = getTargetOpts().CodeModel; 359 if (CodeModel == "default") 360 CodeModel = "small"; 361 Builder.defineMacro("__code_model_" + CodeModel + "__"); 362 363 // Target identification. 364 if (getTriple().getArch() == llvm::Triple::x86_64) { 365 Builder.defineMacro("__amd64__"); 366 Builder.defineMacro("__amd64"); 367 Builder.defineMacro("__x86_64"); 368 Builder.defineMacro("__x86_64__"); 369 if (getTriple().getArchName() == "x86_64h") { 370 Builder.defineMacro("__x86_64h"); 371 Builder.defineMacro("__x86_64h__"); 372 } 373 } else { 374 DefineStd(Builder, "i386", Opts); 375 } 376 377 Builder.defineMacro("__SEG_GS"); 378 Builder.defineMacro("__SEG_FS"); 379 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 380 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 381 382 // Subtarget options. 383 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 384 // truly should be based on -mtune options. 385 using namespace llvm::X86; 386 switch (CPU) { 387 case CK_None: 388 break; 389 case CK_i386: 390 // The rest are coming from the i386 define above. 391 Builder.defineMacro("__tune_i386__"); 392 break; 393 case CK_i486: 394 case CK_WinChipC6: 395 case CK_WinChip2: 396 case CK_C3: 397 defineCPUMacros(Builder, "i486"); 398 break; 399 case CK_PentiumMMX: 400 Builder.defineMacro("__pentium_mmx__"); 401 Builder.defineMacro("__tune_pentium_mmx__"); 402 LLVM_FALLTHROUGH; 403 case CK_i586: 404 case CK_Pentium: 405 defineCPUMacros(Builder, "i586"); 406 defineCPUMacros(Builder, "pentium"); 407 break; 408 case CK_Pentium3: 409 case CK_PentiumM: 410 Builder.defineMacro("__tune_pentium3__"); 411 LLVM_FALLTHROUGH; 412 case CK_Pentium2: 413 case CK_C3_2: 414 Builder.defineMacro("__tune_pentium2__"); 415 LLVM_FALLTHROUGH; 416 case CK_PentiumPro: 417 case CK_i686: 418 defineCPUMacros(Builder, "i686"); 419 defineCPUMacros(Builder, "pentiumpro"); 420 break; 421 case CK_Pentium4: 422 defineCPUMacros(Builder, "pentium4"); 423 break; 424 case CK_Yonah: 425 case CK_Prescott: 426 case CK_Nocona: 427 defineCPUMacros(Builder, "nocona"); 428 break; 429 case CK_Core2: 430 case CK_Penryn: 431 defineCPUMacros(Builder, "core2"); 432 break; 433 case CK_Bonnell: 434 defineCPUMacros(Builder, "atom"); 435 break; 436 case CK_Silvermont: 437 defineCPUMacros(Builder, "slm"); 438 break; 439 case CK_Goldmont: 440 defineCPUMacros(Builder, "goldmont"); 441 break; 442 case CK_GoldmontPlus: 443 defineCPUMacros(Builder, "goldmont_plus"); 444 break; 445 case CK_Tremont: 446 defineCPUMacros(Builder, "tremont"); 447 break; 448 case CK_Nehalem: 449 case CK_Westmere: 450 case CK_SandyBridge: 451 case CK_IvyBridge: 452 case CK_Haswell: 453 case CK_Broadwell: 454 case CK_SkylakeClient: 455 case CK_SkylakeServer: 456 case CK_Cascadelake: 457 case CK_Cooperlake: 458 case CK_Cannonlake: 459 case CK_IcelakeClient: 460 case CK_IcelakeServer: 461 case CK_Tigerlake: 462 case CK_SapphireRapids: 463 // FIXME: Historically, we defined this legacy name, it would be nice to 464 // remove it at some point. We've never exposed fine-grained names for 465 // recent primary x86 CPUs, and we should keep it that way. 466 defineCPUMacros(Builder, "corei7"); 467 break; 468 case CK_KNL: 469 defineCPUMacros(Builder, "knl"); 470 break; 471 case CK_KNM: 472 break; 473 case CK_Lakemont: 474 defineCPUMacros(Builder, "i586", /*Tuning*/false); 475 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 476 Builder.defineMacro("__tune_lakemont__"); 477 break; 478 case CK_K6_2: 479 Builder.defineMacro("__k6_2__"); 480 Builder.defineMacro("__tune_k6_2__"); 481 LLVM_FALLTHROUGH; 482 case CK_K6_3: 483 if (CPU != CK_K6_2) { // In case of fallthrough 484 // FIXME: GCC may be enabling these in cases where some other k6 485 // architecture is specified but -m3dnow is explicitly provided. The 486 // exact semantics need to be determined and emulated here. 487 Builder.defineMacro("__k6_3__"); 488 Builder.defineMacro("__tune_k6_3__"); 489 } 490 LLVM_FALLTHROUGH; 491 case CK_K6: 492 defineCPUMacros(Builder, "k6"); 493 break; 494 case CK_Athlon: 495 case CK_AthlonXP: 496 defineCPUMacros(Builder, "athlon"); 497 if (SSELevel != NoSSE) { 498 Builder.defineMacro("__athlon_sse__"); 499 Builder.defineMacro("__tune_athlon_sse__"); 500 } 501 break; 502 case CK_K8: 503 case CK_K8SSE3: 504 case CK_x86_64: 505 defineCPUMacros(Builder, "k8"); 506 break; 507 case CK_AMDFAM10: 508 defineCPUMacros(Builder, "amdfam10"); 509 break; 510 case CK_BTVER1: 511 defineCPUMacros(Builder, "btver1"); 512 break; 513 case CK_BTVER2: 514 defineCPUMacros(Builder, "btver2"); 515 break; 516 case CK_BDVER1: 517 defineCPUMacros(Builder, "bdver1"); 518 break; 519 case CK_BDVER2: 520 defineCPUMacros(Builder, "bdver2"); 521 break; 522 case CK_BDVER3: 523 defineCPUMacros(Builder, "bdver3"); 524 break; 525 case CK_BDVER4: 526 defineCPUMacros(Builder, "bdver4"); 527 break; 528 case CK_ZNVER1: 529 defineCPUMacros(Builder, "znver1"); 530 break; 531 case CK_ZNVER2: 532 defineCPUMacros(Builder, "znver2"); 533 break; 534 case CK_Geode: 535 defineCPUMacros(Builder, "geode"); 536 break; 537 } 538 539 // Target properties. 540 Builder.defineMacro("__REGISTER_PREFIX__", ""); 541 542 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 543 // functions in glibc header files that use FP Stack inline asm which the 544 // backend can't deal with (PR879). 545 Builder.defineMacro("__NO_MATH_INLINES"); 546 547 if (HasAES) 548 Builder.defineMacro("__AES__"); 549 550 if (HasVAES) 551 Builder.defineMacro("__VAES__"); 552 553 if (HasPCLMUL) 554 Builder.defineMacro("__PCLMUL__"); 555 556 if (HasVPCLMULQDQ) 557 Builder.defineMacro("__VPCLMULQDQ__"); 558 559 if (HasLZCNT) 560 Builder.defineMacro("__LZCNT__"); 561 562 if (HasRDRND) 563 Builder.defineMacro("__RDRND__"); 564 565 if (HasFSGSBASE) 566 Builder.defineMacro("__FSGSBASE__"); 567 568 if (HasBMI) 569 Builder.defineMacro("__BMI__"); 570 571 if (HasBMI2) 572 Builder.defineMacro("__BMI2__"); 573 574 if (HasPOPCNT) 575 Builder.defineMacro("__POPCNT__"); 576 577 if (HasRTM) 578 Builder.defineMacro("__RTM__"); 579 580 if (HasPRFCHW) 581 Builder.defineMacro("__PRFCHW__"); 582 583 if (HasRDSEED) 584 Builder.defineMacro("__RDSEED__"); 585 586 if (HasADX) 587 Builder.defineMacro("__ADX__"); 588 589 if (HasTBM) 590 Builder.defineMacro("__TBM__"); 591 592 if (HasLWP) 593 Builder.defineMacro("__LWP__"); 594 595 if (HasMWAITX) 596 Builder.defineMacro("__MWAITX__"); 597 598 if (HasMOVBE) 599 Builder.defineMacro("__MOVBE__"); 600 601 switch (XOPLevel) { 602 case XOP: 603 Builder.defineMacro("__XOP__"); 604 LLVM_FALLTHROUGH; 605 case FMA4: 606 Builder.defineMacro("__FMA4__"); 607 LLVM_FALLTHROUGH; 608 case SSE4A: 609 Builder.defineMacro("__SSE4A__"); 610 LLVM_FALLTHROUGH; 611 case NoXOP: 612 break; 613 } 614 615 if (HasFMA) 616 Builder.defineMacro("__FMA__"); 617 618 if (HasF16C) 619 Builder.defineMacro("__F16C__"); 620 621 if (HasGFNI) 622 Builder.defineMacro("__GFNI__"); 623 624 if (HasAVX512CD) 625 Builder.defineMacro("__AVX512CD__"); 626 if (HasAVX512VPOPCNTDQ) 627 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 628 if (HasAVX512VNNI) 629 Builder.defineMacro("__AVX512VNNI__"); 630 if (HasAVX512BF16) 631 Builder.defineMacro("__AVX512BF16__"); 632 if (HasAVX512ER) 633 Builder.defineMacro("__AVX512ER__"); 634 if (HasAVX512PF) 635 Builder.defineMacro("__AVX512PF__"); 636 if (HasAVX512DQ) 637 Builder.defineMacro("__AVX512DQ__"); 638 if (HasAVX512BITALG) 639 Builder.defineMacro("__AVX512BITALG__"); 640 if (HasAVX512BW) 641 Builder.defineMacro("__AVX512BW__"); 642 if (HasAVX512VL) 643 Builder.defineMacro("__AVX512VL__"); 644 if (HasAVX512VBMI) 645 Builder.defineMacro("__AVX512VBMI__"); 646 if (HasAVX512VBMI2) 647 Builder.defineMacro("__AVX512VBMI2__"); 648 if (HasAVX512IFMA) 649 Builder.defineMacro("__AVX512IFMA__"); 650 if (HasAVX512VP2INTERSECT) 651 Builder.defineMacro("__AVX512VP2INTERSECT__"); 652 if (HasSHA) 653 Builder.defineMacro("__SHA__"); 654 655 if (HasFXSR) 656 Builder.defineMacro("__FXSR__"); 657 if (HasXSAVE) 658 Builder.defineMacro("__XSAVE__"); 659 if (HasXSAVEOPT) 660 Builder.defineMacro("__XSAVEOPT__"); 661 if (HasXSAVEC) 662 Builder.defineMacro("__XSAVEC__"); 663 if (HasXSAVES) 664 Builder.defineMacro("__XSAVES__"); 665 if (HasPKU) 666 Builder.defineMacro("__PKU__"); 667 if (HasCLFLUSHOPT) 668 Builder.defineMacro("__CLFLUSHOPT__"); 669 if (HasCLWB) 670 Builder.defineMacro("__CLWB__"); 671 if (HasWBNOINVD) 672 Builder.defineMacro("__WBNOINVD__"); 673 if (HasSHSTK) 674 Builder.defineMacro("__SHSTK__"); 675 if (HasSGX) 676 Builder.defineMacro("__SGX__"); 677 if (HasPREFETCHWT1) 678 Builder.defineMacro("__PREFETCHWT1__"); 679 if (HasCLZERO) 680 Builder.defineMacro("__CLZERO__"); 681 if (HasRDPID) 682 Builder.defineMacro("__RDPID__"); 683 if (HasCLDEMOTE) 684 Builder.defineMacro("__CLDEMOTE__"); 685 if (HasWAITPKG) 686 Builder.defineMacro("__WAITPKG__"); 687 if (HasMOVDIRI) 688 Builder.defineMacro("__MOVDIRI__"); 689 if (HasMOVDIR64B) 690 Builder.defineMacro("__MOVDIR64B__"); 691 if (HasPCONFIG) 692 Builder.defineMacro("__PCONFIG__"); 693 if (HasPTWRITE) 694 Builder.defineMacro("__PTWRITE__"); 695 if (HasINVPCID) 696 Builder.defineMacro("__INVPCID__"); 697 if (HasENQCMD) 698 Builder.defineMacro("__ENQCMD__"); 699 if (HasAMXTILE) 700 Builder.defineMacro("__AMXTILE__"); 701 if (HasAMXINT8) 702 Builder.defineMacro("__AMXINT8__"); 703 if (HasAMXBF16) 704 Builder.defineMacro("__AMXBF16__"); 705 if (HasSERIALIZE) 706 Builder.defineMacro("__SERIALIZE__"); 707 if (HasTSXLDTRK) 708 Builder.defineMacro("__TSXLDTRK__"); 709 710 // Each case falls through to the previous one here. 711 switch (SSELevel) { 712 case AVX512F: 713 Builder.defineMacro("__AVX512F__"); 714 LLVM_FALLTHROUGH; 715 case AVX2: 716 Builder.defineMacro("__AVX2__"); 717 LLVM_FALLTHROUGH; 718 case AVX: 719 Builder.defineMacro("__AVX__"); 720 LLVM_FALLTHROUGH; 721 case SSE42: 722 Builder.defineMacro("__SSE4_2__"); 723 LLVM_FALLTHROUGH; 724 case SSE41: 725 Builder.defineMacro("__SSE4_1__"); 726 LLVM_FALLTHROUGH; 727 case SSSE3: 728 Builder.defineMacro("__SSSE3__"); 729 LLVM_FALLTHROUGH; 730 case SSE3: 731 Builder.defineMacro("__SSE3__"); 732 LLVM_FALLTHROUGH; 733 case SSE2: 734 Builder.defineMacro("__SSE2__"); 735 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 736 LLVM_FALLTHROUGH; 737 case SSE1: 738 Builder.defineMacro("__SSE__"); 739 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 740 LLVM_FALLTHROUGH; 741 case NoSSE: 742 break; 743 } 744 745 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 746 switch (SSELevel) { 747 case AVX512F: 748 case AVX2: 749 case AVX: 750 case SSE42: 751 case SSE41: 752 case SSSE3: 753 case SSE3: 754 case SSE2: 755 Builder.defineMacro("_M_IX86_FP", Twine(2)); 756 break; 757 case SSE1: 758 Builder.defineMacro("_M_IX86_FP", Twine(1)); 759 break; 760 default: 761 Builder.defineMacro("_M_IX86_FP", Twine(0)); 762 break; 763 } 764 } 765 766 // Each case falls through to the previous one here. 767 switch (MMX3DNowLevel) { 768 case AMD3DNowAthlon: 769 Builder.defineMacro("__3dNOW_A__"); 770 LLVM_FALLTHROUGH; 771 case AMD3DNow: 772 Builder.defineMacro("__3dNOW__"); 773 LLVM_FALLTHROUGH; 774 case MMX: 775 Builder.defineMacro("__MMX__"); 776 LLVM_FALLTHROUGH; 777 case NoMMX3DNow: 778 break; 779 } 780 781 if (CPU >= CK_i486 || CPU == CK_None) { 782 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 783 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 784 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 785 } 786 if (HasCX8) 787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 788 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 789 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 790 791 if (HasFloat128) 792 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 793 } 794 795 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 796 return llvm::StringSwitch<bool>(Name) 797 .Case("3dnow", true) 798 .Case("3dnowa", true) 799 .Case("adx", true) 800 .Case("aes", true) 801 .Case("amx-bf16", true) 802 .Case("amx-int8", true) 803 .Case("amx-tile", true) 804 .Case("avx", true) 805 .Case("avx2", true) 806 .Case("avx512f", true) 807 .Case("avx512cd", true) 808 .Case("avx512vpopcntdq", true) 809 .Case("avx512vnni", true) 810 .Case("avx512bf16", true) 811 .Case("avx512er", true) 812 .Case("avx512pf", true) 813 .Case("avx512dq", true) 814 .Case("avx512bitalg", true) 815 .Case("avx512bw", true) 816 .Case("avx512vl", true) 817 .Case("avx512vbmi", true) 818 .Case("avx512vbmi2", true) 819 .Case("avx512ifma", true) 820 .Case("avx512vp2intersect", true) 821 .Case("bmi", true) 822 .Case("bmi2", true) 823 .Case("cldemote", true) 824 .Case("clflushopt", true) 825 .Case("clwb", true) 826 .Case("clzero", true) 827 .Case("cx16", true) 828 .Case("enqcmd", true) 829 .Case("f16c", true) 830 .Case("fma", true) 831 .Case("fma4", true) 832 .Case("fsgsbase", true) 833 .Case("fxsr", true) 834 .Case("gfni", true) 835 .Case("invpcid", true) 836 .Case("lwp", true) 837 .Case("lzcnt", true) 838 .Case("mmx", true) 839 .Case("movbe", true) 840 .Case("movdiri", true) 841 .Case("movdir64b", true) 842 .Case("mwaitx", true) 843 .Case("pclmul", true) 844 .Case("pconfig", true) 845 .Case("pku", true) 846 .Case("popcnt", true) 847 .Case("prefetchwt1", true) 848 .Case("prfchw", true) 849 .Case("ptwrite", true) 850 .Case("rdpid", true) 851 .Case("rdrnd", true) 852 .Case("rdseed", true) 853 .Case("rtm", true) 854 .Case("sahf", true) 855 .Case("serialize", true) 856 .Case("sgx", true) 857 .Case("sha", true) 858 .Case("shstk", true) 859 .Case("sse", true) 860 .Case("sse2", true) 861 .Case("sse3", true) 862 .Case("ssse3", true) 863 .Case("sse4", true) 864 .Case("sse4.1", true) 865 .Case("sse4.2", true) 866 .Case("sse4a", true) 867 .Case("tbm", true) 868 .Case("tsxldtrk", true) 869 .Case("vaes", true) 870 .Case("vpclmulqdq", true) 871 .Case("wbnoinvd", true) 872 .Case("waitpkg", true) 873 .Case("x87", true) 874 .Case("xop", true) 875 .Case("xsave", true) 876 .Case("xsavec", true) 877 .Case("xsaves", true) 878 .Case("xsaveopt", true) 879 .Default(false); 880 } 881 882 bool X86TargetInfo::hasFeature(StringRef Feature) const { 883 return llvm::StringSwitch<bool>(Feature) 884 .Case("adx", HasADX) 885 .Case("aes", HasAES) 886 .Case("amx-bf16", HasAMXBF16) 887 .Case("amx-int8", HasAMXINT8) 888 .Case("amx-tile", HasAMXTILE) 889 .Case("avx", SSELevel >= AVX) 890 .Case("avx2", SSELevel >= AVX2) 891 .Case("avx512f", SSELevel >= AVX512F) 892 .Case("avx512cd", HasAVX512CD) 893 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 894 .Case("avx512vnni", HasAVX512VNNI) 895 .Case("avx512bf16", HasAVX512BF16) 896 .Case("avx512er", HasAVX512ER) 897 .Case("avx512pf", HasAVX512PF) 898 .Case("avx512dq", HasAVX512DQ) 899 .Case("avx512bitalg", HasAVX512BITALG) 900 .Case("avx512bw", HasAVX512BW) 901 .Case("avx512vl", HasAVX512VL) 902 .Case("avx512vbmi", HasAVX512VBMI) 903 .Case("avx512vbmi2", HasAVX512VBMI2) 904 .Case("avx512ifma", HasAVX512IFMA) 905 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 906 .Case("bmi", HasBMI) 907 .Case("bmi2", HasBMI2) 908 .Case("cldemote", HasCLDEMOTE) 909 .Case("clflushopt", HasCLFLUSHOPT) 910 .Case("clwb", HasCLWB) 911 .Case("clzero", HasCLZERO) 912 .Case("cx8", HasCX8) 913 .Case("cx16", HasCX16) 914 .Case("enqcmd", HasENQCMD) 915 .Case("f16c", HasF16C) 916 .Case("fma", HasFMA) 917 .Case("fma4", XOPLevel >= FMA4) 918 .Case("fsgsbase", HasFSGSBASE) 919 .Case("fxsr", HasFXSR) 920 .Case("gfni", HasGFNI) 921 .Case("invpcid", HasINVPCID) 922 .Case("lwp", HasLWP) 923 .Case("lzcnt", HasLZCNT) 924 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 925 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 926 .Case("mmx", MMX3DNowLevel >= MMX) 927 .Case("movbe", HasMOVBE) 928 .Case("movdiri", HasMOVDIRI) 929 .Case("movdir64b", HasMOVDIR64B) 930 .Case("mwaitx", HasMWAITX) 931 .Case("pclmul", HasPCLMUL) 932 .Case("pconfig", HasPCONFIG) 933 .Case("pku", HasPKU) 934 .Case("popcnt", HasPOPCNT) 935 .Case("prefetchwt1", HasPREFETCHWT1) 936 .Case("prfchw", HasPRFCHW) 937 .Case("ptwrite", HasPTWRITE) 938 .Case("rdpid", HasRDPID) 939 .Case("rdrnd", HasRDRND) 940 .Case("rdseed", HasRDSEED) 941 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 942 .Case("rtm", HasRTM) 943 .Case("sahf", HasLAHFSAHF) 944 .Case("serialize", HasSERIALIZE) 945 .Case("sgx", HasSGX) 946 .Case("sha", HasSHA) 947 .Case("shstk", HasSHSTK) 948 .Case("sse", SSELevel >= SSE1) 949 .Case("sse2", SSELevel >= SSE2) 950 .Case("sse3", SSELevel >= SSE3) 951 .Case("ssse3", SSELevel >= SSSE3) 952 .Case("sse4.1", SSELevel >= SSE41) 953 .Case("sse4.2", SSELevel >= SSE42) 954 .Case("sse4a", XOPLevel >= SSE4A) 955 .Case("tbm", HasTBM) 956 .Case("tsxldtrk", HasTSXLDTRK) 957 .Case("vaes", HasVAES) 958 .Case("vpclmulqdq", HasVPCLMULQDQ) 959 .Case("wbnoinvd", HasWBNOINVD) 960 .Case("waitpkg", HasWAITPKG) 961 .Case("x86", true) 962 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 963 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 964 .Case("xop", XOPLevel >= XOP) 965 .Case("xsave", HasXSAVE) 966 .Case("xsavec", HasXSAVEC) 967 .Case("xsaves", HasXSAVES) 968 .Case("xsaveopt", HasXSAVEOPT) 969 .Default(false); 970 } 971 972 // We can't use a generic validation scheme for the features accepted here 973 // versus subtarget features accepted in the target attribute because the 974 // bitfield structure that's initialized in the runtime only supports the 975 // below currently rather than the full range of subtarget features. (See 976 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 977 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 978 return llvm::StringSwitch<bool>(FeatureStr) 979 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true) 980 #include "llvm/Support/X86TargetParser.def" 981 .Default(false); 982 } 983 984 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 985 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 986 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM) 987 #include "llvm/Support/X86TargetParser.def" 988 ; 989 // Note, this function should only be used after ensuring the value is 990 // correct, so it asserts if the value is out of range. 991 } 992 993 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { 994 enum class FeatPriority { 995 #define FEATURE(FEAT) FEAT, 996 #include "clang/Basic/X86Target.def" 997 }; 998 switch (Feat) { 999 #define FEATURE(FEAT) \ 1000 case llvm::X86::FEAT: \ 1001 return static_cast<unsigned>(FeatPriority::FEAT); 1002 #include "clang/Basic/X86Target.def" 1003 default: 1004 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 1005 } 1006 } 1007 1008 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1009 // Valid CPUs have a 'key feature' that compares just better than its key 1010 // feature. 1011 using namespace llvm::X86; 1012 CPUKind Kind = parseArchX86(Name); 1013 if (Kind != CK_None) { 1014 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1015 return (getFeaturePriority(KeyFeature) << 1) + 1; 1016 } 1017 1018 // Now we know we have a feature, so get its priority and shift it a few so 1019 // that we have sufficient room for the CPUs (above). 1020 return getFeaturePriority(getFeature(Name)) << 1; 1021 } 1022 1023 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1024 return llvm::StringSwitch<bool>(Name) 1025 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) 1026 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) 1027 #include "clang/Basic/X86Target.def" 1028 .Default(false); 1029 } 1030 1031 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1032 return llvm::StringSwitch<StringRef>(Name) 1033 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) 1034 #include "clang/Basic/X86Target.def" 1035 .Default(Name); 1036 } 1037 1038 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1039 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1040 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1041 #include "clang/Basic/X86Target.def" 1042 .Default(0); 1043 } 1044 1045 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1046 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1047 StringRef WholeList = 1048 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1049 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1050 #include "clang/Basic/X86Target.def" 1051 .Default(""); 1052 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1053 } 1054 1055 // We can't use a generic validation scheme for the cpus accepted here 1056 // versus subtarget cpus accepted in the target attribute because the 1057 // variables intitialized by the runtime only support the below currently 1058 // rather than the full range of cpus. 1059 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1060 return llvm::StringSwitch<bool>(FeatureStr) 1061 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1062 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1063 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1064 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1065 #include "llvm/Support/X86TargetParser.def" 1066 .Default(false); 1067 } 1068 1069 static unsigned matchAsmCCConstraint(const char *&Name) { 1070 auto RV = llvm::StringSwitch<unsigned>(Name) 1071 .Case("@cca", 4) 1072 .Case("@ccae", 5) 1073 .Case("@ccb", 4) 1074 .Case("@ccbe", 5) 1075 .Case("@ccc", 4) 1076 .Case("@cce", 4) 1077 .Case("@ccz", 4) 1078 .Case("@ccg", 4) 1079 .Case("@ccge", 5) 1080 .Case("@ccl", 4) 1081 .Case("@ccle", 5) 1082 .Case("@ccna", 5) 1083 .Case("@ccnae", 6) 1084 .Case("@ccnb", 5) 1085 .Case("@ccnbe", 6) 1086 .Case("@ccnc", 5) 1087 .Case("@ccne", 5) 1088 .Case("@ccnz", 5) 1089 .Case("@ccng", 5) 1090 .Case("@ccnge", 6) 1091 .Case("@ccnl", 5) 1092 .Case("@ccnle", 6) 1093 .Case("@ccno", 5) 1094 .Case("@ccnp", 5) 1095 .Case("@ccns", 5) 1096 .Case("@cco", 4) 1097 .Case("@ccp", 4) 1098 .Case("@ccs", 4) 1099 .Default(0); 1100 return RV; 1101 } 1102 1103 bool X86TargetInfo::validateAsmConstraint( 1104 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1105 switch (*Name) { 1106 default: 1107 return false; 1108 // Constant constraints. 1109 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1110 // instructions. 1111 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1112 // x86_64 instructions. 1113 case 's': 1114 Info.setRequiresImmediate(); 1115 return true; 1116 case 'I': 1117 Info.setRequiresImmediate(0, 31); 1118 return true; 1119 case 'J': 1120 Info.setRequiresImmediate(0, 63); 1121 return true; 1122 case 'K': 1123 Info.setRequiresImmediate(-128, 127); 1124 return true; 1125 case 'L': 1126 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1127 return true; 1128 case 'M': 1129 Info.setRequiresImmediate(0, 3); 1130 return true; 1131 case 'N': 1132 Info.setRequiresImmediate(0, 255); 1133 return true; 1134 case 'O': 1135 Info.setRequiresImmediate(0, 127); 1136 return true; 1137 // Register constraints. 1138 case 'Y': // 'Y' is the first character for several 2-character constraints. 1139 // Shift the pointer to the second character of the constraint. 1140 Name++; 1141 switch (*Name) { 1142 default: 1143 return false; 1144 case 'z': // First SSE register. 1145 case '2': 1146 case 't': // Any SSE register, when SSE2 is enabled. 1147 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1148 case 'm': // Any MMX register, when inter-unit moves enabled. 1149 case 'k': // AVX512 arch mask registers: k1-k7. 1150 Info.setAllowsRegister(); 1151 return true; 1152 } 1153 case 'f': // Any x87 floating point stack register. 1154 // Constraint 'f' cannot be used for output operands. 1155 if (Info.ConstraintStr[0] == '=') 1156 return false; 1157 Info.setAllowsRegister(); 1158 return true; 1159 case 'a': // eax. 1160 case 'b': // ebx. 1161 case 'c': // ecx. 1162 case 'd': // edx. 1163 case 'S': // esi. 1164 case 'D': // edi. 1165 case 'A': // edx:eax. 1166 case 't': // Top of floating point stack. 1167 case 'u': // Second from top of floating point stack. 1168 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1169 case 'y': // Any MMX register. 1170 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1171 case 'x': // Any SSE register. 1172 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1173 // for intermideate k reg operations). 1174 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1175 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1176 case 'l': // "Index" registers: any general register that can be used as an 1177 // index in a base+index memory access. 1178 Info.setAllowsRegister(); 1179 return true; 1180 // Floating point constant constraints. 1181 case 'C': // SSE floating point constant. 1182 case 'G': // x87 floating point constant. 1183 return true; 1184 case '@': 1185 // CC condition changes. 1186 if (auto Len = matchAsmCCConstraint(Name)) { 1187 Name += Len - 1; 1188 Info.setAllowsRegister(); 1189 return true; 1190 } 1191 return false; 1192 } 1193 } 1194 1195 // Below is based on the following information: 1196 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1197 // | Processor Name | Cache Line Size (Bytes) | Source | 1198 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1199 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1200 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1201 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1202 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1203 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1204 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1205 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1206 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1207 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1208 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1209 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1210 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1211 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1212 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1213 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1214 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1215 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1216 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1217 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1218 using namespace llvm::X86; 1219 switch (CPU) { 1220 // i386 1221 case CK_i386: 1222 // i486 1223 case CK_i486: 1224 case CK_WinChipC6: 1225 case CK_WinChip2: 1226 case CK_C3: 1227 // Lakemont 1228 case CK_Lakemont: 1229 return 16; 1230 1231 // i586 1232 case CK_i586: 1233 case CK_Pentium: 1234 case CK_PentiumMMX: 1235 // i686 1236 case CK_PentiumPro: 1237 case CK_i686: 1238 case CK_Pentium2: 1239 case CK_Pentium3: 1240 case CK_PentiumM: 1241 case CK_C3_2: 1242 // K6 1243 case CK_K6: 1244 case CK_K6_2: 1245 case CK_K6_3: 1246 // Geode 1247 case CK_Geode: 1248 return 32; 1249 1250 // Netburst 1251 case CK_Pentium4: 1252 case CK_Prescott: 1253 case CK_Nocona: 1254 // Atom 1255 case CK_Bonnell: 1256 case CK_Silvermont: 1257 case CK_Goldmont: 1258 case CK_GoldmontPlus: 1259 case CK_Tremont: 1260 1261 case CK_Westmere: 1262 case CK_SandyBridge: 1263 case CK_IvyBridge: 1264 case CK_Haswell: 1265 case CK_Broadwell: 1266 case CK_SkylakeClient: 1267 case CK_SkylakeServer: 1268 case CK_Cascadelake: 1269 case CK_Nehalem: 1270 case CK_Cooperlake: 1271 case CK_Cannonlake: 1272 case CK_Tigerlake: 1273 case CK_SapphireRapids: 1274 case CK_IcelakeClient: 1275 case CK_IcelakeServer: 1276 case CK_KNL: 1277 case CK_KNM: 1278 // K7 1279 case CK_Athlon: 1280 case CK_AthlonXP: 1281 // K8 1282 case CK_K8: 1283 case CK_K8SSE3: 1284 case CK_AMDFAM10: 1285 // Bobcat 1286 case CK_BTVER1: 1287 case CK_BTVER2: 1288 // Bulldozer 1289 case CK_BDVER1: 1290 case CK_BDVER2: 1291 case CK_BDVER3: 1292 case CK_BDVER4: 1293 // Zen 1294 case CK_ZNVER1: 1295 case CK_ZNVER2: 1296 // Deprecated 1297 case CK_x86_64: 1298 case CK_Yonah: 1299 case CK_Penryn: 1300 case CK_Core2: 1301 return 64; 1302 1303 // The following currently have unknown cache line sizes (but they are probably all 64): 1304 // Core 1305 case CK_None: 1306 return None; 1307 } 1308 llvm_unreachable("Unknown CPU kind"); 1309 } 1310 1311 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1312 StringRef Constraint, 1313 unsigned Size) const { 1314 // Strip off constraint modifiers. 1315 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1316 Constraint = Constraint.substr(1); 1317 1318 return validateOperandSize(FeatureMap, Constraint, Size); 1319 } 1320 1321 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1322 StringRef Constraint, 1323 unsigned Size) const { 1324 return validateOperandSize(FeatureMap, Constraint, Size); 1325 } 1326 1327 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1328 StringRef Constraint, 1329 unsigned Size) const { 1330 switch (Constraint[0]) { 1331 default: 1332 break; 1333 case 'k': 1334 // Registers k0-k7 (AVX512) size limit is 64 bit. 1335 case 'y': 1336 return Size <= 64; 1337 case 'f': 1338 case 't': 1339 case 'u': 1340 return Size <= 128; 1341 case 'Y': 1342 // 'Y' is the first character for several 2-character constraints. 1343 switch (Constraint[1]) { 1344 default: 1345 return false; 1346 case 'm': 1347 // 'Ym' is synonymous with 'y'. 1348 case 'k': 1349 return Size <= 64; 1350 case 'z': 1351 // XMM0/YMM/ZMM0 1352 if (FeatureMap.lookup("avx512f")) 1353 // ZMM0 can be used if target supports AVX512F. 1354 return Size <= 512U; 1355 else if (FeatureMap.lookup("avx")) 1356 // YMM0 can be used if target supports AVX. 1357 return Size <= 256U; 1358 else if (FeatureMap.lookup("sse")) 1359 return Size <= 128U; 1360 return false; 1361 case 'i': 1362 case 't': 1363 case '2': 1364 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1365 if (SSELevel < SSE2) 1366 return false; 1367 break; 1368 } 1369 break; 1370 case 'v': 1371 case 'x': 1372 if (FeatureMap.lookup("avx512f")) 1373 // 512-bit zmm registers can be used if target supports AVX512F. 1374 return Size <= 512U; 1375 else if (FeatureMap.lookup("avx")) 1376 // 256-bit ymm registers can be used if target supports AVX. 1377 return Size <= 256U; 1378 return Size <= 128U; 1379 1380 } 1381 1382 return true; 1383 } 1384 1385 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1386 switch (*Constraint) { 1387 case '@': 1388 if (auto Len = matchAsmCCConstraint(Constraint)) { 1389 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1390 Constraint += Len - 1; 1391 return Converted; 1392 } 1393 return std::string(1, *Constraint); 1394 case 'a': 1395 return std::string("{ax}"); 1396 case 'b': 1397 return std::string("{bx}"); 1398 case 'c': 1399 return std::string("{cx}"); 1400 case 'd': 1401 return std::string("{dx}"); 1402 case 'S': 1403 return std::string("{si}"); 1404 case 'D': 1405 return std::string("{di}"); 1406 case 'p': // address 1407 return std::string("im"); 1408 case 't': // top of floating point stack. 1409 return std::string("{st}"); 1410 case 'u': // second from top of floating point stack. 1411 return std::string("{st(1)}"); // second from top of floating point stack. 1412 case 'Y': 1413 switch (Constraint[1]) { 1414 default: 1415 // Break from inner switch and fall through (copy single char), 1416 // continue parsing after copying the current constraint into 1417 // the return string. 1418 break; 1419 case 'k': 1420 case 'm': 1421 case 'i': 1422 case 't': 1423 case 'z': 1424 case '2': 1425 // "^" hints llvm that this is a 2 letter constraint. 1426 // "Constraint++" is used to promote the string iterator 1427 // to the next constraint. 1428 return std::string("^") + std::string(Constraint++, 2); 1429 } 1430 LLVM_FALLTHROUGH; 1431 default: 1432 return std::string(1, *Constraint); 1433 } 1434 } 1435 1436 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1437 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1438 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1439 } 1440 1441 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1442 llvm::X86::fillValidCPUArchList(Values); 1443 } 1444 1445 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1446 return llvm::makeArrayRef(GCCRegNames); 1447 } 1448 1449 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1450 return llvm::makeArrayRef(AddlRegNames); 1451 } 1452 1453 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1454 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1455 Builtin::FirstTSBuiltin + 1); 1456 } 1457 1458 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1459 return llvm::makeArrayRef(BuiltinInfoX86, 1460 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1461 } 1462