1 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements RISCV TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCV.h"
14 #include "clang/Basic/MacroBuilder.h"
15 #include "llvm/ADT/StringSwitch.h"
16 
17 using namespace clang;
18 using namespace clang::targets;
19 
20 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
21   static const char *const GCCRegNames[] = {
22       "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
23       "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
24       "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
25       "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
26   return llvm::makeArrayRef(GCCRegNames);
27 }
28 
29 ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
30   static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
31       {{"zero"}, "x0"}, {{"ra"}, "x1"},  {{"sp"}, "x2"},   {{"gp"}, "x3"},
32       {{"tp"}, "x4"},   {{"t0"}, "x5"},  {{"t1"}, "x6"},   {{"t2"}, "x7"},
33       {{"s0"}, "x8"},   {{"s1"}, "x9"},  {{"a0"}, "x10"},  {{"a1"}, "x11"},
34       {{"a2"}, "x12"},  {{"a3"}, "x13"}, {{"a4"}, "x14"},  {{"a5"}, "x15"},
35       {{"a6"}, "x16"},  {{"a7"}, "x17"}, {{"s2"}, "x18"},  {{"s3"}, "x19"},
36       {{"s4"}, "x20"},  {{"s5"}, "x21"}, {{"s6"}, "x22"},  {{"s7"}, "x23"},
37       {{"s8"}, "x24"},  {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
38       {{"t3"}, "x28"},  {{"t4"}, "x29"}, {{"t5"}, "x30"},  {{"t6"}, "x31"}};
39   return llvm::makeArrayRef(GCCRegAliases);
40 }
41 
42 bool RISCVTargetInfo::validateAsmConstraint(
43     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
44   switch (*Name) {
45   default:
46     return false;
47   case 'I':
48     // A 12-bit signed immediate.
49     Info.setRequiresImmediate(-2048, 2047);
50     return true;
51   case 'J':
52     // Integer zero.
53     Info.setRequiresImmediate(0);
54     return true;
55   case 'K':
56     // A 5-bit unsigned immediate for CSR access instructions.
57     Info.setRequiresImmediate(0, 31);
58     return true;
59   }
60 }
61 
62 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
63                                        MacroBuilder &Builder) const {
64   Builder.defineMacro("__ELF__");
65   Builder.defineMacro("__riscv");
66   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
67   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
68   // TODO: modify when more code models and ABIs are supported.
69   Builder.defineMacro("__riscv_cmodel_medlow");
70   Builder.defineMacro("__riscv_float_abi_soft");
71 
72   if (HasM) {
73     Builder.defineMacro("__riscv_mul");
74     Builder.defineMacro("__riscv_div");
75     Builder.defineMacro("__riscv_muldiv");
76   }
77 
78   if (HasA)
79     Builder.defineMacro("__riscv_atomic");
80 
81   if (HasF || HasD) {
82     Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
83     Builder.defineMacro("__riscv_fdiv");
84     Builder.defineMacro("__riscv_fsqrt");
85   }
86 
87   if (HasC)
88     Builder.defineMacro("__riscv_compressed");
89 }
90 
91 /// Return true if has this feature, need to sync with handleTargetFeatures.
92 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
93   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
94   return llvm::StringSwitch<bool>(Feature)
95       .Case("riscv", true)
96       .Case("riscv32", !Is64Bit)
97       .Case("riscv64", Is64Bit)
98       .Case("m", HasM)
99       .Case("a", HasA)
100       .Case("f", HasF)
101       .Case("d", HasD)
102       .Case("c", HasC)
103       .Default(false);
104 }
105 
106 /// Perform initialization based on the user configured set of features.
107 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
108                                            DiagnosticsEngine &Diags) {
109   for (const auto &Feature : Features) {
110     if (Feature == "+m")
111       HasM = true;
112     else if (Feature == "+a")
113       HasA = true;
114     else if (Feature == "+f")
115       HasF = true;
116     else if (Feature == "+d")
117       HasD = true;
118     else if (Feature == "+c")
119       HasC = true;
120   }
121 
122   return true;
123 }
124