1 //===--- PPC.cpp - Implement PPC target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPC.h" 14 #include "clang/Basic/Diagnostic.h" 15 #include "clang/Basic/MacroBuilder.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 18 using namespace clang; 19 using namespace clang::targets; 20 21 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 22 #define BUILTIN(ID, TYPE, ATTRS) \ 23 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 24 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 25 {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr}, 26 #include "clang/Basic/BuiltinsPPC.def" 27 }; 28 29 /// handleTargetFeatures - Perform initialization based on the user 30 /// configured set of features. 31 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 32 DiagnosticsEngine &Diags) { 33 FloatABI = HardFloat; 34 for (const auto &Feature : Features) { 35 if (Feature == "+altivec") { 36 HasAltivec = true; 37 } else if (Feature == "+vsx") { 38 HasVSX = true; 39 } else if (Feature == "+bpermd") { 40 HasBPERMD = true; 41 } else if (Feature == "+extdiv") { 42 HasExtDiv = true; 43 } else if (Feature == "+power8-vector") { 44 HasP8Vector = true; 45 } else if (Feature == "+crypto") { 46 HasP8Crypto = true; 47 } else if (Feature == "+direct-move") { 48 HasDirectMove = true; 49 } else if (Feature == "+htm") { 50 HasHTM = true; 51 } else if (Feature == "+float128") { 52 HasFloat128 = true; 53 } else if (Feature == "+power9-vector") { 54 HasP9Vector = true; 55 } else if (Feature == "+power10-vector") { 56 HasP10Vector = true; 57 } else if (Feature == "+pcrelative-memops") { 58 HasPCRelativeMemops = true; 59 } else if (Feature == "+spe") { 60 HasSPE = true; 61 LongDoubleWidth = LongDoubleAlign = 64; 62 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 63 } else if (Feature == "-hard-float") { 64 FloatABI = SoftFloat; 65 } else if (Feature == "+paired-vector-memops") { 66 PairedVectorMemops = true; 67 } else if (Feature == "+mma") { 68 HasMMA = true; 69 } 70 // TODO: Finish this list and add an assert that we've handled them 71 // all. 72 } 73 74 return true; 75 } 76 77 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 78 /// #defines that are not tied to a specific subtarget. 79 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const { 81 // Target identification. 82 Builder.defineMacro("__ppc__"); 83 Builder.defineMacro("__PPC__"); 84 Builder.defineMacro("_ARCH_PPC"); 85 Builder.defineMacro("__powerpc__"); 86 Builder.defineMacro("__POWERPC__"); 87 if (PointerWidth == 64) { 88 Builder.defineMacro("_ARCH_PPC64"); 89 Builder.defineMacro("__powerpc64__"); 90 Builder.defineMacro("__ppc64__"); 91 Builder.defineMacro("__PPC64__"); 92 } 93 94 // Target properties. 95 if (getTriple().getArch() == llvm::Triple::ppc64le) { 96 Builder.defineMacro("_LITTLE_ENDIAN"); 97 } else { 98 if (!getTriple().isOSNetBSD() && 99 !getTriple().isOSOpenBSD()) 100 Builder.defineMacro("_BIG_ENDIAN"); 101 } 102 103 // ABI options. 104 if (ABI == "elfv1") 105 Builder.defineMacro("_CALL_ELF", "1"); 106 if (ABI == "elfv2") 107 Builder.defineMacro("_CALL_ELF", "2"); 108 109 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 110 // our support post-dates this and it should work on all 64-bit ppc linux 111 // platforms. It is guaranteed to work on all elfv2 platforms. 112 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 113 Builder.defineMacro("_CALL_LINUX", "1"); 114 115 // Subtarget options. 116 if (!getTriple().isOSAIX()){ 117 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 118 } 119 Builder.defineMacro("__REGISTER_PREFIX__", ""); 120 121 // FIXME: Should be controlled by command line option. 122 if (LongDoubleWidth == 128) { 123 Builder.defineMacro("__LONG_DOUBLE_128__"); 124 Builder.defineMacro("__LONGDOUBLE128"); 125 if (Opts.PPCIEEELongDouble) 126 Builder.defineMacro("__LONG_DOUBLE_IEEE128__"); 127 else 128 Builder.defineMacro("__LONG_DOUBLE_IBM128__"); 129 } 130 131 // Define this for elfv2 (64-bit only) or 64-bit darwin. 132 if (ABI == "elfv2" || 133 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 134 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 135 136 if (ArchDefs & ArchDefineName) 137 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 138 if (ArchDefs & ArchDefinePpcgr) 139 Builder.defineMacro("_ARCH_PPCGR"); 140 if (ArchDefs & ArchDefinePpcsq) 141 Builder.defineMacro("_ARCH_PPCSQ"); 142 if (ArchDefs & ArchDefine440) 143 Builder.defineMacro("_ARCH_440"); 144 if (ArchDefs & ArchDefine603) 145 Builder.defineMacro("_ARCH_603"); 146 if (ArchDefs & ArchDefine604) 147 Builder.defineMacro("_ARCH_604"); 148 if (ArchDefs & ArchDefinePwr4) 149 Builder.defineMacro("_ARCH_PWR4"); 150 if (ArchDefs & ArchDefinePwr5) 151 Builder.defineMacro("_ARCH_PWR5"); 152 if (ArchDefs & ArchDefinePwr5x) 153 Builder.defineMacro("_ARCH_PWR5X"); 154 if (ArchDefs & ArchDefinePwr6) 155 Builder.defineMacro("_ARCH_PWR6"); 156 if (ArchDefs & ArchDefinePwr6x) 157 Builder.defineMacro("_ARCH_PWR6X"); 158 if (ArchDefs & ArchDefinePwr7) 159 Builder.defineMacro("_ARCH_PWR7"); 160 if (ArchDefs & ArchDefinePwr8) 161 Builder.defineMacro("_ARCH_PWR8"); 162 if (ArchDefs & ArchDefinePwr9) 163 Builder.defineMacro("_ARCH_PWR9"); 164 if (ArchDefs & ArchDefinePwr10) 165 Builder.defineMacro("_ARCH_PWR10"); 166 if (ArchDefs & ArchDefineA2) 167 Builder.defineMacro("_ARCH_A2"); 168 if (ArchDefs & ArchDefineE500) 169 Builder.defineMacro("__NO_LWSYNC__"); 170 if (ArchDefs & ArchDefineFuture) 171 Builder.defineMacro("_ARCH_PWR_FUTURE"); 172 173 if (HasAltivec) { 174 Builder.defineMacro("__VEC__", "10206"); 175 Builder.defineMacro("__ALTIVEC__"); 176 } 177 if (HasSPE) { 178 Builder.defineMacro("__SPE__"); 179 Builder.defineMacro("__NO_FPRS__"); 180 } 181 if (HasVSX) 182 Builder.defineMacro("__VSX__"); 183 if (HasP8Vector) 184 Builder.defineMacro("__POWER8_VECTOR__"); 185 if (HasP8Crypto) 186 Builder.defineMacro("__CRYPTO__"); 187 if (HasHTM) 188 Builder.defineMacro("__HTM__"); 189 if (HasFloat128) 190 Builder.defineMacro("__FLOAT128__"); 191 if (HasP9Vector) 192 Builder.defineMacro("__POWER9_VECTOR__"); 193 if (HasMMA) 194 Builder.defineMacro("__MMA__"); 195 if (HasP10Vector) 196 Builder.defineMacro("__POWER10_VECTOR__"); 197 198 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 200 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 201 if (PointerWidth == 64) 202 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 203 204 // We have support for the bswap intrinsics so we can define this. 205 Builder.defineMacro("__HAVE_BSWAP__", "1"); 206 207 // FIXME: The following are not yet generated here by Clang, but are 208 // generated by GCC: 209 // 210 // _SOFT_FLOAT_ 211 // __RECIP_PRECISION__ 212 // __APPLE_ALTIVEC__ 213 // __RECIP__ 214 // __RECIPF__ 215 // __RSQRTE__ 216 // __RSQRTEF__ 217 // _SOFT_DOUBLE_ 218 // __NO_LWSYNC__ 219 // __CMODEL_MEDIUM__ 220 // __CMODEL_LARGE__ 221 // _CALL_SYSV 222 // _CALL_DARWIN 223 } 224 225 // Handle explicit options being passed to the compiler here: if we've 226 // explicitly turned off vsx and turned on any of: 227 // - power8-vector 228 // - direct-move 229 // - float128 230 // - power9-vector 231 // - paired-vector-memops 232 // - mma 233 // - power10-vector 234 // then go ahead and error since the customer has expressed an incompatible 235 // set of options. 236 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 237 const std::vector<std::string> &FeaturesVec) { 238 239 // vsx was not explicitly turned off. 240 if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end()) 241 return true; 242 243 auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) { 244 if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) { 245 Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx"; 246 return true; 247 } 248 return false; 249 }; 250 251 bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector"); 252 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move"); 253 Found |= FindVSXSubfeature("+float128", "-mfloat128"); 254 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector"); 255 Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops"); 256 Found |= FindVSXSubfeature("+mma", "-mmma"); 257 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector"); 258 259 // Return false if any vsx subfeatures was found. 260 return !Found; 261 } 262 263 bool PPCTargetInfo::initFeatureMap( 264 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 265 const std::vector<std::string> &FeaturesVec) const { 266 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 267 .Case("7400", true) 268 .Case("g4", true) 269 .Case("7450", true) 270 .Case("g4+", true) 271 .Case("970", true) 272 .Case("g5", true) 273 .Case("pwr6", true) 274 .Case("pwr7", true) 275 .Case("pwr8", true) 276 .Case("pwr9", true) 277 .Case("ppc64", true) 278 .Case("ppc64le", true) 279 .Default(false); 280 281 Features["power9-vector"] = (CPU == "pwr9"); 282 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 283 .Case("ppc64le", true) 284 .Case("pwr9", true) 285 .Case("pwr8", true) 286 .Default(false); 287 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 288 .Case("ppc64le", true) 289 .Case("pwr9", true) 290 .Case("pwr8", true) 291 .Default(false); 292 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 293 .Case("ppc64le", true) 294 .Case("pwr9", true) 295 .Case("pwr8", true) 296 .Case("pwr7", true) 297 .Default(false); 298 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 299 .Case("ppc64le", true) 300 .Case("pwr9", true) 301 .Case("pwr8", true) 302 .Case("pwr7", true) 303 .Default(false); 304 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 305 .Case("ppc64le", true) 306 .Case("pwr9", true) 307 .Case("pwr8", true) 308 .Default(false); 309 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 310 .Case("ppc64le", true) 311 .Case("pwr9", true) 312 .Case("pwr8", true) 313 .Case("pwr7", true) 314 .Default(false); 315 Features["htm"] = llvm::StringSwitch<bool>(CPU) 316 .Case("ppc64le", true) 317 .Case("pwr9", true) 318 .Case("pwr8", true) 319 .Default(false); 320 321 Features["spe"] = llvm::StringSwitch<bool>(CPU) 322 .Case("8548", true) 323 .Case("e500", true) 324 .Default(false); 325 326 // Power10 includes all the same features as Power9 plus any features specific 327 // to the Power10 core. 328 if (CPU == "pwr10" || CPU == "power10") { 329 initFeatureMap(Features, Diags, "pwr9", FeaturesVec); 330 addP10SpecificFeatures(Features); 331 } 332 333 // Future CPU should include all of the features of Power 10 as well as any 334 // additional features (yet to be determined) specific to it. 335 if (CPU == "future") { 336 initFeatureMap(Features, Diags, "pwr10", FeaturesVec); 337 addFutureSpecificFeatures(Features); 338 } 339 340 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 341 return false; 342 343 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && 344 llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { 345 // We have __float128 on PPC but not power 9 and above. 346 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU; 347 return false; 348 } 349 350 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 351 } 352 353 // Add any Power10 specific features. 354 void PPCTargetInfo::addP10SpecificFeatures( 355 llvm::StringMap<bool> &Features) const { 356 Features["htm"] = false; // HTM was removed for P10. 357 Features["paired-vector-memops"] = true; 358 Features["mma"] = true; 359 Features["power10-vector"] = true; 360 Features["pcrelative-memops"] = true; 361 return; 362 } 363 364 // Add features specific to the "Future" CPU. 365 void PPCTargetInfo::addFutureSpecificFeatures( 366 llvm::StringMap<bool> &Features) const { 367 return; 368 } 369 370 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 371 return llvm::StringSwitch<bool>(Feature) 372 .Case("powerpc", true) 373 .Case("altivec", HasAltivec) 374 .Case("vsx", HasVSX) 375 .Case("power8-vector", HasP8Vector) 376 .Case("crypto", HasP8Crypto) 377 .Case("direct-move", HasDirectMove) 378 .Case("htm", HasHTM) 379 .Case("bpermd", HasBPERMD) 380 .Case("extdiv", HasExtDiv) 381 .Case("float128", HasFloat128) 382 .Case("power9-vector", HasP9Vector) 383 .Case("paired-vector-memops", PairedVectorMemops) 384 .Case("power10-vector", HasP10Vector) 385 .Case("pcrelative-memops", HasPCRelativeMemops) 386 .Case("spe", HasSPE) 387 .Case("mma", HasMMA) 388 .Default(false); 389 } 390 391 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 392 StringRef Name, bool Enabled) const { 393 if (Enabled) { 394 // If we're enabling any of the vsx based features then enable vsx and 395 // altivec. We'll diagnose any problems later. 396 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 397 .Case("vsx", true) 398 .Case("direct-move", true) 399 .Case("power8-vector", true) 400 .Case("power9-vector", true) 401 .Case("paired-vector-memops", true) 402 .Case("power10-vector", true) 403 .Case("float128", true) 404 .Case("mma", true) 405 .Default(false); 406 if (FeatureHasVSX) 407 Features["vsx"] = Features["altivec"] = true; 408 if (Name == "power9-vector") 409 Features["power8-vector"] = true; 410 else if (Name == "power10-vector") 411 Features["power8-vector"] = Features["power9-vector"] = true; 412 if (Name == "pcrel") 413 Features["pcrelative-memops"] = true; 414 else 415 Features[Name] = true; 416 } else { 417 // If we're disabling altivec or vsx go ahead and disable all of the vsx 418 // features. 419 if ((Name == "altivec") || (Name == "vsx")) 420 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 421 Features["float128"] = Features["power9-vector"] = 422 Features["paired-vector-memops"] = Features["mma"] = 423 Features["power10-vector"] = false; 424 if (Name == "power8-vector") 425 Features["power9-vector"] = Features["paired-vector-memops"] = 426 Features["mma"] = Features["power10-vector"] = false; 427 else if (Name == "power9-vector") 428 Features["paired-vector-memops"] = Features["mma"] = 429 Features["power10-vector"] = false; 430 if (Name == "pcrel") 431 Features["pcrelative-memops"] = false; 432 else 433 Features[Name] = false; 434 } 435 } 436 437 const char *const PPCTargetInfo::GCCRegNames[] = { 438 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", 439 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", 440 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", 441 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3", 442 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", 443 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", 444 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", 445 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3", 446 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3", 447 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", 448 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 449 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", 450 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp" 451 }; 452 453 ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const { 454 return llvm::makeArrayRef(GCCRegNames); 455 } 456 457 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 458 // While some of these aliases do map to different registers 459 // they still share the same register name. 460 {{"0"}, "r0"}, {{"1"}, "r1"}, {{"2"}, "r2"}, {{"3"}, "r3"}, 461 {{"4"}, "r4"}, {{"5"}, "r5"}, {{"6"}, "r6"}, {{"7"}, "r7"}, 462 {{"8"}, "r8"}, {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"}, 463 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"}, {{"15"}, "r15"}, 464 {{"16"}, "r16"}, {{"17"}, "r17"}, {{"18"}, "r18"}, {{"19"}, "r19"}, 465 {{"20"}, "r20"}, {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"}, 466 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"}, {{"27"}, "r27"}, 467 {{"28"}, "r28"}, {{"29"}, "r29"}, {{"30"}, "r30"}, {{"31"}, "r31"}, 468 {{"fr0"}, "f0"}, {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"}, 469 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"}, {{"fr7"}, "f7"}, 470 {{"fr8"}, "f8"}, {{"fr9"}, "f9"}, {{"fr10"}, "f10"}, {{"fr11"}, "f11"}, 471 {{"fr12"}, "f12"}, {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"}, 472 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, {{"fr19"}, "f19"}, 473 {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"}, 474 {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"}, 475 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"}, 476 {{"cc"}, "cr0"}, 477 }; 478 479 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 480 return llvm::makeArrayRef(GCCRegAliases); 481 } 482 483 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers". 484 // vs0 ~ vs31 is mapping to 32 - 63, 485 // vs32 ~ vs63 is mapping to 77 - 108. 486 const TargetInfo::AddlRegName GCCAddlRegNames[] = { 487 // Table of additional register names to use in user input. 488 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35}, 489 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39}, 490 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43}, 491 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47}, 492 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51}, 493 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55}, 494 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59}, 495 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63}, 496 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80}, 497 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84}, 498 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88}, 499 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92}, 500 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96}, 501 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100}, 502 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104}, 503 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108}, 504 }; 505 506 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const { 507 if (ABI == "elfv2") 508 return llvm::makeArrayRef(GCCAddlRegNames); 509 else 510 return TargetInfo::getGCCAddlRegNames(); 511 } 512 513 static constexpr llvm::StringLiteral ValidCPUNames[] = { 514 {"generic"}, {"440"}, {"450"}, {"601"}, {"602"}, 515 {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"}, 516 {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"}, 517 {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"}, 518 {"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"}, 519 {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"}, 520 {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, 521 {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"}, 522 {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"}, 523 {"powerpc"}, {"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, 524 {"ppc64le"}, {"future"}}; 525 526 bool PPCTargetInfo::isValidCPUName(StringRef Name) const { 527 return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames); 528 } 529 530 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 531 Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames)); 532 } 533 534 void PPCTargetInfo::adjust(LangOptions &Opts) { 535 if (HasAltivec) 536 Opts.AltiVec = 1; 537 TargetInfo::adjust(Opts); 538 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble()) 539 LongDoubleFormat = Opts.PPCIEEELongDouble 540 ? &llvm::APFloat::IEEEquad() 541 : &llvm::APFloat::PPCDoubleDouble(); 542 } 543 544 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const { 545 return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin - 546 Builtin::FirstTSBuiltin); 547 } 548