1 //===--- PPC.cpp - Implement PPC target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPC.h" 14 #include "clang/Basic/Diagnostic.h" 15 #include "clang/Basic/MacroBuilder.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 18 using namespace clang; 19 using namespace clang::targets; 20 21 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 22 #define BUILTIN(ID, TYPE, ATTRS) \ 23 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 24 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 25 {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr}, 26 #include "clang/Basic/BuiltinsPPC.def" 27 }; 28 29 /// handleTargetFeatures - Perform initialization based on the user 30 /// configured set of features. 31 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 32 DiagnosticsEngine &Diags) { 33 FloatABI = HardFloat; 34 for (const auto &Feature : Features) { 35 if (Feature == "+altivec") { 36 HasAltivec = true; 37 } else if (Feature == "+vsx") { 38 HasVSX = true; 39 } else if (Feature == "+bpermd") { 40 HasBPERMD = true; 41 } else if (Feature == "+extdiv") { 42 HasExtDiv = true; 43 } else if (Feature == "+power8-vector") { 44 HasP8Vector = true; 45 } else if (Feature == "+crypto") { 46 HasP8Crypto = true; 47 } else if (Feature == "+direct-move") { 48 HasDirectMove = true; 49 } else if (Feature == "+qpx") { 50 HasQPX = true; 51 } else if (Feature == "+htm") { 52 HasHTM = true; 53 } else if (Feature == "+float128") { 54 HasFloat128 = true; 55 } else if (Feature == "+power9-vector") { 56 HasP9Vector = true; 57 } else if (Feature == "+pcrelative-memops") { 58 HasPCRelativeMemops = true; 59 } else if (Feature == "+spe") { 60 HasSPE = true; 61 LongDoubleWidth = LongDoubleAlign = 64; 62 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 63 } else if (Feature == "-hard-float") { 64 FloatABI = SoftFloat; 65 } 66 // TODO: Finish this list and add an assert that we've handled them 67 // all. 68 } 69 70 return true; 71 } 72 73 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 74 /// #defines that are not tied to a specific subtarget. 75 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 76 MacroBuilder &Builder) const { 77 // Target identification. 78 Builder.defineMacro("__ppc__"); 79 Builder.defineMacro("__PPC__"); 80 Builder.defineMacro("_ARCH_PPC"); 81 Builder.defineMacro("__powerpc__"); 82 Builder.defineMacro("__POWERPC__"); 83 if (PointerWidth == 64) { 84 Builder.defineMacro("_ARCH_PPC64"); 85 Builder.defineMacro("__powerpc64__"); 86 Builder.defineMacro("__ppc64__"); 87 Builder.defineMacro("__PPC64__"); 88 } 89 90 // Target properties. 91 if (getTriple().getArch() == llvm::Triple::ppc64le) { 92 Builder.defineMacro("_LITTLE_ENDIAN"); 93 } else { 94 if (!getTriple().isOSNetBSD() && 95 !getTriple().isOSOpenBSD()) 96 Builder.defineMacro("_BIG_ENDIAN"); 97 } 98 99 // ABI options. 100 if (ABI == "elfv1" || ABI == "elfv1-qpx") 101 Builder.defineMacro("_CALL_ELF", "1"); 102 if (ABI == "elfv2") 103 Builder.defineMacro("_CALL_ELF", "2"); 104 105 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 106 // our support post-dates this and it should work on all 64-bit ppc linux 107 // platforms. It is guaranteed to work on all elfv2 platforms. 108 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 109 Builder.defineMacro("_CALL_LINUX", "1"); 110 111 // Subtarget options. 112 if (!getTriple().isOSAIX()){ 113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 114 } 115 Builder.defineMacro("__REGISTER_PREFIX__", ""); 116 117 // FIXME: Should be controlled by command line option. 118 if (LongDoubleWidth == 128) { 119 Builder.defineMacro("__LONG_DOUBLE_128__"); 120 Builder.defineMacro("__LONGDOUBLE128"); 121 } 122 123 // Define this for elfv2 (64-bit only) or 64-bit darwin. 124 if (ABI == "elfv2" || 125 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 126 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 127 128 if (ArchDefs & ArchDefineName) 129 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 130 if (ArchDefs & ArchDefinePpcgr) 131 Builder.defineMacro("_ARCH_PPCGR"); 132 if (ArchDefs & ArchDefinePpcsq) 133 Builder.defineMacro("_ARCH_PPCSQ"); 134 if (ArchDefs & ArchDefine440) 135 Builder.defineMacro("_ARCH_440"); 136 if (ArchDefs & ArchDefine603) 137 Builder.defineMacro("_ARCH_603"); 138 if (ArchDefs & ArchDefine604) 139 Builder.defineMacro("_ARCH_604"); 140 if (ArchDefs & ArchDefinePwr4) 141 Builder.defineMacro("_ARCH_PWR4"); 142 if (ArchDefs & ArchDefinePwr5) 143 Builder.defineMacro("_ARCH_PWR5"); 144 if (ArchDefs & ArchDefinePwr5x) 145 Builder.defineMacro("_ARCH_PWR5X"); 146 if (ArchDefs & ArchDefinePwr6) 147 Builder.defineMacro("_ARCH_PWR6"); 148 if (ArchDefs & ArchDefinePwr6x) 149 Builder.defineMacro("_ARCH_PWR6X"); 150 if (ArchDefs & ArchDefinePwr7) 151 Builder.defineMacro("_ARCH_PWR7"); 152 if (ArchDefs & ArchDefinePwr8) 153 Builder.defineMacro("_ARCH_PWR8"); 154 if (ArchDefs & ArchDefinePwr9) 155 Builder.defineMacro("_ARCH_PWR9"); 156 if (ArchDefs & ArchDefinePwr10) 157 Builder.defineMacro("_ARCH_PWR10"); 158 if (ArchDefs & ArchDefineA2) 159 Builder.defineMacro("_ARCH_A2"); 160 if (ArchDefs & ArchDefineA2q) { 161 Builder.defineMacro("_ARCH_A2Q"); 162 Builder.defineMacro("_ARCH_QP"); 163 } 164 if (ArchDefs & ArchDefineE500) 165 Builder.defineMacro("__NO_LWSYNC__"); 166 if (ArchDefs & ArchDefineFuture) 167 Builder.defineMacro("_ARCH_PWR_FUTURE"); 168 169 if (getTriple().getVendor() == llvm::Triple::BGQ) { 170 Builder.defineMacro("__bg__"); 171 Builder.defineMacro("__THW_BLUEGENE__"); 172 Builder.defineMacro("__bgq__"); 173 Builder.defineMacro("__TOS_BGQ__"); 174 } 175 176 if (HasAltivec) { 177 Builder.defineMacro("__VEC__", "10206"); 178 Builder.defineMacro("__ALTIVEC__"); 179 } 180 if (HasSPE) { 181 Builder.defineMacro("__SPE__"); 182 Builder.defineMacro("__NO_FPRS__"); 183 } 184 if (HasVSX) 185 Builder.defineMacro("__VSX__"); 186 if (HasP8Vector) 187 Builder.defineMacro("__POWER8_VECTOR__"); 188 if (HasP8Crypto) 189 Builder.defineMacro("__CRYPTO__"); 190 if (HasHTM) 191 Builder.defineMacro("__HTM__"); 192 if (HasFloat128) 193 Builder.defineMacro("__FLOAT128__"); 194 if (HasP9Vector) 195 Builder.defineMacro("__POWER9_VECTOR__"); 196 197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 198 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 200 if (PointerWidth == 64) 201 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 202 203 // We have support for the bswap intrinsics so we can define this. 204 Builder.defineMacro("__HAVE_BSWAP__", "1"); 205 206 // FIXME: The following are not yet generated here by Clang, but are 207 // generated by GCC: 208 // 209 // _SOFT_FLOAT_ 210 // __RECIP_PRECISION__ 211 // __APPLE_ALTIVEC__ 212 // __RECIP__ 213 // __RECIPF__ 214 // __RSQRTE__ 215 // __RSQRTEF__ 216 // _SOFT_DOUBLE_ 217 // __NO_LWSYNC__ 218 // __CMODEL_MEDIUM__ 219 // __CMODEL_LARGE__ 220 // _CALL_SYSV 221 // _CALL_DARWIN 222 } 223 224 // Handle explicit options being passed to the compiler here: if we've 225 // explicitly turned off vsx and turned on any of: 226 // - power8-vector 227 // - direct-move 228 // - float128 229 // - power9-vector 230 // then go ahead and error since the customer has expressed an incompatible 231 // set of options. 232 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 233 const std::vector<std::string> &FeaturesVec) { 234 235 // vsx was not explicitly turned off. 236 if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end()) 237 return true; 238 239 auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) { 240 if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) { 241 Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx"; 242 return true; 243 } 244 return false; 245 }; 246 247 bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector"); 248 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move"); 249 Found |= FindVSXSubfeature("+float128", "-mfloat128"); 250 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector"); 251 252 // Return false if any vsx subfeatures was found. 253 return !Found; 254 } 255 256 bool PPCTargetInfo::initFeatureMap( 257 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 258 const std::vector<std::string> &FeaturesVec) const { 259 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 260 .Case("7400", true) 261 .Case("g4", true) 262 .Case("7450", true) 263 .Case("g4+", true) 264 .Case("970", true) 265 .Case("g5", true) 266 .Case("pwr6", true) 267 .Case("pwr7", true) 268 .Case("pwr8", true) 269 .Case("pwr9", true) 270 .Case("ppc64", true) 271 .Case("ppc64le", true) 272 .Default(false); 273 274 Features["qpx"] = (CPU == "a2q"); 275 Features["power9-vector"] = (CPU == "pwr9"); 276 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 277 .Case("ppc64le", true) 278 .Case("pwr9", true) 279 .Case("pwr8", true) 280 .Default(false); 281 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 282 .Case("ppc64le", true) 283 .Case("pwr9", true) 284 .Case("pwr8", true) 285 .Default(false); 286 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 287 .Case("ppc64le", true) 288 .Case("pwr9", true) 289 .Case("pwr8", true) 290 .Case("pwr7", true) 291 .Default(false); 292 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 293 .Case("ppc64le", true) 294 .Case("pwr9", true) 295 .Case("pwr8", true) 296 .Case("pwr7", true) 297 .Default(false); 298 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 299 .Case("ppc64le", true) 300 .Case("pwr9", true) 301 .Case("pwr8", true) 302 .Default(false); 303 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 304 .Case("ppc64le", true) 305 .Case("pwr9", true) 306 .Case("pwr8", true) 307 .Case("pwr7", true) 308 .Default(false); 309 Features["htm"] = llvm::StringSwitch<bool>(CPU) 310 .Case("ppc64le", true) 311 .Case("pwr9", true) 312 .Case("pwr8", true) 313 .Default(false); 314 315 Features["spe"] = llvm::StringSwitch<bool>(CPU) 316 .Case("8548", true) 317 .Case("e500", true) 318 .Default(false); 319 320 // Power10 includes all the same features as Power9 plus any features specific 321 // to the Power10 core. 322 if (CPU == "pwr10" || CPU == "power10") { 323 initFeatureMap(Features, Diags, "pwr9", FeaturesVec); 324 addP10SpecificFeatures(Features); 325 } 326 327 // Future CPU should include all of the features of Power 10 as well as any 328 // additional features (yet to be determined) specific to it. 329 if (CPU == "future") { 330 initFeatureMap(Features, Diags, "pwr10", FeaturesVec); 331 addFutureSpecificFeatures(Features); 332 } 333 334 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 335 return false; 336 337 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && 338 llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { 339 // We have __float128 on PPC but not power 9 and above. 340 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU; 341 return false; 342 } 343 344 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 345 } 346 347 // Add any Power10 specific features. 348 void PPCTargetInfo::addP10SpecificFeatures( 349 llvm::StringMap<bool> &Features) const { 350 Features["htm"] = false; // HTM was removed for P10. 351 Features["pcrelative-memops"] = true; 352 return; 353 } 354 355 // Add features specific to the "Future" CPU. 356 void PPCTargetInfo::addFutureSpecificFeatures( 357 llvm::StringMap<bool> &Features) const { 358 return; 359 } 360 361 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 362 return llvm::StringSwitch<bool>(Feature) 363 .Case("powerpc", true) 364 .Case("altivec", HasAltivec) 365 .Case("vsx", HasVSX) 366 .Case("power8-vector", HasP8Vector) 367 .Case("crypto", HasP8Crypto) 368 .Case("direct-move", HasDirectMove) 369 .Case("qpx", HasQPX) 370 .Case("htm", HasHTM) 371 .Case("bpermd", HasBPERMD) 372 .Case("extdiv", HasExtDiv) 373 .Case("float128", HasFloat128) 374 .Case("power9-vector", HasP9Vector) 375 .Case("pcrelative-memops", HasPCRelativeMemops) 376 .Case("spe", HasSPE) 377 .Default(false); 378 } 379 380 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 381 StringRef Name, bool Enabled) const { 382 if (Enabled) { 383 // If we're enabling any of the vsx based features then enable vsx and 384 // altivec. We'll diagnose any problems later. 385 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 386 .Case("vsx", true) 387 .Case("direct-move", true) 388 .Case("power8-vector", true) 389 .Case("power9-vector", true) 390 .Case("float128", true) 391 .Default(false); 392 if (FeatureHasVSX) 393 Features["vsx"] = Features["altivec"] = true; 394 if (Name == "power9-vector") 395 Features["power8-vector"] = true; 396 if (Name == "pcrel") 397 Features["pcrelative-memops"] = true; 398 else 399 Features[Name] = true; 400 } else { 401 // If we're disabling altivec or vsx go ahead and disable all of the vsx 402 // features. 403 if ((Name == "altivec") || (Name == "vsx")) 404 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 405 Features["float128"] = Features["power9-vector"] = false; 406 if (Name == "power8-vector") 407 Features["power9-vector"] = false; 408 if (Name == "pcrel") 409 Features["pcrelative-memops"] = false; 410 else 411 Features[Name] = false; 412 } 413 } 414 415 const char *const PPCTargetInfo::GCCRegNames[] = { 416 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", 417 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", 418 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", 419 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3", 420 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", 421 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", 422 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", 423 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3", 424 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3", 425 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", 426 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 427 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", 428 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp" 429 }; 430 431 ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const { 432 return llvm::makeArrayRef(GCCRegNames); 433 } 434 435 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 436 // While some of these aliases do map to different registers 437 // they still share the same register name. 438 {{"0"}, "r0"}, {{"1"}, "r1"}, {{"2"}, "r2"}, {{"3"}, "r3"}, 439 {{"4"}, "r4"}, {{"5"}, "r5"}, {{"6"}, "r6"}, {{"7"}, "r7"}, 440 {{"8"}, "r8"}, {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"}, 441 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"}, {{"15"}, "r15"}, 442 {{"16"}, "r16"}, {{"17"}, "r17"}, {{"18"}, "r18"}, {{"19"}, "r19"}, 443 {{"20"}, "r20"}, {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"}, 444 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"}, {{"27"}, "r27"}, 445 {{"28"}, "r28"}, {{"29"}, "r29"}, {{"30"}, "r30"}, {{"31"}, "r31"}, 446 {{"fr0"}, "f0"}, {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"}, 447 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"}, {{"fr7"}, "f7"}, 448 {{"fr8"}, "f8"}, {{"fr9"}, "f9"}, {{"fr10"}, "f10"}, {{"fr11"}, "f11"}, 449 {{"fr12"}, "f12"}, {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"}, 450 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, {{"fr19"}, "f19"}, 451 {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"}, 452 {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"}, 453 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"}, 454 {{"cc"}, "cr0"}, 455 }; 456 457 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 458 return llvm::makeArrayRef(GCCRegAliases); 459 } 460 461 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers". 462 // vs0 ~ vs31 is mapping to 32 - 63, 463 // vs32 ~ vs63 is mapping to 77 - 108. 464 const TargetInfo::AddlRegName GCCAddlRegNames[] = { 465 // Table of additional register names to use in user input. 466 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35}, 467 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39}, 468 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43}, 469 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47}, 470 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51}, 471 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55}, 472 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59}, 473 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63}, 474 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80}, 475 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84}, 476 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88}, 477 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92}, 478 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96}, 479 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100}, 480 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104}, 481 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108}, 482 }; 483 484 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const { 485 if (ABI == "elfv2") 486 return llvm::makeArrayRef(GCCAddlRegNames); 487 else 488 return TargetInfo::getGCCAddlRegNames(); 489 } 490 491 static constexpr llvm::StringLiteral ValidCPUNames[] = { 492 {"generic"}, {"440"}, {"450"}, {"601"}, {"602"}, 493 {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"}, 494 {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"}, 495 {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"}, 496 {"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"}, 497 {"e5500"}, {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, 498 {"power5"}, {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, 499 {"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, 500 {"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, 501 {"pwr10"}, {"powerpc"}, {"ppc"}, {"powerpc64"}, {"ppc64"}, 502 {"powerpc64le"}, {"ppc64le"}, {"future"}}; 503 504 bool PPCTargetInfo::isValidCPUName(StringRef Name) const { 505 return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames); 506 } 507 508 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 509 Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames)); 510 } 511 512 void PPCTargetInfo::adjust(LangOptions &Opts) { 513 if (HasAltivec) 514 Opts.AltiVec = 1; 515 TargetInfo::adjust(Opts); 516 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble()) 517 LongDoubleFormat = Opts.PPCIEEELongDouble 518 ? &llvm::APFloat::IEEEquad() 519 : &llvm::APFloat::PPCDoubleDouble(); 520 } 521 522 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const { 523 return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin - 524 Builtin::FirstTSBuiltin); 525 } 526