1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <[email protected]> 28 * Gareth Hughes <[email protected]> 29 * Keith Whitwell <[email protected]> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 56 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 57 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 58 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 59 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 60 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 61 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 62 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 63 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 64 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 65 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 66 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 67 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 68 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 69 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 70 71 #define AMDGPU_GEM_DOMAIN_CPU 0x1 72 #define AMDGPU_GEM_DOMAIN_GTT 0x2 73 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 74 #define AMDGPU_GEM_DOMAIN_GDS 0x8 75 #define AMDGPU_GEM_DOMAIN_GWS 0x10 76 #define AMDGPU_GEM_DOMAIN_OA 0x20 77 78 /* Flag that CPU access will be required for the case of VRAM domain */ 79 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 80 /* Flag that CPU access will not work, this VRAM domain is invisible */ 81 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 82 /* Flag that USWC attributes should be used for GTT */ 83 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 84 /* Flag that the memory should be in VRAM and cleared */ 85 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 86 /* Flag that create shadow bo(GTT) while allocating vram bo */ 87 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 88 /* Flag that allocating the BO should use linear VRAM */ 89 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 90 91 struct drm_amdgpu_gem_create_in { 92 /** the requested memory size */ 93 __u64 bo_size; 94 /** physical start_addr alignment in bytes for some HW requirements */ 95 __u64 alignment; 96 /** the requested memory domains */ 97 __u64 domains; 98 /** allocation flags */ 99 __u64 domain_flags; 100 }; 101 102 struct drm_amdgpu_gem_create_out { 103 /** returned GEM object handle */ 104 __u32 handle; 105 __u32 _pad; 106 }; 107 108 union drm_amdgpu_gem_create { 109 struct drm_amdgpu_gem_create_in in; 110 struct drm_amdgpu_gem_create_out out; 111 }; 112 113 /** Opcode to create new residency list. */ 114 #define AMDGPU_BO_LIST_OP_CREATE 0 115 /** Opcode to destroy previously created residency list */ 116 #define AMDGPU_BO_LIST_OP_DESTROY 1 117 /** Opcode to update resource information in the list */ 118 #define AMDGPU_BO_LIST_OP_UPDATE 2 119 120 struct drm_amdgpu_bo_list_in { 121 /** Type of operation */ 122 __u32 operation; 123 /** Handle of list or 0 if we want to create one */ 124 __u32 list_handle; 125 /** Number of BOs in list */ 126 __u32 bo_number; 127 /** Size of each element describing BO */ 128 __u32 bo_info_size; 129 /** Pointer to array describing BOs */ 130 __u64 bo_info_ptr; 131 }; 132 133 struct drm_amdgpu_bo_list_entry { 134 /** Handle of BO */ 135 __u32 bo_handle; 136 /** New (if specified) BO priority to be used during migration */ 137 __u32 bo_priority; 138 }; 139 140 struct drm_amdgpu_bo_list_out { 141 /** Handle of resource list */ 142 __u32 list_handle; 143 __u32 _pad; 144 }; 145 146 union drm_amdgpu_bo_list { 147 struct drm_amdgpu_bo_list_in in; 148 struct drm_amdgpu_bo_list_out out; 149 }; 150 151 /* context related */ 152 #define AMDGPU_CTX_OP_ALLOC_CTX 1 153 #define AMDGPU_CTX_OP_FREE_CTX 2 154 #define AMDGPU_CTX_OP_QUERY_STATE 3 155 156 /* GPU reset status */ 157 #define AMDGPU_CTX_NO_RESET 0 158 /* this the context caused it */ 159 #define AMDGPU_CTX_GUILTY_RESET 1 160 /* some other context caused it */ 161 #define AMDGPU_CTX_INNOCENT_RESET 2 162 /* unknown cause */ 163 #define AMDGPU_CTX_UNKNOWN_RESET 3 164 165 struct drm_amdgpu_ctx_in { 166 /** AMDGPU_CTX_OP_* */ 167 __u32 op; 168 /** For future use, no flags defined so far */ 169 __u32 flags; 170 __u32 ctx_id; 171 __u32 _pad; 172 }; 173 174 union drm_amdgpu_ctx_out { 175 struct { 176 __u32 ctx_id; 177 __u32 _pad; 178 } alloc; 179 180 struct { 181 /** For future use, no flags defined so far */ 182 __u64 flags; 183 /** Number of resets caused by this context so far. */ 184 __u32 hangs; 185 /** Reset status since the last call of the ioctl. */ 186 __u32 reset_status; 187 } state; 188 }; 189 190 union drm_amdgpu_ctx { 191 struct drm_amdgpu_ctx_in in; 192 union drm_amdgpu_ctx_out out; 193 }; 194 195 /* vm ioctl */ 196 #define AMDGPU_VM_OP_RESERVE_VMID 1 197 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 198 199 struct drm_amdgpu_vm_in { 200 /** AMDGPU_VM_OP_* */ 201 __u32 op; 202 __u32 flags; 203 }; 204 205 struct drm_amdgpu_vm_out { 206 /** For future use, no flags defined so far */ 207 __u64 flags; 208 }; 209 210 union drm_amdgpu_vm { 211 struct drm_amdgpu_vm_in in; 212 struct drm_amdgpu_vm_out out; 213 }; 214 215 /* 216 * This is not a reliable API and you should expect it to fail for any 217 * number of reasons and have fallback path that do not use userptr to 218 * perform any operation. 219 */ 220 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 221 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 222 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 223 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 224 225 struct drm_amdgpu_gem_userptr { 226 __u64 addr; 227 __u64 size; 228 /* AMDGPU_GEM_USERPTR_* */ 229 __u32 flags; 230 /* Resulting GEM handle */ 231 __u32 handle; 232 }; 233 234 /* SI-CI-VI: */ 235 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 236 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 237 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 238 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 239 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 240 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 241 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 242 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 243 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 244 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 245 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 246 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 247 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 248 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 249 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 250 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 251 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 252 253 /* GFX9 and later: */ 254 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 255 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 256 257 /* Set/Get helpers for tiling flags. */ 258 #define AMDGPU_TILING_SET(field, value) \ 259 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 260 #define AMDGPU_TILING_GET(value, field) \ 261 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 262 263 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 264 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 265 266 /** The same structure is shared for input/output */ 267 struct drm_amdgpu_gem_metadata { 268 /** GEM Object handle */ 269 __u32 handle; 270 /** Do we want get or set metadata */ 271 __u32 op; 272 struct { 273 /** For future use, no flags defined so far */ 274 __u64 flags; 275 /** family specific tiling info */ 276 __u64 tiling_info; 277 __u32 data_size_bytes; 278 __u32 data[64]; 279 } data; 280 }; 281 282 struct drm_amdgpu_gem_mmap_in { 283 /** the GEM object handle */ 284 __u32 handle; 285 __u32 _pad; 286 }; 287 288 struct drm_amdgpu_gem_mmap_out { 289 /** mmap offset from the vma offset manager */ 290 __u64 addr_ptr; 291 }; 292 293 union drm_amdgpu_gem_mmap { 294 struct drm_amdgpu_gem_mmap_in in; 295 struct drm_amdgpu_gem_mmap_out out; 296 }; 297 298 struct drm_amdgpu_gem_wait_idle_in { 299 /** GEM object handle */ 300 __u32 handle; 301 /** For future use, no flags defined so far */ 302 __u32 flags; 303 /** Absolute timeout to wait */ 304 __u64 timeout; 305 }; 306 307 struct drm_amdgpu_gem_wait_idle_out { 308 /** BO status: 0 - BO is idle, 1 - BO is busy */ 309 __u32 status; 310 /** Returned current memory domain */ 311 __u32 domain; 312 }; 313 314 union drm_amdgpu_gem_wait_idle { 315 struct drm_amdgpu_gem_wait_idle_in in; 316 struct drm_amdgpu_gem_wait_idle_out out; 317 }; 318 319 struct drm_amdgpu_wait_cs_in { 320 /* Command submission handle 321 * handle equals 0 means none to wait for 322 * handle equals ~0ull means wait for the latest sequence number 323 */ 324 __u64 handle; 325 /** Absolute timeout to wait */ 326 __u64 timeout; 327 __u32 ip_type; 328 __u32 ip_instance; 329 __u32 ring; 330 __u32 ctx_id; 331 }; 332 333 struct drm_amdgpu_wait_cs_out { 334 /** CS status: 0 - CS completed, 1 - CS still busy */ 335 __u64 status; 336 }; 337 338 union drm_amdgpu_wait_cs { 339 struct drm_amdgpu_wait_cs_in in; 340 struct drm_amdgpu_wait_cs_out out; 341 }; 342 343 struct drm_amdgpu_fence { 344 __u32 ctx_id; 345 __u32 ip_type; 346 __u32 ip_instance; 347 __u32 ring; 348 __u64 seq_no; 349 }; 350 351 struct drm_amdgpu_wait_fences_in { 352 /** This points to uint64_t * which points to fences */ 353 __u64 fences; 354 __u32 fence_count; 355 __u32 wait_all; 356 __u64 timeout_ns; 357 }; 358 359 struct drm_amdgpu_wait_fences_out { 360 __u32 status; 361 __u32 first_signaled; 362 }; 363 364 union drm_amdgpu_wait_fences { 365 struct drm_amdgpu_wait_fences_in in; 366 struct drm_amdgpu_wait_fences_out out; 367 }; 368 369 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 370 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 371 372 /* Sets or returns a value associated with a buffer. */ 373 struct drm_amdgpu_gem_op { 374 /** GEM object handle */ 375 __u32 handle; 376 /** AMDGPU_GEM_OP_* */ 377 __u32 op; 378 /** Input or return value */ 379 __u64 value; 380 }; 381 382 #define AMDGPU_VA_OP_MAP 1 383 #define AMDGPU_VA_OP_UNMAP 2 384 #define AMDGPU_VA_OP_CLEAR 3 385 #define AMDGPU_VA_OP_REPLACE 4 386 387 /* Delay the page table update till the next CS */ 388 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 389 390 /* Mapping flags */ 391 /* readable mapping */ 392 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 393 /* writable mapping */ 394 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 395 /* executable mapping, new for VI */ 396 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 397 /* partially resident texture */ 398 #define AMDGPU_VM_PAGE_PRT (1 << 4) 399 /* MTYPE flags use bit 5 to 8 */ 400 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 401 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 402 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 403 /* Use NC MTYPE instead of default MTYPE */ 404 #define AMDGPU_VM_MTYPE_NC (1 << 5) 405 /* Use WC MTYPE instead of default MTYPE */ 406 #define AMDGPU_VM_MTYPE_WC (2 << 5) 407 /* Use CC MTYPE instead of default MTYPE */ 408 #define AMDGPU_VM_MTYPE_CC (3 << 5) 409 /* Use UC MTYPE instead of default MTYPE */ 410 #define AMDGPU_VM_MTYPE_UC (4 << 5) 411 412 struct drm_amdgpu_gem_va { 413 /** GEM object handle */ 414 __u32 handle; 415 __u32 _pad; 416 /** AMDGPU_VA_OP_* */ 417 __u32 operation; 418 /** AMDGPU_VM_PAGE_* */ 419 __u32 flags; 420 /** va address to assign . Must be correctly aligned.*/ 421 __u64 va_address; 422 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 423 __u64 offset_in_bo; 424 /** Specify mapping size. Must be correctly aligned. */ 425 __u64 map_size; 426 }; 427 428 #define AMDGPU_HW_IP_GFX 0 429 #define AMDGPU_HW_IP_COMPUTE 1 430 #define AMDGPU_HW_IP_DMA 2 431 #define AMDGPU_HW_IP_UVD 3 432 #define AMDGPU_HW_IP_VCE 4 433 #define AMDGPU_HW_IP_UVD_ENC 5 434 #define AMDGPU_HW_IP_VCN_DEC 6 435 #define AMDGPU_HW_IP_VCN_ENC 7 436 #define AMDGPU_HW_IP_NUM 8 437 438 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 439 440 #define AMDGPU_CHUNK_ID_IB 0x01 441 #define AMDGPU_CHUNK_ID_FENCE 0x02 442 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 443 444 struct drm_amdgpu_cs_chunk { 445 __u32 chunk_id; 446 __u32 length_dw; 447 __u64 chunk_data; 448 }; 449 450 struct drm_amdgpu_cs_in { 451 /** Rendering context id */ 452 __u32 ctx_id; 453 /** Handle of resource list associated with CS */ 454 __u32 bo_list_handle; 455 __u32 num_chunks; 456 __u32 _pad; 457 /** this points to __u64 * which point to cs chunks */ 458 __u64 chunks; 459 }; 460 461 struct drm_amdgpu_cs_out { 462 __u64 handle; 463 }; 464 465 union drm_amdgpu_cs { 466 struct drm_amdgpu_cs_in in; 467 struct drm_amdgpu_cs_out out; 468 }; 469 470 /* Specify flags to be used for IB */ 471 472 /* This IB should be submitted to CE */ 473 #define AMDGPU_IB_FLAG_CE (1<<0) 474 475 /* Preamble flag, which means the IB could be dropped if no context switch */ 476 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 477 478 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 479 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 480 481 struct drm_amdgpu_cs_chunk_ib { 482 __u32 _pad; 483 /** AMDGPU_IB_FLAG_* */ 484 __u32 flags; 485 /** Virtual address to begin IB execution */ 486 __u64 va_start; 487 /** Size of submission */ 488 __u32 ib_bytes; 489 /** HW IP to submit to */ 490 __u32 ip_type; 491 /** HW IP index of the same type to submit to */ 492 __u32 ip_instance; 493 /** Ring index to submit to */ 494 __u32 ring; 495 }; 496 497 struct drm_amdgpu_cs_chunk_dep { 498 __u32 ip_type; 499 __u32 ip_instance; 500 __u32 ring; 501 __u32 ctx_id; 502 __u64 handle; 503 }; 504 505 struct drm_amdgpu_cs_chunk_fence { 506 __u32 handle; 507 __u32 offset; 508 }; 509 510 struct drm_amdgpu_cs_chunk_data { 511 union { 512 struct drm_amdgpu_cs_chunk_ib ib_data; 513 struct drm_amdgpu_cs_chunk_fence fence_data; 514 }; 515 }; 516 517 /** 518 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 519 * 520 */ 521 #define AMDGPU_IDS_FLAGS_FUSION 0x1 522 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 523 524 /* indicate if acceleration can be working */ 525 #define AMDGPU_INFO_ACCEL_WORKING 0x00 526 /* get the crtc_id from the mode object id? */ 527 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 528 /* query hw IP info */ 529 #define AMDGPU_INFO_HW_IP_INFO 0x02 530 /* query hw IP instance count for the specified type */ 531 #define AMDGPU_INFO_HW_IP_COUNT 0x03 532 /* timestamp for GL_ARB_timer_query */ 533 #define AMDGPU_INFO_TIMESTAMP 0x05 534 /* Query the firmware version */ 535 #define AMDGPU_INFO_FW_VERSION 0x0e 536 /* Subquery id: Query VCE firmware version */ 537 #define AMDGPU_INFO_FW_VCE 0x1 538 /* Subquery id: Query UVD firmware version */ 539 #define AMDGPU_INFO_FW_UVD 0x2 540 /* Subquery id: Query GMC firmware version */ 541 #define AMDGPU_INFO_FW_GMC 0x03 542 /* Subquery id: Query GFX ME firmware version */ 543 #define AMDGPU_INFO_FW_GFX_ME 0x04 544 /* Subquery id: Query GFX PFP firmware version */ 545 #define AMDGPU_INFO_FW_GFX_PFP 0x05 546 /* Subquery id: Query GFX CE firmware version */ 547 #define AMDGPU_INFO_FW_GFX_CE 0x06 548 /* Subquery id: Query GFX RLC firmware version */ 549 #define AMDGPU_INFO_FW_GFX_RLC 0x07 550 /* Subquery id: Query GFX MEC firmware version */ 551 #define AMDGPU_INFO_FW_GFX_MEC 0x08 552 /* Subquery id: Query SMC firmware version */ 553 #define AMDGPU_INFO_FW_SMC 0x0a 554 /* Subquery id: Query SDMA firmware version */ 555 #define AMDGPU_INFO_FW_SDMA 0x0b 556 /* Subquery id: Query PSP SOS firmware version */ 557 #define AMDGPU_INFO_FW_SOS 0x0c 558 /* Subquery id: Query PSP ASD firmware version */ 559 #define AMDGPU_INFO_FW_ASD 0x0d 560 /* number of bytes moved for TTM migration */ 561 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 562 /* the used VRAM size */ 563 #define AMDGPU_INFO_VRAM_USAGE 0x10 564 /* the used GTT size */ 565 #define AMDGPU_INFO_GTT_USAGE 0x11 566 /* Information about GDS, etc. resource configuration */ 567 #define AMDGPU_INFO_GDS_CONFIG 0x13 568 /* Query information about VRAM and GTT domains */ 569 #define AMDGPU_INFO_VRAM_GTT 0x14 570 /* Query information about register in MMR address space*/ 571 #define AMDGPU_INFO_READ_MMR_REG 0x15 572 /* Query information about device: rev id, family, etc. */ 573 #define AMDGPU_INFO_DEV_INFO 0x16 574 /* visible vram usage */ 575 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 576 /* number of TTM buffer evictions */ 577 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 578 /* Query memory about VRAM and GTT domains */ 579 #define AMDGPU_INFO_MEMORY 0x19 580 /* Query vce clock table */ 581 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 582 /* Query vbios related information */ 583 #define AMDGPU_INFO_VBIOS 0x1B 584 /* Subquery id: Query vbios size */ 585 #define AMDGPU_INFO_VBIOS_SIZE 0x1 586 /* Subquery id: Query vbios image */ 587 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 588 /* Query UVD handles */ 589 #define AMDGPU_INFO_NUM_HANDLES 0x1C 590 /* Query sensor related information */ 591 #define AMDGPU_INFO_SENSOR 0x1D 592 /* Subquery id: Query GPU shader clock */ 593 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 594 /* Subquery id: Query GPU memory clock */ 595 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 596 /* Subquery id: Query GPU temperature */ 597 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 598 /* Subquery id: Query GPU load */ 599 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 600 /* Subquery id: Query average GPU power */ 601 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 602 /* Subquery id: Query northbridge voltage */ 603 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 604 /* Subquery id: Query graphics voltage */ 605 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 606 /* Number of VRAM page faults on CPU access. */ 607 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 608 609 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 610 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 611 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 612 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 613 614 struct drm_amdgpu_query_fw { 615 /** AMDGPU_INFO_FW_* */ 616 __u32 fw_type; 617 /** 618 * Index of the IP if there are more IPs of 619 * the same type. 620 */ 621 __u32 ip_instance; 622 /** 623 * Index of the engine. Whether this is used depends 624 * on the firmware type. (e.g. MEC, SDMA) 625 */ 626 __u32 index; 627 __u32 _pad; 628 }; 629 630 /* Input structure for the INFO ioctl */ 631 struct drm_amdgpu_info { 632 /* Where the return value will be stored */ 633 __u64 return_pointer; 634 /* The size of the return value. Just like "size" in "snprintf", 635 * it limits how many bytes the kernel can write. */ 636 __u32 return_size; 637 /* The query request id. */ 638 __u32 query; 639 640 union { 641 struct { 642 __u32 id; 643 __u32 _pad; 644 } mode_crtc; 645 646 struct { 647 /** AMDGPU_HW_IP_* */ 648 __u32 type; 649 /** 650 * Index of the IP if there are more IPs of the same 651 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 652 */ 653 __u32 ip_instance; 654 } query_hw_ip; 655 656 struct { 657 __u32 dword_offset; 658 /** number of registers to read */ 659 __u32 count; 660 __u32 instance; 661 /** For future use, no flags defined so far */ 662 __u32 flags; 663 } read_mmr_reg; 664 665 struct drm_amdgpu_query_fw query_fw; 666 667 struct { 668 __u32 type; 669 __u32 offset; 670 } vbios_info; 671 672 struct { 673 __u32 type; 674 } sensor_info; 675 }; 676 }; 677 678 struct drm_amdgpu_info_gds { 679 /** GDS GFX partition size */ 680 __u32 gds_gfx_partition_size; 681 /** GDS compute partition size */ 682 __u32 compute_partition_size; 683 /** total GDS memory size */ 684 __u32 gds_total_size; 685 /** GWS size per GFX partition */ 686 __u32 gws_per_gfx_partition; 687 /** GSW size per compute partition */ 688 __u32 gws_per_compute_partition; 689 /** OA size per GFX partition */ 690 __u32 oa_per_gfx_partition; 691 /** OA size per compute partition */ 692 __u32 oa_per_compute_partition; 693 __u32 _pad; 694 }; 695 696 struct drm_amdgpu_info_vram_gtt { 697 __u64 vram_size; 698 __u64 vram_cpu_accessible_size; 699 __u64 gtt_size; 700 }; 701 702 struct drm_amdgpu_heap_info { 703 /** max. physical memory */ 704 __u64 total_heap_size; 705 706 /** Theoretical max. available memory in the given heap */ 707 __u64 usable_heap_size; 708 709 /** 710 * Number of bytes allocated in the heap. This includes all processes 711 * and private allocations in the kernel. It changes when new buffers 712 * are allocated, freed, and moved. It cannot be larger than 713 * heap_size. 714 */ 715 __u64 heap_usage; 716 717 /** 718 * Theoretical possible max. size of buffer which 719 * could be allocated in the given heap 720 */ 721 __u64 max_allocation; 722 }; 723 724 struct drm_amdgpu_memory_info { 725 struct drm_amdgpu_heap_info vram; 726 struct drm_amdgpu_heap_info cpu_accessible_vram; 727 struct drm_amdgpu_heap_info gtt; 728 }; 729 730 struct drm_amdgpu_info_firmware { 731 __u32 ver; 732 __u32 feature; 733 }; 734 735 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 736 #define AMDGPU_VRAM_TYPE_GDDR1 1 737 #define AMDGPU_VRAM_TYPE_DDR2 2 738 #define AMDGPU_VRAM_TYPE_GDDR3 3 739 #define AMDGPU_VRAM_TYPE_GDDR4 4 740 #define AMDGPU_VRAM_TYPE_GDDR5 5 741 #define AMDGPU_VRAM_TYPE_HBM 6 742 #define AMDGPU_VRAM_TYPE_DDR3 7 743 744 struct drm_amdgpu_info_device { 745 /** PCI Device ID */ 746 __u32 device_id; 747 /** Internal chip revision: A0, A1, etc.) */ 748 __u32 chip_rev; 749 __u32 external_rev; 750 /** Revision id in PCI Config space */ 751 __u32 pci_rev; 752 __u32 family; 753 __u32 num_shader_engines; 754 __u32 num_shader_arrays_per_engine; 755 /* in KHz */ 756 __u32 gpu_counter_freq; 757 __u64 max_engine_clock; 758 __u64 max_memory_clock; 759 /* cu information */ 760 __u32 cu_active_number; 761 __u32 cu_ao_mask; 762 __u32 cu_bitmap[4][4]; 763 /** Render backend pipe mask. One render backend is CB+DB. */ 764 __u32 enabled_rb_pipes_mask; 765 __u32 num_rb_pipes; 766 __u32 num_hw_gfx_contexts; 767 __u32 _pad; 768 __u64 ids_flags; 769 /** Starting virtual address for UMDs. */ 770 __u64 virtual_address_offset; 771 /** The maximum virtual address */ 772 __u64 virtual_address_max; 773 /** Required alignment of virtual addresses. */ 774 __u32 virtual_address_alignment; 775 /** Page table entry - fragment size */ 776 __u32 pte_fragment_size; 777 __u32 gart_page_size; 778 /** constant engine ram size*/ 779 __u32 ce_ram_size; 780 /** video memory type info*/ 781 __u32 vram_type; 782 /** video memory bit width*/ 783 __u32 vram_bit_width; 784 /* vce harvesting instance */ 785 __u32 vce_harvest_config; 786 /* gfx double offchip LDS buffers */ 787 __u32 gc_double_offchip_lds_buf; 788 /* NGG Primitive Buffer */ 789 __u64 prim_buf_gpu_addr; 790 /* NGG Position Buffer */ 791 __u64 pos_buf_gpu_addr; 792 /* NGG Control Sideband */ 793 __u64 cntl_sb_buf_gpu_addr; 794 /* NGG Parameter Cache */ 795 __u64 param_buf_gpu_addr; 796 __u32 prim_buf_size; 797 __u32 pos_buf_size; 798 __u32 cntl_sb_buf_size; 799 __u32 param_buf_size; 800 /* wavefront size*/ 801 __u32 wave_front_size; 802 /* shader visible vgprs*/ 803 __u32 num_shader_visible_vgprs; 804 /* CU per shader array*/ 805 __u32 num_cu_per_sh; 806 /* number of tcc blocks*/ 807 __u32 num_tcc_blocks; 808 /* gs vgt table depth*/ 809 __u32 gs_vgt_table_depth; 810 /* gs primitive buffer depth*/ 811 __u32 gs_prim_buffer_depth; 812 /* max gs wavefront per vgt*/ 813 __u32 max_gs_waves_per_vgt; 814 __u32 _pad1; 815 }; 816 817 struct drm_amdgpu_info_hw_ip { 818 /** Version of h/w IP */ 819 __u32 hw_ip_version_major; 820 __u32 hw_ip_version_minor; 821 /** Capabilities */ 822 __u64 capabilities_flags; 823 /** command buffer address start alignment*/ 824 __u32 ib_start_alignment; 825 /** command buffer size alignment*/ 826 __u32 ib_size_alignment; 827 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 828 __u32 available_rings; 829 __u32 _pad; 830 }; 831 832 struct drm_amdgpu_info_num_handles { 833 /** Max handles as supported by firmware for UVD */ 834 __u32 uvd_max_handles; 835 /** Handles currently in use for UVD */ 836 __u32 uvd_used_handles; 837 }; 838 839 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 840 841 struct drm_amdgpu_info_vce_clock_table_entry { 842 /** System clock */ 843 __u32 sclk; 844 /** Memory clock */ 845 __u32 mclk; 846 /** VCE clock */ 847 __u32 eclk; 848 __u32 pad; 849 }; 850 851 struct drm_amdgpu_info_vce_clock_table { 852 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 853 __u32 num_valid_entries; 854 __u32 pad; 855 }; 856 857 /* 858 * Supported GPU families 859 */ 860 #define AMDGPU_FAMILY_UNKNOWN 0 861 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 862 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 863 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 864 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 865 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 866 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 867 #define AMDGPU_FAMILY_RV 142 /* Raven */ 868 869 #if defined(__cplusplus) 870 } 871 #endif 872 873 #endif 874