1 /* 2 * Internal header file for Samsung S3C2410 serial ports (UART0-2) 3 * 4 * Copyright (C) 2002 Shane Nay ([email protected]) 5 * 6 * Additional defines, Copyright 2003 Simtec Electronics ([email protected]) 7 * 8 * Adapted from: 9 * 10 * Internal header file for MX1ADS serial ports (UART1 & 2) 11 * 12 * Copyright (C) 2002 Shane Nay ([email protected]) 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 */ 28 29 #ifndef __ASM_ARM_REGS_SERIAL_H 30 #define __ASM_ARM_REGS_SERIAL_H 31 32 #define S3C2410_URXH (0x24) 33 #define S3C2410_UTXH (0x20) 34 #define S3C2410_ULCON (0x00) 35 #define S3C2410_UCON (0x04) 36 #define S3C2410_UFCON (0x08) 37 #define S3C2410_UMCON (0x0C) 38 #define S3C2410_UBRDIV (0x28) 39 #define S3C2410_UTRSTAT (0x10) 40 #define S3C2410_UERSTAT (0x14) 41 #define S3C2410_UFSTAT (0x18) 42 #define S3C2410_UMSTAT (0x1C) 43 44 #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) 45 46 #define S3C2410_LCON_CS5 (0x0) 47 #define S3C2410_LCON_CS6 (0x1) 48 #define S3C2410_LCON_CS7 (0x2) 49 #define S3C2410_LCON_CS8 (0x3) 50 #define S3C2410_LCON_CSMASK (0x3) 51 52 #define S3C2410_LCON_PNONE (0x0) 53 #define S3C2410_LCON_PEVEN (0x5 << 3) 54 #define S3C2410_LCON_PODD (0x4 << 3) 55 #define S3C2410_LCON_PMASK (0x7 << 3) 56 57 #define S3C2410_LCON_STOPB (1<<2) 58 #define S3C2410_LCON_IRM (1<<6) 59 60 #define S3C2440_UCON_CLKMASK (3<<10) 61 #define S3C2440_UCON_CLKSHIFT (10) 62 #define S3C2440_UCON_PCLK (0<<10) 63 #define S3C2440_UCON_UCLK (1<<10) 64 #define S3C2440_UCON_PCLK2 (2<<10) 65 #define S3C2440_UCON_FCLK (3<<10) 66 #define S3C2443_UCON_EPLL (3<<10) 67 68 #define S3C6400_UCON_CLKMASK (3<<10) 69 #define S3C6400_UCON_CLKSHIFT (10) 70 #define S3C6400_UCON_PCLK (0<<10) 71 #define S3C6400_UCON_PCLK2 (2<<10) 72 #define S3C6400_UCON_UCLK0 (1<<10) 73 #define S3C6400_UCON_UCLK1 (3<<10) 74 75 #define S3C2440_UCON2_FCLK_EN (1<<15) 76 #define S3C2440_UCON0_DIVMASK (15 << 12) 77 #define S3C2440_UCON1_DIVMASK (15 << 12) 78 #define S3C2440_UCON2_DIVMASK (7 << 12) 79 #define S3C2440_UCON_DIVSHIFT (12) 80 81 #define S3C2412_UCON_CLKMASK (3<<10) 82 #define S3C2412_UCON_CLKSHIFT (10) 83 #define S3C2412_UCON_UCLK (1<<10) 84 #define S3C2412_UCON_USYSCLK (3<<10) 85 #define S3C2412_UCON_PCLK (0<<10) 86 #define S3C2412_UCON_PCLK2 (2<<10) 87 88 #define S3C2410_UCON_CLKMASK (1 << 10) 89 #define S3C2410_UCON_CLKSHIFT (10) 90 #define S3C2410_UCON_UCLK (1<<10) 91 #define S3C2410_UCON_SBREAK (1<<4) 92 93 #define S3C2410_UCON_TXILEVEL (1<<9) 94 #define S3C2410_UCON_RXILEVEL (1<<8) 95 #define S3C2410_UCON_TXIRQMODE (1<<2) 96 #define S3C2410_UCON_RXIRQMODE (1<<0) 97 #define S3C2410_UCON_RXFIFO_TOI (1<<7) 98 #define S3C2443_UCON_RXERR_IRQEN (1<<6) 99 #define S3C2443_UCON_LOOPBACK (1<<5) 100 101 #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 102 S3C2410_UCON_RXILEVEL | \ 103 S3C2410_UCON_TXIRQMODE | \ 104 S3C2410_UCON_RXIRQMODE | \ 105 S3C2410_UCON_RXFIFO_TOI) 106 107 #define S3C2410_UFCON_FIFOMODE (1<<0) 108 #define S3C2410_UFCON_TXTRIG0 (0<<6) 109 #define S3C2410_UFCON_RXTRIG8 (1<<4) 110 #define S3C2410_UFCON_RXTRIG12 (2<<4) 111 112 /* S3C2440 FIFO trigger levels */ 113 #define S3C2440_UFCON_RXTRIG1 (0<<4) 114 #define S3C2440_UFCON_RXTRIG8 (1<<4) 115 #define S3C2440_UFCON_RXTRIG16 (2<<4) 116 #define S3C2440_UFCON_RXTRIG32 (3<<4) 117 118 #define S3C2440_UFCON_TXTRIG0 (0<<6) 119 #define S3C2440_UFCON_TXTRIG16 (1<<6) 120 #define S3C2440_UFCON_TXTRIG32 (2<<6) 121 #define S3C2440_UFCON_TXTRIG48 (3<<6) 122 123 #define S3C2410_UFCON_RESETBOTH (3<<1) 124 #define S3C2410_UFCON_RESETTX (1<<2) 125 #define S3C2410_UFCON_RESETRX (1<<1) 126 127 #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 128 S3C2410_UFCON_TXTRIG0 | \ 129 S3C2410_UFCON_RXTRIG8 ) 130 131 #define S3C2410_UMCOM_AFC (1<<4) 132 #define S3C2410_UMCOM_RTS_LOW (1<<0) 133 134 #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ 135 #define S3C2412_UMCON_AFC_56 (1<<5) 136 #define S3C2412_UMCON_AFC_48 (2<<5) 137 #define S3C2412_UMCON_AFC_40 (3<<5) 138 #define S3C2412_UMCON_AFC_32 (4<<5) 139 #define S3C2412_UMCON_AFC_24 (5<<5) 140 #define S3C2412_UMCON_AFC_16 (6<<5) 141 #define S3C2412_UMCON_AFC_8 (7<<5) 142 143 #define S3C2410_UFSTAT_TXFULL (1<<9) 144 #define S3C2410_UFSTAT_RXFULL (1<<8) 145 #define S3C2410_UFSTAT_TXMASK (15<<4) 146 #define S3C2410_UFSTAT_TXSHIFT (4) 147 #define S3C2410_UFSTAT_RXMASK (15<<0) 148 #define S3C2410_UFSTAT_RXSHIFT (0) 149 150 /* UFSTAT S3C2443 same as S3C2440 */ 151 #define S3C2440_UFSTAT_TXFULL (1<<14) 152 #define S3C2440_UFSTAT_RXFULL (1<<6) 153 #define S3C2440_UFSTAT_TXSHIFT (8) 154 #define S3C2440_UFSTAT_RXSHIFT (0) 155 #define S3C2440_UFSTAT_TXMASK (63<<8) 156 #define S3C2440_UFSTAT_RXMASK (63) 157 158 #define S3C2410_UTRSTAT_TXE (1<<2) 159 #define S3C2410_UTRSTAT_TXFE (1<<1) 160 #define S3C2410_UTRSTAT_RXDR (1<<0) 161 162 #define S3C2410_UERSTAT_OVERRUN (1<<0) 163 #define S3C2410_UERSTAT_FRAME (1<<2) 164 #define S3C2410_UERSTAT_BREAK (1<<3) 165 #define S3C2443_UERSTAT_PARITY (1<<1) 166 167 #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ 168 S3C2410_UERSTAT_FRAME | \ 169 S3C2410_UERSTAT_BREAK) 170 171 #define S3C2410_UMSTAT_CTS (1<<0) 172 #define S3C2410_UMSTAT_DeltaCTS (1<<2) 173 174 #define S3C2443_DIVSLOT (0x2C) 175 176 /* S3C64XX interrupt registers. */ 177 #define S3C64XX_UINTP 0x30 178 #define S3C64XX_UINTSP 0x34 179 #define S3C64XX_UINTM 0x38 180 181 #define S3C64XX_UINTM_RXD (0) 182 #define S3C64XX_UINTM_TXD (2) 183 #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD) 184 #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD) 185 186 /* Following are specific to S5PV210 */ 187 #define S5PV210_UCON_CLKMASK (1<<10) 188 #define S5PV210_UCON_CLKSHIFT (10) 189 #define S5PV210_UCON_PCLK (0<<10) 190 #define S5PV210_UCON_UCLK (1<<10) 191 192 #define S5PV210_UFCON_TXTRIG0 (0<<8) 193 #define S5PV210_UFCON_TXTRIG4 (1<<8) 194 #define S5PV210_UFCON_TXTRIG8 (2<<8) 195 #define S5PV210_UFCON_TXTRIG16 (3<<8) 196 #define S5PV210_UFCON_TXTRIG32 (4<<8) 197 #define S5PV210_UFCON_TXTRIG64 (5<<8) 198 #define S5PV210_UFCON_TXTRIG128 (6<<8) 199 #define S5PV210_UFCON_TXTRIG256 (7<<8) 200 201 #define S5PV210_UFCON_RXTRIG1 (0<<4) 202 #define S5PV210_UFCON_RXTRIG4 (1<<4) 203 #define S5PV210_UFCON_RXTRIG8 (2<<4) 204 #define S5PV210_UFCON_RXTRIG16 (3<<4) 205 #define S5PV210_UFCON_RXTRIG32 (4<<4) 206 #define S5PV210_UFCON_RXTRIG64 (5<<4) 207 #define S5PV210_UFCON_RXTRIG128 (6<<4) 208 #define S5PV210_UFCON_RXTRIG256 (7<<4) 209 210 #define S5PV210_UFSTAT_TXFULL (1<<24) 211 #define S5PV210_UFSTAT_RXFULL (1<<8) 212 #define S5PV210_UFSTAT_TXMASK (255<<16) 213 #define S5PV210_UFSTAT_TXSHIFT (16) 214 #define S5PV210_UFSTAT_RXMASK (255<<0) 215 #define S5PV210_UFSTAT_RXSHIFT (0) 216 217 #define S3C2410_UCON_CLKSEL0 (1 << 0) 218 #define S3C2410_UCON_CLKSEL1 (1 << 1) 219 #define S3C2410_UCON_CLKSEL2 (1 << 2) 220 #define S3C2410_UCON_CLKSEL3 (1 << 3) 221 222 /* Default values for s5pv210 UCON and UFCON uart registers */ 223 #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 224 S3C2410_UCON_RXILEVEL | \ 225 S3C2410_UCON_TXIRQMODE | \ 226 S3C2410_UCON_RXIRQMODE | \ 227 S3C2410_UCON_RXFIFO_TOI | \ 228 S3C2443_UCON_RXERR_IRQEN) 229 230 #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 231 S5PV210_UFCON_TXTRIG4 | \ 232 S5PV210_UFCON_RXTRIG4) 233 234 #ifndef __ASSEMBLY__ 235 236 #include <linux/serial_core.h> 237 238 /* configuration structure for per-machine configurations for the 239 * serial port 240 * 241 * the pointer is setup by the machine specific initialisation from the 242 * arch/arm/mach-s3c2410/ directory. 243 */ 244 245 struct s3c2410_uartcfg { 246 unsigned char hwport; /* hardware port number */ 247 unsigned char unused; 248 unsigned short flags; 249 upf_t uart_flags; /* default uart flags */ 250 unsigned int clk_sel; 251 252 unsigned int has_fracval; 253 254 unsigned long ucon; /* value of ucon for port */ 255 unsigned long ulcon; /* value of ulcon for port */ 256 unsigned long ufcon; /* value of ufcon for port */ 257 }; 258 259 #endif /* __ASSEMBLY__ */ 260 261 #endif /* __ASM_ARM_REGS_SERIAL_H */ 262 263