1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __TI_SYSC_DATA_H__ 4 #define __TI_SYSC_DATA_H__ 5 6 enum ti_sysc_module_type { 7 TI_SYSC_OMAP2, 8 TI_SYSC_OMAP2_TIMER, 9 TI_SYSC_OMAP3_SHAM, 10 TI_SYSC_OMAP3_AES, 11 TI_SYSC_OMAP4, 12 TI_SYSC_OMAP4_TIMER, 13 TI_SYSC_OMAP4_SIMPLE, 14 TI_SYSC_OMAP34XX_SR, 15 TI_SYSC_OMAP36XX_SR, 16 TI_SYSC_OMAP4_SR, 17 TI_SYSC_OMAP4_MCASP, 18 TI_SYSC_OMAP4_USB_HOST_FS, 19 TI_SYSC_DRA7_MCAN, 20 }; 21 22 struct ti_sysc_cookie { 23 void *data; 24 void *clkdm; 25 }; 26 27 /** 28 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 29 * @midle_shift: Offset of the midle bit 30 * @clkact_shift: Offset of the clockactivity bit 31 * @sidle_shift: Offset of the sidle bit 32 * @enwkup_shift: Offset of the enawakeup bit 33 * @srst_shift: Offset of the softreset bit 34 * @autoidle_shift: Offset of the autoidle bit 35 * @dmadisable_shift: Offset of the dmadisable bit 36 * @emufree_shift; Offset of the emufree bit 37 * 38 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 39 * feature is not available. 40 */ 41 struct sysc_regbits { 42 s8 midle_shift; 43 s8 clkact_shift; 44 s8 sidle_shift; 45 s8 enwkup_shift; 46 s8 srst_shift; 47 s8 autoidle_shift; 48 s8 dmadisable_shift; 49 s8 emufree_shift; 50 }; 51 52 #define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22) 53 #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21) 54 #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) 55 #define SYSC_MODULE_QUIRK_AESS BIT(19) 56 #define SYSC_MODULE_QUIRK_SGX BIT(18) 57 #define SYSC_MODULE_QUIRK_HDQ1W BIT(17) 58 #define SYSC_MODULE_QUIRK_I2C BIT(16) 59 #define SYSC_MODULE_QUIRK_WDT BIT(15) 60 #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) 61 #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) 62 #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) 63 #define SYSC_QUIRK_SWSUP_SIDLE BIT(11) 64 #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) 65 #define SYSC_QUIRK_LEGACY_IDLE BIT(9) 66 #define SYSC_QUIRK_RESET_STATUS BIT(8) 67 #define SYSC_QUIRK_NO_IDLE BIT(7) 68 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 69 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 70 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 71 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 72 #define SYSC_QUIRK_16BIT BIT(2) 73 #define SYSC_QUIRK_UNCACHED BIT(1) 74 #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 75 76 #define SYSC_NR_IDLEMODES 4 77 78 /** 79 * struct sysc_capabilities - capabilities for an interconnect target module 80 * @type: sysc type identifier for the module 81 * @sysc_mask: bitmask of supported SYSCONFIG register bits 82 * @regbits: bitmask of SYSCONFIG register bits 83 * @mod_quirks: bitmask of module specific quirks 84 */ 85 struct sysc_capabilities { 86 const enum ti_sysc_module_type type; 87 const u32 sysc_mask; 88 const struct sysc_regbits *regbits; 89 const u32 mod_quirks; 90 }; 91 92 /** 93 * struct sysc_config - configuration for an interconnect target module 94 * @sysc_val: configured value for sysc register 95 * @syss_mask: configured mask value for SYSSTATUS register 96 * @midlemodes: bitmask of supported master idle modes 97 * @sidlemodes: bitmask of supported slave idle modes 98 * @srst_udelay: optional delay needed after OCP soft reset 99 * @quirks: bitmask of enabled quirks 100 */ 101 struct sysc_config { 102 u32 sysc_val; 103 u32 syss_mask; 104 u8 midlemodes; 105 u8 sidlemodes; 106 u8 srst_udelay; 107 u32 quirks; 108 }; 109 110 enum sysc_registers { 111 SYSC_REVISION, 112 SYSC_SYSCONFIG, 113 SYSC_SYSSTATUS, 114 SYSC_MAX_REGS, 115 }; 116 117 /** 118 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module 119 * @name: legacy "ti,hwmods" module name 120 * @module_pa: physical address of the interconnect target module 121 * @module_size: size of the interconnect target module 122 * @offsets: array of register offsets as listed in enum sysc_registers 123 * @nr_offsets: number of registers 124 * @cap: interconnect target module capabilities 125 * @cfg: interconnect target module configuration 126 * 127 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig 128 * based on device tree data parsed by ti-sysc driver. 129 */ 130 struct ti_sysc_module_data { 131 const char *name; 132 u64 module_pa; 133 u32 module_size; 134 int *offsets; 135 int nr_offsets; 136 const struct sysc_capabilities *cap; 137 struct sysc_config *cfg; 138 }; 139 140 struct device; 141 struct clk; 142 143 struct ti_sysc_platform_data { 144 struct of_dev_auxdata *auxdata; 145 bool (*soc_type_gp)(void); 146 int (*init_clockdomain)(struct device *dev, struct clk *fck, 147 struct clk *ick, struct ti_sysc_cookie *cookie); 148 void (*clkdm_deny_idle)(struct device *dev, 149 const struct ti_sysc_cookie *cookie); 150 void (*clkdm_allow_idle)(struct device *dev, 151 const struct ti_sysc_cookie *cookie); 152 int (*init_module)(struct device *dev, 153 const struct ti_sysc_module_data *data, 154 struct ti_sysc_cookie *cookie); 155 int (*enable_module)(struct device *dev, 156 const struct ti_sysc_cookie *cookie); 157 int (*idle_module)(struct device *dev, 158 const struct ti_sysc_cookie *cookie); 159 int (*shutdown_module)(struct device *dev, 160 const struct ti_sysc_cookie *cookie); 161 }; 162 163 #endif /* __TI_SYSC_DATA_H__ */ 164