1 #ifndef __TI_SYSC_DATA_H__ 2 #define __TI_SYSC_DATA_H__ 3 4 enum ti_sysc_module_type { 5 TI_SYSC_OMAP2, 6 TI_SYSC_OMAP2_TIMER, 7 TI_SYSC_OMAP3_SHAM, 8 TI_SYSC_OMAP3_AES, 9 TI_SYSC_OMAP4, 10 TI_SYSC_OMAP4_TIMER, 11 TI_SYSC_OMAP4_SIMPLE, 12 TI_SYSC_OMAP34XX_SR, 13 TI_SYSC_OMAP36XX_SR, 14 TI_SYSC_OMAP4_SR, 15 TI_SYSC_OMAP4_MCASP, 16 TI_SYSC_OMAP4_USB_HOST_FS, 17 TI_SYSC_DRA7_MCAN, 18 }; 19 20 struct ti_sysc_cookie { 21 void *data; 22 }; 23 24 /** 25 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets 26 * @midle_shift: Offset of the midle bit 27 * @clkact_shift: Offset of the clockactivity bit 28 * @sidle_shift: Offset of the sidle bit 29 * @enwkup_shift: Offset of the enawakeup bit 30 * @srst_shift: Offset of the softreset bit 31 * @autoidle_shift: Offset of the autoidle bit 32 * @dmadisable_shift: Offset of the dmadisable bit 33 * @emufree_shift; Offset of the emufree bit 34 * 35 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a 36 * feature is not available. 37 */ 38 struct sysc_regbits { 39 s8 midle_shift; 40 s8 clkact_shift; 41 s8 sidle_shift; 42 s8 enwkup_shift; 43 s8 srst_shift; 44 s8 autoidle_shift; 45 s8 dmadisable_shift; 46 s8 emufree_shift; 47 }; 48 49 #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) 50 #define SYSC_QUIRK_LEGACY_IDLE BIT(9) 51 #define SYSC_QUIRK_RESET_STATUS BIT(8) 52 #define SYSC_QUIRK_NO_IDLE BIT(7) 53 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) 54 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) 55 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) 56 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3) 57 #define SYSC_QUIRK_16BIT BIT(2) 58 #define SYSC_QUIRK_UNCACHED BIT(1) 59 #define SYSC_QUIRK_USE_CLOCKACT BIT(0) 60 61 #define SYSC_NR_IDLEMODES 4 62 63 /** 64 * struct sysc_capabilities - capabilities for an interconnect target module 65 * 66 * @sysc_mask: bitmask of supported SYSCONFIG register bits 67 * @regbits: bitmask of SYSCONFIG register bits 68 * @mod_quirks: bitmask of module specific quirks 69 */ 70 struct sysc_capabilities { 71 const enum ti_sysc_module_type type; 72 const u32 sysc_mask; 73 const struct sysc_regbits *regbits; 74 const u32 mod_quirks; 75 }; 76 77 /** 78 * struct sysc_config - configuration for an interconnect target module 79 * @sysc_val: configured value for sysc register 80 * @midlemodes: bitmask of supported master idle modes 81 * @sidlemodes: bitmask of supported master idle modes 82 * @srst_udelay: optional delay needed after OCP soft reset 83 * @quirks: bitmask of enabled quirks 84 */ 85 struct sysc_config { 86 u32 sysc_val; 87 u32 syss_mask; 88 u8 midlemodes; 89 u8 sidlemodes; 90 u8 srst_udelay; 91 u32 quirks; 92 }; 93 94 enum sysc_registers { 95 SYSC_REVISION, 96 SYSC_SYSCONFIG, 97 SYSC_SYSSTATUS, 98 SYSC_MAX_REGS, 99 }; 100 101 /** 102 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module 103 * @name: legacy "ti,hwmods" module name 104 * @module_pa: physical address of the interconnect target module 105 * @module_size: size of the interconnect target module 106 * @offsets: array of register offsets as listed in enum sysc_registers 107 * @nr_offsets: number of registers 108 * @cap: interconnect target module capabilities 109 * @cfg: interconnect target module configuration 110 * 111 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig 112 * based on device tree data parsed by ti-sysc driver. 113 */ 114 struct ti_sysc_module_data { 115 const char *name; 116 u64 module_pa; 117 u32 module_size; 118 int *offsets; 119 int nr_offsets; 120 const struct sysc_capabilities *cap; 121 struct sysc_config *cfg; 122 }; 123 124 struct device; 125 126 struct ti_sysc_platform_data { 127 struct of_dev_auxdata *auxdata; 128 int (*init_module)(struct device *dev, 129 const struct ti_sysc_module_data *data, 130 struct ti_sysc_cookie *cookie); 131 int (*enable_module)(struct device *dev, 132 const struct ti_sysc_cookie *cookie); 133 int (*idle_module)(struct device *dev, 134 const struct ti_sysc_cookie *cookie); 135 int (*shutdown_module)(struct device *dev, 136 const struct ti_sysc_cookie *cookie); 137 }; 138 139 #endif /* __TI_SYSC_DATA_H__ */ 140