1 /* 2 * Core driver interface to access RICOH_RC5T583 power management chip. 3 * 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 5 * Author: Laxman dewangan <[email protected]> 6 * 7 * Based on code 8 * Copyright (C) 2011 RICOH COMPANY,LTD 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24 #ifndef __LINUX_MFD_RC5T583_H 25 #define __LINUX_MFD_RC5T583_H 26 27 #include <linux/mutex.h> 28 #include <linux/types.h> 29 #include <linux/regmap.h> 30 31 #define RC5T583_MAX_REGS 0xF8 32 33 /* Maximum number of main interrupts */ 34 #define MAX_MAIN_INTERRUPT 5 35 #define RC5T583_MAX_GPEDGE_REG 2 36 #define RC5T583_MAX_INTERRUPT_MASK_REGS 9 37 38 /* Interrupt enable register */ 39 #define RC5T583_INT_EN_SYS1 0x19 40 #define RC5T583_INT_EN_SYS2 0x1D 41 #define RC5T583_INT_EN_DCDC 0x41 42 #define RC5T583_INT_EN_RTC 0xED 43 #define RC5T583_INT_EN_ADC1 0x90 44 #define RC5T583_INT_EN_ADC2 0x91 45 #define RC5T583_INT_EN_ADC3 0x92 46 47 /* Interrupt status registers (monitor regs in Ricoh)*/ 48 #define RC5T583_INTC_INTPOL 0xAD 49 #define RC5T583_INTC_INTEN 0xAE 50 #define RC5T583_INTC_INTMON 0xAF 51 52 #define RC5T583_INT_MON_GRP 0xAF 53 #define RC5T583_INT_MON_SYS1 0x1B 54 #define RC5T583_INT_MON_SYS2 0x1F 55 #define RC5T583_INT_MON_DCDC 0x43 56 #define RC5T583_INT_MON_RTC 0xEE 57 58 /* Interrupt clearing registers */ 59 #define RC5T583_INT_IR_SYS1 0x1A 60 #define RC5T583_INT_IR_SYS2 0x1E 61 #define RC5T583_INT_IR_DCDC 0x42 62 #define RC5T583_INT_IR_RTC 0xEE 63 #define RC5T583_INT_IR_ADCL 0x94 64 #define RC5T583_INT_IR_ADCH 0x95 65 #define RC5T583_INT_IR_ADCEND 0x96 66 #define RC5T583_INT_IR_GPIOR 0xA9 67 #define RC5T583_INT_IR_GPIOF 0xAA 68 69 /* Sleep sequence registers */ 70 #define RC5T583_SLPSEQ1 0x21 71 #define RC5T583_SLPSEQ2 0x22 72 #define RC5T583_SLPSEQ3 0x23 73 #define RC5T583_SLPSEQ4 0x24 74 #define RC5T583_SLPSEQ5 0x25 75 #define RC5T583_SLPSEQ6 0x26 76 #define RC5T583_SLPSEQ7 0x27 77 #define RC5T583_SLPSEQ8 0x28 78 #define RC5T583_SLPSEQ9 0x29 79 #define RC5T583_SLPSEQ10 0x2A 80 #define RC5T583_SLPSEQ11 0x2B 81 82 /* Regulator registers */ 83 #define RC5T583_REG_DC0CTL 0x30 84 #define RC5T583_REG_DC0DAC 0x31 85 #define RC5T583_REG_DC0LATCTL 0x32 86 #define RC5T583_REG_SR0CTL 0x33 87 88 #define RC5T583_REG_DC1CTL 0x34 89 #define RC5T583_REG_DC1DAC 0x35 90 #define RC5T583_REG_DC1LATCTL 0x36 91 #define RC5T583_REG_SR1CTL 0x37 92 93 #define RC5T583_REG_DC2CTL 0x38 94 #define RC5T583_REG_DC2DAC 0x39 95 #define RC5T583_REG_DC2LATCTL 0x3A 96 #define RC5T583_REG_SR2CTL 0x3B 97 98 #define RC5T583_REG_DC3CTL 0x3C 99 #define RC5T583_REG_DC3DAC 0x3D 100 #define RC5T583_REG_DC3LATCTL 0x3E 101 #define RC5T583_REG_SR3CTL 0x3F 102 103 104 #define RC5T583_REG_LDOEN1 0x50 105 #define RC5T583_REG_LDOEN2 0x51 106 #define RC5T583_REG_LDODIS1 0x52 107 #define RC5T583_REG_LDODIS2 0x53 108 109 #define RC5T583_REG_LDO0DAC 0x54 110 #define RC5T583_REG_LDO1DAC 0x55 111 #define RC5T583_REG_LDO2DAC 0x56 112 #define RC5T583_REG_LDO3DAC 0x57 113 #define RC5T583_REG_LDO4DAC 0x58 114 #define RC5T583_REG_LDO5DAC 0x59 115 #define RC5T583_REG_LDO6DAC 0x5A 116 #define RC5T583_REG_LDO7DAC 0x5B 117 #define RC5T583_REG_LDO8DAC 0x5C 118 #define RC5T583_REG_LDO9DAC 0x5D 119 120 #define RC5T583_REG_DC0DAC_DS 0x60 121 #define RC5T583_REG_DC1DAC_DS 0x61 122 #define RC5T583_REG_DC2DAC_DS 0x62 123 #define RC5T583_REG_DC3DAC_DS 0x63 124 125 #define RC5T583_REG_LDO0DAC_DS 0x64 126 #define RC5T583_REG_LDO1DAC_DS 0x65 127 #define RC5T583_REG_LDO2DAC_DS 0x66 128 #define RC5T583_REG_LDO3DAC_DS 0x67 129 #define RC5T583_REG_LDO4DAC_DS 0x68 130 #define RC5T583_REG_LDO5DAC_DS 0x69 131 #define RC5T583_REG_LDO6DAC_DS 0x6A 132 #define RC5T583_REG_LDO7DAC_DS 0x6B 133 #define RC5T583_REG_LDO8DAC_DS 0x6C 134 #define RC5T583_REG_LDO9DAC_DS 0x6D 135 136 /* GPIO register base address */ 137 #define RC5T583_GPIO_IOSEL 0xA0 138 #define RC5T583_GPIO_PDEN 0xA1 139 #define RC5T583_GPIO_IOOUT 0xA2 140 #define RC5T583_GPIO_PGSEL 0xA3 141 #define RC5T583_GPIO_GPINV 0xA4 142 #define RC5T583_GPIO_GPDEB 0xA5 143 #define RC5T583_GPIO_GPEDGE1 0xA6 144 #define RC5T583_GPIO_GPEDGE2 0xA7 145 #define RC5T583_GPIO_EN_INT 0xA8 146 #define RC5T583_GPIO_MON_IOIN 0xAB 147 #define RC5T583_GPIO_GPOFUNC 0xAC 148 149 /* RTC registers */ 150 #define RC5T583_RTC_SEC 0xE0 151 #define RC5T583_RTC_MIN 0xE1 152 #define RC5T583_RTC_HOUR 0xE2 153 #define RC5T583_RTC_WDAY 0xE3 154 #define RC5T583_RTC_DAY 0xE4 155 #define RC5T583_RTC_MONTH 0xE5 156 #define RC5T583_RTC_YEAR 0xE6 157 #define RC5T583_RTC_ADJ 0xE7 158 #define RC5T583_RTC_AW_MIN 0xE8 159 #define RC5T583_RTC_AW_HOUR 0xE9 160 #define RC5T583_RTC_AW_WEEK 0xEA 161 #define RC5T583_RTC_AD_MIN 0xEB 162 #define RC5T583_RTC_AD_HOUR 0xEC 163 #define RC5T583_RTC_CTL1 0xED 164 #define RC5T583_RTC_CTL2 0xEE 165 #define RC5T583_RTC_AY_MIN 0xF0 166 #define RC5T583_RTC_AY_HOUR 0xF1 167 #define RC5T583_RTC_AY_DAY 0xF2 168 #define RC5T583_RTC_AY_MONTH 0xF3 169 #define RC5T583_RTC_AY_YEAR 0xF4 170 171 /* RICOH_RC5T583 IRQ definitions */ 172 enum { 173 RC5T583_IRQ_ONKEY, 174 RC5T583_IRQ_ACOK, 175 RC5T583_IRQ_LIDOPEN, 176 RC5T583_IRQ_PREOT, 177 RC5T583_IRQ_CLKSTP, 178 RC5T583_IRQ_ONKEY_OFF, 179 RC5T583_IRQ_WD, 180 RC5T583_IRQ_EN_PWRREQ1, 181 RC5T583_IRQ_EN_PWRREQ2, 182 RC5T583_IRQ_PRE_VINDET, 183 184 RC5T583_IRQ_DC0LIM, 185 RC5T583_IRQ_DC1LIM, 186 RC5T583_IRQ_DC2LIM, 187 RC5T583_IRQ_DC3LIM, 188 189 RC5T583_IRQ_CTC, 190 RC5T583_IRQ_YALE, 191 RC5T583_IRQ_DALE, 192 RC5T583_IRQ_WALE, 193 194 RC5T583_IRQ_AIN1L, 195 RC5T583_IRQ_AIN2L, 196 RC5T583_IRQ_AIN3L, 197 RC5T583_IRQ_VBATL, 198 RC5T583_IRQ_VIN3L, 199 RC5T583_IRQ_VIN8L, 200 RC5T583_IRQ_AIN1H, 201 RC5T583_IRQ_AIN2H, 202 RC5T583_IRQ_AIN3H, 203 RC5T583_IRQ_VBATH, 204 RC5T583_IRQ_VIN3H, 205 RC5T583_IRQ_VIN8H, 206 RC5T583_IRQ_ADCEND, 207 208 RC5T583_IRQ_GPIO0, 209 RC5T583_IRQ_GPIO1, 210 RC5T583_IRQ_GPIO2, 211 RC5T583_IRQ_GPIO3, 212 RC5T583_IRQ_GPIO4, 213 RC5T583_IRQ_GPIO5, 214 RC5T583_IRQ_GPIO6, 215 RC5T583_IRQ_GPIO7, 216 217 /* Should be last entry */ 218 RC5T583_MAX_IRQS, 219 }; 220 221 /* Ricoh583 gpio definitions */ 222 enum { 223 RC5T583_GPIO0, 224 RC5T583_GPIO1, 225 RC5T583_GPIO2, 226 RC5T583_GPIO3, 227 RC5T583_GPIO4, 228 RC5T583_GPIO5, 229 RC5T583_GPIO6, 230 RC5T583_GPIO7, 231 232 /* Should be last entry */ 233 RC5T583_MAX_GPIO, 234 }; 235 236 enum { 237 RC5T583_DS_NONE, 238 RC5T583_DS_DC0, 239 RC5T583_DS_DC1, 240 RC5T583_DS_DC2, 241 RC5T583_DS_DC3, 242 RC5T583_DS_LDO0, 243 RC5T583_DS_LDO1, 244 RC5T583_DS_LDO2, 245 RC5T583_DS_LDO3, 246 RC5T583_DS_LDO4, 247 RC5T583_DS_LDO5, 248 RC5T583_DS_LDO6, 249 RC5T583_DS_LDO7, 250 RC5T583_DS_LDO8, 251 RC5T583_DS_LDO9, 252 RC5T583_DS_PSO0, 253 RC5T583_DS_PSO1, 254 RC5T583_DS_PSO2, 255 RC5T583_DS_PSO3, 256 RC5T583_DS_PSO4, 257 RC5T583_DS_PSO5, 258 RC5T583_DS_PSO6, 259 RC5T583_DS_PSO7, 260 261 /* Should be last entry */ 262 RC5T583_DS_MAX, 263 }; 264 265 /* 266 * Ricoh pmic RC5T583 supports sleep through two external controls. 267 * The output of gpios and regulator can be enable/disable through 268 * this external signals. 269 */ 270 enum { 271 RC5T583_EXT_PWRREQ1_CONTROL = 0x1, 272 RC5T583_EXT_PWRREQ2_CONTROL = 0x2, 273 }; 274 275 enum { 276 RC5T583_REGULATOR_DC0, 277 RC5T583_REGULATOR_DC1, 278 RC5T583_REGULATOR_DC2, 279 RC5T583_REGULATOR_DC3, 280 RC5T583_REGULATOR_LDO0, 281 RC5T583_REGULATOR_LDO1, 282 RC5T583_REGULATOR_LDO2, 283 RC5T583_REGULATOR_LDO3, 284 RC5T583_REGULATOR_LDO4, 285 RC5T583_REGULATOR_LDO5, 286 RC5T583_REGULATOR_LDO6, 287 RC5T583_REGULATOR_LDO7, 288 RC5T583_REGULATOR_LDO8, 289 RC5T583_REGULATOR_LDO9, 290 291 /* Should be last entry */ 292 RC5T583_REGULATOR_MAX, 293 }; 294 295 struct rc5t583 { 296 struct device *dev; 297 struct regmap *regmap; 298 int chip_irq; 299 int irq_base; 300 struct mutex irq_lock; 301 unsigned long group_irq_en[MAX_MAIN_INTERRUPT]; 302 303 /* For main interrupt bits in INTC */ 304 uint8_t intc_inten_reg; 305 306 /* For group interrupt bits and address */ 307 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS]; 308 309 /* For gpio edge */ 310 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG]; 311 }; 312 313 /* 314 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. 315 * The board specific data is provided through this structure. 316 * @irq_base: Irq base number on which this device registers their interrupts. 317 * @gpio_base: GPIO base from which gpio of this device will start. 318 * @enable_shutdown: Enable shutdown through the input pin "shutdown". 319 * @regulator_deepsleep_slot: The slot number on which device goes to sleep 320 * in device sleep mode. 321 * @regulator_ext_pwr_control: External power request regulator control. The 322 * regulator output enable/disable is controlled by the external 323 * power request input state. 324 * @reg_init_data: Regulator init data. 325 */ 326 327 struct rc5t583_platform_data { 328 int irq_base; 329 int gpio_base; 330 bool enable_shutdown; 331 int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX]; 332 unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX]; 333 struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX]; 334 }; 335 336 static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) 337 { 338 struct rc5t583 *rc5t583 = dev_get_drvdata(dev); 339 return regmap_write(rc5t583->regmap, reg, val); 340 } 341 342 static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) 343 { 344 struct rc5t583 *rc5t583 = dev_get_drvdata(dev); 345 unsigned int ival; 346 int ret; 347 ret = regmap_read(rc5t583->regmap, reg, &ival); 348 if (!ret) 349 *val = (uint8_t)ival; 350 return ret; 351 } 352 353 static inline int rc5t583_set_bits(struct device *dev, unsigned int reg, 354 unsigned int bit_mask) 355 { 356 struct rc5t583 *rc5t583 = dev_get_drvdata(dev); 357 return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask); 358 } 359 360 static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg, 361 unsigned int bit_mask) 362 { 363 struct rc5t583 *rc5t583 = dev_get_drvdata(dev); 364 return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0); 365 } 366 367 static inline int rc5t583_update(struct device *dev, unsigned int reg, 368 unsigned int val, unsigned int mask) 369 { 370 struct rc5t583 *rc5t583 = dev_get_drvdata(dev); 371 return regmap_update_bits(rc5t583->regmap, reg, mask, val); 372 } 373 374 int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id, 375 int ext_pwr_req, int deepsleep_slot_nr); 376 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base); 377 int rc5t583_irq_exit(struct rc5t583 *rc5t583); 378 379 #endif 380