1 /* 2 * include/linux/fsl_devices.h 3 * 4 * Definitions for any platform device related flags or structures for 5 * Freescale processor devices 6 * 7 * Maintainer: Kumar Gala <[email protected]> 8 * 9 * Copyright 2004 Freescale Semiconductor, Inc 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #ifdef __KERNEL__ 18 #ifndef _FSL_DEVICE_H_ 19 #define _FSL_DEVICE_H_ 20 21 #include <linux/types.h> 22 #include <linux/phy.h> 23 24 /* 25 * Some conventions on how we handle peripherals on Freescale chips 26 * 27 * unique device: a platform_device entry in fsl_plat_devs[] plus 28 * associated device information in its platform_data structure. 29 * 30 * A chip is described by a set of unique devices. 31 * 32 * Each sub-arch has its own master list of unique devices and 33 * enumerates them by enum fsl_devices in a sub-arch specific header 34 * 35 * The platform data structure is broken into two parts. The 36 * first is device specific information that help identify any 37 * unique features of a peripheral. The second is any 38 * information that may be defined by the board or how the device 39 * is connected externally of the chip. 40 * 41 * naming conventions: 42 * - platform data structures: <driver>_platform_data 43 * - platform data device flags: FSL_<driver>_DEV_<FLAG> 44 * - platform data board flags: FSL_<driver>_BRD_<FLAG> 45 * 46 */ 47 48 struct gianfar_platform_data { 49 /* device specific information */ 50 u32 device_flags; 51 /* board specific information */ 52 u32 board_flags; 53 u32 bus_id; 54 u32 phy_id; 55 u8 mac_addr[6]; 56 }; 57 58 struct gianfar_mdio_data { 59 /* board specific information */ 60 int irq[32]; 61 }; 62 63 /* Flags related to gianfar device features */ 64 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 65 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 66 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 67 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 68 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 69 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 70 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 71 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 72 73 /* Flags in gianfar_platform_data */ 74 #define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */ 75 #define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */ 76 77 struct fsl_i2c_platform_data { 78 /* device specific information */ 79 u32 device_flags; 80 }; 81 82 /* Flags related to I2C device features */ 83 #define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001 84 #define FSL_I2C_DEV_CLOCK_5200 0x00000002 85 86 enum fsl_usb2_operating_modes { 87 FSL_USB2_MPH_HOST, 88 FSL_USB2_DR_HOST, 89 FSL_USB2_DR_DEVICE, 90 FSL_USB2_DR_OTG, 91 }; 92 93 enum fsl_usb2_phy_modes { 94 FSL_USB2_PHY_NONE, 95 FSL_USB2_PHY_ULPI, 96 FSL_USB2_PHY_UTMI, 97 FSL_USB2_PHY_UTMI_WIDE, 98 FSL_USB2_PHY_SERIAL, 99 }; 100 101 struct fsl_usb2_platform_data { 102 /* board specific information */ 103 enum fsl_usb2_operating_modes operating_mode; 104 enum fsl_usb2_phy_modes phy_mode; 105 unsigned int port_enables; 106 }; 107 108 /* Flags in fsl_usb2_mph_platform_data */ 109 #define FSL_USB2_PORT0_ENABLED 0x00000001 110 #define FSL_USB2_PORT1_ENABLED 0x00000002 111 112 struct fsl_spi_platform_data { 113 u32 initial_spmode; /* initial SPMODE value */ 114 u16 bus_num; 115 116 /* board specific information */ 117 u16 max_chipselect; 118 void (*activate_cs)(u8 cs, u8 polarity); 119 void (*deactivate_cs)(u8 cs, u8 polarity); 120 u32 sysclk; 121 }; 122 123 #endif /* _FSL_DEVICE_H_ */ 124 #endif /* __KERNEL__ */ 125