1 /* 2 * include/linux/fsl_devices.h 3 * 4 * Definitions for any platform device related flags or structures for 5 * Freescale processor devices 6 * 7 * Maintainer: Kumar Gala <[email protected]> 8 * 9 * Copyright 2004 Freescale Semiconductor, Inc 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #ifndef _FSL_DEVICE_H_ 18 #define _FSL_DEVICE_H_ 19 20 #include <linux/types.h> 21 #include <linux/phy.h> 22 23 /* 24 * Some conventions on how we handle peripherals on Freescale chips 25 * 26 * unique device: a platform_device entry in fsl_plat_devs[] plus 27 * associated device information in its platform_data structure. 28 * 29 * A chip is described by a set of unique devices. 30 * 31 * Each sub-arch has its own master list of unique devices and 32 * enumerates them by enum fsl_devices in a sub-arch specific header 33 * 34 * The platform data structure is broken into two parts. The 35 * first is device specific information that help identify any 36 * unique features of a peripheral. The second is any 37 * information that may be defined by the board or how the device 38 * is connected externally of the chip. 39 * 40 * naming conventions: 41 * - platform data structures: <driver>_platform_data 42 * - platform data device flags: FSL_<driver>_DEV_<FLAG> 43 * - platform data board flags: FSL_<driver>_BRD_<FLAG> 44 * 45 */ 46 47 struct gianfar_platform_data { 48 /* device specific information */ 49 u32 device_flags; 50 /* board specific information */ 51 u32 board_flags; 52 int mdio_bus; /* Bus controlled by us */ 53 char bus_id[MII_BUS_ID_SIZE]; /* Bus PHY is on */ 54 u32 phy_id; 55 u8 mac_addr[6]; 56 phy_interface_t interface; 57 }; 58 59 struct gianfar_mdio_data { 60 /* board specific information */ 61 int irq[32]; 62 }; 63 64 /* Flags related to gianfar device features */ 65 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 66 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 67 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 68 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 69 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 70 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 71 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 72 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 73 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 74 75 /* Flags in gianfar_platform_data */ 76 #define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */ 77 #define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */ 78 79 struct fsl_i2c_platform_data { 80 /* device specific information */ 81 u32 device_flags; 82 }; 83 84 /* Flags related to I2C device features */ 85 #define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001 86 #define FSL_I2C_DEV_CLOCK_5200 0x00000002 87 88 enum fsl_usb2_operating_modes { 89 FSL_USB2_MPH_HOST, 90 FSL_USB2_DR_HOST, 91 FSL_USB2_DR_DEVICE, 92 FSL_USB2_DR_OTG, 93 }; 94 95 enum fsl_usb2_phy_modes { 96 FSL_USB2_PHY_NONE, 97 FSL_USB2_PHY_ULPI, 98 FSL_USB2_PHY_UTMI, 99 FSL_USB2_PHY_UTMI_WIDE, 100 FSL_USB2_PHY_SERIAL, 101 }; 102 103 struct fsl_usb2_platform_data { 104 /* board specific information */ 105 enum fsl_usb2_operating_modes operating_mode; 106 enum fsl_usb2_phy_modes phy_mode; 107 unsigned int port_enables; 108 }; 109 110 /* Flags in fsl_usb2_mph_platform_data */ 111 #define FSL_USB2_PORT0_ENABLED 0x00000001 112 #define FSL_USB2_PORT1_ENABLED 0x00000002 113 114 struct fsl_spi_platform_data { 115 u32 initial_spmode; /* initial SPMODE value */ 116 u16 bus_num; 117 bool qe_mode; 118 /* board specific information */ 119 u16 max_chipselect; 120 void (*activate_cs)(u8 cs, u8 polarity); 121 void (*deactivate_cs)(u8 cs, u8 polarity); 122 u32 sysclk; 123 }; 124 125 struct mpc8xx_pcmcia_ops { 126 void(*hw_ctrl)(int slot, int enable); 127 int(*voltage_set)(int slot, int vcc, int vpp); 128 }; 129 130 /* Returns non-zero if the current suspend operation would 131 * lead to a deep sleep (i.e. power removed from the core, 132 * instead of just the clock). 133 */ 134 int fsl_deep_sleep(void); 135 136 #endif /* _FSL_DEVICE_H_ */ 137