1 /* 2 * TI clock drivers support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef __LINUX_CLK_TI_H__ 16 #define __LINUX_CLK_TI_H__ 17 18 #include <linux/clkdev.h> 19 20 /** 21 * struct dpll_data - DPLL registers and integration data 22 * @mult_div1_reg: register containing the DPLL M and N bitfields 23 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg 24 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg 25 * @clk_bypass: struct clk pointer to the clock's bypass clock input 26 * @clk_ref: struct clk pointer to the clock's reference clock input 27 * @control_reg: register containing the DPLL mode bitfield 28 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 29 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 30 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 31 * @last_rounded_m4xen: cache of the last M4X result of 32 * omap4_dpll_regm4xen_round_rate() 33 * @last_rounded_lpmode: cache of the last lpmode result of 34 * omap4_dpll_lpmode_recalc() 35 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 36 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() 37 * @min_divider: minimum valid non-bypass divider value (actual) 38 * @max_divider: maximum valid non-bypass divider value (actual) 39 * @modes: possible values of @enable_mask 40 * @autoidle_reg: register containing the DPLL autoidle mode bitfield 41 * @idlest_reg: register containing the DPLL idle status bitfield 42 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 43 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 44 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg 45 * @dcc_rate: rate atleast which DCC @dcc_mask must be set 46 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 47 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg 48 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg 49 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg 50 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs 51 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs 52 * @flags: DPLL type/features (see below) 53 * 54 * Possible values for @flags: 55 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) 56 * 57 * @freqsel_mask is only used on the OMAP34xx family and AM35xx. 58 * 59 * XXX Some DPLLs have multiple bypass inputs, so it's not technically 60 * correct to only have one @clk_bypass pointer. 61 * 62 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, 63 * @last_rounded_n) should be separated from the runtime-fixed fields 64 * and placed into a different structure, so that the runtime-fixed data 65 * can be placed into read-only space. 66 */ 67 struct dpll_data { 68 void __iomem *mult_div1_reg; 69 u32 mult_mask; 70 u32 div1_mask; 71 struct clk *clk_bypass; 72 struct clk *clk_ref; 73 void __iomem *control_reg; 74 u32 enable_mask; 75 unsigned long last_rounded_rate; 76 u16 last_rounded_m; 77 u8 last_rounded_m4xen; 78 u8 last_rounded_lpmode; 79 u16 max_multiplier; 80 u8 last_rounded_n; 81 u8 min_divider; 82 u16 max_divider; 83 u8 modes; 84 void __iomem *autoidle_reg; 85 void __iomem *idlest_reg; 86 u32 autoidle_mask; 87 u32 freqsel_mask; 88 u32 idlest_mask; 89 u32 dco_mask; 90 u32 sddiv_mask; 91 u32 dcc_mask; 92 unsigned long dcc_rate; 93 u32 lpmode_mask; 94 u32 m4xen_mask; 95 u8 auto_recal_bit; 96 u8 recal_en_bit; 97 u8 recal_st_bit; 98 u8 flags; 99 }; 100 101 struct clk_hw_omap; 102 103 /** 104 * struct clk_hw_omap_ops - OMAP clk ops 105 * @find_idlest: find idlest register information for a clock 106 * @find_companion: find companion clock register information for a clock, 107 * basically converts CM_ICLKEN* <-> CM_FCLKEN* 108 * @allow_idle: enables autoidle hardware functionality for a clock 109 * @deny_idle: prevent autoidle hardware functionality for a clock 110 */ 111 struct clk_hw_omap_ops { 112 void (*find_idlest)(struct clk_hw_omap *oclk, 113 void __iomem **idlest_reg, 114 u8 *idlest_bit, u8 *idlest_val); 115 void (*find_companion)(struct clk_hw_omap *oclk, 116 void __iomem **other_reg, 117 u8 *other_bit); 118 void (*allow_idle)(struct clk_hw_omap *oclk); 119 void (*deny_idle)(struct clk_hw_omap *oclk); 120 }; 121 122 /** 123 * struct clk_hw_omap - OMAP struct clk 124 * @node: list_head connecting this clock into the full clock list 125 * @enable_reg: register to write to enable the clock (see @enable_bit) 126 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) 127 * @flags: see "struct clk.flags possibilities" above 128 * @clksel_reg: for clksel clks, register va containing src/divisor select 129 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector 130 * @clksel: for clksel clks, pointer to struct clksel for this clock 131 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock 132 * @clkdm_name: clockdomain name that this clock is contained in 133 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime 134 * @ops: clock ops for this clock 135 */ 136 struct clk_hw_omap { 137 struct clk_hw hw; 138 struct list_head node; 139 unsigned long fixed_rate; 140 u8 fixed_div; 141 void __iomem *enable_reg; 142 u8 enable_bit; 143 u8 flags; 144 void __iomem *clksel_reg; 145 u32 clksel_mask; 146 const struct clksel *clksel; 147 struct dpll_data *dpll_data; 148 const char *clkdm_name; 149 struct clockdomain *clkdm; 150 const struct clk_hw_omap_ops *ops; 151 }; 152 153 /* 154 * struct clk_hw_omap.flags possibilities 155 * 156 * XXX document the rest of the clock flags here 157 * 158 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed 159 * with 32bit ops, by default OMAP1 uses 16bit ops. 160 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support. 161 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent 162 * clock is put to no-idle mode. 163 * ENABLE_ON_INIT: Clock is enabled on init. 164 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0' 165 * disable. This inverts the behavior making '0' enable and '1' disable. 166 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL 167 * bits share the same register. This flag allows the 168 * omap4_dpllmx*() code to determine which GATE_CTRL bit field 169 * should be used. This is a temporary solution - a better approach 170 * would be to associate clock type-specific data with the clock, 171 * similar to the struct dpll_data approach. 172 * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers. 173 */ 174 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 175 #define CLOCK_IDLE_CONTROL (1 << 1) 176 #define CLOCK_NO_IDLE_PARENT (1 << 2) 177 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 178 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 179 #define CLOCK_CLKOUTX2 (1 << 5) 180 #define MEMMAP_ADDRESSING (1 << 6) 181 182 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 183 #define DPLL_LOW_POWER_STOP 0x1 184 #define DPLL_LOW_POWER_BYPASS 0x5 185 #define DPLL_LOCKED 0x7 186 187 /* DPLL Type and DCO Selection Flags */ 188 #define DPLL_J_TYPE 0x1 189 190 /* Composite clock component types */ 191 enum { 192 CLK_COMPONENT_TYPE_GATE = 0, 193 CLK_COMPONENT_TYPE_DIVIDER, 194 CLK_COMPONENT_TYPE_MUX, 195 CLK_COMPONENT_TYPE_MAX, 196 }; 197 198 /** 199 * struct ti_dt_clk - OMAP DT clock alias declarations 200 * @lk: clock lookup definition 201 * @node_name: clock DT node to map to 202 */ 203 struct ti_dt_clk { 204 struct clk_lookup lk; 205 char *node_name; 206 }; 207 208 #define DT_CLK(dev, con, name) \ 209 { \ 210 .lk = { \ 211 .dev_id = dev, \ 212 .con_id = con, \ 213 }, \ 214 .node_name = name, \ 215 } 216 217 /* Maximum number of clock memmaps */ 218 #define CLK_MAX_MEMMAPS 4 219 220 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 221 222 /** 223 * struct clk_omap_reg - OMAP register declaration 224 * @offset: offset from the master IP module base address 225 * @index: index of the master IP module 226 */ 227 struct clk_omap_reg { 228 u16 offset; 229 u16 index; 230 }; 231 232 /** 233 * struct ti_clk_ll_ops - low-level register access ops for a clock 234 * @clk_readl: pointer to register read function 235 * @clk_writel: pointer to register write function 236 * 237 * Low-level register access ops are generally used by the basic clock types 238 * (clk-gate, clk-mux, clk-divider etc.) to provide support for various 239 * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be 240 * used by other hardware-specific clock drivers if needed. 241 */ 242 struct ti_clk_ll_ops { 243 u32 (*clk_readl)(void __iomem *reg); 244 void (*clk_writel)(u32 val, void __iomem *reg); 245 }; 246 247 extern struct ti_clk_ll_ops *ti_clk_ll_ops; 248 249 extern const struct clk_ops ti_clk_divider_ops; 250 extern const struct clk_ops ti_clk_mux_ops; 251 252 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 253 254 void omap2_init_clk_hw_omap_clocks(struct clk *clk); 255 int omap3_noncore_dpll_enable(struct clk_hw *hw); 256 void omap3_noncore_dpll_disable(struct clk_hw *hw); 257 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 258 unsigned long parent_rate); 259 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 260 unsigned long parent_rate); 261 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 262 unsigned long target_rate, 263 unsigned long *parent_rate); 264 u8 omap2_init_dpll_parent(struct clk_hw *hw); 265 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 266 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 267 unsigned long *parent_rate); 268 void omap2_init_clk_clkdm(struct clk_hw *clk); 269 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 270 unsigned long parent_rate); 271 int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate, 272 unsigned long parent_rate); 273 long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate, 274 unsigned long *prate); 275 int omap2_clkops_enable_clkdm(struct clk_hw *hw); 276 void omap2_clkops_disable_clkdm(struct clk_hw *hw); 277 int omap2_clk_disable_autoidle_all(void); 278 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 279 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 280 unsigned long parent_rate); 281 int omap2_dflt_clk_enable(struct clk_hw *hw); 282 void omap2_dflt_clk_disable(struct clk_hw *hw); 283 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 284 void omap3_clk_lock_dpll5(void); 285 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, 286 unsigned long parent_rate); 287 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, 288 unsigned long parent_rate); 289 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); 290 void omap2xxx_clkt_vps_init(void); 291 292 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); 293 void ti_dt_clocks_register(struct ti_dt_clk *oclks); 294 void ti_dt_clk_init_provider(struct device_node *np, int index); 295 void ti_dt_clockdomains_setup(void); 296 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 297 ti_of_clk_init_cb_t func); 298 int of_ti_clk_autoidle_setup(struct device_node *node); 299 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 300 301 int omap3430_dt_clk_init(void); 302 int omap3630_dt_clk_init(void); 303 int am35xx_dt_clk_init(void); 304 int ti81xx_dt_clk_init(void); 305 int omap4xxx_dt_clk_init(void); 306 int omap5xxx_dt_clk_init(void); 307 int dra7xx_dt_clk_init(void); 308 int am33xx_dt_clk_init(void); 309 int am43xx_dt_clk_init(void); 310 int omap2420_dt_clk_init(void); 311 int omap2430_dt_clk_init(void); 312 313 #ifdef CONFIG_OF 314 void of_ti_clk_allow_autoidle_all(void); 315 void of_ti_clk_deny_autoidle_all(void); 316 #else 317 static inline void of_ti_clk_allow_autoidle_all(void) { } 318 static inline void of_ti_clk_deny_autoidle_all(void) { } 319 #endif 320 321 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 322 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 323 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 324 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 325 extern const struct clk_hw_omap_ops clkhwops_wait; 326 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 327 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 328 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 329 extern const struct clk_hw_omap_ops clkhwops_iclk; 330 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 331 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 332 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 333 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 334 335 #endif 336