1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 4 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 5 */ 6 #ifndef __LINUX_CLK_PROVIDER_H 7 #define __LINUX_CLK_PROVIDER_H 8 9 #include <linux/of.h> 10 #include <linux/of_clk.h> 11 12 /* 13 * flags used across common struct clk. these flags should only affect the 14 * top-level framework. custom flags for dealing with hardware specifics 15 * belong in struct clk_foo 16 * 17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 18 */ 19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 23 /* unused */ 24 /* unused */ 25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 31 /* parents need enable during gate/ungate, set rate and re-parent */ 32 #define CLK_OPS_PARENT_ENABLE BIT(12) 33 /* duty cycle call may be forwarded to the parent clock */ 34 #define CLK_DUTY_CYCLE_PARENT BIT(13) 35 36 struct clk; 37 struct clk_hw; 38 struct clk_core; 39 struct dentry; 40 41 /** 42 * struct clk_rate_request - Structure encoding the clk constraints that 43 * a clock user might require. 44 * 45 * @rate: Requested clock rate. This field will be adjusted by 46 * clock drivers according to hardware capabilities. 47 * @min_rate: Minimum rate imposed by clk users. 48 * @max_rate: Maximum rate imposed by clk users. 49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 50 * requested constraints. 51 * @best_parent_hw: The most appropriate parent clock that fulfills the 52 * requested constraints. 53 * 54 */ 55 struct clk_rate_request { 56 unsigned long rate; 57 unsigned long min_rate; 58 unsigned long max_rate; 59 unsigned long best_parent_rate; 60 struct clk_hw *best_parent_hw; 61 }; 62 63 /** 64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock 65 * 66 * @num: Numerator of the duty cycle ratio 67 * @den: Denominator of the duty cycle ratio 68 */ 69 struct clk_duty { 70 unsigned int num; 71 unsigned int den; 72 }; 73 74 /** 75 * struct clk_ops - Callback operations for hardware clocks; these are to 76 * be provided by the clock implementation, and will be called by drivers 77 * through the clk_* api. 78 * 79 * @prepare: Prepare the clock for enabling. This must not return until 80 * the clock is fully prepared, and it's safe to call clk_enable. 81 * This callback is intended to allow clock implementations to 82 * do any initialisation that may sleep. Called with 83 * prepare_lock held. 84 * 85 * @unprepare: Release the clock from its prepared state. This will typically 86 * undo any work done in the @prepare callback. Called with 87 * prepare_lock held. 88 * 89 * @is_prepared: Queries the hardware to determine if the clock is prepared. 90 * This function is allowed to sleep. Optional, if this op is not 91 * set then the prepare count will be used. 92 * 93 * @unprepare_unused: Unprepare the clock atomically. Only called from 94 * clk_disable_unused for prepare clocks with special needs. 95 * Called with prepare mutex held. This function may sleep. 96 * 97 * @enable: Enable the clock atomically. This must not return until the 98 * clock is generating a valid clock signal, usable by consumer 99 * devices. Called with enable_lock held. This function must not 100 * sleep. 101 * 102 * @disable: Disable the clock atomically. Called with enable_lock held. 103 * This function must not sleep. 104 * 105 * @is_enabled: Queries the hardware to determine if the clock is enabled. 106 * This function must not sleep. Optional, if this op is not 107 * set then the enable count will be used. 108 * 109 * @disable_unused: Disable the clock atomically. Only called from 110 * clk_disable_unused for gate clocks with special needs. 111 * Called with enable_lock held. This function must not 112 * sleep. 113 * 114 * @save_context: Save the context of the clock in prepration for poweroff. 115 * 116 * @restore_context: Restore the context of the clock after a restoration 117 * of power. 118 * 119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 120 * parent rate is an input parameter. It is up to the caller to 121 * ensure that the prepare_mutex is held across this call. 122 * Returns the calculated rate. Optional, but recommended - if 123 * this op is not set then clock rate will be initialized to 0. 124 * 125 * @round_rate: Given a target rate as input, returns the closest rate actually 126 * supported by the clock. The parent rate is an input/output 127 * parameter. 128 * 129 * @determine_rate: Given a target rate as input, returns the closest rate 130 * actually supported by the clock, and optionally the parent clock 131 * that should be used to provide the clock rate. 132 * 133 * @set_parent: Change the input source of this clock; for clocks with multiple 134 * possible parents specify a new parent by passing in the index 135 * as a u8 corresponding to the parent in either the .parent_names 136 * or .parents arrays. This function in affect translates an 137 * array index into the value programmed into the hardware. 138 * Returns 0 on success, -EERROR otherwise. 139 * 140 * @get_parent: Queries the hardware to determine the parent of a clock. The 141 * return value is a u8 which specifies the index corresponding to 142 * the parent clock. This index can be applied to either the 143 * .parent_names or .parents arrays. In short, this function 144 * translates the parent value read from hardware into an array 145 * index. Currently only called when the clock is initialized by 146 * __clk_init. This callback is mandatory for clocks with 147 * multiple parents. It is optional (and unnecessary) for clocks 148 * with 0 or 1 parents. 149 * 150 * @set_rate: Change the rate of this clock. The requested rate is specified 151 * by the second argument, which should typically be the return 152 * of .round_rate call. The third argument gives the parent rate 153 * which is likely helpful for most .set_rate implementation. 154 * Returns 0 on success, -EERROR otherwise. 155 * 156 * @set_rate_and_parent: Change the rate and the parent of this clock. The 157 * requested rate is specified by the second argument, which 158 * should typically be the return of .round_rate call. The 159 * third argument gives the parent rate which is likely helpful 160 * for most .set_rate_and_parent implementation. The fourth 161 * argument gives the parent index. This callback is optional (and 162 * unnecessary) for clocks with 0 or 1 parents as well as 163 * for clocks that can tolerate switching the rate and the parent 164 * separately via calls to .set_parent and .set_rate. 165 * Returns 0 on success, -EERROR otherwise. 166 * 167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 168 * is expressed in ppb (parts per billion). The parent accuracy is 169 * an input parameter. 170 * Returns the calculated accuracy. Optional - if this op is not 171 * set then clock accuracy will be initialized to parent accuracy 172 * or 0 (perfect clock) if clock has no parent. 173 * 174 * @get_phase: Queries the hardware to get the current phase of a clock. 175 * Returned values are 0-359 degrees on success, negative 176 * error codes on failure. 177 * 178 * @set_phase: Shift the phase this clock signal in degrees specified 179 * by the second argument. Valid values for degrees are 180 * 0-359. Return 0 on success, otherwise -EERROR. 181 * 182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio 183 * of a clock. Returned values denominator cannot be 0 and must be 184 * superior or equal to the numerator. 185 * 186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by 187 * the numerator (2nd argurment) and denominator (3rd argument). 188 * Argument must be a valid ratio (denominator > 0 189 * and >= numerator) Return 0 on success, otherwise -EERROR. 190 * 191 * @init: Perform platform-specific initialization magic. 192 * This is not used by any of the basic clock types. 193 * This callback exist for HW which needs to perform some 194 * initialisation magic for CCF to get an accurate view of the 195 * clock. It may also be used dynamic resource allocation is 196 * required. It shall not used to deal with clock parameters, 197 * such as rate or parents. 198 * Returns 0 on success, -EERROR otherwise. 199 * 200 * @terminate: Free any resource allocated by init. 201 * 202 * @debug_init: Set up type-specific debugfs entries for this clock. This 203 * is called once, after the debugfs directory entry for this 204 * clock has been created. The dentry pointer representing that 205 * directory is provided as an argument. Called with 206 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 207 * 208 * 209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 210 * implementations to split any work between atomic (enable) and sleepable 211 * (prepare) contexts. If enabling a clock requires code that might sleep, 212 * this must be done in clk_prepare. Clock enable code that will never be 213 * called in a sleepable context may be implemented in clk_enable. 214 * 215 * Typically, drivers will call clk_prepare when a clock may be needed later 216 * (eg. when a device is opened), and clk_enable when the clock is actually 217 * required (eg. from an interrupt). Note that clk_prepare MUST have been 218 * called before clk_enable. 219 */ 220 struct clk_ops { 221 int (*prepare)(struct clk_hw *hw); 222 void (*unprepare)(struct clk_hw *hw); 223 int (*is_prepared)(struct clk_hw *hw); 224 void (*unprepare_unused)(struct clk_hw *hw); 225 int (*enable)(struct clk_hw *hw); 226 void (*disable)(struct clk_hw *hw); 227 int (*is_enabled)(struct clk_hw *hw); 228 void (*disable_unused)(struct clk_hw *hw); 229 int (*save_context)(struct clk_hw *hw); 230 void (*restore_context)(struct clk_hw *hw); 231 unsigned long (*recalc_rate)(struct clk_hw *hw, 232 unsigned long parent_rate); 233 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 234 unsigned long *parent_rate); 235 int (*determine_rate)(struct clk_hw *hw, 236 struct clk_rate_request *req); 237 int (*set_parent)(struct clk_hw *hw, u8 index); 238 u8 (*get_parent)(struct clk_hw *hw); 239 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 240 unsigned long parent_rate); 241 int (*set_rate_and_parent)(struct clk_hw *hw, 242 unsigned long rate, 243 unsigned long parent_rate, u8 index); 244 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 245 unsigned long parent_accuracy); 246 int (*get_phase)(struct clk_hw *hw); 247 int (*set_phase)(struct clk_hw *hw, int degrees); 248 int (*get_duty_cycle)(struct clk_hw *hw, 249 struct clk_duty *duty); 250 int (*set_duty_cycle)(struct clk_hw *hw, 251 struct clk_duty *duty); 252 int (*init)(struct clk_hw *hw); 253 void (*terminate)(struct clk_hw *hw); 254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 255 }; 256 257 /** 258 * struct clk_parent_data - clk parent information 259 * @hw: parent clk_hw pointer (used for clk providers with internal clks) 260 * @fw_name: parent name local to provider registering clk 261 * @name: globally unique parent name (used as a fallback) 262 * @index: parent index local to provider registering clk (if @fw_name absent) 263 */ 264 struct clk_parent_data { 265 const struct clk_hw *hw; 266 const char *fw_name; 267 const char *name; 268 int index; 269 }; 270 271 /** 272 * struct clk_init_data - holds init data that's common to all clocks and is 273 * shared between the clock provider and the common clock framework. 274 * 275 * @name: clock name 276 * @ops: operations this clock supports 277 * @parent_names: array of string names for all possible parents 278 * @parent_data: array of parent data for all possible parents (when some 279 * parents are external to the clk controller) 280 * @parent_hws: array of pointers to all possible parents (when all parents 281 * are internal to the clk controller) 282 * @num_parents: number of possible parents 283 * @flags: framework-level hints and quirks 284 */ 285 struct clk_init_data { 286 const char *name; 287 const struct clk_ops *ops; 288 /* Only one of the following three should be assigned */ 289 const char * const *parent_names; 290 const struct clk_parent_data *parent_data; 291 const struct clk_hw **parent_hws; 292 u8 num_parents; 293 unsigned long flags; 294 }; 295 296 /** 297 * struct clk_hw - handle for traversing from a struct clk to its corresponding 298 * hardware-specific structure. struct clk_hw should be declared within struct 299 * clk_foo and then referenced by the struct clk instance that uses struct 300 * clk_foo's clk_ops 301 * 302 * @core: pointer to the struct clk_core instance that points back to this 303 * struct clk_hw instance 304 * 305 * @clk: pointer to the per-user struct clk instance that can be used to call 306 * into the clk API 307 * 308 * @init: pointer to struct clk_init_data that contains the init data shared 309 * with the common clock framework. This pointer will be set to NULL once 310 * a clk_register() variant is called on this clk_hw pointer. 311 */ 312 struct clk_hw { 313 struct clk_core *core; 314 struct clk *clk; 315 const struct clk_init_data *init; 316 }; 317 318 /* 319 * DOC: Basic clock implementations common to many platforms 320 * 321 * Each basic clock hardware type is comprised of a structure describing the 322 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 323 * unique flags for that hardware type, a registration function and an 324 * alternative macro for static initialization 325 */ 326 327 /** 328 * struct clk_fixed_rate - fixed-rate clock 329 * @hw: handle between common and hardware-specific interfaces 330 * @fixed_rate: constant frequency of clock 331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) 332 * @flags: hardware specific flags 333 * 334 * Flags: 335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk 336 * instead of what's set in @fixed_accuracy. 337 */ 338 struct clk_fixed_rate { 339 struct clk_hw hw; 340 unsigned long fixed_rate; 341 unsigned long fixed_accuracy; 342 unsigned long flags; 343 }; 344 345 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0) 346 347 extern const struct clk_ops clk_fixed_rate_ops; 348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, 349 struct device_node *np, const char *name, 350 const char *parent_name, const struct clk_hw *parent_hw, 351 const struct clk_parent_data *parent_data, unsigned long flags, 352 unsigned long fixed_rate, unsigned long fixed_accuracy, 353 unsigned long clk_fixed_flags, bool devm); 354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 355 const char *parent_name, unsigned long flags, 356 unsigned long fixed_rate); 357 /** 358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock 359 * framework 360 * @dev: device that is registering this clock 361 * @name: name of this clock 362 * @parent_name: name of clock's parent 363 * @flags: framework-specific flags 364 * @fixed_rate: non-adjustable clock rate 365 */ 366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ 367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ 368 NULL, (flags), (fixed_rate), 0, 0, false) 369 370 /** 371 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock 372 * framework 373 * @dev: device that is registering this clock 374 * @name: name of this clock 375 * @parent_name: name of clock's parent 376 * @flags: framework-specific flags 377 * @fixed_rate: non-adjustable clock rate 378 */ 379 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \ 380 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \ 381 NULL, (flags), (fixed_rate), 0, 0, true) 382 /** 383 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with 384 * the clock framework 385 * @dev: device that is registering this clock 386 * @name: name of this clock 387 * @parent_hw: pointer to parent clk 388 * @flags: framework-specific flags 389 * @fixed_rate: non-adjustable clock rate 390 */ 391 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \ 392 fixed_rate) \ 393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \ 394 NULL, (flags), (fixed_rate), 0, 0, false) 395 /** 396 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with 397 * the clock framework 398 * @dev: device that is registering this clock 399 * @name: name of this clock 400 * @parent_data: parent clk data 401 * @flags: framework-specific flags 402 * @fixed_rate: non-adjustable clock rate 403 */ 404 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \ 405 fixed_rate) \ 406 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 407 (parent_data), (flags), (fixed_rate), 0, \ 408 0, false) 409 /** 410 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with 411 * the clock framework 412 * @dev: device that is registering this clock 413 * @name: name of this clock 414 * @parent_name: name of clock's parent 415 * @flags: framework-specific flags 416 * @fixed_rate: non-adjustable clock rate 417 * @fixed_accuracy: non-adjustable clock accuracy 418 */ 419 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \ 420 flags, fixed_rate, \ 421 fixed_accuracy) \ 422 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \ 423 NULL, NULL, (flags), (fixed_rate), \ 424 (fixed_accuracy), 0, false) 425 /** 426 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate 427 * clock with the clock framework 428 * @dev: device that is registering this clock 429 * @name: name of this clock 430 * @parent_hw: pointer to parent clk 431 * @flags: framework-specific flags 432 * @fixed_rate: non-adjustable clock rate 433 * @fixed_accuracy: non-adjustable clock accuracy 434 */ 435 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \ 436 parent_hw, flags, fixed_rate, fixed_accuracy) \ 437 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \ 438 NULL, NULL, (flags), (fixed_rate), \ 439 (fixed_accuracy), 0, false) 440 /** 441 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate 442 * clock with the clock framework 443 * @dev: device that is registering this clock 444 * @name: name of this clock 445 * @parent_name: name of clock's parent 446 * @flags: framework-specific flags 447 * @fixed_rate: non-adjustable clock rate 448 * @fixed_accuracy: non-adjustable clock accuracy 449 */ 450 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \ 451 parent_data, flags, fixed_rate, fixed_accuracy) \ 452 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 453 (parent_data), NULL, (flags), \ 454 (fixed_rate), (fixed_accuracy), 0, false) 455 /** 456 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with 457 * the clock framework 458 * @dev: device that is registering this clock 459 * @name: name of this clock 460 * @parent_name: name of clock's parent 461 * @flags: framework-specific flags 462 * @fixed_rate: non-adjustable clock rate 463 */ 464 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \ 465 flags, fixed_rate) \ 466 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ 467 (parent_data), (flags), (fixed_rate), 0, \ 468 CLK_FIXED_RATE_PARENT_ACCURACY, false) 469 470 void clk_unregister_fixed_rate(struct clk *clk); 471 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 472 473 void of_fixed_clk_setup(struct device_node *np); 474 475 /** 476 * struct clk_gate - gating clock 477 * 478 * @hw: handle between common and hardware-specific interfaces 479 * @reg: register controlling gate 480 * @bit_idx: single bit controlling gate 481 * @flags: hardware-specific flags 482 * @lock: register lock 483 * 484 * Clock which can gate its output. Implements .enable & .disable 485 * 486 * Flags: 487 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 488 * enable the clock. Setting this flag does the opposite: setting the bit 489 * disable the clock and clearing it enables the clock 490 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 491 * of this register, and mask of gate bits are in higher 16-bit of this 492 * register. While setting the gate bits, higher 16-bit should also be 493 * updated to indicate changing gate bits. 494 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for 495 * the gate register. Setting this flag makes the register accesses big 496 * endian. 497 */ 498 struct clk_gate { 499 struct clk_hw hw; 500 void __iomem *reg; 501 u8 bit_idx; 502 u8 flags; 503 spinlock_t *lock; 504 }; 505 506 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 507 508 #define CLK_GATE_SET_TO_DISABLE BIT(0) 509 #define CLK_GATE_HIWORD_MASK BIT(1) 510 #define CLK_GATE_BIG_ENDIAN BIT(2) 511 512 extern const struct clk_ops clk_gate_ops; 513 struct clk_hw *__clk_hw_register_gate(struct device *dev, 514 struct device_node *np, const char *name, 515 const char *parent_name, const struct clk_hw *parent_hw, 516 const struct clk_parent_data *parent_data, 517 unsigned long flags, 518 void __iomem *reg, u8 bit_idx, 519 u8 clk_gate_flags, spinlock_t *lock); 520 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, 521 struct device_node *np, const char *name, 522 const char *parent_name, const struct clk_hw *parent_hw, 523 const struct clk_parent_data *parent_data, 524 unsigned long flags, 525 void __iomem *reg, u8 bit_idx, 526 u8 clk_gate_flags, spinlock_t *lock); 527 struct clk *clk_register_gate(struct device *dev, const char *name, 528 const char *parent_name, unsigned long flags, 529 void __iomem *reg, u8 bit_idx, 530 u8 clk_gate_flags, spinlock_t *lock); 531 /** 532 * clk_hw_register_gate - register a gate clock with the clock framework 533 * @dev: device that is registering this clock 534 * @name: name of this clock 535 * @parent_name: name of this clock's parent 536 * @flags: framework-specific flags for this clock 537 * @reg: register address to control gating of this clock 538 * @bit_idx: which bit in the register controls gating of this clock 539 * @clk_gate_flags: gate-specific flags for this clock 540 * @lock: shared register lock for this clock 541 */ 542 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \ 543 clk_gate_flags, lock) \ 544 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ 545 NULL, (flags), (reg), (bit_idx), \ 546 (clk_gate_flags), (lock)) 547 /** 548 * clk_hw_register_gate_parent_hw - register a gate clock with the clock 549 * framework 550 * @dev: device that is registering this clock 551 * @name: name of this clock 552 * @parent_hw: pointer to parent clk 553 * @flags: framework-specific flags for this clock 554 * @reg: register address to control gating of this clock 555 * @bit_idx: which bit in the register controls gating of this clock 556 * @clk_gate_flags: gate-specific flags for this clock 557 * @lock: shared register lock for this clock 558 */ 559 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \ 560 bit_idx, clk_gate_flags, lock) \ 561 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \ 562 NULL, (flags), (reg), (bit_idx), \ 563 (clk_gate_flags), (lock)) 564 /** 565 * clk_hw_register_gate_parent_data - register a gate clock with the clock 566 * framework 567 * @dev: device that is registering this clock 568 * @name: name of this clock 569 * @parent_data: parent clk data 570 * @flags: framework-specific flags for this clock 571 * @reg: register address to control gating of this clock 572 * @bit_idx: which bit in the register controls gating of this clock 573 * @clk_gate_flags: gate-specific flags for this clock 574 * @lock: shared register lock for this clock 575 */ 576 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \ 577 bit_idx, clk_gate_flags, lock) \ 578 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \ 579 (flags), (reg), (bit_idx), \ 580 (clk_gate_flags), (lock)) 581 /** 582 * devm_clk_hw_register_gate - register a gate clock with the clock framework 583 * @dev: device that is registering this clock 584 * @name: name of this clock 585 * @parent_name: name of this clock's parent 586 * @flags: framework-specific flags for this clock 587 * @reg: register address to control gating of this clock 588 * @bit_idx: which bit in the register controls gating of this clock 589 * @clk_gate_flags: gate-specific flags for this clock 590 * @lock: shared register lock for this clock 591 */ 592 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\ 593 clk_gate_flags, lock) \ 594 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \ 595 NULL, (flags), (reg), (bit_idx), \ 596 (clk_gate_flags), (lock)) 597 void clk_unregister_gate(struct clk *clk); 598 void clk_hw_unregister_gate(struct clk_hw *hw); 599 int clk_gate_is_enabled(struct clk_hw *hw); 600 601 struct clk_div_table { 602 unsigned int val; 603 unsigned int div; 604 }; 605 606 /** 607 * struct clk_divider - adjustable divider clock 608 * 609 * @hw: handle between common and hardware-specific interfaces 610 * @reg: register containing the divider 611 * @shift: shift to the divider bit field 612 * @width: width of the divider bit field 613 * @table: array of value/divider pairs, last entry should have div = 0 614 * @lock: register lock 615 * 616 * Clock with an adjustable divider affecting its output frequency. Implements 617 * .recalc_rate, .set_rate and .round_rate 618 * 619 * Flags: 620 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 621 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 622 * the raw value read from the register, with the value of zero considered 623 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 624 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 625 * the hardware register 626 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 627 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 628 * Some hardware implementations gracefully handle this case and allow a 629 * zero divisor by not modifying their input clock 630 * (divide by one / bypass). 631 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 632 * of this register, and mask of divider bits are in higher 16-bit of this 633 * register. While setting the divider bits, higher 16-bit should also be 634 * updated to indicate changing divider bits. 635 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 636 * to the closest integer instead of the up one. 637 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 638 * not be changed by the clock framework. 639 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 640 * except when the value read from the register is zero, the divisor is 641 * 2^width of the field. 642 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used 643 * for the divider register. Setting this flag makes the register accesses 644 * big endian. 645 */ 646 struct clk_divider { 647 struct clk_hw hw; 648 void __iomem *reg; 649 u8 shift; 650 u8 width; 651 u8 flags; 652 const struct clk_div_table *table; 653 spinlock_t *lock; 654 }; 655 656 #define clk_div_mask(width) ((1 << (width)) - 1) 657 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 658 659 #define CLK_DIVIDER_ONE_BASED BIT(0) 660 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 661 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 662 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 663 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 664 #define CLK_DIVIDER_READ_ONLY BIT(5) 665 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 666 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 667 668 extern const struct clk_ops clk_divider_ops; 669 extern const struct clk_ops clk_divider_ro_ops; 670 671 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 672 unsigned int val, const struct clk_div_table *table, 673 unsigned long flags, unsigned long width); 674 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 675 unsigned long rate, unsigned long *prate, 676 const struct clk_div_table *table, 677 u8 width, unsigned long flags); 678 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 679 unsigned long rate, unsigned long *prate, 680 const struct clk_div_table *table, u8 width, 681 unsigned long flags, unsigned int val); 682 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 683 const struct clk_div_table *table, u8 width, 684 unsigned long flags); 685 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, 686 const struct clk_div_table *table, u8 width, 687 unsigned long flags, unsigned int val); 688 int divider_get_val(unsigned long rate, unsigned long parent_rate, 689 const struct clk_div_table *table, u8 width, 690 unsigned long flags); 691 692 struct clk_hw *__clk_hw_register_divider(struct device *dev, 693 struct device_node *np, const char *name, 694 const char *parent_name, const struct clk_hw *parent_hw, 695 const struct clk_parent_data *parent_data, unsigned long flags, 696 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, 697 const struct clk_div_table *table, spinlock_t *lock); 698 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, 699 struct device_node *np, const char *name, 700 const char *parent_name, const struct clk_hw *parent_hw, 701 const struct clk_parent_data *parent_data, unsigned long flags, 702 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, 703 const struct clk_div_table *table, spinlock_t *lock); 704 struct clk *clk_register_divider_table(struct device *dev, const char *name, 705 const char *parent_name, unsigned long flags, 706 void __iomem *reg, u8 shift, u8 width, 707 u8 clk_divider_flags, const struct clk_div_table *table, 708 spinlock_t *lock); 709 /** 710 * clk_register_divider - register a divider clock with the clock framework 711 * @dev: device registering this clock 712 * @name: name of this clock 713 * @parent_name: name of clock's parent 714 * @flags: framework-specific flags 715 * @reg: register address to adjust divider 716 * @shift: number of bits to shift the bitfield 717 * @width: width of the bitfield 718 * @clk_divider_flags: divider-specific flags for this clock 719 * @lock: shared register lock for this clock 720 */ 721 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ 722 clk_divider_flags, lock) \ 723 clk_register_divider_table((dev), (name), (parent_name), (flags), \ 724 (reg), (shift), (width), \ 725 (clk_divider_flags), NULL, (lock)) 726 /** 727 * clk_hw_register_divider - register a divider clock with the clock framework 728 * @dev: device registering this clock 729 * @name: name of this clock 730 * @parent_name: name of clock's parent 731 * @flags: framework-specific flags 732 * @reg: register address to adjust divider 733 * @shift: number of bits to shift the bitfield 734 * @width: width of the bitfield 735 * @clk_divider_flags: divider-specific flags for this clock 736 * @lock: shared register lock for this clock 737 */ 738 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 739 width, clk_divider_flags, lock) \ 740 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 741 NULL, (flags), (reg), (shift), (width), \ 742 (clk_divider_flags), NULL, (lock)) 743 /** 744 * clk_hw_register_divider_parent_hw - register a divider clock with the clock 745 * framework 746 * @dev: device registering this clock 747 * @name: name of this clock 748 * @parent_hw: pointer to parent clk 749 * @flags: framework-specific flags 750 * @reg: register address to adjust divider 751 * @shift: number of bits to shift the bitfield 752 * @width: width of the bitfield 753 * @clk_divider_flags: divider-specific flags for this clock 754 * @lock: shared register lock for this clock 755 */ 756 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \ 757 shift, width, clk_divider_flags, \ 758 lock) \ 759 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 760 NULL, (flags), (reg), (shift), (width), \ 761 (clk_divider_flags), NULL, (lock)) 762 /** 763 * clk_hw_register_divider_parent_data - register a divider clock with the clock 764 * framework 765 * @dev: device registering this clock 766 * @name: name of this clock 767 * @parent_data: parent clk data 768 * @flags: framework-specific flags 769 * @reg: register address to adjust divider 770 * @shift: number of bits to shift the bitfield 771 * @width: width of the bitfield 772 * @clk_divider_flags: divider-specific flags for this clock 773 * @lock: shared register lock for this clock 774 */ 775 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \ 776 reg, shift, width, \ 777 clk_divider_flags, lock) \ 778 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 779 (parent_data), (flags), (reg), (shift), \ 780 (width), (clk_divider_flags), NULL, (lock)) 781 /** 782 * clk_hw_register_divider_table - register a table based divider clock with 783 * the clock framework 784 * @dev: device registering this clock 785 * @name: name of this clock 786 * @parent_name: name of clock's parent 787 * @flags: framework-specific flags 788 * @reg: register address to adjust divider 789 * @shift: number of bits to shift the bitfield 790 * @width: width of the bitfield 791 * @clk_divider_flags: divider-specific flags for this clock 792 * @table: array of divider/value pairs ending with a div set to 0 793 * @lock: shared register lock for this clock 794 */ 795 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ 796 shift, width, clk_divider_flags, table, \ 797 lock) \ 798 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 799 NULL, (flags), (reg), (shift), (width), \ 800 (clk_divider_flags), (table), (lock)) 801 /** 802 * clk_hw_register_divider_table_parent_hw - register a table based divider 803 * clock with the clock framework 804 * @dev: device registering this clock 805 * @name: name of this clock 806 * @parent_hw: pointer to parent clk 807 * @flags: framework-specific flags 808 * @reg: register address to adjust divider 809 * @shift: number of bits to shift the bitfield 810 * @width: width of the bitfield 811 * @clk_divider_flags: divider-specific flags for this clock 812 * @table: array of divider/value pairs ending with a div set to 0 813 * @lock: shared register lock for this clock 814 */ 815 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \ 816 reg, shift, width, \ 817 clk_divider_flags, table, \ 818 lock) \ 819 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \ 820 NULL, (flags), (reg), (shift), (width), \ 821 (clk_divider_flags), (table), (lock)) 822 /** 823 * clk_hw_register_divider_table_parent_data - register a table based divider 824 * clock with the clock framework 825 * @dev: device registering this clock 826 * @name: name of this clock 827 * @parent_data: parent clk data 828 * @flags: framework-specific flags 829 * @reg: register address to adjust divider 830 * @shift: number of bits to shift the bitfield 831 * @width: width of the bitfield 832 * @clk_divider_flags: divider-specific flags for this clock 833 * @table: array of divider/value pairs ending with a div set to 0 834 * @lock: shared register lock for this clock 835 */ 836 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \ 837 flags, reg, shift, width, \ 838 clk_divider_flags, table, \ 839 lock) \ 840 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ 841 (parent_data), (flags), (reg), (shift), \ 842 (width), (clk_divider_flags), (table), \ 843 (lock)) 844 /** 845 * devm_clk_hw_register_divider - register a divider clock with the clock framework 846 * @dev: device registering this clock 847 * @name: name of this clock 848 * @parent_name: name of clock's parent 849 * @flags: framework-specific flags 850 * @reg: register address to adjust divider 851 * @shift: number of bits to shift the bitfield 852 * @width: width of the bitfield 853 * @clk_divider_flags: divider-specific flags for this clock 854 * @lock: shared register lock for this clock 855 */ 856 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \ 857 width, clk_divider_flags, lock) \ 858 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \ 859 NULL, (flags), (reg), (shift), (width), \ 860 (clk_divider_flags), NULL, (lock)) 861 /** 862 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework 863 * @dev: device registering this clock 864 * @name: name of this clock 865 * @parent_hw: pointer to parent clk 866 * @flags: framework-specific flags 867 * @reg: register address to adjust divider 868 * @shift: number of bits to shift the bitfield 869 * @width: width of the bitfield 870 * @clk_divider_flags: divider-specific flags for this clock 871 * @lock: shared register lock for this clock 872 */ 873 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \ 874 reg, shift, width, \ 875 clk_divider_flags, lock) \ 876 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ 877 (parent_hw), NULL, (flags), (reg), \ 878 (shift), (width), (clk_divider_flags), \ 879 NULL, (lock)) 880 /** 881 * devm_clk_hw_register_divider_table - register a table based divider clock 882 * with the clock framework (devres variant) 883 * @dev: device registering this clock 884 * @name: name of this clock 885 * @parent_name: name of clock's parent 886 * @flags: framework-specific flags 887 * @reg: register address to adjust divider 888 * @shift: number of bits to shift the bitfield 889 * @width: width of the bitfield 890 * @clk_divider_flags: divider-specific flags for this clock 891 * @table: array of divider/value pairs ending with a div set to 0 892 * @lock: shared register lock for this clock 893 */ 894 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \ 895 reg, shift, width, \ 896 clk_divider_flags, table, lock) \ 897 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \ 898 NULL, NULL, (flags), (reg), (shift), \ 899 (width), (clk_divider_flags), (table), \ 900 (lock)) 901 902 void clk_unregister_divider(struct clk *clk); 903 void clk_hw_unregister_divider(struct clk_hw *hw); 904 905 /** 906 * struct clk_mux - multiplexer clock 907 * 908 * @hw: handle between common and hardware-specific interfaces 909 * @reg: register controlling multiplexer 910 * @table: array of register values corresponding to the parent index 911 * @shift: shift to multiplexer bit field 912 * @mask: mask of mutliplexer bit field 913 * @flags: hardware-specific flags 914 * @lock: register lock 915 * 916 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 917 * and .recalc_rate 918 * 919 * Flags: 920 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 921 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 922 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 923 * register, and mask of mux bits are in higher 16-bit of this register. 924 * While setting the mux bits, higher 16-bit should also be updated to 925 * indicate changing mux bits. 926 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the 927 * .get_parent clk_op. 928 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 929 * frequency. 930 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for 931 * the mux register. Setting this flag makes the register accesses big 932 * endian. 933 */ 934 struct clk_mux { 935 struct clk_hw hw; 936 void __iomem *reg; 937 const u32 *table; 938 u32 mask; 939 u8 shift; 940 u8 flags; 941 spinlock_t *lock; 942 }; 943 944 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 945 946 #define CLK_MUX_INDEX_ONE BIT(0) 947 #define CLK_MUX_INDEX_BIT BIT(1) 948 #define CLK_MUX_HIWORD_MASK BIT(2) 949 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 950 #define CLK_MUX_ROUND_CLOSEST BIT(4) 951 #define CLK_MUX_BIG_ENDIAN BIT(5) 952 953 extern const struct clk_ops clk_mux_ops; 954 extern const struct clk_ops clk_mux_ro_ops; 955 956 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, 957 const char *name, u8 num_parents, 958 const char * const *parent_names, 959 const struct clk_hw **parent_hws, 960 const struct clk_parent_data *parent_data, 961 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 962 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 963 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, 964 const char *name, u8 num_parents, 965 const char * const *parent_names, 966 const struct clk_hw **parent_hws, 967 const struct clk_parent_data *parent_data, 968 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 969 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 970 struct clk *clk_register_mux_table(struct device *dev, const char *name, 971 const char * const *parent_names, u8 num_parents, 972 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, 973 u8 clk_mux_flags, const u32 *table, spinlock_t *lock); 974 975 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 976 shift, width, clk_mux_flags, lock) \ 977 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \ 978 (flags), (reg), (shift), BIT((width)) - 1, \ 979 (clk_mux_flags), NULL, (lock)) 980 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \ 981 flags, reg, shift, mask, clk_mux_flags, \ 982 table, lock) \ 983 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 984 (parent_names), NULL, NULL, (flags), (reg), \ 985 (shift), (mask), (clk_mux_flags), (table), \ 986 (lock)) 987 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \ 988 num_parents, flags, reg, shift, mask, \ 989 clk_mux_flags, table, lock) \ 990 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 991 NULL, NULL, (parent_data), (flags), (reg), \ 992 (shift), (mask), (clk_mux_flags), (table), \ 993 (lock)) 994 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 995 shift, width, clk_mux_flags, lock) \ 996 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 997 (parent_names), NULL, NULL, (flags), (reg), \ 998 (shift), BIT((width)) - 1, (clk_mux_flags), \ 999 NULL, (lock)) 1000 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \ 1001 reg, shift, width, clk_mux_flags, lock) \ 1002 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1003 (parent_hws), NULL, (flags), (reg), (shift), \ 1004 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 1005 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \ 1006 flags, reg, shift, width, \ 1007 clk_mux_flags, lock) \ 1008 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ 1009 (parent_data), (flags), (reg), (shift), \ 1010 BIT((width)) - 1, (clk_mux_flags), NULL, (lock)) 1011 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ 1012 num_parents, flags, reg, shift, \ 1013 width, clk_mux_flags, table, \ 1014 lock) \ 1015 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \ 1016 (parent_data), (flags), (reg), (shift), \ 1017 BIT((width)) - 1, (clk_mux_flags), table, (lock)) 1018 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \ 1019 shift, width, clk_mux_flags, lock) \ 1020 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \ 1021 (parent_names), NULL, NULL, (flags), (reg), \ 1022 (shift), BIT((width)) - 1, (clk_mux_flags), \ 1023 NULL, (lock)) 1024 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \ 1025 num_parents, flags, reg, shift, \ 1026 width, clk_mux_flags, lock) \ 1027 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1028 (parent_hws), NULL, (flags), (reg), \ 1029 (shift), BIT((width)) - 1, \ 1030 (clk_mux_flags), NULL, (lock)) 1031 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \ 1032 num_parents, flags, reg, shift, \ 1033 width, clk_mux_flags, table, \ 1034 lock) \ 1035 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \ 1036 NULL, (parent_data), (flags), (reg), (shift), \ 1037 BIT((width)) - 1, (clk_mux_flags), table, (lock)) 1038 1039 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, 1040 unsigned int val); 1041 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); 1042 1043 void clk_unregister_mux(struct clk *clk); 1044 void clk_hw_unregister_mux(struct clk_hw *hw); 1045 1046 void of_fixed_factor_clk_setup(struct device_node *node); 1047 1048 /** 1049 * struct clk_fixed_factor - fixed multiplier and divider clock 1050 * 1051 * @hw: handle between common and hardware-specific interfaces 1052 * @mult: multiplier 1053 * @div: divider 1054 * 1055 * Clock with a fixed multiplier and divider. The output frequency is the 1056 * parent clock rate divided by div and multiplied by mult. 1057 * Implements .recalc_rate, .set_rate and .round_rate 1058 */ 1059 1060 struct clk_fixed_factor { 1061 struct clk_hw hw; 1062 unsigned int mult; 1063 unsigned int div; 1064 }; 1065 1066 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 1067 1068 extern const struct clk_ops clk_fixed_factor_ops; 1069 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 1070 const char *parent_name, unsigned long flags, 1071 unsigned int mult, unsigned int div); 1072 void clk_unregister_fixed_factor(struct clk *clk); 1073 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 1074 const char *name, const char *parent_name, unsigned long flags, 1075 unsigned int mult, unsigned int div); 1076 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 1077 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, 1078 const char *name, const char *parent_name, unsigned long flags, 1079 unsigned int mult, unsigned int div); 1080 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, 1081 const char *name, unsigned int index, unsigned long flags, 1082 unsigned int mult, unsigned int div); 1083 1084 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, 1085 const char *name, const struct clk_hw *parent_hw, 1086 unsigned long flags, unsigned int mult, unsigned int div); 1087 1088 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, 1089 const char *name, const struct clk_hw *parent_hw, 1090 unsigned long flags, unsigned int mult, unsigned int div); 1091 /** 1092 * struct clk_fractional_divider - adjustable fractional divider clock 1093 * 1094 * @hw: handle between common and hardware-specific interfaces 1095 * @reg: register containing the divider 1096 * @mshift: shift to the numerator bit field 1097 * @mwidth: width of the numerator bit field 1098 * @nshift: shift to the denominator bit field 1099 * @nwidth: width of the denominator bit field 1100 * @lock: register lock 1101 * 1102 * Clock with adjustable fractional divider affecting its output frequency. 1103 * 1104 * Flags: 1105 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator 1106 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED 1107 * is set then the numerator and denominator are both the value read 1108 * plus one. 1109 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are 1110 * used for the divider register. Setting this flag makes the register 1111 * accesses big endian. 1112 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might 1113 * be saturated and the caller will get quite far from the good enough 1114 * approximation. Instead the caller may require, by setting this flag, 1115 * to shift left by a few bits in case, when the asked one is quite small 1116 * to satisfy the desired range of denominator. It assumes that on the 1117 * caller's side the power-of-two capable prescaler exists. 1118 */ 1119 struct clk_fractional_divider { 1120 struct clk_hw hw; 1121 void __iomem *reg; 1122 u8 mshift; 1123 u8 mwidth; 1124 u32 mmask; 1125 u8 nshift; 1126 u8 nwidth; 1127 u32 nmask; 1128 u8 flags; 1129 void (*approximation)(struct clk_hw *hw, 1130 unsigned long rate, unsigned long *parent_rate, 1131 unsigned long *m, unsigned long *n); 1132 spinlock_t *lock; 1133 }; 1134 1135 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 1136 1137 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) 1138 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) 1139 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2) 1140 1141 struct clk *clk_register_fractional_divider(struct device *dev, 1142 const char *name, const char *parent_name, unsigned long flags, 1143 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1144 u8 clk_divider_flags, spinlock_t *lock); 1145 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 1146 const char *name, const char *parent_name, unsigned long flags, 1147 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 1148 u8 clk_divider_flags, spinlock_t *lock); 1149 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 1150 1151 /** 1152 * struct clk_multiplier - adjustable multiplier clock 1153 * 1154 * @hw: handle between common and hardware-specific interfaces 1155 * @reg: register containing the multiplier 1156 * @shift: shift to the multiplier bit field 1157 * @width: width of the multiplier bit field 1158 * @lock: register lock 1159 * 1160 * Clock with an adjustable multiplier affecting its output frequency. 1161 * Implements .recalc_rate, .set_rate and .round_rate 1162 * 1163 * Flags: 1164 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 1165 * from the register, with 0 being a valid value effectively 1166 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 1167 * set, then a null multiplier will be considered as a bypass, 1168 * leaving the parent rate unmodified. 1169 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 1170 * rounded to the closest integer instead of the down one. 1171 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are 1172 * used for the multiplier register. Setting this flag makes the register 1173 * accesses big endian. 1174 */ 1175 struct clk_multiplier { 1176 struct clk_hw hw; 1177 void __iomem *reg; 1178 u8 shift; 1179 u8 width; 1180 u8 flags; 1181 spinlock_t *lock; 1182 }; 1183 1184 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 1185 1186 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 1187 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 1188 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) 1189 1190 extern const struct clk_ops clk_multiplier_ops; 1191 1192 /*** 1193 * struct clk_composite - aggregate clock of mux, divider and gate clocks 1194 * 1195 * @hw: handle between common and hardware-specific interfaces 1196 * @mux_hw: handle between composite and hardware-specific mux clock 1197 * @rate_hw: handle between composite and hardware-specific rate clock 1198 * @gate_hw: handle between composite and hardware-specific gate clock 1199 * @mux_ops: clock ops for mux 1200 * @rate_ops: clock ops for rate 1201 * @gate_ops: clock ops for gate 1202 */ 1203 struct clk_composite { 1204 struct clk_hw hw; 1205 struct clk_ops ops; 1206 1207 struct clk_hw *mux_hw; 1208 struct clk_hw *rate_hw; 1209 struct clk_hw *gate_hw; 1210 1211 const struct clk_ops *mux_ops; 1212 const struct clk_ops *rate_ops; 1213 const struct clk_ops *gate_ops; 1214 }; 1215 1216 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 1217 1218 struct clk *clk_register_composite(struct device *dev, const char *name, 1219 const char * const *parent_names, int num_parents, 1220 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1221 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1222 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1223 unsigned long flags); 1224 struct clk *clk_register_composite_pdata(struct device *dev, const char *name, 1225 const struct clk_parent_data *parent_data, int num_parents, 1226 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1227 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1228 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1229 unsigned long flags); 1230 void clk_unregister_composite(struct clk *clk); 1231 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 1232 const char * const *parent_names, int num_parents, 1233 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1234 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1235 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1236 unsigned long flags); 1237 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, 1238 const char *name, 1239 const struct clk_parent_data *parent_data, int num_parents, 1240 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1241 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1242 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1243 unsigned long flags); 1244 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, 1245 const char *name, const struct clk_parent_data *parent_data, 1246 int num_parents, 1247 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 1248 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 1249 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 1250 unsigned long flags); 1251 void clk_hw_unregister_composite(struct clk_hw *hw); 1252 1253 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 1254 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 1255 1256 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 1257 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 1258 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); 1259 1260 void clk_unregister(struct clk *clk); 1261 1262 void clk_hw_unregister(struct clk_hw *hw); 1263 1264 /* helper functions */ 1265 const char *__clk_get_name(const struct clk *clk); 1266 const char *clk_hw_get_name(const struct clk_hw *hw); 1267 #ifdef CONFIG_COMMON_CLK 1268 struct clk_hw *__clk_get_hw(struct clk *clk); 1269 #else 1270 static inline struct clk_hw *__clk_get_hw(struct clk *clk) 1271 { 1272 return (struct clk_hw *)clk; 1273 } 1274 #endif 1275 1276 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id); 1277 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw, 1278 const char *con_id); 1279 1280 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 1281 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 1282 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 1283 unsigned int index); 1284 int clk_hw_get_parent_index(struct clk_hw *hw); 1285 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); 1286 unsigned int __clk_get_enable_count(struct clk *clk); 1287 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 1288 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 1289 #define clk_hw_can_set_rate_parent(hw) \ 1290 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) 1291 1292 bool clk_hw_is_prepared(const struct clk_hw *hw); 1293 bool clk_hw_rate_is_protected(const struct clk_hw *hw); 1294 bool clk_hw_is_enabled(const struct clk_hw *hw); 1295 bool __clk_is_enabled(struct clk *clk); 1296 struct clk *__clk_lookup(const char *name); 1297 int __clk_mux_determine_rate(struct clk_hw *hw, 1298 struct clk_rate_request *req); 1299 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 1300 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 1301 struct clk_rate_request *req); 1302 int clk_mux_determine_rate_flags(struct clk_hw *hw, 1303 struct clk_rate_request *req, 1304 unsigned long flags); 1305 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 1306 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 1307 unsigned long max_rate); 1308 1309 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 1310 { 1311 dst->clk = src->clk; 1312 dst->core = src->core; 1313 } 1314 1315 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 1316 unsigned long *prate, 1317 const struct clk_div_table *table, 1318 u8 width, unsigned long flags) 1319 { 1320 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 1321 rate, prate, table, width, flags); 1322 } 1323 1324 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 1325 unsigned long *prate, 1326 const struct clk_div_table *table, 1327 u8 width, unsigned long flags, 1328 unsigned int val) 1329 { 1330 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 1331 rate, prate, table, width, flags, 1332 val); 1333 } 1334 1335 /* 1336 * FIXME clock api without lock protection 1337 */ 1338 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 1339 1340 struct clk_onecell_data { 1341 struct clk **clks; 1342 unsigned int clk_num; 1343 }; 1344 1345 struct clk_hw_onecell_data { 1346 unsigned int num; 1347 struct clk_hw *hws[]; 1348 }; 1349 1350 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 1351 1352 /* 1353 * Use this macro when you have a driver that requires two initialization 1354 * routines, one at of_clk_init(), and one at platform device probe 1355 */ 1356 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 1357 static void __init name##_of_clk_init_driver(struct device_node *np) \ 1358 { \ 1359 of_node_clear_flag(np, OF_POPULATED); \ 1360 fn(np); \ 1361 } \ 1362 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 1363 1364 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 1365 (&(struct clk_init_data) { \ 1366 .flags = _flags, \ 1367 .name = _name, \ 1368 .parent_names = (const char *[]) { _parent }, \ 1369 .num_parents = 1, \ 1370 .ops = _ops, \ 1371 }) 1372 1373 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ 1374 (&(struct clk_init_data) { \ 1375 .flags = _flags, \ 1376 .name = _name, \ 1377 .parent_hws = (const struct clk_hw*[]) { _parent }, \ 1378 .num_parents = 1, \ 1379 .ops = _ops, \ 1380 }) 1381 1382 /* 1383 * This macro is intended for drivers to be able to share the otherwise 1384 * individual struct clk_hw[] compound literals created by the compiler 1385 * when using CLK_HW_INIT_HW. It does NOT support multiple parents. 1386 */ 1387 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ 1388 (&(struct clk_init_data) { \ 1389 .flags = _flags, \ 1390 .name = _name, \ 1391 .parent_hws = _parent, \ 1392 .num_parents = 1, \ 1393 .ops = _ops, \ 1394 }) 1395 1396 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ 1397 (&(struct clk_init_data) { \ 1398 .flags = _flags, \ 1399 .name = _name, \ 1400 .parent_data = (const struct clk_parent_data[]) { \ 1401 { .fw_name = _parent }, \ 1402 }, \ 1403 .num_parents = 1, \ 1404 .ops = _ops, \ 1405 }) 1406 1407 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 1408 (&(struct clk_init_data) { \ 1409 .flags = _flags, \ 1410 .name = _name, \ 1411 .parent_names = _parents, \ 1412 .num_parents = ARRAY_SIZE(_parents), \ 1413 .ops = _ops, \ 1414 }) 1415 1416 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ 1417 (&(struct clk_init_data) { \ 1418 .flags = _flags, \ 1419 .name = _name, \ 1420 .parent_hws = _parents, \ 1421 .num_parents = ARRAY_SIZE(_parents), \ 1422 .ops = _ops, \ 1423 }) 1424 1425 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ 1426 (&(struct clk_init_data) { \ 1427 .flags = _flags, \ 1428 .name = _name, \ 1429 .parent_data = _parents, \ 1430 .num_parents = ARRAY_SIZE(_parents), \ 1431 .ops = _ops, \ 1432 }) 1433 1434 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 1435 (&(struct clk_init_data) { \ 1436 .flags = _flags, \ 1437 .name = _name, \ 1438 .parent_names = NULL, \ 1439 .num_parents = 0, \ 1440 .ops = _ops, \ 1441 }) 1442 1443 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 1444 _div, _mult, _flags) \ 1445 struct clk_fixed_factor _struct = { \ 1446 .div = _div, \ 1447 .mult = _mult, \ 1448 .hw.init = CLK_HW_INIT(_name, \ 1449 _parent, \ 1450 &clk_fixed_factor_ops, \ 1451 _flags), \ 1452 } 1453 1454 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ 1455 _div, _mult, _flags) \ 1456 struct clk_fixed_factor _struct = { \ 1457 .div = _div, \ 1458 .mult = _mult, \ 1459 .hw.init = CLK_HW_INIT_HW(_name, \ 1460 _parent, \ 1461 &clk_fixed_factor_ops, \ 1462 _flags), \ 1463 } 1464 1465 /* 1466 * This macro allows the driver to reuse the _parent array for multiple 1467 * fixed factor clk declarations. 1468 */ 1469 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ 1470 _div, _mult, _flags) \ 1471 struct clk_fixed_factor _struct = { \ 1472 .div = _div, \ 1473 .mult = _mult, \ 1474 .hw.init = CLK_HW_INIT_HWS(_name, \ 1475 _parent, \ 1476 &clk_fixed_factor_ops, \ 1477 _flags), \ 1478 } 1479 1480 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ 1481 _div, _mult, _flags) \ 1482 struct clk_fixed_factor _struct = { \ 1483 .div = _div, \ 1484 .mult = _mult, \ 1485 .hw.init = CLK_HW_INIT_FW_NAME(_name, \ 1486 _parent, \ 1487 &clk_fixed_factor_ops, \ 1488 _flags), \ 1489 } 1490 1491 #ifdef CONFIG_OF 1492 int of_clk_add_provider(struct device_node *np, 1493 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1494 void *data), 1495 void *data); 1496 int of_clk_add_hw_provider(struct device_node *np, 1497 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1498 void *data), 1499 void *data); 1500 int devm_of_clk_add_hw_provider(struct device *dev, 1501 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1502 void *data), 1503 void *data); 1504 void of_clk_del_provider(struct device_node *np); 1505 1506 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 1507 void *data); 1508 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 1509 void *data); 1510 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 1511 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 1512 void *data); 1513 int of_clk_parent_fill(struct device_node *np, const char **parents, 1514 unsigned int size); 1515 int of_clk_detect_critical(struct device_node *np, int index, 1516 unsigned long *flags); 1517 1518 #else /* !CONFIG_OF */ 1519 1520 static inline int of_clk_add_provider(struct device_node *np, 1521 struct clk *(*clk_src_get)(struct of_phandle_args *args, 1522 void *data), 1523 void *data) 1524 { 1525 return 0; 1526 } 1527 static inline int of_clk_add_hw_provider(struct device_node *np, 1528 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1529 void *data), 1530 void *data) 1531 { 1532 return 0; 1533 } 1534 static inline int devm_of_clk_add_hw_provider(struct device *dev, 1535 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 1536 void *data), 1537 void *data) 1538 { 1539 return 0; 1540 } 1541 static inline void of_clk_del_provider(struct device_node *np) {} 1542 1543 static inline struct clk *of_clk_src_simple_get( 1544 struct of_phandle_args *clkspec, void *data) 1545 { 1546 return ERR_PTR(-ENOENT); 1547 } 1548 static inline struct clk_hw * 1549 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 1550 { 1551 return ERR_PTR(-ENOENT); 1552 } 1553 static inline struct clk *of_clk_src_onecell_get( 1554 struct of_phandle_args *clkspec, void *data) 1555 { 1556 return ERR_PTR(-ENOENT); 1557 } 1558 static inline struct clk_hw * 1559 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 1560 { 1561 return ERR_PTR(-ENOENT); 1562 } 1563 static inline int of_clk_parent_fill(struct device_node *np, 1564 const char **parents, unsigned int size) 1565 { 1566 return 0; 1567 } 1568 static inline int of_clk_detect_critical(struct device_node *np, int index, 1569 unsigned long *flags) 1570 { 1571 return 0; 1572 } 1573 #endif /* CONFIG_OF */ 1574 1575 void clk_gate_restore_context(struct clk_hw *hw); 1576 1577 #endif /* CLK_PROVIDER_H */ 1578