1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 17 #ifdef CONFIG_COMMON_CLK 18 19 /* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32 33 struct clk_hw; 34 35 /** 36 * struct clk_ops - Callback operations for hardware clocks; these are to 37 * be provided by the clock implementation, and will be called by drivers 38 * through the clk_* api. 39 * 40 * @prepare: Prepare the clock for enabling. This must not return until 41 * the clock is fully prepared, and it's safe to call clk_enable. 42 * This callback is intended to allow clock implementations to 43 * do any initialisation that may sleep. Called with 44 * prepare_lock held. 45 * 46 * @unprepare: Release the clock from its prepared state. This will typically 47 * undo any work done in the @prepare callback. Called with 48 * prepare_lock held. 49 * 50 * @is_prepared: Queries the hardware to determine if the clock is prepared. 51 * This function is allowed to sleep. Optional, if this op is not 52 * set then the prepare count will be used. 53 * 54 * @unprepare_unused: Unprepare the clock atomically. Only called from 55 * clk_disable_unused for prepare clocks with special needs. 56 * Called with prepare mutex held. This function may sleep. 57 * 58 * @enable: Enable the clock atomically. This must not return until the 59 * clock is generating a valid clock signal, usable by consumer 60 * devices. Called with enable_lock held. This function must not 61 * sleep. 62 * 63 * @disable: Disable the clock atomically. Called with enable_lock held. 64 * This function must not sleep. 65 * 66 * @is_enabled: Queries the hardware to determine if the clock is enabled. 67 * This function must not sleep. Optional, if this op is not 68 * set then the enable count will be used. 69 * 70 * @disable_unused: Disable the clock atomically. Only called from 71 * clk_disable_unused for gate clocks with special needs. 72 * Called with enable_lock held. This function must not 73 * sleep. 74 * 75 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 76 * parent rate is an input parameter. It is up to the caller to 77 * ensure that the prepare_mutex is held across this call. 78 * Returns the calculated rate. Optional, but recommended - if 79 * this op is not set then clock rate will be initialized to 0. 80 * 81 * @round_rate: Given a target rate as input, returns the closest rate actually 82 * supported by the clock. 83 * 84 * @determine_rate: Given a target rate as input, returns the closest rate 85 * actually supported by the clock, and optionally the parent clock 86 * that should be used to provide the clock rate. 87 * 88 * @get_parent: Queries the hardware to determine the parent of a clock. The 89 * return value is a u8 which specifies the index corresponding to 90 * the parent clock. This index can be applied to either the 91 * .parent_names or .parents arrays. In short, this function 92 * translates the parent value read from hardware into an array 93 * index. Currently only called when the clock is initialized by 94 * __clk_init. This callback is mandatory for clocks with 95 * multiple parents. It is optional (and unnecessary) for clocks 96 * with 0 or 1 parents. 97 * 98 * @set_parent: Change the input source of this clock; for clocks with multiple 99 * possible parents specify a new parent by passing in the index 100 * as a u8 corresponding to the parent in either the .parent_names 101 * or .parents arrays. This function in affect translates an 102 * array index into the value programmed into the hardware. 103 * Returns 0 on success, -EERROR otherwise. 104 * 105 * @set_rate: Change the rate of this clock. The requested rate is specified 106 * by the second argument, which should typically be the return 107 * of .round_rate call. The third argument gives the parent rate 108 * which is likely helpful for most .set_rate implementation. 109 * Returns 0 on success, -EERROR otherwise. 110 * 111 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 112 * implementations to split any work between atomic (enable) and sleepable 113 * (prepare) contexts. If enabling a clock requires code that might sleep, 114 * this must be done in clk_prepare. Clock enable code that will never be 115 * called in a sleepable context may be implemented in clk_enable. 116 * 117 * Typically, drivers will call clk_prepare when a clock may be needed later 118 * (eg. when a device is opened), and clk_enable when the clock is actually 119 * required (eg. from an interrupt). Note that clk_prepare MUST have been 120 * called before clk_enable. 121 */ 122 struct clk_ops { 123 int (*prepare)(struct clk_hw *hw); 124 void (*unprepare)(struct clk_hw *hw); 125 int (*is_prepared)(struct clk_hw *hw); 126 void (*unprepare_unused)(struct clk_hw *hw); 127 int (*enable)(struct clk_hw *hw); 128 void (*disable)(struct clk_hw *hw); 129 int (*is_enabled)(struct clk_hw *hw); 130 void (*disable_unused)(struct clk_hw *hw); 131 unsigned long (*recalc_rate)(struct clk_hw *hw, 132 unsigned long parent_rate); 133 long (*round_rate)(struct clk_hw *hw, unsigned long, 134 unsigned long *); 135 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 136 unsigned long *best_parent_rate, 137 struct clk **best_parent_clk); 138 int (*set_parent)(struct clk_hw *hw, u8 index); 139 u8 (*get_parent)(struct clk_hw *hw); 140 int (*set_rate)(struct clk_hw *hw, unsigned long, 141 unsigned long); 142 void (*init)(struct clk_hw *hw); 143 }; 144 145 /** 146 * struct clk_init_data - holds init data that's common to all clocks and is 147 * shared between the clock provider and the common clock framework. 148 * 149 * @name: clock name 150 * @ops: operations this clock supports 151 * @parent_names: array of string names for all possible parents 152 * @num_parents: number of possible parents 153 * @flags: framework-level hints and quirks 154 */ 155 struct clk_init_data { 156 const char *name; 157 const struct clk_ops *ops; 158 const char **parent_names; 159 u8 num_parents; 160 unsigned long flags; 161 }; 162 163 /** 164 * struct clk_hw - handle for traversing from a struct clk to its corresponding 165 * hardware-specific structure. struct clk_hw should be declared within struct 166 * clk_foo and then referenced by the struct clk instance that uses struct 167 * clk_foo's clk_ops 168 * 169 * @clk: pointer to the struct clk instance that points back to this struct 170 * clk_hw instance 171 * 172 * @init: pointer to struct clk_init_data that contains the init data shared 173 * with the common clock framework. 174 */ 175 struct clk_hw { 176 struct clk *clk; 177 const struct clk_init_data *init; 178 }; 179 180 /* 181 * DOC: Basic clock implementations common to many platforms 182 * 183 * Each basic clock hardware type is comprised of a structure describing the 184 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 185 * unique flags for that hardware type, a registration function and an 186 * alternative macro for static initialization 187 */ 188 189 /** 190 * struct clk_fixed_rate - fixed-rate clock 191 * @hw: handle between common and hardware-specific interfaces 192 * @fixed_rate: constant frequency of clock 193 */ 194 struct clk_fixed_rate { 195 struct clk_hw hw; 196 unsigned long fixed_rate; 197 u8 flags; 198 }; 199 200 extern const struct clk_ops clk_fixed_rate_ops; 201 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 202 const char *parent_name, unsigned long flags, 203 unsigned long fixed_rate); 204 205 void of_fixed_clk_setup(struct device_node *np); 206 207 /** 208 * struct clk_gate - gating clock 209 * 210 * @hw: handle between common and hardware-specific interfaces 211 * @reg: register controlling gate 212 * @bit_idx: single bit controlling gate 213 * @flags: hardware-specific flags 214 * @lock: register lock 215 * 216 * Clock which can gate its output. Implements .enable & .disable 217 * 218 * Flags: 219 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 220 * enable the clock. Setting this flag does the opposite: setting the bit 221 * disable the clock and clearing it enables the clock 222 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 223 * of this register, and mask of gate bits are in higher 16-bit of this 224 * register. While setting the gate bits, higher 16-bit should also be 225 * updated to indicate changing gate bits. 226 */ 227 struct clk_gate { 228 struct clk_hw hw; 229 void __iomem *reg; 230 u8 bit_idx; 231 u8 flags; 232 spinlock_t *lock; 233 }; 234 235 #define CLK_GATE_SET_TO_DISABLE BIT(0) 236 #define CLK_GATE_HIWORD_MASK BIT(1) 237 238 extern const struct clk_ops clk_gate_ops; 239 struct clk *clk_register_gate(struct device *dev, const char *name, 240 const char *parent_name, unsigned long flags, 241 void __iomem *reg, u8 bit_idx, 242 u8 clk_gate_flags, spinlock_t *lock); 243 244 struct clk_div_table { 245 unsigned int val; 246 unsigned int div; 247 }; 248 249 /** 250 * struct clk_divider - adjustable divider clock 251 * 252 * @hw: handle between common and hardware-specific interfaces 253 * @reg: register containing the divider 254 * @shift: shift to the divider bit field 255 * @width: width of the divider bit field 256 * @table: array of value/divider pairs, last entry should have div = 0 257 * @lock: register lock 258 * 259 * Clock with an adjustable divider affecting its output frequency. Implements 260 * .recalc_rate, .set_rate and .round_rate 261 * 262 * Flags: 263 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 264 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 265 * the raw value read from the register, with the value of zero considered 266 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 267 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 268 * the hardware register 269 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 270 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 271 * Some hardware implementations gracefully handle this case and allow a 272 * zero divisor by not modifying their input clock 273 * (divide by one / bypass). 274 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 275 * of this register, and mask of divider bits are in higher 16-bit of this 276 * register. While setting the divider bits, higher 16-bit should also be 277 * updated to indicate changing divider bits. 278 */ 279 struct clk_divider { 280 struct clk_hw hw; 281 void __iomem *reg; 282 u8 shift; 283 u8 width; 284 u8 flags; 285 const struct clk_div_table *table; 286 spinlock_t *lock; 287 }; 288 289 #define CLK_DIVIDER_ONE_BASED BIT(0) 290 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 291 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 292 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 293 294 extern const struct clk_ops clk_divider_ops; 295 struct clk *clk_register_divider(struct device *dev, const char *name, 296 const char *parent_name, unsigned long flags, 297 void __iomem *reg, u8 shift, u8 width, 298 u8 clk_divider_flags, spinlock_t *lock); 299 struct clk *clk_register_divider_table(struct device *dev, const char *name, 300 const char *parent_name, unsigned long flags, 301 void __iomem *reg, u8 shift, u8 width, 302 u8 clk_divider_flags, const struct clk_div_table *table, 303 spinlock_t *lock); 304 305 /** 306 * struct clk_mux - multiplexer clock 307 * 308 * @hw: handle between common and hardware-specific interfaces 309 * @reg: register controlling multiplexer 310 * @shift: shift to multiplexer bit field 311 * @width: width of mutliplexer bit field 312 * @flags: hardware-specific flags 313 * @lock: register lock 314 * 315 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 316 * and .recalc_rate 317 * 318 * Flags: 319 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 320 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 321 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 322 * register, and mask of mux bits are in higher 16-bit of this register. 323 * While setting the mux bits, higher 16-bit should also be updated to 324 * indicate changing mux bits. 325 */ 326 struct clk_mux { 327 struct clk_hw hw; 328 void __iomem *reg; 329 u32 *table; 330 u32 mask; 331 u8 shift; 332 u8 flags; 333 spinlock_t *lock; 334 }; 335 336 #define CLK_MUX_INDEX_ONE BIT(0) 337 #define CLK_MUX_INDEX_BIT BIT(1) 338 #define CLK_MUX_HIWORD_MASK BIT(2) 339 #define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 340 341 extern const struct clk_ops clk_mux_ops; 342 extern const struct clk_ops clk_mux_ro_ops; 343 344 struct clk *clk_register_mux(struct device *dev, const char *name, 345 const char **parent_names, u8 num_parents, unsigned long flags, 346 void __iomem *reg, u8 shift, u8 width, 347 u8 clk_mux_flags, spinlock_t *lock); 348 349 struct clk *clk_register_mux_table(struct device *dev, const char *name, 350 const char **parent_names, u8 num_parents, unsigned long flags, 351 void __iomem *reg, u8 shift, u32 mask, 352 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 353 354 void of_fixed_factor_clk_setup(struct device_node *node); 355 356 /** 357 * struct clk_fixed_factor - fixed multiplier and divider clock 358 * 359 * @hw: handle between common and hardware-specific interfaces 360 * @mult: multiplier 361 * @div: divider 362 * 363 * Clock with a fixed multiplier and divider. The output frequency is the 364 * parent clock rate divided by div and multiplied by mult. 365 * Implements .recalc_rate, .set_rate and .round_rate 366 */ 367 368 struct clk_fixed_factor { 369 struct clk_hw hw; 370 unsigned int mult; 371 unsigned int div; 372 }; 373 374 extern struct clk_ops clk_fixed_factor_ops; 375 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 376 const char *parent_name, unsigned long flags, 377 unsigned int mult, unsigned int div); 378 379 /*** 380 * struct clk_composite - aggregate clock of mux, divider and gate clocks 381 * 382 * @hw: handle between common and hardware-specific interfaces 383 * @mux_hw: handle between composite and hardware-specific mux clock 384 * @rate_hw: handle between composite and hardware-specific rate clock 385 * @gate_hw: handle between composite and hardware-specific gate clock 386 * @mux_ops: clock ops for mux 387 * @rate_ops: clock ops for rate 388 * @gate_ops: clock ops for gate 389 */ 390 struct clk_composite { 391 struct clk_hw hw; 392 struct clk_ops ops; 393 394 struct clk_hw *mux_hw; 395 struct clk_hw *rate_hw; 396 struct clk_hw *gate_hw; 397 398 const struct clk_ops *mux_ops; 399 const struct clk_ops *rate_ops; 400 const struct clk_ops *gate_ops; 401 }; 402 403 struct clk *clk_register_composite(struct device *dev, const char *name, 404 const char **parent_names, int num_parents, 405 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 406 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 407 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 408 unsigned long flags); 409 410 /** 411 * clk_register - allocate a new clock, register it and return an opaque cookie 412 * @dev: device that is registering this clock 413 * @hw: link to hardware-specific clock data 414 * 415 * clk_register is the primary interface for populating the clock tree with new 416 * clock nodes. It returns a pointer to the newly allocated struct clk which 417 * cannot be dereferenced by driver code but may be used in conjuction with the 418 * rest of the clock API. In the event of an error clk_register will return an 419 * error code; drivers must test for an error code after calling clk_register. 420 */ 421 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 422 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 423 424 void clk_unregister(struct clk *clk); 425 void devm_clk_unregister(struct device *dev, struct clk *clk); 426 427 /* helper functions */ 428 const char *__clk_get_name(struct clk *clk); 429 struct clk_hw *__clk_get_hw(struct clk *clk); 430 u8 __clk_get_num_parents(struct clk *clk); 431 struct clk *__clk_get_parent(struct clk *clk); 432 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 433 unsigned int __clk_get_enable_count(struct clk *clk); 434 unsigned int __clk_get_prepare_count(struct clk *clk); 435 unsigned long __clk_get_rate(struct clk *clk); 436 unsigned long __clk_get_flags(struct clk *clk); 437 bool __clk_is_prepared(struct clk *clk); 438 bool __clk_is_enabled(struct clk *clk); 439 struct clk *__clk_lookup(const char *name); 440 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 441 unsigned long *best_parent_rate, 442 struct clk **best_parent_p); 443 444 /* 445 * FIXME clock api without lock protection 446 */ 447 int __clk_prepare(struct clk *clk); 448 void __clk_unprepare(struct clk *clk); 449 void __clk_reparent(struct clk *clk, struct clk *new_parent); 450 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 451 452 struct of_device_id; 453 454 typedef void (*of_clk_init_cb_t)(struct device_node *); 455 456 struct clk_onecell_data { 457 struct clk **clks; 458 unsigned int clk_num; 459 }; 460 461 #define CLK_OF_DECLARE(name, compat, fn) \ 462 static const struct of_device_id __clk_of_table_##name \ 463 __used __section(__clk_of_table) \ 464 = { .compatible = compat, .data = fn }; 465 466 #ifdef CONFIG_OF 467 int of_clk_add_provider(struct device_node *np, 468 struct clk *(*clk_src_get)(struct of_phandle_args *args, 469 void *data), 470 void *data); 471 void of_clk_del_provider(struct device_node *np); 472 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 473 void *data); 474 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 475 const char *of_clk_get_parent_name(struct device_node *np, int index); 476 477 void of_clk_init(const struct of_device_id *matches); 478 479 #else /* !CONFIG_OF */ 480 481 static inline int of_clk_add_provider(struct device_node *np, 482 struct clk *(*clk_src_get)(struct of_phandle_args *args, 483 void *data), 484 void *data) 485 { 486 return 0; 487 } 488 #define of_clk_del_provider(np) \ 489 { while (0); } 490 static inline struct clk *of_clk_src_simple_get( 491 struct of_phandle_args *clkspec, void *data) 492 { 493 return ERR_PTR(-ENOENT); 494 } 495 static inline struct clk *of_clk_src_onecell_get( 496 struct of_phandle_args *clkspec, void *data) 497 { 498 return ERR_PTR(-ENOENT); 499 } 500 static inline const char *of_clk_get_parent_name(struct device_node *np, 501 int index) 502 { 503 return NULL; 504 } 505 #define of_clk_init(matches) \ 506 { while (0); } 507 #endif /* CONFIG_OF */ 508 509 /* 510 * wrap access to peripherals in accessor routines 511 * for improved portability across platforms 512 */ 513 514 static inline u32 clk_readl(u32 __iomem *reg) 515 { 516 return readl(reg); 517 } 518 519 static inline void clk_writel(u32 val, u32 __iomem *reg) 520 { 521 writel(val, reg); 522 } 523 524 #endif /* CONFIG_COMMON_CLK */ 525 #endif /* CLK_PROVIDER_H */ 526