1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_clk.h> 17 18 #ifdef CONFIG_COMMON_CLK 19 20 /* 21 * flags used across common struct clk. these flags should only affect the 22 * top-level framework. custom flags for dealing with hardware specifics 23 * belong in struct clk_foo 24 * 25 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 26 */ 27 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 28 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 29 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 30 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 31 /* unused */ 32 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 33 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 34 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 35 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 36 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 37 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 38 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 39 /* parents need enable during gate/ungate, set rate and re-parent */ 40 #define CLK_OPS_PARENT_ENABLE BIT(12) 41 42 struct clk; 43 struct clk_hw; 44 struct clk_core; 45 struct dentry; 46 47 /** 48 * struct clk_rate_request - Structure encoding the clk constraints that 49 * a clock user might require. 50 * 51 * @rate: Requested clock rate. This field will be adjusted by 52 * clock drivers according to hardware capabilities. 53 * @min_rate: Minimum rate imposed by clk users. 54 * @max_rate: Maximum rate imposed by clk users. 55 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 56 * requested constraints. 57 * @best_parent_hw: The most appropriate parent clock that fulfills the 58 * requested constraints. 59 * 60 */ 61 struct clk_rate_request { 62 unsigned long rate; 63 unsigned long min_rate; 64 unsigned long max_rate; 65 unsigned long best_parent_rate; 66 struct clk_hw *best_parent_hw; 67 }; 68 69 /** 70 * struct clk_ops - Callback operations for hardware clocks; these are to 71 * be provided by the clock implementation, and will be called by drivers 72 * through the clk_* api. 73 * 74 * @prepare: Prepare the clock for enabling. This must not return until 75 * the clock is fully prepared, and it's safe to call clk_enable. 76 * This callback is intended to allow clock implementations to 77 * do any initialisation that may sleep. Called with 78 * prepare_lock held. 79 * 80 * @unprepare: Release the clock from its prepared state. This will typically 81 * undo any work done in the @prepare callback. Called with 82 * prepare_lock held. 83 * 84 * @is_prepared: Queries the hardware to determine if the clock is prepared. 85 * This function is allowed to sleep. Optional, if this op is not 86 * set then the prepare count will be used. 87 * 88 * @unprepare_unused: Unprepare the clock atomically. Only called from 89 * clk_disable_unused for prepare clocks with special needs. 90 * Called with prepare mutex held. This function may sleep. 91 * 92 * @enable: Enable the clock atomically. This must not return until the 93 * clock is generating a valid clock signal, usable by consumer 94 * devices. Called with enable_lock held. This function must not 95 * sleep. 96 * 97 * @disable: Disable the clock atomically. Called with enable_lock held. 98 * This function must not sleep. 99 * 100 * @is_enabled: Queries the hardware to determine if the clock is enabled. 101 * This function must not sleep. Optional, if this op is not 102 * set then the enable count will be used. 103 * 104 * @disable_unused: Disable the clock atomically. Only called from 105 * clk_disable_unused for gate clocks with special needs. 106 * Called with enable_lock held. This function must not 107 * sleep. 108 * 109 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 110 * parent rate is an input parameter. It is up to the caller to 111 * ensure that the prepare_mutex is held across this call. 112 * Returns the calculated rate. Optional, but recommended - if 113 * this op is not set then clock rate will be initialized to 0. 114 * 115 * @round_rate: Given a target rate as input, returns the closest rate actually 116 * supported by the clock. The parent rate is an input/output 117 * parameter. 118 * 119 * @determine_rate: Given a target rate as input, returns the closest rate 120 * actually supported by the clock, and optionally the parent clock 121 * that should be used to provide the clock rate. 122 * 123 * @set_parent: Change the input source of this clock; for clocks with multiple 124 * possible parents specify a new parent by passing in the index 125 * as a u8 corresponding to the parent in either the .parent_names 126 * or .parents arrays. This function in affect translates an 127 * array index into the value programmed into the hardware. 128 * Returns 0 on success, -EERROR otherwise. 129 * 130 * @get_parent: Queries the hardware to determine the parent of a clock. The 131 * return value is a u8 which specifies the index corresponding to 132 * the parent clock. This index can be applied to either the 133 * .parent_names or .parents arrays. In short, this function 134 * translates the parent value read from hardware into an array 135 * index. Currently only called when the clock is initialized by 136 * __clk_init. This callback is mandatory for clocks with 137 * multiple parents. It is optional (and unnecessary) for clocks 138 * with 0 or 1 parents. 139 * 140 * @set_rate: Change the rate of this clock. The requested rate is specified 141 * by the second argument, which should typically be the return 142 * of .round_rate call. The third argument gives the parent rate 143 * which is likely helpful for most .set_rate implementation. 144 * Returns 0 on success, -EERROR otherwise. 145 * 146 * @set_rate_and_parent: Change the rate and the parent of this clock. The 147 * requested rate is specified by the second argument, which 148 * should typically be the return of .round_rate call. The 149 * third argument gives the parent rate which is likely helpful 150 * for most .set_rate_and_parent implementation. The fourth 151 * argument gives the parent index. This callback is optional (and 152 * unnecessary) for clocks with 0 or 1 parents as well as 153 * for clocks that can tolerate switching the rate and the parent 154 * separately via calls to .set_parent and .set_rate. 155 * Returns 0 on success, -EERROR otherwise. 156 * 157 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 158 * is expressed in ppb (parts per billion). The parent accuracy is 159 * an input parameter. 160 * Returns the calculated accuracy. Optional - if this op is not 161 * set then clock accuracy will be initialized to parent accuracy 162 * or 0 (perfect clock) if clock has no parent. 163 * 164 * @get_phase: Queries the hardware to get the current phase of a clock. 165 * Returned values are 0-359 degrees on success, negative 166 * error codes on failure. 167 * 168 * @set_phase: Shift the phase this clock signal in degrees specified 169 * by the second argument. Valid values for degrees are 170 * 0-359. Return 0 on success, otherwise -EERROR. 171 * 172 * @init: Perform platform-specific initialization magic. 173 * This is not not used by any of the basic clock types. 174 * Please consider other ways of solving initialization problems 175 * before using this callback, as its use is discouraged. 176 * 177 * @debug_init: Set up type-specific debugfs entries for this clock. This 178 * is called once, after the debugfs directory entry for this 179 * clock has been created. The dentry pointer representing that 180 * directory is provided as an argument. Called with 181 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 182 * 183 * 184 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 185 * implementations to split any work between atomic (enable) and sleepable 186 * (prepare) contexts. If enabling a clock requires code that might sleep, 187 * this must be done in clk_prepare. Clock enable code that will never be 188 * called in a sleepable context may be implemented in clk_enable. 189 * 190 * Typically, drivers will call clk_prepare when a clock may be needed later 191 * (eg. when a device is opened), and clk_enable when the clock is actually 192 * required (eg. from an interrupt). Note that clk_prepare MUST have been 193 * called before clk_enable. 194 */ 195 struct clk_ops { 196 int (*prepare)(struct clk_hw *hw); 197 void (*unprepare)(struct clk_hw *hw); 198 int (*is_prepared)(struct clk_hw *hw); 199 void (*unprepare_unused)(struct clk_hw *hw); 200 int (*enable)(struct clk_hw *hw); 201 void (*disable)(struct clk_hw *hw); 202 int (*is_enabled)(struct clk_hw *hw); 203 void (*disable_unused)(struct clk_hw *hw); 204 unsigned long (*recalc_rate)(struct clk_hw *hw, 205 unsigned long parent_rate); 206 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 207 unsigned long *parent_rate); 208 int (*determine_rate)(struct clk_hw *hw, 209 struct clk_rate_request *req); 210 int (*set_parent)(struct clk_hw *hw, u8 index); 211 u8 (*get_parent)(struct clk_hw *hw); 212 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 213 unsigned long parent_rate); 214 int (*set_rate_and_parent)(struct clk_hw *hw, 215 unsigned long rate, 216 unsigned long parent_rate, u8 index); 217 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 218 unsigned long parent_accuracy); 219 int (*get_phase)(struct clk_hw *hw); 220 int (*set_phase)(struct clk_hw *hw, int degrees); 221 void (*init)(struct clk_hw *hw); 222 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 223 }; 224 225 /** 226 * struct clk_init_data - holds init data that's common to all clocks and is 227 * shared between the clock provider and the common clock framework. 228 * 229 * @name: clock name 230 * @ops: operations this clock supports 231 * @parent_names: array of string names for all possible parents 232 * @num_parents: number of possible parents 233 * @flags: framework-level hints and quirks 234 */ 235 struct clk_init_data { 236 const char *name; 237 const struct clk_ops *ops; 238 const char * const *parent_names; 239 u8 num_parents; 240 unsigned long flags; 241 }; 242 243 /** 244 * struct clk_hw - handle for traversing from a struct clk to its corresponding 245 * hardware-specific structure. struct clk_hw should be declared within struct 246 * clk_foo and then referenced by the struct clk instance that uses struct 247 * clk_foo's clk_ops 248 * 249 * @core: pointer to the struct clk_core instance that points back to this 250 * struct clk_hw instance 251 * 252 * @clk: pointer to the per-user struct clk instance that can be used to call 253 * into the clk API 254 * 255 * @init: pointer to struct clk_init_data that contains the init data shared 256 * with the common clock framework. 257 */ 258 struct clk_hw { 259 struct clk_core *core; 260 struct clk *clk; 261 const struct clk_init_data *init; 262 }; 263 264 /* 265 * DOC: Basic clock implementations common to many platforms 266 * 267 * Each basic clock hardware type is comprised of a structure describing the 268 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 269 * unique flags for that hardware type, a registration function and an 270 * alternative macro for static initialization 271 */ 272 273 /** 274 * struct clk_fixed_rate - fixed-rate clock 275 * @hw: handle between common and hardware-specific interfaces 276 * @fixed_rate: constant frequency of clock 277 */ 278 struct clk_fixed_rate { 279 struct clk_hw hw; 280 unsigned long fixed_rate; 281 unsigned long fixed_accuracy; 282 u8 flags; 283 }; 284 285 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) 286 287 extern const struct clk_ops clk_fixed_rate_ops; 288 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 289 const char *parent_name, unsigned long flags, 290 unsigned long fixed_rate); 291 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, 292 const char *parent_name, unsigned long flags, 293 unsigned long fixed_rate); 294 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 295 const char *name, const char *parent_name, unsigned long flags, 296 unsigned long fixed_rate, unsigned long fixed_accuracy); 297 void clk_unregister_fixed_rate(struct clk *clk); 298 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, 299 const char *name, const char *parent_name, unsigned long flags, 300 unsigned long fixed_rate, unsigned long fixed_accuracy); 301 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 302 303 void of_fixed_clk_setup(struct device_node *np); 304 305 /** 306 * struct clk_gate - gating clock 307 * 308 * @hw: handle between common and hardware-specific interfaces 309 * @reg: register controlling gate 310 * @bit_idx: single bit controlling gate 311 * @flags: hardware-specific flags 312 * @lock: register lock 313 * 314 * Clock which can gate its output. Implements .enable & .disable 315 * 316 * Flags: 317 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 318 * enable the clock. Setting this flag does the opposite: setting the bit 319 * disable the clock and clearing it enables the clock 320 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 321 * of this register, and mask of gate bits are in higher 16-bit of this 322 * register. While setting the gate bits, higher 16-bit should also be 323 * updated to indicate changing gate bits. 324 */ 325 struct clk_gate { 326 struct clk_hw hw; 327 void __iomem *reg; 328 u8 bit_idx; 329 u8 flags; 330 spinlock_t *lock; 331 }; 332 333 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 334 335 #define CLK_GATE_SET_TO_DISABLE BIT(0) 336 #define CLK_GATE_HIWORD_MASK BIT(1) 337 338 extern const struct clk_ops clk_gate_ops; 339 struct clk *clk_register_gate(struct device *dev, const char *name, 340 const char *parent_name, unsigned long flags, 341 void __iomem *reg, u8 bit_idx, 342 u8 clk_gate_flags, spinlock_t *lock); 343 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, 344 const char *parent_name, unsigned long flags, 345 void __iomem *reg, u8 bit_idx, 346 u8 clk_gate_flags, spinlock_t *lock); 347 void clk_unregister_gate(struct clk *clk); 348 void clk_hw_unregister_gate(struct clk_hw *hw); 349 int clk_gate_is_enabled(struct clk_hw *hw); 350 351 struct clk_div_table { 352 unsigned int val; 353 unsigned int div; 354 }; 355 356 /** 357 * struct clk_divider - adjustable divider clock 358 * 359 * @hw: handle between common and hardware-specific interfaces 360 * @reg: register containing the divider 361 * @shift: shift to the divider bit field 362 * @width: width of the divider bit field 363 * @table: array of value/divider pairs, last entry should have div = 0 364 * @lock: register lock 365 * 366 * Clock with an adjustable divider affecting its output frequency. Implements 367 * .recalc_rate, .set_rate and .round_rate 368 * 369 * Flags: 370 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 371 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 372 * the raw value read from the register, with the value of zero considered 373 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 374 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 375 * the hardware register 376 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 377 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 378 * Some hardware implementations gracefully handle this case and allow a 379 * zero divisor by not modifying their input clock 380 * (divide by one / bypass). 381 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 382 * of this register, and mask of divider bits are in higher 16-bit of this 383 * register. While setting the divider bits, higher 16-bit should also be 384 * updated to indicate changing divider bits. 385 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 386 * to the closest integer instead of the up one. 387 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 388 * not be changed by the clock framework. 389 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 390 * except when the value read from the register is zero, the divisor is 391 * 2^width of the field. 392 */ 393 struct clk_divider { 394 struct clk_hw hw; 395 void __iomem *reg; 396 u8 shift; 397 u8 width; 398 u8 flags; 399 const struct clk_div_table *table; 400 spinlock_t *lock; 401 }; 402 403 #define clk_div_mask(width) ((1 << (width)) - 1) 404 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 405 406 #define CLK_DIVIDER_ONE_BASED BIT(0) 407 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 408 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 409 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 410 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 411 #define CLK_DIVIDER_READ_ONLY BIT(5) 412 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 413 414 extern const struct clk_ops clk_divider_ops; 415 extern const struct clk_ops clk_divider_ro_ops; 416 417 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 418 unsigned int val, const struct clk_div_table *table, 419 unsigned long flags, unsigned long width); 420 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 421 unsigned long rate, unsigned long *prate, 422 const struct clk_div_table *table, 423 u8 width, unsigned long flags); 424 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 425 unsigned long rate, unsigned long *prate, 426 const struct clk_div_table *table, u8 width, 427 unsigned long flags, unsigned int val); 428 int divider_get_val(unsigned long rate, unsigned long parent_rate, 429 const struct clk_div_table *table, u8 width, 430 unsigned long flags); 431 432 struct clk *clk_register_divider(struct device *dev, const char *name, 433 const char *parent_name, unsigned long flags, 434 void __iomem *reg, u8 shift, u8 width, 435 u8 clk_divider_flags, spinlock_t *lock); 436 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, 437 const char *parent_name, unsigned long flags, 438 void __iomem *reg, u8 shift, u8 width, 439 u8 clk_divider_flags, spinlock_t *lock); 440 struct clk *clk_register_divider_table(struct device *dev, const char *name, 441 const char *parent_name, unsigned long flags, 442 void __iomem *reg, u8 shift, u8 width, 443 u8 clk_divider_flags, const struct clk_div_table *table, 444 spinlock_t *lock); 445 struct clk_hw *clk_hw_register_divider_table(struct device *dev, 446 const char *name, const char *parent_name, unsigned long flags, 447 void __iomem *reg, u8 shift, u8 width, 448 u8 clk_divider_flags, const struct clk_div_table *table, 449 spinlock_t *lock); 450 void clk_unregister_divider(struct clk *clk); 451 void clk_hw_unregister_divider(struct clk_hw *hw); 452 453 /** 454 * struct clk_mux - multiplexer clock 455 * 456 * @hw: handle between common and hardware-specific interfaces 457 * @reg: register controlling multiplexer 458 * @table: array of register values corresponding to the parent index 459 * @shift: shift to multiplexer bit field 460 * @mask: mask of mutliplexer bit field 461 * @flags: hardware-specific flags 462 * @lock: register lock 463 * 464 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 465 * and .recalc_rate 466 * 467 * Flags: 468 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 469 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 470 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 471 * register, and mask of mux bits are in higher 16-bit of this register. 472 * While setting the mux bits, higher 16-bit should also be updated to 473 * indicate changing mux bits. 474 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 475 * frequency. 476 */ 477 struct clk_mux { 478 struct clk_hw hw; 479 void __iomem *reg; 480 u32 *table; 481 u32 mask; 482 u8 shift; 483 u8 flags; 484 spinlock_t *lock; 485 }; 486 487 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 488 489 #define CLK_MUX_INDEX_ONE BIT(0) 490 #define CLK_MUX_INDEX_BIT BIT(1) 491 #define CLK_MUX_HIWORD_MASK BIT(2) 492 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 493 #define CLK_MUX_ROUND_CLOSEST BIT(4) 494 495 extern const struct clk_ops clk_mux_ops; 496 extern const struct clk_ops clk_mux_ro_ops; 497 498 struct clk *clk_register_mux(struct device *dev, const char *name, 499 const char * const *parent_names, u8 num_parents, 500 unsigned long flags, 501 void __iomem *reg, u8 shift, u8 width, 502 u8 clk_mux_flags, spinlock_t *lock); 503 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, 504 const char * const *parent_names, u8 num_parents, 505 unsigned long flags, 506 void __iomem *reg, u8 shift, u8 width, 507 u8 clk_mux_flags, spinlock_t *lock); 508 509 struct clk *clk_register_mux_table(struct device *dev, const char *name, 510 const char * const *parent_names, u8 num_parents, 511 unsigned long flags, 512 void __iomem *reg, u8 shift, u32 mask, 513 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 514 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, 515 const char * const *parent_names, u8 num_parents, 516 unsigned long flags, 517 void __iomem *reg, u8 shift, u32 mask, 518 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 519 520 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, 521 unsigned int val); 522 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); 523 524 void clk_unregister_mux(struct clk *clk); 525 void clk_hw_unregister_mux(struct clk_hw *hw); 526 527 void of_fixed_factor_clk_setup(struct device_node *node); 528 529 /** 530 * struct clk_fixed_factor - fixed multiplier and divider clock 531 * 532 * @hw: handle between common and hardware-specific interfaces 533 * @mult: multiplier 534 * @div: divider 535 * 536 * Clock with a fixed multiplier and divider. The output frequency is the 537 * parent clock rate divided by div and multiplied by mult. 538 * Implements .recalc_rate, .set_rate and .round_rate 539 */ 540 541 struct clk_fixed_factor { 542 struct clk_hw hw; 543 unsigned int mult; 544 unsigned int div; 545 }; 546 547 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 548 549 extern const struct clk_ops clk_fixed_factor_ops; 550 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 551 const char *parent_name, unsigned long flags, 552 unsigned int mult, unsigned int div); 553 void clk_unregister_fixed_factor(struct clk *clk); 554 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 555 const char *name, const char *parent_name, unsigned long flags, 556 unsigned int mult, unsigned int div); 557 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 558 559 /** 560 * struct clk_fractional_divider - adjustable fractional divider clock 561 * 562 * @hw: handle between common and hardware-specific interfaces 563 * @reg: register containing the divider 564 * @mshift: shift to the numerator bit field 565 * @mwidth: width of the numerator bit field 566 * @nshift: shift to the denominator bit field 567 * @nwidth: width of the denominator bit field 568 * @lock: register lock 569 * 570 * Clock with adjustable fractional divider affecting its output frequency. 571 */ 572 struct clk_fractional_divider { 573 struct clk_hw hw; 574 void __iomem *reg; 575 u8 mshift; 576 u8 mwidth; 577 u32 mmask; 578 u8 nshift; 579 u8 nwidth; 580 u32 nmask; 581 u8 flags; 582 void (*approximation)(struct clk_hw *hw, 583 unsigned long rate, unsigned long *parent_rate, 584 unsigned long *m, unsigned long *n); 585 spinlock_t *lock; 586 }; 587 588 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 589 590 extern const struct clk_ops clk_fractional_divider_ops; 591 struct clk *clk_register_fractional_divider(struct device *dev, 592 const char *name, const char *parent_name, unsigned long flags, 593 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 594 u8 clk_divider_flags, spinlock_t *lock); 595 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 596 const char *name, const char *parent_name, unsigned long flags, 597 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 598 u8 clk_divider_flags, spinlock_t *lock); 599 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 600 601 /** 602 * struct clk_multiplier - adjustable multiplier clock 603 * 604 * @hw: handle between common and hardware-specific interfaces 605 * @reg: register containing the multiplier 606 * @shift: shift to the multiplier bit field 607 * @width: width of the multiplier bit field 608 * @lock: register lock 609 * 610 * Clock with an adjustable multiplier affecting its output frequency. 611 * Implements .recalc_rate, .set_rate and .round_rate 612 * 613 * Flags: 614 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 615 * from the register, with 0 being a valid value effectively 616 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 617 * set, then a null multiplier will be considered as a bypass, 618 * leaving the parent rate unmodified. 619 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 620 * rounded to the closest integer instead of the down one. 621 */ 622 struct clk_multiplier { 623 struct clk_hw hw; 624 void __iomem *reg; 625 u8 shift; 626 u8 width; 627 u8 flags; 628 spinlock_t *lock; 629 }; 630 631 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 632 633 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 634 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 635 636 extern const struct clk_ops clk_multiplier_ops; 637 638 /*** 639 * struct clk_composite - aggregate clock of mux, divider and gate clocks 640 * 641 * @hw: handle between common and hardware-specific interfaces 642 * @mux_hw: handle between composite and hardware-specific mux clock 643 * @rate_hw: handle between composite and hardware-specific rate clock 644 * @gate_hw: handle between composite and hardware-specific gate clock 645 * @mux_ops: clock ops for mux 646 * @rate_ops: clock ops for rate 647 * @gate_ops: clock ops for gate 648 */ 649 struct clk_composite { 650 struct clk_hw hw; 651 struct clk_ops ops; 652 653 struct clk_hw *mux_hw; 654 struct clk_hw *rate_hw; 655 struct clk_hw *gate_hw; 656 657 const struct clk_ops *mux_ops; 658 const struct clk_ops *rate_ops; 659 const struct clk_ops *gate_ops; 660 }; 661 662 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 663 664 struct clk *clk_register_composite(struct device *dev, const char *name, 665 const char * const *parent_names, int num_parents, 666 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 667 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 668 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 669 unsigned long flags); 670 void clk_unregister_composite(struct clk *clk); 671 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 672 const char * const *parent_names, int num_parents, 673 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 674 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 675 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 676 unsigned long flags); 677 void clk_hw_unregister_composite(struct clk_hw *hw); 678 679 /*** 680 * struct clk_gpio_gate - gpio gated clock 681 * 682 * @hw: handle between common and hardware-specific interfaces 683 * @gpiod: gpio descriptor 684 * 685 * Clock with a gpio control for enabling and disabling the parent clock. 686 * Implements .enable, .disable and .is_enabled 687 */ 688 689 struct clk_gpio { 690 struct clk_hw hw; 691 struct gpio_desc *gpiod; 692 }; 693 694 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) 695 696 extern const struct clk_ops clk_gpio_gate_ops; 697 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 698 const char *parent_name, struct gpio_desc *gpiod, 699 unsigned long flags); 700 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 701 const char *parent_name, struct gpio_desc *gpiod, 702 unsigned long flags); 703 void clk_hw_unregister_gpio_gate(struct clk_hw *hw); 704 705 /** 706 * struct clk_gpio_mux - gpio controlled clock multiplexer 707 * 708 * @hw: see struct clk_gpio 709 * @gpiod: gpio descriptor to select the parent of this clock multiplexer 710 * 711 * Clock with a gpio control for selecting the parent clock. 712 * Implements .get_parent, .set_parent and .determine_rate 713 */ 714 715 extern const struct clk_ops clk_gpio_mux_ops; 716 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 717 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 718 unsigned long flags); 719 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 720 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 721 unsigned long flags); 722 void clk_hw_unregister_gpio_mux(struct clk_hw *hw); 723 724 /** 725 * clk_register - allocate a new clock, register it and return an opaque cookie 726 * @dev: device that is registering this clock 727 * @hw: link to hardware-specific clock data 728 * 729 * clk_register is the primary interface for populating the clock tree with new 730 * clock nodes. It returns a pointer to the newly allocated struct clk which 731 * cannot be dereferenced by driver code but may be used in conjuction with the 732 * rest of the clock API. In the event of an error clk_register will return an 733 * error code; drivers must test for an error code after calling clk_register. 734 */ 735 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 736 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 737 738 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 739 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 740 741 void clk_unregister(struct clk *clk); 742 void devm_clk_unregister(struct device *dev, struct clk *clk); 743 744 void clk_hw_unregister(struct clk_hw *hw); 745 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); 746 747 /* helper functions */ 748 const char *__clk_get_name(const struct clk *clk); 749 const char *clk_hw_get_name(const struct clk_hw *hw); 750 struct clk_hw *__clk_get_hw(struct clk *clk); 751 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 752 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 753 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 754 unsigned int index); 755 unsigned int __clk_get_enable_count(struct clk *clk); 756 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 757 unsigned long __clk_get_flags(struct clk *clk); 758 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 759 bool clk_hw_is_prepared(const struct clk_hw *hw); 760 bool clk_hw_rate_is_protected(const struct clk_hw *hw); 761 bool clk_hw_is_enabled(const struct clk_hw *hw); 762 bool __clk_is_enabled(struct clk *clk); 763 struct clk *__clk_lookup(const char *name); 764 int __clk_mux_determine_rate(struct clk_hw *hw, 765 struct clk_rate_request *req); 766 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 767 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 768 struct clk_rate_request *req); 769 int clk_mux_determine_rate_flags(struct clk_hw *hw, 770 struct clk_rate_request *req, 771 unsigned long flags); 772 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 773 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 774 unsigned long max_rate); 775 776 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 777 { 778 dst->clk = src->clk; 779 dst->core = src->core; 780 } 781 782 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 783 unsigned long *prate, 784 const struct clk_div_table *table, 785 u8 width, unsigned long flags) 786 { 787 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 788 rate, prate, table, width, flags); 789 } 790 791 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 792 unsigned long *prate, 793 const struct clk_div_table *table, 794 u8 width, unsigned long flags, 795 unsigned int val) 796 { 797 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 798 rate, prate, table, width, flags, 799 val); 800 } 801 802 /* 803 * FIXME clock api without lock protection 804 */ 805 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 806 807 struct of_device_id; 808 809 struct clk_onecell_data { 810 struct clk **clks; 811 unsigned int clk_num; 812 }; 813 814 struct clk_hw_onecell_data { 815 unsigned int num; 816 struct clk_hw *hws[]; 817 }; 818 819 extern struct of_device_id __clk_of_table; 820 821 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 822 823 /* 824 * Use this macro when you have a driver that requires two initialization 825 * routines, one at of_clk_init(), and one at platform device probe 826 */ 827 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 828 static void __init name##_of_clk_init_driver(struct device_node *np) \ 829 { \ 830 of_node_clear_flag(np, OF_POPULATED); \ 831 fn(np); \ 832 } \ 833 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 834 835 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 836 (&(struct clk_init_data) { \ 837 .flags = _flags, \ 838 .name = _name, \ 839 .parent_names = (const char *[]) { _parent }, \ 840 .num_parents = 1, \ 841 .ops = _ops, \ 842 }) 843 844 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 845 (&(struct clk_init_data) { \ 846 .flags = _flags, \ 847 .name = _name, \ 848 .parent_names = _parents, \ 849 .num_parents = ARRAY_SIZE(_parents), \ 850 .ops = _ops, \ 851 }) 852 853 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 854 (&(struct clk_init_data) { \ 855 .flags = _flags, \ 856 .name = _name, \ 857 .parent_names = NULL, \ 858 .num_parents = 0, \ 859 .ops = _ops, \ 860 }) 861 862 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 863 _div, _mult, _flags) \ 864 struct clk_fixed_factor _struct = { \ 865 .div = _div, \ 866 .mult = _mult, \ 867 .hw.init = CLK_HW_INIT(_name, \ 868 _parent, \ 869 &clk_fixed_factor_ops, \ 870 _flags), \ 871 } 872 873 #ifdef CONFIG_OF 874 int of_clk_add_provider(struct device_node *np, 875 struct clk *(*clk_src_get)(struct of_phandle_args *args, 876 void *data), 877 void *data); 878 int of_clk_add_hw_provider(struct device_node *np, 879 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 880 void *data), 881 void *data); 882 int devm_of_clk_add_hw_provider(struct device *dev, 883 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 884 void *data), 885 void *data); 886 void of_clk_del_provider(struct device_node *np); 887 void devm_of_clk_del_provider(struct device *dev); 888 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 889 void *data); 890 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 891 void *data); 892 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 893 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 894 void *data); 895 int of_clk_parent_fill(struct device_node *np, const char **parents, 896 unsigned int size); 897 int of_clk_detect_critical(struct device_node *np, int index, 898 unsigned long *flags); 899 900 #else /* !CONFIG_OF */ 901 902 static inline int of_clk_add_provider(struct device_node *np, 903 struct clk *(*clk_src_get)(struct of_phandle_args *args, 904 void *data), 905 void *data) 906 { 907 return 0; 908 } 909 static inline int of_clk_add_hw_provider(struct device_node *np, 910 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 911 void *data), 912 void *data) 913 { 914 return 0; 915 } 916 static inline int devm_of_clk_add_hw_provider(struct device *dev, 917 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 918 void *data), 919 void *data) 920 { 921 return 0; 922 } 923 static inline void of_clk_del_provider(struct device_node *np) {} 924 static inline void devm_of_clk_del_provider(struct device *dev) {} 925 static inline struct clk *of_clk_src_simple_get( 926 struct of_phandle_args *clkspec, void *data) 927 { 928 return ERR_PTR(-ENOENT); 929 } 930 static inline struct clk_hw * 931 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 932 { 933 return ERR_PTR(-ENOENT); 934 } 935 static inline struct clk *of_clk_src_onecell_get( 936 struct of_phandle_args *clkspec, void *data) 937 { 938 return ERR_PTR(-ENOENT); 939 } 940 static inline struct clk_hw * 941 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 942 { 943 return ERR_PTR(-ENOENT); 944 } 945 static inline int of_clk_parent_fill(struct device_node *np, 946 const char **parents, unsigned int size) 947 { 948 return 0; 949 } 950 static inline int of_clk_detect_critical(struct device_node *np, int index, 951 unsigned long *flags) 952 { 953 return 0; 954 } 955 #endif /* CONFIG_OF */ 956 957 /* 958 * wrap access to peripherals in accessor routines 959 * for improved portability across platforms 960 */ 961 962 #if IS_ENABLED(CONFIG_PPC) 963 964 static inline u32 clk_readl(u32 __iomem *reg) 965 { 966 return ioread32be(reg); 967 } 968 969 static inline void clk_writel(u32 val, u32 __iomem *reg) 970 { 971 iowrite32be(val, reg); 972 } 973 974 #else /* platform dependent I/O accessors */ 975 976 static inline u32 clk_readl(u32 __iomem *reg) 977 { 978 return readl(reg); 979 } 980 981 static inline void clk_writel(u32 val, u32 __iomem *reg) 982 { 983 writel(val, reg); 984 } 985 986 #endif /* platform dependent I/O accessors */ 987 988 #endif /* CONFIG_COMMON_CLK */ 989 #endif /* CLK_PROVIDER_H */ 990